From b18dd28caf6d15159047b2d8b3f4bd4af40193bd Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Mon, 27 Jul 2020 18:24:42 -0700
Subject: [PATCH 01/16] Add configuration for Tiny Z80

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/HBIOS/Config/EZZ80_tz80.asm | 41 ++++++++++++++++++++++++++++++
 Source/HBIOS/Makefile              |  1 +
 Source/HBIOS/cfg_dyno.asm          |  2 ++
 Source/HBIOS/cfg_ezz80.asm         |  2 ++
 Source/HBIOS/cfg_master.asm        |  2 ++
 Source/HBIOS/cfg_mk4.asm           |  2 ++
 Source/HBIOS/cfg_n8.asm            |  2 ++
 Source/HBIOS/cfg_rcz180.asm        |  2 ++
 Source/HBIOS/cfg_rcz80.asm         |  2 ++
 Source/HBIOS/cfg_sbc.asm           |  2 ++
 Source/HBIOS/cfg_scz180.asm        |  2 ++
 Source/HBIOS/cfg_zeta.asm          |  2 ++
 Source/HBIOS/cfg_zeta2.asm         |  2 ++
 Source/HBIOS/hbios.asm             | 16 ++++++++++++
 14 files changed, 80 insertions(+)
 create mode 100644 Source/HBIOS/Config/EZZ80_tz80.asm

diff --git a/Source/HBIOS/Config/EZZ80_tz80.asm b/Source/HBIOS/Config/EZZ80_tz80.asm
new file mode 100644
index 00000000..93a45e94
--- /dev/null
+++ b/Source/HBIOS/Config/EZZ80_tz80.asm
@@ -0,0 +1,41 @@
+;
+;==================================================================================================
+;   EASY Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "TINYZ80"
+;
+#include "cfg_ezz80.asm"
+;
+CPUOSC		.SET	16000000	; CPU OSC FREQ IN MHZ
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+EIPCENABLE	.SET	TRUE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+CTCBASE		.SET	$10		; CTC BASE I/O ADDRESS
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
+LEDPORT		.SET	$6E		; STATUS LED PORT ADDRESS
+SIO0BASE	.SET	$18		; SIO 0: REGISTERS BASE ADR
+IDE0BASE	.SET	$90		; IDE 0: IO BASE ADDRESS
diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile
index 6ee90216..294ddf1a 100644
--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -3,6 +3,7 @@ OBJECTS =
 ifeq (1,1)
 OBJECTS += DYNO_std.rom DYNO_std.com
 OBJECTS += EZZ80_std.rom EZZ80_std.com
+OBJECTS += EZZ80_tz80.rom EZZ80_tz80.com
 OBJECTS += MK4_std.rom MK4_std.com
 OBJECTS += N8_std.rom N8_std.com
 OBJECTS += RCZ180_ext.rom RCZ180_ext.com
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 3a073290..41c41471 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -154,3 +154,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index 9036a113..20e9c5ef 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -169,3 +169,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 53f062fd..17a84abc 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -230,3 +230,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index 630b47f1..e8f9da73 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -184,3 +184,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index 65db812a..6e60cd26 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -184,3 +184,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index a221334a..5f6c0354 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -179,3 +179,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 9a078f5c..de1476f4 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -184,3 +184,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 482fe08c..0e83b015 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -185,3 +185,5 @@ PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 0450a6a6..77f06047 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -175,3 +175,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 75ddc039..f13aeb61 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -133,3 +133,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 1582373c..a91ad204 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -138,3 +138,5 @@ PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS
 PPI_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
 UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 6e696cb6..40b0d392 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -860,6 +860,22 @@ HB_START:
 ;
 #ENDIF
 ;
+#IF (EIPCENABLE)
+	LD	A,$7B			; CLEAR WDTE BIT (DISABLE WATCHDOG)
+	OUT	($F0),A
+	LD	A,$B1			; DISABLE WDT - SECOND KEY
+	OUT 	($F1),A
+	LD	A,$00			; SET SYSTEM CONTROL REGISTER POINTER
+					; (SCRP) TO POINT TO WAIT STATE
+	OUT	($EE),A			; CONTROL REGISTER (WCR)
+	LD	A,$00			; NO WAIT STATES
+	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
+	LD	A,$03			; SET SCRP TO POINT TO MISCELLANEOUS
+	OUT	($EE),A			; CONTROL REGISTER (MCR)
+	LD	A,$10			; DIVIDE CLOCK BY 1, /CS0 DISABLE
+	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
+#ENDIF
+;
 #IF (MEMMGR == MM_Z2)
 	; SET PAGING REGISTERS
 #IFDEF ROMBOOT

From b4713fa3ff081770f87eb8f7b6ffb12615d08bb2 Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Mon, 27 Jul 2020 18:26:53 -0700
Subject: [PATCH 02/16] Add Tiny Z80 image file name

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/Doc/GettingStarted.md | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/Source/Doc/GettingStarted.md b/Source/Doc/GettingStarted.md
index ba84859b..c3d486d7 100644
--- a/Source/Doc/GettingStarted.md
+++ b/Source/Doc/GettingStarted.md
@@ -153,6 +153,7 @@ the appropriate ROM image for your hardware.
 | RC Z180\*      | RCZ180_ext.rom           | 115200      | RC2014 w/ Z180 CPU & 512K banked RAM/ROM module  |
 | RC Z180\*      | RCZ180_nat.rom           | 115200      | RC2014 w/ Z180 CPU & 512K native RAM/ROM module  |
 | Easy Z80       | EZZ80_std.rom            | 115200      | Sergey Kiselev's Easy Z80                        |
+| Tiny Z80       | EZZ80_tz80.rom           | 115200      | Sergey Kiselev's Tiny Z80                        |
 | SC126          | SCZ180_126.rom           | 115200      | Stephen Cousin's SC126 Z180                      |
 | SC130          | SCZ180_130.rom           | 115200      | Stephen Cousin's SC130 Z180                      |
 | SC131          | SCZ180_131.rom           | 115200      | Stephen Cousin's SC131 Z180                      |
@@ -1218,4 +1219,4 @@ RetroBrew Computers projects is via the community forums:
 
 Submission of issues and bugs are welcome at the [RomWBW GitHub Repository](https://github.com/wwarthen/RomWBW).
 
-Also feel free to email !author at [!authmail](mailto:!authmail).
\ No newline at end of file
+Also feel free to email !author at [!authmail](mailto:!authmail).

From f482801b94aac5d3e8ce2a625446befc906ef769 Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Sat, 1 Aug 2020 13:24:13 -0700
Subject: [PATCH 03/16] Add definitions for Z80 EIPC / Z84C15

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/HBIOS/eipc.inc | 75 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 Source/HBIOS/eipc.inc

diff --git a/Source/HBIOS/eipc.inc b/Source/HBIOS/eipc.inc
new file mode 100644
index 00000000..24519d62
--- /dev/null
+++ b/Source/HBIOS/eipc.inc
@@ -0,0 +1,75 @@
+;
+; Z80 EIPC (Z84C15) REGISTERS
+;
+EIPC_SCRP	.EQU	$EE		; SYSTEM CONTROL REGISTER POINTER
+EIPC_SCDP	.EQU	$EF		; SYSTEM CONTROL DATA PORT
+EIPC_WDTMR	.EQU	$F0		; WATCHDOG TIMER MASTER REGISTER
+EIPC_WDTCR	.EQU	$F1		; WATCHDOG TIMER COMMAND REGISTER
+EIPC_INTPR	.EQU	$F4		; INTERRUPT PRIORITY REGISTER
+;
+; SYSTEM CONTROL REGISTERS (REGISTER NUMBER TO BE WRITTEN TO EIPC_SCRP)
+;
+EIPC_WCR	.EQU	$00		; WAIT STATE CONTROL REGISTER
+EIPC_MWBR	.EQU	$01		; MEMORY WAIT BOUNDARY REGISTER
+EIPC_CSBR	.EQU	$02		; CHIP SELECT BOUNDARY REGISTER
+EIPC_MCR	.EQU	$03		; MISCELLANEOUS CONTROL REGISTER
+;
+; WAIT STATE VALUES (FOR EIPC_WCR)
+;
+EIPC_IO_0WS	.EQU	$00		; NO (ZERO) I/O WAIT STATES
+EIPC_IO_2WS	.EQU	$01		; 2 I/O WAIT STATES
+EIPC_IO_4WS	.EQU	$02		; 4 I/O WAIT STATES
+EIPC_IO_6WS	.EQU	$03		; 6 I/O WAIT STATES
+EIPC_MEM_OWS	.EQU	$00		; NO (ZERO) MEMORY WAIT STATES
+EIPC_MEM_1WS	.EQU	$04		; 1 MEMORY WAIT STATE
+EIPC_MEM_1WS	.EQU	$08		; 2 MEMORY WAIT STATES
+EIPC_MEM_1WS	.EQU	$0C		; 3 MEMORY WAIT STATES
+EIPC_OCF_0WS	.EQU	$00		; NO ADDITIONAL WAIT ON OP-CODE FETCH
+EIPC_OCF_1WS	.EQU	$10		; +1 WAIT STATE ON OP-CODE FETCH
+EIPC_INT_0WS	.EQU	$00		; NO WAIT ON INTERRUPT VECTOR READ
+EIPC_INT_1WS	.EQU	$20		; 1 WAIT STATE ON INT. VECTOR READ
+EIPC_CHAIN_0WS	.EQU	$00		; 0 WAIT ON INT ACK. / 0 WAIT ON RETI
+EIPC_CHAIN_2WS	.EQU	$40		; 2 WAIT ON INT ACK. / 0 WAIT ON RETI
+EIPC_CHAIN_4WS	.EQU	$80		; 4 WAIT ON INT ACK. / 2 WAIT ON RETI
+EIPC_CHAIN_6WS	.EQU	$C0		; 6 WAIT ON INT ACK. / 4 WAIT ON RETI
+;
+; MISCELLANEOUS CONTROL REGISTER VALUES
+;
+EIPC_CS0_DIS	.EQU	$00		; DISABLE /CS0
+EIPC_CS0_ENA	.EQU	$01		; ENABLE /CS0
+EIPC_CS1_DIS	.EQU	$00		; DISABLE /CS1
+EIPC_CS1_ENA	.EQU	$02		; ENABLE /CS1
+EIPC_32CRC_DIS	.EQU	$00		; DISABLE 32-BIT CRC FOR SIO CHANNEL A
+EIPC_32CRC_ENA	.EQU	$04		; ENABLE 32-BIT CRC FOR SIO CHANNEL A
+EIPC_RSTOUT_DIS	.EQU	$08		; DISABLE RESET OUTPUT
+EIPC_RSTOUT_ENA	.EQU	$00		; ENABLE RESET OUTPUT
+EIPC_CLKDIV1	.EQU	$10		; DIVIDE XTAL/CGC CLOCK BY ONE
+EIPC_CLKDIV2	.EQU	$00		; DIVIDE XTAL/CGC CLOCK BY TWO
+;
+; WATCHDOG TIMER MASTER REGISTER VALUES
+;
+EIPC_WDT_CONST	.EQU	$03		; MUST SET LOWER THREE BITS TO 011
+EIPC_HALT_IDLE1 .EQU	$00		; HALT / POWER DOWN MODE - IDLE 1 MODE
+EIPC_HALT_IDLE2 .EQU	$08		; HALT / POWER DOWN MODE - IDLE 2 MODE
+EIPC_HALT_STOP	.EQU	$10		; HALT / POWER DOWN MODE - STOP MODE
+EIPC_HALT_RUN	.EQU	$18		; HALT / POWER DOWN MODE - RUN MODE
+EIPC_WDT_P2_16	.EQU	$00		; SET WATCHDOG PERIOD TO TOC * 2^16
+EIPC_WDT_P2_18	.EQU	$20		; SET WATCHDOG PERIOD TO TOC * 2^18
+EIPC_WDT_P2_20	.EQU	$40		; SET WATCHDOG PERIOD TO TOC * 2^20
+EIPC_WDT_P2_22	.EQU	$60		; SET WATCHDOG PERIOD TO TOC * 2^22
+EIPC_WDTE	.EQU	$80		; ENABLE WATCHDOG TIMER
+;
+; WATCHDOG TIMER COMMAND REGISTER VALUES
+; 
+EIPC_DIS_WDT	.EQU	$B1		; DISABLE WATCHDOG TIMER
+EIPC_CLR_WDT	.EQU	$4E		; CLEAR WATCHDOG TIMER
+EIPC_HLT_MODE	.EQU	$DB		; CHANGE HALT MODE
+;
+; INTERRUPT PRIORITY REGISTER VALUES
+;
+EIPC_CTC_SIO_PIO	.EQU	$00	; PRIORITY HIGH TO LOW: CTC, SIO, PIO
+EIPC_SIO_CTC_PIO	.EQU	$01	; PRIORITY HIGH TO LOW: SIO, CTC, PIO
+EIPC_CTC_PIO_SIO	.EQU	$02	; PRIORITY HIGH TO LOW: CTC, PIO, SIO
+EIPC_PIO_SIO_CTC	.EQU	$03	; PRIORITY HIGH TO LOW: PIO, SIO, CTC
+EIPC_PIC_CTC_SIO	.EQU	$04	; PRIORITY HIGH TO LOW: PIO, CTC, SIO
+EIPC_SIO_PIO_CTC	.EQU	$05	; PRIORITY HIGH TO LOW: SIO, PIO, CTC

From 78cd69e34d210fd1d91bed4e8f8d7e1aa44ec9cd Mon Sep 17 00:00:00 2001
From: Sergey Kiselev <skiselev@gmail.com>
Date: Sat, 1 Aug 2020 13:24:43 -0700
Subject: [PATCH 04/16] Use definitions for Z80 EIPC / Z84C15

Signed-off-by: Sergey Kiselev <skiselev@gmail.com>
---
 Source/HBIOS/hbios.asm | 24 ++++++++++++------------
 Source/HBIOS/std.asm   |  3 +++
 2 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 40b0d392..4e9a5f8a 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -861,19 +861,19 @@ HB_START:
 #ENDIF
 ;
 #IF (EIPCENABLE)
-	LD	A,$7B			; CLEAR WDTE BIT (DISABLE WATCHDOG)
-	OUT	($F0),A
-	LD	A,$B1			; DISABLE WDT - SECOND KEY
-	OUT 	($F1),A
-	LD	A,$00			; SET SYSTEM CONTROL REGISTER POINTER
+	LD	A,(EIPC_WDT_CONST | EIPC_HALT_RUN | EIPC_WDT_P2_22)
+	OUT	(EIPC_WDTMR),A		; CLEAR WDTE BIT (DISABLE WATCHDOG)
+	LD	A,EIPC_DIS_WDT		; DISABLE WDT - SECOND KEY
+	OUT 	(EIPC_WDTCR),A
+	LD	A,EIPC_WCR		; SET SYSTEM CONTROL REGISTER POINTER
 					; (SCRP) TO POINT TO WAIT STATE
-	OUT	($EE),A			; CONTROL REGISTER (WCR)
-	LD	A,$00			; NO WAIT STATES
-	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
-	LD	A,$03			; SET SCRP TO POINT TO MISCELLANEOUS
-	OUT	($EE),A			; CONTROL REGISTER (MCR)
-	LD	A,$10			; DIVIDE CLOCK BY 1, /CS0 DISABLE
-	OUT	($EF),A			; SET SYSTEM CONTROL DATA PORT (SCDP)
+	OUT	(EIPC_SCRP),A		; CONTROL REGISTER (WCR)
+	LD	A,(EIPC_IO_0WS | EIPC_MEM_OWS | EIPC_OCF_0WS | EIPC_INT_0WS | EIPC_CHAIN_0WS)
+	OUT	(EIPC_SCDP),A		; NO WAIT STATES
+	LD	A,EIPC_MCR		; SET SCRP TO POINT TO MISCELLANEOUS
+	OUT	(EIPC_SCRP),A		; CONTROL REGISTER (MCR)
+	LD	A,EIPC_CLKDIV1		; DIVIDE CLOCK BY 1, /CS0 DISABLE
+	OUT	(EIPC_SCDP),A		; SET SYSTEM CONTROL DATA PORT (SCDP)
 #ENDIF
 ;
 #IF (MEMMGR == MM_Z2)
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index f0aa880d..9a51672a 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -327,6 +327,9 @@ FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
   #IF (CPUFAM == CPU_Z180)
     #INCLUDE "z180.inc"
   #ENDIF
+  #IF (EIPCENABLE)
+    #INCLUDE "eipc.inc"
+  #ENDIF
 #ENDIF
 ;
 ; SETUP DEFAULT CPU SPEED VALUES

From f078b98c5d7a77998683492a683deefec8b3fd2b Mon Sep 17 00:00:00 2001
From: mlukasek <martin@lukasek.cz>
Date: Sat, 10 Oct 2020 02:54:29 +0200
Subject: [PATCH 05/16] EIPC_MEM_xWS values corrected

---
 Source/HBIOS/eipc.inc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Source/HBIOS/eipc.inc b/Source/HBIOS/eipc.inc
index 24519d62..6497e63d 100644
--- a/Source/HBIOS/eipc.inc
+++ b/Source/HBIOS/eipc.inc
@@ -22,8 +22,8 @@ EIPC_IO_4WS	.EQU	$02		; 4 I/O WAIT STATES
 EIPC_IO_6WS	.EQU	$03		; 6 I/O WAIT STATES
 EIPC_MEM_OWS	.EQU	$00		; NO (ZERO) MEMORY WAIT STATES
 EIPC_MEM_1WS	.EQU	$04		; 1 MEMORY WAIT STATE
-EIPC_MEM_1WS	.EQU	$08		; 2 MEMORY WAIT STATES
-EIPC_MEM_1WS	.EQU	$0C		; 3 MEMORY WAIT STATES
+EIPC_MEM_2WS	.EQU	$08		; 2 MEMORY WAIT STATES
+EIPC_MEM_3WS	.EQU	$0C		; 3 MEMORY WAIT STATES
 EIPC_OCF_0WS	.EQU	$00		; NO ADDITIONAL WAIT ON OP-CODE FETCH
 EIPC_OCF_1WS	.EQU	$10		; +1 WAIT STATE ON OP-CODE FETCH
 EIPC_INT_0WS	.EQU	$00		; NO WAIT ON INTERRUPT VECTOR READ

From 705e1944c9eb996e4b78916ab7ca4892368c9942 Mon Sep 17 00:00:00 2001
From: Cocoacrumbs <kvnieuwe@telenet.be>
Date: Sat, 23 Jan 2021 15:38:41 +0100
Subject: [PATCH 06/16] Fix for multiple definition of 'verbose' in
 RomWBW/Tools/unix/uz80as/uz80as.h

---
 Tools/unix/uz80as/uz80as.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Tools/unix/uz80as/uz80as.h b/Tools/unix/uz80as/uz80as.h
index 511da085..19e71764 100644
--- a/Tools/unix/uz80as/uz80as.h
+++ b/Tools/unix/uz80as/uz80as.h
@@ -8,7 +8,7 @@
 #ifndef UZ80AS_H
 #define UZ80AS_H
 
-int verbose;
+static int verbose;
 
 /* matchtab.flags */
 enum {

From d3d59d6922a748b399f992c2bf7872406bb5fe4b Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Sat, 23 Jan 2021 09:02:12 -0800
Subject: [PATCH 07/16] Update commit.yml

---
 .github/workflows/commit.yml | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/commit.yml b/.github/workflows/commit.yml
index 7cdbe1a0..088fca37 100644
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -13,7 +13,7 @@ jobs:
     runs-on: ubuntu-latest
 
     steps:
-      - uses: rlespinasse/github-slug-action@1.1.0
+      - uses: rlespinasse/github-slug-action@v3.x
         
       - uses: actions/checkout@v2
           
@@ -28,4 +28,4 @@ jobs:
         uses: actions/upload-artifact@v1
         with:
           name: RomWBW-${{env.GITHUB_REF_SLUG}}-${{env.GITHUB_SHA_SHORT}}
-          path: .
\ No newline at end of file
+          path: .

From 8a7bc97fea27bf10a23c61ee508522a60e2909c6 Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Sat, 30 Jan 2021 18:46:03 -0800
Subject: [PATCH 08/16] Update commit.yml

Trying to get GitHub build scripts to use Pacific Time Zone.
---
 .github/workflows/commit.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/commit.yml b/.github/workflows/commit.yml
index 088fca37..689e14c1 100644
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -19,6 +19,7 @@ jobs:
           
       - name: Build
         run: |
+          export TZ='America/Los_Angeles'
           sudo apt-get install libncurses-dev
           make
           make clean

From bec1c46d21815570e3084381220b5f5a931e61c6 Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 9 Feb 2021 16:44:05 +1100
Subject: [PATCH 09/16] acia - whitespace

---
 Source/HBIOS/acia.asm | 578 +++++++++++++++++++++---------------------
 1 file changed, 289 insertions(+), 289 deletions(-)

diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm
index 2e030a76..38947a61 100644
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -25,37 +25,37 @@
 ;     | RIE   | TC2   | TC1   | WS3   | WS2   | WS1   | CDS2  | CDS1  |
 ;     +-------+-------+-------+-------+-------+-------+-------+-------+
 ;
-;	RIE:	RECEIVE INTERRUPT ENABLE (RECEIVE DATA REGISTER FULL)
-;
-;	TC:	TRANSMIT CONTROL (TRANSMIT DATA REGISTER EMPTY)
-;		0 0 - /RTS=LOW, TDRE INT DISABLED
-;		0 1 - /RTS=LOW, TDRE INT ENABLED
-;		1 0 - /RTS=HIGH, TDRE INT DISABLED
-;		1 1 - /RTS=LOW, TRANSMIT BREAK, TDRE INT DISABLED
-;	
-;	WS:	WORD SELECT (DATA BITS, PARITY, STOP BITS)
-;		0 0 0 - 7,E,2
-;		0 0 1 - 7,O,2
-;		0 1 0 - 7,E,1
-;		0 1 1 - 7,O,1
-;		1 0 0 - 8,N,2
-;		1 0 1 - 8,N,1
-;		1 1 0 - 8,E,1
-;		1 1 1 - 8,O,1
-;
-;	CDS:	COUNTER DIVIDE SELECT
-;		0 0 - DIVIDE BY 1
-;		0 1 - DIVIDE BY 16
-;		1 0 - DIVIDE BY 64
-;		1 1 - MASTER RESET
-;
-ACIA_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
+;       RIE:    RECEIVE INTERRUPT ENABLE (RECEIVE DATA REGISTER FULL)
+;
+;       TC:     TRANSMIT CONTROL (TRANSMIT DATA REGISTER EMPTY)
+;               0 0 - /RTS=LOW, TDRE INT DISABLED
+;               0 1 - /RTS=LOW, TDRE INT ENABLED
+;               1 0 - /RTS=HIGH, TDRE INT DISABLED
+;               1 1 - /RTS=LOW, TRANSMIT BREAK, TDRE INT DISABLED
+;        
+;       WS:     WORD SELECT (DATA BITS, PARITY, STOP BITS)
+;               0 0 0 - 7,E,2
+;               0 0 1 - 7,O,2
+;               0 1 0 - 7,E,1
+;               0 1 1 - 7,O,1
+;               1 0 0 - 8,N,2
+;               1 0 1 - 8,N,1
+;               1 1 0 - 8,E,1
+;               1 1 1 - 8,O,1
+;
+;       CDS:    COUNTER DIVIDE SELECT
+;               0 0 - DIVIDE BY 1
+;               0 1 - DIVIDE BY 16
+;               1 0 - DIVIDE BY 64
+;               1 1 - MASTER RESET
+;
+ACIA_BUFSZ      .EQU    32              ; RECEIVE RING BUFFER SIZE
 ;
 ACIA_NONE       .EQU    0
 ACIA_ACIA       .EQU    1
 ;
-ACIA_RTSON	.EQU	%00000000	; BIT MASK TO ASSERT RTS
-ACIA_RTSOFF	.EQU	%01000000	; BIT MASK TO DEASSERT RTS
+ACIA_RTSON      .EQU    %00000000       ; BIT MASK TO ASSERT RTS
+ACIA_RTSOFF     .EQU    %01000000       ; BIT MASK TO DEASSERT RTS
 ;
 #IF (INTMODE > 1)
         .ECHO   "*** ERROR: UNSUPPORTED INTMODE FOR ACIA DRIVER!!!\n"
@@ -70,34 +70,34 @@ ACIA_PREINIT:
 ; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMIAIN
 ; DISABLED.
 ;
-        LD      B,ACIA_CFGCNT		; LOOP CONTROL
+        LD      B,ACIA_CFGCNT           ; LOOP CONTROL
         XOR     A                       ; ZERO TO ACCUM
         LD      (ACIA_DEV),A            ; CURRENT DEVICE NUMBER
-	LD	IY,ACIA_CFG		; POINT TO START OF CFG TABLE
+        LD      IY,ACIA_CFG             ; POINT TO START OF CFG TABLE
 ACIA_PREINIT0:
-	PUSH	BC			; SAVE LOOP CONTROL
-	CALL	ACIA_INITUNIT		; HAND OFF TO GENERIC INIT CODE
-	POP	BC			; RESTORE LOOP CONTROL
-;
-	LD	A,(IY+1)		; GET THE ACIA TYPE DETECTED
-	OR	A			; SET FLAGS
-	JR	Z,ACIA_PREINIT2		; SKIP IT IF NOTHING FOUND
-;	
-	PUSH	BC			; SAVE LOOP CONTROL
-	PUSH	IY			; CFG ENTRY ADDRESS
-	POP	DE			; ... TO DE
-	LD	BC,ACIA_FNTBL		; BC := FUNCTION TABLE ADDRESS
-	CALL	NZ,CIO_ADDENT		; ADD ENTRY IF ACIA FOUND, BC:DE
-	POP	BC			; RESTORE LOOP CONTROL
-;
-ACIA_PREINIT2:	
-	LD	DE,ACIA_CFGSIZ		; SIZE OF CFG ENTRY
-	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
-	DJNZ	ACIA_PREINIT0		; LOOP UNTIL DONE
+        PUSH    BC                      ; SAVE LOOP CONTROL
+        CALL    ACIA_INITUNIT           ; HAND OFF TO GENERIC INIT CODE
+        POP     BC                      ; RESTORE LOOP CONTROL
+;
+        LD      A,(IY+1)                ; GET THE ACIA TYPE DETECTED
+        OR      A                       ; SET FLAGS
+        JR      Z,ACIA_PREINIT2         ; SKIP IT IF NOTHING FOUND
+;        
+        PUSH    BC                      ; SAVE LOOP CONTROL
+        PUSH    IY                      ; CFG ENTRY ADDRESS
+        POP     DE                      ; ... TO DE
+        LD      BC,ACIA_FNTBL           ; BC := FUNCTION TABLE ADDRESS
+        CALL    NZ,CIO_ADDENT           ; ADD ENTRY IF ACIA FOUND, BC:DE
+        POP     BC                      ; RESTORE LOOP CONTROL
+;
+ACIA_PREINIT2:        
+        LD      DE,ACIA_CFGSIZ          ; SIZE OF CFG ENTRY
+        ADD     IY,DE                   ; BUMP IY TO NEXT ENTRY
+        DJNZ    ACIA_PREINIT0           ; LOOP UNTIL DONE
 ;
 ACIA_PREINIT3:
-	XOR	A			; SIGNAL SUCCESS
-	RET				; AND RETURN
+        XOR     A                       ; SIGNAL SUCCESS
+        RET                             ; AND RETURN
 ;
 ; ACIA INITIALIZATION ROUTINE
 ;
@@ -115,22 +115,22 @@ ACIA_INITUNIT:
 ;
 #IF (INTMODE == 1)
         ; ADD IM1 INT CALL LIST ENTRY
-        LD      L,(IY+8)		; GET INT HANDLER PTR
-        LD      H,(IY+9)		; ... INTO HL
+        LD      L,(IY+8)                ; GET INT HANDLER PTR
+        LD      H,(IY+9)                ; ... INTO HL
         CALL    HB_ADDIM1               ; ADD TO IM1 CALL LIST
 #ENDIF
 ;
 #IF (INTMODE > 1)
-	.ECHO	"*** ERROR: ACIA DEVICE DOES NOT SUPPORT INTMODE 2!!!\n"
-	!!!	; FORCE AN ASSEMBLY ERROR
+        .ECHO        "*** ERROR: ACIA DEVICE DOES NOT SUPPORT INTMODE 2!!!\n"
+        !!!        ; FORCE AN ASSEMBLY ERROR
 #ENDIF
 ;
-	; IT IS EASY TO SPECIFY A SERIAL CONFIG THAT CANNOT BE IMPLEMENTED
-	; DUE TO THE CONSTRAINTS OF THE ACIA.  HERE WE FORCE A GENERIC
-	; FAILSAFE CONFIG ONTO THE CHANNEL.  IF THE SUBSEQUENT "REAL"
-	; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT
-	; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG.
-	CALL	ACIA_INITSAFE
+        ; IT IS EASY TO SPECIFY A SERIAL CONFIG THAT CANNOT BE IMPLEMENTED
+        ; DUE TO THE CONSTRAINTS OF THE ACIA.  HERE WE FORCE A GENERIC
+        ; FAILSAFE CONFIG ONTO THE CHANNEL.  IF THE SUBSEQUENT "REAL"
+        ; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT
+        ; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG.
+        CALL    ACIA_INITSAFE
 ;
         ; SET DEFAULT CONFIG
         LD      DE,-1                   ; LEAVE CONFIG ALONE
@@ -141,20 +141,20 @@ ACIA_INITUNIT:
 ;
 ;
 ACIA_INIT:
-	LD	B,ACIA_CFGCNT		; COUNT OF POSSIBLE ACIA UNITS
-	LD	IY,ACIA_CFG		; POINT TO START OF CFG TABLE
+        LD      B,ACIA_CFGCNT           ; COUNT OF POSSIBLE ACIA UNITS
+        LD      IY,ACIA_CFG             ; POINT TO START OF CFG TABLE
 ACIA_INIT1:
-	PUSH	BC			; SAVE LOOP CONTROL
-	LD	A,(IY+1)		; GET ACIA TYPE
-	OR	A			; SET FLAGS
-	CALL	NZ,ACIA_PRTCFG		; PRINT IF NOT ZERO
-	POP	BC			; RESTORE LOOP CONTROL
-	LD	DE,ACIA_CFGSIZ		; SIZE OF CFG ENTRY
-	ADD	IY,DE			; BUMP IY TO NEXT ENTRY
-	DJNZ	ACIA_INIT1		; LOOP TILL DONE
-;
-	XOR	A			; SIGNAL SUCCESS
-	RET				; DONE
+        PUSH    BC                      ; SAVE LOOP CONTROL
+        LD      A,(IY+1)                ; GET ACIA TYPE
+        OR      A                       ; SET FLAGS
+        CALL    NZ,ACIA_PRTCFG          ; PRINT IF NOT ZERO
+        POP     BC                      ; RESTORE LOOP CONTROL
+        LD      DE,ACIA_CFGSIZ          ; SIZE OF CFG ENTRY
+        ADD     IY,DE                   ; BUMP IY TO NEXT ENTRY
+        DJNZ    ACIA_INIT1              ; LOOP TILL DONE
+;
+        XOR     A                       ; SIGNAL SUCCESS
+        RET                             ; DONE
 ;
 ; INTERRUPT HANDLERS
 ;
@@ -165,21 +165,21 @@ ACIA_INIT1:
 ;
 ACIA0_INT:
 ACIA1_INT:
-	CALL	PANIC
+        CALL    PANIC
 ;
 #ENDIF
 ;
 #IF (INTMODE > 0)
 ;
 ACIA0_INT:
-	LD	IY,ACIA0_CFG		; POINT TO ACIA0 CFG
-	JR	ACIA_INTRCV		; TRY TO RECEIVE FROM IT AND RETURN
+        LD      IY,ACIA0_CFG            ; POINT TO ACIA0 CFG
+        JR      ACIA_INTRCV             ; TRY TO RECEIVE FROM IT AND RETURN
 ;
 #IF (ACIACNT >= 2)
 ;
 ACIA1_INT:
-	LD	IY,ACIA1_CFG		; POINT TO ACIA1 CFG
-	JR	ACIA_INTRCV		; TRY TO RECEIVE FROM IT AND RETURN
+        LD      IY,ACIA1_CFG            ; POINT TO ACIA1 CFG
+        JR      ACIA_INTRCV             ; TRY TO RECEIVE FROM IT AND RETURN
 ;
 #ENDIF
 ;
@@ -187,62 +187,62 @@ ACIA1_INT:
 ; BASED ON UNIT CFG POINTED TO BY IY
 ;
 ACIA_INTRCV:
-	; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
-	LD	C,(IY+3)		; CMD/STAT PORT TO C
-	IN	A,(C)			; GET STATUS
-	AND	$01			; ISOLATE RECEIVE READY BIT
-	RET	Z			; NOTHING AVAILABLE ON CURRENT CHANNEL
+        ; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
+        LD      C,(IY+3)                ; CMD/STAT PORT TO C
+        IN      A,(C)                   ; GET STATUS
+        AND     $01                     ; ISOLATE RECEIVE READY BIT
+        RET     Z                       ; NOTHING AVAILABLE ON CURRENT CHANNEL
 ;
 ACIA_INTRCV1:
-	; RECEIVE CHARACTER INTO BUFFER
+        ; RECEIVE CHARACTER INTO BUFFER
         INC     C                       ; DATA PORT
-	IN	A,(C)			; READ PORT
+        IN      A,(C)                   ; READ PORT
         DEC     C                       ; BACK TO CONTROL PORT
-	LD	B,A			; SAVE BYTE READ
-	LD	L,(IY+6)		; SET HL TO
-	LD	H,(IY+7)		; ... START OF BUFFER STRUCT
-	LD	A,(HL)			; GET COUNT
-	CP	ACIA_BUFSZ		; COMPARE TO BUFFER SIZE
-	JR	Z,ACIA_INTRCV4		; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
-	INC	A			; INCREMENT THE COUNT
-	LD	(HL),A			; AND SAVE IT
-	CP	ACIA_BUFSZ / 2		; BUFFER GETTING FULL?
-	JR	NZ,ACIA_INTRCV2		; IF NOT, BYPASS CLEARING RTS
-	LD	A,(ACIA_CMD)		; CONFIG BYTE W/O RTS BIT
-	OR	ACIA_RTSOFF		; CLEAR RTS
-	OUT	(C),A			; DO IT
+        LD      B,A                     ; SAVE BYTE READ
+        LD      L,(IY+6)                ; SET HL TO
+        LD      H,(IY+7)                ; ... START OF BUFFER STRUCT
+        LD      A,(HL)                  ; GET COUNT
+        CP      ACIA_BUFSZ              ; COMPARE TO BUFFER SIZE
+        JR      Z,ACIA_INTRCV4          ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
+        INC     A                       ; INCREMENT THE COUNT
+        LD      (HL),A                  ; AND SAVE IT
+        CP      ACIA_BUFSZ / 2          ; BUFFER GETTING FULL?
+        JR      NZ,ACIA_INTRCV2         ; IF NOT, BYPASS CLEARING RTS
+        LD      A,(ACIA_CMD)            ; CONFIG BYTE W/O RTS BIT
+        OR      ACIA_RTSOFF             ; CLEAR RTS
+        OUT     (C),A                   ; DO IT
 ACIA_INTRCV2:
-	INC	HL			; HL NOW HAS ADR OF HEAD PTR
-	PUSH	HL			; SAVE ADR OF HEAD PTR
-	LD	A,(HL)			; DEREFERENCE HL
-	INC	HL
-	LD	H,(HL)
-	LD	L,A			; HL IS NOW ACTUAL HEAD PTR
-	LD	(HL),B			; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD
-	INC	HL			; BUMP HEAD POINTER
-	POP	DE			; RECOVER ADR OF HEAD PTR
-	LD	A,L			; GET LOW BYTE OF HEAD PTR
-	SUB	ACIA_BUFSZ+4		; SUBTRACT SIZE OF BUFFER AND POINTER
-	CP	E			; IF EQUAL TO START, HEAD PTR IS PAST BUF END
-	JR	NZ,ACIA_INTRCV3		; IF NOT, BYPASS
-	LD	H,D			; SET HL TO
-	LD	L,E			; ... HEAD PTR ADR
-	INC	HL			; BUMP PAST HEAD PTR
-	INC	HL
-	INC	HL
-	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
+        INC     HL                      ; HL NOW HAS ADR OF HEAD PTR
+        PUSH    HL                      ; SAVE ADR OF HEAD PTR
+        LD      A,(HL)                  ; DEREFERENCE HL
+        INC     HL
+        LD      H,(HL)
+        LD      L,A                     ; HL IS NOW ACTUAL HEAD PTR
+        LD      (HL),B                  ; SAVE CHARACTER RECEIVED IN BUFFER AT HEAD
+        INC     HL                      ; BUMP HEAD POINTER
+        POP     DE                      ; RECOVER ADR OF HEAD PTR
+        LD      A,L                     ; GET LOW BYTE OF HEAD PTR
+        SUB     ACIA_BUFSZ+4            ; SUBTRACT SIZE OF BUFFER AND POINTER
+        CP      E                       ; IF EQUAL TO START, HEAD PTR IS PAST BUF END
+        JR      NZ,ACIA_INTRCV3         ; IF NOT, BYPASS
+        LD      H,D                     ; SET HL TO
+        LD      L,E                     ; ... HEAD PTR ADR
+        INC     HL                      ; BUMP PAST HEAD PTR
+        INC     HL
+        INC     HL
+        INC     HL                      ; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
 ACIA_INTRCV3:
-	EX	DE,HL			; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR
-	LD	(HL),E			; SAVE UPDATED HEAD PTR
-	INC	HL
-	LD	(HL),D
-	; CHECK FOR MORE PENDING...
-	IN	A,(C)			; GET STATUS
-	RRA				; READY BIT TO CF
-	JR	C,ACIA_INTRCV1		; IF SET, DO SOME MORE
+        EX      DE,HL                   ; DE := HEAD PTR VAL, HL := ADR OF HEAD PTR
+        LD      (HL),E                  ; SAVE UPDATED HEAD PTR
+        INC     HL
+        LD      (HL),D
+        ; CHECK FOR MORE PENDING...
+        IN      A,(C)                   ; GET STATUS
+        RRA                             ; READY BIT TO CF
+        JR      C,ACIA_INTRCV1          ; IF SET, DO SOME MORE
 ACIA_INTRCV4:
-	OR	$FF			; NZ SET TO INDICATE INT HANDLED
-	RET				; AND RETURN
+        OR      $FF                     ; NZ SET TO INDICATE INT HANDLED
+        RET                             ; AND RETURN
 ;
 #ENDIF
 ;
@@ -277,49 +277,49 @@ ACIA_IN:
 #ELSE
 ;
 ACIA_IN:
-	CALL	ACIA_IST		; SEE IF CHAR AVAILABLE
-	JR	Z,ACIA_IN		; LOOP UNTIL SO
-	HB_DI				; AVOID COLLISION WITH INT HANDLER
-	LD	L,(IY+6)		; SET HL TO
-	LD	H,(IY+7)		; ... START OF BUFFER STRUCT
-	LD	A,(HL)			; GET COUNT
-	DEC	A			; DECREMENT COUNT
-	LD	(HL),A			; SAVE UPDATED COUNT
-	CP	ACIA_BUFSZ / 4		; BUFFER LOW THRESHOLD
-	JR	NZ,ACIA_IN1		; IF NOT, BYPASS SETTING RTS
-	LD	C,(IY+3)		; C IS CMD/STATUS PORT ADR
-	LD	A,(ACIA_CMD)		; CONFIG BYTE W/O RTS BIT
-	OR	ACIA_RTSON		; SET RTS
-	OUT	(C),A			; DO IT
+        CALL    ACIA_IST                ; SEE IF CHAR AVAILABLE
+        JR      Z,ACIA_IN               ; LOOP UNTIL SO
+        HB_DI                           ; AVOID COLLISION WITH INT HANDLER
+        LD      L,(IY+6)                ; SET HL TO
+        LD      H,(IY+7)                ; ... START OF BUFFER STRUCT
+        LD      A,(HL)                  ; GET COUNT
+        DEC     A                       ; DECREMENT COUNT
+        LD      (HL),A                  ; SAVE UPDATED COUNT
+        CP      ACIA_BUFSZ / 4          ; BUFFER LOW THRESHOLD
+        JR      NZ,ACIA_IN1             ; IF NOT, BYPASS SETTING RTS
+        LD      C,(IY+3)                ; C IS CMD/STATUS PORT ADR
+        LD      A,(ACIA_CMD)            ; CONFIG BYTE W/O RTS BIT
+        OR      ACIA_RTSON              ; SET RTS
+        OUT     (C),A                   ; DO IT
 ACIA_IN1:
-	INC	HL
-	INC	HL
-	INC	HL			; HL NOW HAS ADR OF TAIL PTR
-	PUSH	HL			; SAVE ADR OF TAIL PTR
-	LD	A,(HL)			; DEREFERENCE HL
-	INC	HL
-	LD	H,(HL)
-	LD	L,A			; HL IS NOW ACTUAL TAIL PTR
-	LD	C,(HL)			; C := CHAR TO BE RETURNED
-	INC	HL			; BUMP TAIL PTR
-	POP	DE			; RECOVER ADR OF TAIL PTR
-	LD	A,L			; GET LOW BYTE OF TAIL PTR
-	SUB	ACIA_BUFSZ+2		; SUBTRACT SIZE OF BUFFER AND POINTER
-	CP	E			; IF EQUAL TO START, TAIL PTR IS PAST BUF END
-	JR	NZ,ACIA_IN2		; IF NOT, BYPASS
-	LD	H,D			; SET HL TO
-	LD	L,E			; ... TAIL PTR ADR
-	INC	HL			; BUMP PAST TAIL PTR
-	INC	HL			; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
+        INC     HL
+        INC     HL
+        INC     HL                      ; HL NOW HAS ADR OF TAIL PTR
+        PUSH    HL                      ; SAVE ADR OF TAIL PTR
+        LD      A,(HL)                  ; DEREFERENCE HL
+        INC     HL
+        LD      H,(HL)
+        LD      L,A                     ; HL IS NOW ACTUAL TAIL PTR
+        LD      C,(HL)                  ; C := CHAR TO BE RETURNED
+        INC     HL                      ; BUMP TAIL PTR
+        POP     DE                      ; RECOVER ADR OF TAIL PTR
+        LD      A,L                     ; GET LOW BYTE OF TAIL PTR
+        SUB     ACIA_BUFSZ+2            ; SUBTRACT SIZE OF BUFFER AND POINTER
+        CP      E                       ; IF EQUAL TO START, TAIL PTR IS PAST BUF END
+        JR      NZ,ACIA_IN2             ; IF NOT, BYPASS
+        LD      H,D                     ; SET HL TO
+        LD      L,E                     ; ... TAIL PTR ADR
+        INC     HL                      ; BUMP PAST TAIL PTR
+        INC     HL                      ; ... SO HL NOW HAS ADR OF ACTUAL BUFFER START
 ACIA_IN2:
-	EX	DE,HL			; DE := TAIL PTR VAL, HL := ADR OF TAIL PTR
-	LD	(HL),E			; SAVE UPDATED TAIL PTR
-	INC	HL
-	LD	(HL),D
-	LD	E,C			; MOVE CHAR TO RETURN TO E
-	HB_EI				; INTERRUPTS OK AGAIN
-	XOR	A			; SIGNAL SUCCESS
-	RET				; AND DONE
+        EX      DE,HL                   ; DE := TAIL PTR VAL, HL := ADR OF TAIL PTR
+        LD      (HL),E                  ; SAVE UPDATED TAIL PTR
+        INC     HL
+        LD      (HL),D
+        LD      E,C                     ; MOVE CHAR TO RETURN TO E
+        HB_EI                           ; INTERRUPTS OK AGAIN
+        XOR     A                       ; SIGNAL SUCCESS
+        RET                             ; AND DONE
 ;
 #ENDIF
 ;
@@ -350,12 +350,12 @@ ACIA_IST:
 #ELSE
 ;
 ACIA_IST:
-	LD	L,(IY+6)		; GET ADDRESS
-	LD	H,(IY+7)		; ... OF RECEIVE BUFFER
-	LD	A,(HL)			; BUFFER UTILIZATION COUNT
-	OR	A			; SET FLAGS
-	JP	Z,CIO_IDLE		; NOT READY, RETURN VIA IDLE PROCESSING
-	RET
+        LD      L,(IY+6)                ; GET ADDRESS
+        LD      H,(IY+7)                ; ... OF RECEIVE BUFFER
+        LD      A,(HL)                  ; BUFFER UTILIZATION COUNT
+        OR      A                       ; SET FLAGS
+        JP      Z,CIO_IDLE              ; NOT READY, RETURN VIA IDLE PROCESSING
+        RET
 ;
 #ENDIF
 ;
@@ -384,150 +384,150 @@ ACIA_INITDEV:
 ACIA_INITDEVX:
 ;
 #IF (ACIADEBUG)
-	CALL	NEWLINE
-	PRTS("ACIA$")
-	LD	A,(IY+2)
-	CALL	PRTDECB
-	CALL	COUT
-	CALL	PC_COLON
+        CALL    NEWLINE
+        PRTS("ACIA$")
+        LD      A,(IY+2)
+        CALL    PRTDECB
+        CALL    COUT
+        CALL    PC_COLON
 #ENDIF
 ;
-	; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
-	LD	A,D			; TEST DE FOR
-	AND	E			; ... VALUE OF -1
-	INC	A			; ... SO Z SET IF -1
-	JR	NZ,ACIA_INITDEV1	; IF DE == -1, REINIT CURRENT CONFIG
+        ; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)
+        LD      A,D                     ; TEST DE FOR
+        AND     E                       ; ... VALUE OF -1
+        INC     A                       ; ... SO Z SET IF -1
+        JR      NZ,ACIA_INITDEV1        ; IF DE == -1, REINIT CURRENT CONFIG
 ;
-	; LOAD EXISTING CONFIG TO REINIT
-	LD	E,(IY+4)		; LOW BYTE
-	LD	D,(IY+5)		; HIGH BYTE	
+        ; LOAD EXISTING CONFIG TO REINIT
+        LD      E,(IY+4)                ; LOW BYTE
+        LD      D,(IY+5)                ; HIGH BYTE        
 ;
 ACIA_INITDEV1:
 ;
 #IF (ACIADEBUG)
-	PUSH	DE
-	POP	BC
-	PRTS(" CFG=$")
-	CALL	PRTHEXWORD
+        PUSH    DE
+        POP     BC
+        PRTS(" CFG=$")
+        CALL    PRTHEXWORD
 #ENDIF
 ;
-	LD	A,E			; GET CONFIG LSB
-	AND	$E0			; CHECK FOR DTR, XON, PARITY=MARK/SPACE
-	JR	NZ,ACIA_INITFAIL	; IF ANY BIT SET, FAIL, NOT SUPPORTED
+        LD      A,E                     ; GET CONFIG LSB
+        AND     $E0                     ; CHECK FOR DTR, XON, PARITY=MARK/SPACE
+        JR      NZ,ACIA_INITFAIL        ; IF ANY BIT SET, FAIL, NOT SUPPORTED
 ;
-	LD	A,D			; GET CONFIG MSB
-	AND	$1F			; ISOLATE ENCODED BAUD RATE
+        LD      A,D                     ; GET CONFIG MSB
+        AND     $1F                     ; ISOLATE ENCODED BAUD RATE
 ;
 #IF (ACIADEBUG)
-	PRTS(" ENC=$")
-	CALL	PRTHEXBYTE
+        PRTS(" ENC=$")
+        CALL    PRTHEXBYTE
 #ENDIF
 ;
-	; BAUD RATE
-	PUSH	DE			; SAVE REQUESTED CONFIG
-	LD	L,(IY+10)		; LOAD CLK FREQ
-	LD	H,(IY+11)		; ... INTO DE:HL
-	LD	E,(IY+12)		; ... "
-	LD	D,(IY+13)		; ... "
-	LD	C,75			; BAUD RATE ENCODING CONSTANT
-	CALL	ENCODE			; C = TEST BAUD RATE (ENCODED) = BAUDTST
-	POP	DE			; GET REQ CONFIG BACK, D = BAUDREQ
-;
-	; BIT 4 (DIV 3) OF BAUDREQ AND BAUDTST MUST MATCH!
-	LD	A,C			; A = BAUDTST
-	XOR	D			; XOR WITH BAUDREQ
-	BIT	4,A			; DO BIT 4 VALS MATCH?
-	JR	NZ,ACIA_INITFAIL	; IF NOT, BAIL OUT
-;	
-	LD	A,C			; BAUDTST TO A
-	AND	$0F			; ISOLATE DIV 2 BAUD BITS
-	LD	C,A			; C = BAUDTST
-;	
-	LD	A,D			; MSB W/ BAUD RATE TO A
-	AND	$0F			; ISOLATE DIV 2 BAUD BITS
-	LD	L,A			; L = BAUDREQ
-;	
-	LD	A,C			; A = BAUDTST
-	LD	B,%00000000		; ACIA VAL FOR DIV 1
-	CP	L			; BAUDTST = BAUDREQ?
-	JR	Z,ACIA_INITBROK		; IF MATCH, WE ARE DONE
-;	
-	SUB	4			; DIVIDE BY 16 (NOW DIV 16 TOT)
-	JR	C,ACIA_INITFAIL		; FAIL IF UNDERFLOW
-	LD	B,%00000001		; ACIA VAL FOR DIV 16
-	CP	L			; BAUDTST = BAUDREQ?
-	JR	Z,ACIA_INITBROK		; IF MATCH, WE ARE DONE
-;	
-	SUB	2			; DIVIDE BY 4 (NOW DIV 64 TOT)
-	JR	C,ACIA_INITFAIL		; FAIL IF UNDERFLOW
-	LD	B,%00000010		; ACIA R4 VAL FOR DIV 32
-	CP	L			; BAUDTST = BAUDREQ?
-	JR	Z,ACIA_INITBROK		; IF MATCH, WE ARE DONE
+        ; BAUD RATE
+        PUSH    DE                      ; SAVE REQUESTED CONFIG
+        LD      L,(IY+10)               ; LOAD CLK FREQ
+        LD      H,(IY+11)               ; ... INTO DE:HL
+        LD      E,(IY+12)               ; ... "
+        LD      D,(IY+13)               ; ... "
+        LD      C,75                    ; BAUD RATE ENCODING CONSTANT
+        CALL    ENCODE                  ; C = TEST BAUD RATE (ENCODED) = BAUDTST
+        POP     DE                      ; GET REQ CONFIG BACK, D = BAUDREQ
+;
+        ; BIT 4 (DIV 3) OF BAUDREQ AND BAUDTST MUST MATCH!
+        LD      A,C                     ; A = BAUDTST
+        XOR     D                       ; XOR WITH BAUDREQ
+        BIT     4,A                     ; DO BIT 4 VALS MATCH?
+        JR      NZ,ACIA_INITFAIL        ; IF NOT, BAIL OUT
+;        
+        LD      A,C                     ; BAUDTST TO A
+        AND     $0F                     ; ISOLATE DIV 2 BAUD BITS
+        LD      C,A                     ; C = BAUDTST
+;        
+        LD      A,D                     ; MSB W/ BAUD RATE TO A
+        AND     $0F                     ; ISOLATE DIV 2 BAUD BITS
+        LD      L,A                     ; L = BAUDREQ
+;        
+        LD      A,C                     ; A = BAUDTST
+        LD      B,%00000000             ; ACIA VAL FOR DIV 1
+        CP      L                       ; BAUDTST = BAUDREQ?
+        JR      Z,ACIA_INITBROK         ; IF MATCH, WE ARE DONE
+;        
+        SUB     4                       ; DIVIDE BY 16 (NOW DIV 16 TOT)
+        JR      C,ACIA_INITFAIL         ; FAIL IF UNDERFLOW
+        LD      B,%00000001             ; ACIA VAL FOR DIV 16
+        CP      L                       ; BAUDTST = BAUDREQ?
+        JR      Z,ACIA_INITBROK         ; IF MATCH, WE ARE DONE
+;        
+        SUB     2                       ; DIVIDE BY 4 (NOW DIV 64 TOT)
+        JR      C,ACIA_INITFAIL         ; FAIL IF UNDERFLOW
+        LD      B,%00000010             ; ACIA R4 VAL FOR DIV 32
+        CP      L                       ; BAUDTST = BAUDREQ?
+        JR      Z,ACIA_INITBROK         ; IF MATCH, WE ARE DONE
 ;
 ACIA_INITFAIL:
 ;
 #IF (ACIADEBUG)
-	PRTS(" BAD CFG$")	
+        PRTS(" BAD CFG$")        
 #ENDIF
 ;
-	OR	$FF
-	RET				; INVALID CONFIG
-;	
+        OR      $FF
+        RET                             ; INVALID CONFIG
+;        
 ACIA_INITBROK:
-	; REG B HAS WORKING CONFIG VALUE W/ BAUD RATE BITS
-	LD	C,B			; WORKING VAL TO C
-	LD	A,E			; LSB OF INCOMING CONFIG
-	AND	%00111111		; ISOLATE LOW 6 BITS TO COMPARE
-	LD	B,8			; WORD SELECT TABLE SIZE
-	LD	HL,ACIA_WSTBL		; POINT TO TABLE
+        ; REG B HAS WORKING CONFIG VALUE W/ BAUD RATE BITS
+        LD      C,B                     ; WORKING VAL TO C
+        LD      A,E                     ; LSB OF INCOMING CONFIG
+        AND     %00111111               ; ISOLATE LOW 6 BITS TO COMPARE
+        LD      B,8                     ; WORD SELECT TABLE SIZE
+        LD      HL,ACIA_WSTBL           ; POINT TO TABLE
 ACIA_INITWS:
-	CP	(HL)			; MATCH?
-	JR	Z,ACIA_INITWS2		; IF SO, REG B HAS ACIA VAL + 1
-	INC	HL			; NEXT ENTRY
-	DJNZ	ACIA_INITWS		; KEEP CHECKING TILL DONE
-	JR	ACIA_INITFAIL		; FAIL IF NO MATCH
-	
+        CP      (HL)                    ; MATCH?
+        JR      Z,ACIA_INITWS2          ; IF SO, REG B HAS ACIA VAL + 1
+        INC     HL                      ; NEXT ENTRY
+        DJNZ    ACIA_INITWS             ; KEEP CHECKING TILL DONE
+        JR      ACIA_INITFAIL           ; FAIL IF NO MATCH
+        
 ACIA_WSTBL:
-	.DB	%00001011		; 8/O/1
-	.DB	%00011011		; 8/E/1
-	.DB	%00000011		; 8/N/1
-	.DB	%00000111		; 8/N/2
-	.DB	%00001010		; 7/O/1
-	.DB	%00011010		; 7/E/1
-	.DB	%00001110		; 7/O/2
-	.DB	%00011110		; 7/E/2
+        .DB     %00001011               ; 8/O/1
+        .DB     %00011011               ; 8/E/1
+        .DB     %00000011               ; 8/N/1
+        .DB     %00000111               ; 8/N/2
+        .DB     %00001010               ; 7/O/1
+        .DB     %00011010               ; 7/E/1
+        .DB     %00001110               ; 7/O/2
+        .DB     %00011110               ; 7/E/2
 
 ACIA_INITWS2:
-	LD	A,B			; PUT FANAL VALUE IN A
-	DEC	A			; ZERO INDEX ADJUSTMENT
-	RLA				; MOVE BITS TO
-	RLA				; ... PROPER LOCATION
-	OR	C			; COMBINE WITH WORKING VALUE
-	JR	ACIA_INITGO
+        LD      A,B                     ; PUT FANAL VALUE IN A
+        DEC     A                       ; ZERO INDEX ADJUSTMENT
+        RLA                             ; MOVE BITS TO
+        RLA                             ; ... PROPER LOCATION
+        OR      C                       ; COMBINE WITH WORKING VALUE
+        JR      ACIA_INITGO
 ;
 ACIA_INITSAFE:
-	LD	A,%00010110		; DEFAULT CONFIG
+        LD      A,%00010110             ; DEFAULT CONFIG
 ;
 ACIA_INITGO:
 ;
 #IF (INTMODE > 0)
-	OR	%10000000		; ENABLE RCV INT
+        OR      %10000000               ; ENABLE RCV INT
 #ENDIF
 ;
-	LD	(ACIA_CMD),A		; SAVE SHADOW REGISTER
+        LD      (ACIA_CMD),A            ; SAVE SHADOW REGISTER
 ;
 #IF (ACIADEBUG)
-	PRTS(" CMD=$")
-	CALL	PRTHEXBYTE
-	LD	DE,65
-	CALL	VDELAY			; WAIT FOR FINAL CHAR TO SEND
+        PRTS(" CMD=$")
+        CALL    PRTHEXBYTE
+        LD      DE,65
+        CALL    VDELAY                  ; WAIT FOR FINAL CHAR TO SEND
 #ENDIF
 ;
         ; PROGRAM THE ACIA CHIP
         LD      C,(IY+3)                ; COMMAND PORT
         LD      A,$FF                   ; MASTER RESET
         OUT     (C),A                   ; DO IT
-	LD	A,(ACIA_CMD)		; RESTORE CONFIG VALUE
+        LD      A,(ACIA_CMD)            ; RESTORE CONFIG VALUE
         OUT     (C),A                   ; DO IT
 ;
 #IF (INTMODE > 0)
@@ -583,9 +583,9 @@ ACIA_DEVICE:
 ; AND COMPACT FLASH MODULES DURING DETECTION PROBES.
 ;
 ACIA_DETECT:
-	LD	A,(IY+3)		; BASE PORT ADDRESS
-	ADD	A,$20			; OFFSET (SEE ABOVE)
-	LD	C,A			; PUT IN C FOR I/O
+        LD      A,(IY+3)                ; BASE PORT ADDRESS
+        ADD     A,$20                   ; OFFSET (SEE ABOVE)
+        LD      C,A                     ; PUT IN C FOR I/O
         CALL    ACIA_DETECT2            ; CHECK IT
         JR      Z,ACIA_DETECT1          ; FOUND IT, RECORD IT
         LD      A,ACIA_NONE             ; NOTHING FOUND
@@ -659,7 +659,7 @@ ACIA_STR_ACIA   .DB     "ACIA$"
 ; WORKING VARIABLES
 ;
 ACIA_DEV        .DB     0               ; DEVICE NUM USED DURING INIT
-ACIA_CMD	.DB	0		; COMMAND PORT SHADOW REGISTER
+ACIA_CMD        .DB     0               ; COMMAND PORT SHADOW REGISTER
 ;
 #IF (INTMODE == 0)
 ;
@@ -704,11 +704,11 @@ ACIA0_CFG:
         .DB     ACIA0BASE               ; BASE PORT
         .DW     ACIA0CFG                ; LINE CONFIGURATION
         .DW     ACIA0_RCVBUF            ; POINTER TO RCV BUFFER STRUCT
-	.DW     ACIA0_INT		; INT HANDLER POINTER
-	.DW	(ACIA0CLK / ACIA0DIV) & $FFFF	; CLOCK FREQ AS
-	.DW	(ACIA0CLK / ACIA0DIV) >> 16	; ... DWORD VALUE
+        .DW     ACIA0_INT                ; INT HANDLER POINTER
+        .DW     (ACIA0CLK / ACIA0DIV) & $FFFF   ; CLOCK FREQ AS
+        .DW     (ACIA0CLK / ACIA0DIV) >> 16     ; ... DWORD VALUE
 ;
-ACIA_CFGSIZ	.EQU	$ - ACIA_CFG	; SIZE OF ONE CFG TABLE ENTRY
+ACIA_CFGSIZ     .EQU    $ - ACIA_CFG    ; SIZE OF ONE CFG TABLE ENTRY
 ;
 #IF (ACIACNT >= 2)
 ;
@@ -720,10 +720,10 @@ ACIA1_CFG:
         .DB     ACIA1BASE               ; BASE PORT
         .DW     ACIA1CFG                ; LINE CONFIGURATION
         .DW     ACIA1_RCVBUF            ; POINTER TO RCV BUFFER STRUCT
-	.DW     ACIA1_INT		; INT HANDLER POINTER
-	.DW	(ACIA1CLK / ACIA1DIV) & $FFFF	; CLOCK FREQ AS
-	.DW	(ACIA1CLK / ACIA1DIV) >> 16	; ... DWORD VALUE
+        .DW     ACIA1_INT                ; INT HANDLER POINTER
+        .DW     (ACIA1CLK / ACIA1DIV) & $FFFF   ; CLOCK FREQ AS
+        .DW     (ACIA1CLK / ACIA1DIV) >> 16     ; ... DWORD VALUE
 ;
 #ENDIF
 ;
-ACIA_CFGCNT	.EQU    ($ - ACIA_CFG) / ACIA_CFGSIZ
+ACIA_CFGCNT     .EQU    ($ - ACIA_CFG) / ACIA_CFGSIZ

From 33d2f590551e9feccd8684f31440b9ade4cb1b16 Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 9 Feb 2021 17:42:13 +1100
Subject: [PATCH 10/16] fix divergence from wwarthen-dev

---
 .github/workflows/commit.yml | 38 ++++++++++++++++++++++++++++++++----
 1 file changed, 34 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/commit.yml b/.github/workflows/commit.yml
index cb919bdf..84e9fcc3 100644
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -9,7 +9,7 @@ on:
       - v*
 
 jobs:
-  build:
+  buildLinux:
 
     runs-on: ubuntu-latest
 
@@ -17,7 +17,7 @@ jobs:
       - uses: rlespinasse/github-slug-action@v3.x
         
       - uses: actions/checkout@v2
-          
+
       - name: Build
         run: |
           export TZ='America/Los_Angeles'
@@ -25,9 +25,39 @@ jobs:
           make
           make clean
           rm -rf .git*
-        
+
+      - name: List Output	
+        run: |	
+          cd Binary	
+          ls -l	
+          find -type f -exec md5sum '{}' \;	
+      	
+      - name: Upload Artifact	
+        uses: actions/upload-artifact@v1	
+        with:	
+          name: RomWBW_Linux-${{env.GITHUB_REF_SLUG}}-${{env.GITHUB_SHA_SHORT}}	
+          path: .	
+
+  buildMacOS:	
+    runs-on: macos-latest	
+
+    steps:	
+      - uses: actions/checkout@v2	
+
+      - name: Build	
+        run: |	
+          export TZ='America/Los_Angeles'	
+          make	
+          make clean	
+          rm -rf .git*	
+      - name: List Output	
+        run: |	
+          cd Binary	
+          ls -l	
+          find . -type f -exec md5 -r -- '{}' +;
+
       - name: Upload Artifact
         uses: actions/upload-artifact@v1
         with:
-          name: RomWBW-${{env.GITHUB_REF_SLUG}}-${{env.GITHUB_SHA_SHORT}}
+          name: RomWBW_MacOS
           path: .

From 74d25aa2dfbc75ab48e6c86bedc1c5dcb3e69ad3 Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 9 Feb 2021 17:51:16 +1100
Subject: [PATCH 11/16] fix divergence from wwarthen-dev

---
 .github/workflows/commit.yml | 32 +++++++++++++++++---------------
 Source/Doc/GettingStarted.md |  1 -
 2 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/.github/workflows/commit.yml b/.github/workflows/commit.yml
index 84e9fcc3..bd44f3b0 100644
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -18,20 +18,20 @@ jobs:
         
       - uses: actions/checkout@v2
 
-      - name: Build
-        run: |
-          export TZ='America/Los_Angeles'
-          sudo apt-get install libncurses-dev
-          make
-          make clean
-          rm -rf .git*
+      - name: Build	
+        run: |	
+          export TZ='America/Los_Angeles'	
+          sudo apt-get install libncurses-dev	
+          make	
+          make clean	
+          rm -rf .git*	
 
       - name: List Output	
         run: |	
           cd Binary	
           ls -l	
           find -type f -exec md5sum '{}' \;	
-      	
+
       - name: Upload Artifact	
         uses: actions/upload-artifact@v1	
         with:	
@@ -42,14 +42,16 @@ jobs:
     runs-on: macos-latest	
 
     steps:	
-      - uses: actions/checkout@v2	
+      - uses: actions/checkout@v2
+
+      - name: Build
+        run: |
+          export TZ='America/Los_Angeles'
+          sudo apt-get install libncurses-dev
+          make
+          make clean
+          rm -rf .git*
 
-      - name: Build	
-        run: |	
-          export TZ='America/Los_Angeles'	
-          make	
-          make clean	
-          rm -rf .git*	
       - name: List Output	
         run: |	
           cd Binary	
diff --git a/Source/Doc/GettingStarted.md b/Source/Doc/GettingStarted.md
index 78adf0cb..35337ab5 100644
--- a/Source/Doc/GettingStarted.md
+++ b/Source/Doc/GettingStarted.md
@@ -153,7 +153,6 @@ the appropriate ROM image for your hardware.
 | RC Z180\*      | RCZ180_ext.rom           | 115200      | RC2014 w/ Z180 CPU & 512K banked RAM/ROM module  |
 | RC Z180\*      | RCZ180_nat.rom           | 115200      | RC2014 w/ Z180 CPU & 512K native RAM/ROM module  |
 | Easy Z80       | EZZ80_std.rom            | 115200      | Sergey Kiselev's Easy Z80                        |
-| Tiny Z80       | EZZ80_tz80.rom           | 115200      | Sergey Kiselev's Tiny Z80                        |
 | SC126          | SCZ180_126.rom           | 115200      | Stephen Cousin's SC126 Z180                      |
 | SC130          | SCZ180_130.rom           | 115200      | Stephen Cousin's SC130 Z180                      |
 | SC131          | SCZ180_131.rom           | 115200      | Stephen Cousin's SC131 Z180                      |

From 08b8a17d302340840fd094a4de3727c59696fd14 Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 9 Feb 2021 17:54:56 +1100
Subject: [PATCH 12/16] fix more divergence from wwarthen-dev

---
 .github/workflows/commit.yml | 48 ++++++++++++++++++------------------
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/.github/workflows/commit.yml b/.github/workflows/commit.yml
index bd44f3b0..6fba9cd4 100644
--- a/.github/workflows/commit.yml
+++ b/.github/workflows/commit.yml
@@ -18,30 +18,30 @@ jobs:
         
       - uses: actions/checkout@v2
 
-      - name: Build	
-        run: |	
-          export TZ='America/Los_Angeles'	
-          sudo apt-get install libncurses-dev	
-          make	
-          make clean	
-          rm -rf .git*	
+      - name: Build
+        run: |
+          export TZ='America/Los_Angeles'
+          sudo apt-get install libncurses-dev
+          make
+          make clean
+          rm -rf .git*
 
-      - name: List Output	
-        run: |	
-          cd Binary	
-          ls -l	
-          find -type f -exec md5sum '{}' \;	
+      - name: List Output
+        run: |
+          cd Binary
+          ls -l
+          find -type f -exec md5sum '{}' \;
 
-      - name: Upload Artifact	
-        uses: actions/upload-artifact@v1	
-        with:	
-          name: RomWBW_Linux-${{env.GITHUB_REF_SLUG}}-${{env.GITHUB_SHA_SHORT}}	
-          path: .	
+      - name: Upload Artifact
+        uses: actions/upload-artifact@v1
+        with:
+          name: RomWBW_Linux-${{env.GITHUB_REF_SLUG}}-${{env.GITHUB_SHA_SHORT}}
+          path: .
 
-  buildMacOS:	
-    runs-on: macos-latest	
+  buildMacOS:
+    runs-on: macos-latest
 
-    steps:	
+    steps:
       - uses: actions/checkout@v2
 
       - name: Build
@@ -52,10 +52,10 @@ jobs:
           make clean
           rm -rf .git*
 
-      - name: List Output	
-        run: |	
-          cd Binary	
-          ls -l	
+      - name: List Output
+        run: |
+          cd Binary
+          ls -l
           find . -type f -exec md5 -r -- '{}' +;
 
       - name: Upload Artifact

From b41f865c1d9471eb53bc9c8d23101d15f7f1681b Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 9 Feb 2021 17:59:54 +1100
Subject: [PATCH 13/16] acia.asm whitespace

---
 Source/HBIOS/acia.asm | 52 +++++++++++++++++++++----------------------
 1 file changed, 26 insertions(+), 26 deletions(-)

diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm
index c1053dca..d65fa763 100644
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -115,12 +115,12 @@ ACIA_INITUNIT:
         CALL    HB_ADDIM1               ; ADD TO IM1 CALL LIST
 #ENDIF
 ;
-	; IT IS EASY TO SPECIFY A SERIAL CONFIG THAT CANNOT BE IMPLEMENTED
-	; DUE TO THE CONSTRAINTS OF THE ACIA.  HERE WE FORCE A GENERIC
-	; FAILSAFE CONFIG ONTO THE CHANNEL.  IF THE SUBSEQUENT "REAL"
-	; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT
-	; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG.
-	CALL	ACIA_INITSAFE
+        ; IT IS EASY TO SPECIFY A SERIAL CONFIG THAT CANNOT BE IMPLEMENTED
+        ; DUE TO THE CONSTRAINTS OF THE ACIA.  HERE WE FORCE A GENERIC
+        ; FAILSAFE CONFIG ONTO THE CHANNEL.  IF THE SUBSEQUENT "REAL"
+        ; CONFIG FAILS, AT LEAST THE CHIP WILL BE ABLE TO SPIT DATA OUT
+        ; AT A RATIONAL BAUD/DATA/PARITY/STOP CONFIG.
+        CALL    ACIA_INITSAFE
 ;
         ; SET DEFAULT CONFIG
         LD      DE,-1                   ; LEAVE CONFIG ALONE
@@ -155,7 +155,7 @@ ACIA_INIT1:
 ;
 ACIA0_INT:
 ACIA1_INT:
-	CALL	PANIC			; NO RETURN
+        CALL    PANIC                   ; NO RETURN
 ;
 #ENDIF
 ;
@@ -393,7 +393,7 @@ ACIA_INITDEVX:
         LD      D,(IY+5)                ; HIGH BYTE        
 ;
 ACIA_INITDEV1:
-	LD	(ACIA_NEWCFG),DE	; SAVE NEW CONFIG
+        LD      (ACIA_NEWCFG),DE        ; SAVE NEW CONFIG
 ;
 #IF (ACIADEBUG)
         PUSH    DE
@@ -489,18 +489,18 @@ ACIA_WSTBL:
         .DB     %00011110               ; 7/E/2
 
 ACIA_INITWS2:
-	LD	A,B			; PUT FANAL VALUE IN A
-	DEC	A			; ZERO INDEX ADJUSTMENT
-	RLA				; MOVE BITS TO
-	RLA				; ... PROPER LOCATION
-	OR	C			; COMBINE WITH WORKING VALUE
+        LD      A,B                     ; PUT FANAL VALUE IN A
+        DEC     A                       ; ZERO INDEX ADJUSTMENT
+        RLA                             ; MOVE BITS TO
+        RLA                             ; ... PROPER LOCATION
+        OR      C                       ; COMBINE WITH WORKING VALUE
 ;
-	; SAVE CONFIG PERMANENTLY NOW
-	LD	DE,(ACIA_NEWCFG)		; GET NEW CONFIG BACK
-	LD	(IY+4),E		; SAVE LOW WORD
-	LD	(IY+5),D		; SAVE HI WORD
+        ; SAVE CONFIG PERMANENTLY NOW
+        LD      DE,(ACIA_NEWCFG)        ; GET NEW CONFIG BACK
+        LD      (IY+4),E                ; SAVE LOW WORD
+        LD      (IY+5),D                ; SAVE HI WORD
 ;
-	JR	ACIA_INITGO
+        JR      ACIA_INITGO
 ;
 ACIA_INITSAFE:
         LD      A,%00010110             ; DEFAULT CONFIG
@@ -508,7 +508,7 @@ ACIA_INITSAFE:
 ACIA_INITGO:
 ;
 #IF (INTMODE == 1)
-	OR	%10000000		; ENABLE RCV INT
+        OR      %10000000               ; ENABLE RCV INT
 #ENDIF
 ;
         LD      (ACIA_CMD),A            ; SAVE SHADOW REGISTER
@@ -568,16 +568,16 @@ ACIA_DEVICE:
         LD      D,CIODEV_ACIA           ; D := DEVICE TYPE
         LD      E,(IY)                  ; E := PHYSICAL UNIT
         LD      C,$00                   ; C := DEVICE TYPE, 0x00 IS RS-232
-	LD	H,0			; H := 0, DRIVER HAS NO MODES
-	LD	L,(IY+3)		; L := BASE I/O ADDRESS
+        LD      H,0                     ; H := 0, DRIVER HAS NO MODES
+        LD      L,(IY+3)                ; L := BASE I/O ADDRESS
         XOR     A                       ; SIGNAL SUCCESS
         RET
 ;
 ; ACIA DETECTION ROUTINE
 ;
 ACIA_DETECT:
-	LD	A,(IY+3)		; BASE PORT ADDRESS
-	LD	C,A			; PUT IN C FOR I/O
+        LD      A,(IY+3)                ; BASE PORT ADDRESS
+        LD      C,A                     ; PUT IN C FOR I/O
         CALL    ACIA_DETECT2            ; CHECK IT
         JR      Z,ACIA_DETECT1          ; FOUND IT, RECORD IT
         LD      A,ACIA_NONE             ; NOTHING FOUND
@@ -597,7 +597,7 @@ ACIA_DETECT2:
         RET     NZ                      ; RETURN IF NOT ZERO
         LD      A,$02                   ; CLEAR MASTER RESET
         OUT     (C),A                   ; DO IT
-	IN	A,(C)			; GET STATUS AGAIN
+        IN      A,(C)                   ; GET STATUS AGAIN
         ; CHECK FOR EXPECTED BITS:
         ;   TDRE=1, DCD & CTS = 0
         AND     %00001110               ; BIT MASK FOR "STABLE" BITS
@@ -652,8 +652,8 @@ ACIA_STR_ACIA   .DB     "ACIA$"
 ; WORKING VARIABLES
 ;
 ACIA_DEV        .DB     0               ; DEVICE NUM USED DURING INIT
-ACIA_CMD	.DB	0		; COMMAND PORT SHADOW REGISTER
-ACIA_NEWCFG	.DW	0		; TEMP STORE FOR NEW CFG
+ACIA_CMD        .DB     0               ; COMMAND PORT SHADOW REGISTER
+ACIA_NEWCFG     .DW     0               ; TEMP STORE FOR NEW CFG
 ;
 #IF (INTMODE != 1)
 ;

From 36ba566c954e558f7c4e61678215b4b955c37207 Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 9 Feb 2021 18:04:02 +1100
Subject: [PATCH 14/16] acia - assert RTS fix

---
 Source/HBIOS/acia.asm | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm
index d65fa763..2c440023 100644
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -54,7 +54,7 @@ ACIA_BUFSZ      .EQU    32              ; RECEIVE RING BUFFER SIZE
 ACIA_NONE       .EQU    0
 ACIA_ACIA       .EQU    1
 ;
-ACIA_RTSON      .EQU    %00000000       ; BIT MASK TO ASSERT RTS
+ACIA_RTSON      .EQU    %10111111       ; BIT MASK TO ASSERT RTS
 ACIA_RTSOFF     .EQU    %01000000       ; BIT MASK TO DEASSERT RTS
 ;
 ;
@@ -199,7 +199,7 @@ ACIA_INTRCV1:
         CP      ACIA_BUFSZ / 2          ; BUFFER GETTING FULL?
         JR      NZ,ACIA_INTRCV2         ; IF NOT, BYPASS CLEARING RTS
         LD      A,(ACIA_CMD)            ; CONFIG BYTE W/O RTS BIT
-        OR      ACIA_RTSOFF             ; CLEAR RTS
+        OR      ACIA_RTSOFF             ; DEASSERT RTS
         OUT     (C),A                   ; DO IT
 ACIA_INTRCV2:
         INC     HL                      ; HL NOW HAS ADR OF HEAD PTR
@@ -279,7 +279,7 @@ ACIA_IN:
         JR      NZ,ACIA_IN1             ; IF NOT, BYPASS SETTING RTS
         LD      C,(IY+3)                ; C IS CMD/STATUS PORT ADR
         LD      A,(ACIA_CMD)            ; CONFIG BYTE W/O RTS BIT
-        OR      ACIA_RTSON              ; SET RTS
+        AND     ACIA_RTSON              ; ASSERT RTS
         OUT     (C),A                   ; DO IT
 ACIA_IN1:
         INC     HL

From 38531bc9831bbf3300bcfb134d164cfa7461d239 Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Tue, 9 Feb 2021 18:11:40 +1100
Subject: [PATCH 15/16] acia - receive test optimisation

---
 Source/HBIOS/acia.asm | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm
index 2c440023..1dc69bdd 100644
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -180,8 +180,8 @@ ACIA_INTRCV:
         ; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
         LD      C,(IY+3)                ; CMD/STAT PORT TO C
         IN      A,(C)                   ; GET STATUS
-        AND     $01                     ; ISOLATE RECEIVE READY BIT
-        RET     Z                       ; NOTHING AVAILABLE ON CURRENT CHANNEL
+        RRA                             ; READY BIT TO CF
+        RET     NC                      ; NOTHING AVAILABLE ON CURRENT CHANNEL
 ;
 ACIA_INTRCV1:
         ; RECEIVE CHARACTER INTO BUFFER

From f6ecaa7cb51570e82355028ffa6f3e55fd09bd7a Mon Sep 17 00:00:00 2001
From: Phillip Stevens <phillip.stevens@gmail.com>
Date: Wed, 10 Feb 2021 02:58:57 +1100
Subject: [PATCH 16/16] acia - make reset consistent / correct

---
 Source/HBIOS/acia.asm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Source/HBIOS/acia.asm b/Source/HBIOS/acia.asm
index 1dc69bdd..f670298c 100644
--- a/Source/HBIOS/acia.asm
+++ b/Source/HBIOS/acia.asm
@@ -522,7 +522,7 @@ ACIA_INITGO:
 ;
         ; PROGRAM THE ACIA CHIP
         LD      C,(IY+3)                ; COMMAND PORT
-        LD      A,$FF                   ; MASTER RESET
+        LD      A,$03                   ; MASTER RESET
         OUT     (C),A                   ; DO IT
         LD      A,(ACIA_CMD)            ; RESTORE CONFIG VALUE
         OUT     (C),A                   ; DO IT