diff --git a/Source/HBIOS/uart.asm b/Source/HBIOS/uart.asm
index 8b7acec0..06df7e96 100644
--- a/Source/HBIOS/uart.asm
+++ b/Source/HBIOS/uart.asm
@@ -542,7 +542,10 @@ UART_INITDEV1A:
 	; SETUP FCR, BIT 5 IS KEPT ON EVEN THOUGH IT IS PROBABLY
 	; IRRELEVANT BECAUSE IT ONLY APPLIES TO 750 AND DLAB IS
 	; NOW OFF, BUT DOESN'T HURT.
-	LD	A,%00100111		; FIFO ENABLE & RESET
+	; BITS 7-6 DEFINE THE FIFO RECEIVE INTERRUPT THRESHOLD. WE
+	; USE A VALUE 0F %01 FOR THESE BITS WHICH REDUCES THE
+	; FREQUENCY OF INTERRUPTS DURING HEAVY RECEIVE OPERATIONS.
+	LD	A,%01100111		; FIFO ENABLE & RESET
 	UART_OUTP(UART_FCR)		; DO IT
 ;
 	; SETUP LCR FROM SECOND CONFIG BYTE
@@ -569,6 +572,7 @@ UART_INITDEV1B:
 ;
 	; TEST FOR EFR CAPABLE CHIPS
 	LD	A,(IY+1)		; GET UART TYPE
+	AND	$0F			; ISOLATE LOW NIBBLE
 	CP	UART_16650		; 16650?
 	JR	Z,UART_INITDEV2		; USE EFR REGISTER
 	CP	UART_16850		; 16850?
@@ -577,6 +581,7 @@ UART_INITDEV1B:
 ;
 UART_INITDEV2:
 	; WE HAVE AN EFR CAPABLE CHIP, SET EFR REGISTER
+	; NOTE THAT AN EFR CAPABLE CHIP IMPLIES IT IS CAPABLE OF AFC!
 	UART_INP(UART_LCR)		; GET CURRENT LCR VALUE
 	PUSH	AF			; SAVE IT
 	LD	A,$BF			; VALUE TO ACCESS EFR
diff --git a/Source/ver.inc b/Source/ver.inc
index 4758c3aa..3af4b31e 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.119"
+#DEFINE BIOSVER	"3.1.1-pre.120"
diff --git a/Source/ver.lib b/Source/ver.lib
index 43784d5d..b7f6f4f1 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.119"
+	db	"3.1.1-pre.120"
 	endm