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@ -58,6 +58,7 @@ UARTCBASE .EQU $80 |
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UARTMBASE .EQU $48 |
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UART4BASE .EQU $C0 |
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UARTRBASE .EQU $A0 |
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UARTDBASE .EQU $80 |
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; |
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#IF (UARTINTS) |
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; |
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@ -557,6 +558,16 @@ UART_INITDEV1A: |
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LD A,(IY+5) ; GET CONFIG BYTE |
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AND ~$1F ; REMOVE ENCODED BAUD RATE BITS |
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OR $03 ; FORCE RTS & DTR |
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; |
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; SOME NEWER UARTS USE MCR:3 TO ACTIVATE THE INTERRUPT LINE. |
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; ALTHOUGH OTHER UARTS USE MCR:3 TO CONTROL A GPIO LINE CALLED |
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; OUT2, NO ROMWBW HARDWARE USES THIS GPIO LINE. SO, HERE, WE |
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; JUST SET MCR:3 TO ACTIVATE THE INTERRUPT LINE. NOTE THAT |
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; EVEN IF WE ARE NOT USING INTERRUPTS FOR THIS UART, THE |
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; INTERRUPT LINE MUST STILL BE ACTIVATED SO THAT IT WILL |
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; PRESENT A DEASSERTED CONDITION TO THE CPU. OTHERWISE, THE |
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; INTERRUPT LINE MAY BE LEFT FLOATING WHICH IS DEFINITELY BAD. |
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OR $08 ; ACTIVATE INT LINE |
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; |
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; THE MCR REGISTER AFE BIT WILL NORMALLY BE SET/RESET BY THE |
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; VALUE OF THE CONFIG BYTE. HOWEVER, IF THE CHIP IS NOT AFC CAPABLE |
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@ -1058,6 +1069,22 @@ UART_CFG_MFP: |
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.DW UARTCFG ; LINE CONFIGURATION |
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.DW 0 ; SHOULD NEVER NEED INT HANDLER |
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#ENDIF |
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#IF (UARTDUAL) |
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; DUAL UART CHANNEL A |
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.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) |
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.DB 0 ; UART TYPE |
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.DB UARTDBASE ; IO PORT BASE (RBR, THR) |
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.DB UARTDBASE + UART_LSR ; LINE STATUS PORT (LSR) |
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.DW UARTCFG ; LINE CONFIGURATION |
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.DW 0 ; SHOULD NEVER NEED INT HANDLER |
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; DUAL UART CHANNEL B |
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.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) |
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.DB 0 ; UART TYPE |
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.DB UARTDBASE+8 ; IO PORT BASE (RBR, THR) |
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.DB UARTDBASE+8 + UART_LSR ; LINE STATUS PORT (LSR) |
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.DW UARTCFG ; LINE CONFIGURATION |
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.DW 0 ; SHOULD NEVER NEED INT HANDLER |
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#ENDIF |
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; |
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UART_CNT .EQU ($ - UART_CFG) / 8 |
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; |
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b1ackmai1er
4 years ago
GitHub