From 3e1e640bb377543bd08dd24c72593c1f3c5c650c Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 23 May 2025 14:54:38 -0700 Subject: [PATCH 001/162] Minor PCF Changes - Slightly modified to be more consistent with typical RomWBW driver config. --- Source/HBIOS/cfg_DUO.asm | 2 ++ Source/HBIOS/cfg_DYNO.asm | 1 - Source/HBIOS/cfg_EPITX.asm | 1 - Source/HBIOS/cfg_EZZ80.asm | 1 - Source/HBIOS/cfg_FZ80.asm | 1 - Source/HBIOS/cfg_GMZ180.asm | 1 - Source/HBIOS/cfg_HEATH.asm | 1 - Source/HBIOS/cfg_MASTER.asm | 4 +-- Source/HBIOS/cfg_MBC.asm | 1 - Source/HBIOS/cfg_MK4.asm | 1 - Source/HBIOS/cfg_MON.asm | 1 - Source/HBIOS/cfg_N8.asm | 1 - Source/HBIOS/cfg_NABU.asm | 1 - Source/HBIOS/cfg_RCEZ80.asm | 1 - Source/HBIOS/cfg_RCZ180.asm | 1 - Source/HBIOS/cfg_RCZ280.asm | 1 - Source/HBIOS/cfg_RCZ80.asm | 4 +-- Source/HBIOS/cfg_RPH.asm | 1 - Source/HBIOS/cfg_S100.asm | 1 - Source/HBIOS/cfg_SBC.asm | 1 - Source/HBIOS/cfg_SCZ180.asm | 1 - Source/HBIOS/cfg_Z80RETRO.asm | 1 - Source/HBIOS/cfg_ZETA.asm | 1 - Source/HBIOS/cfg_ZETA2.asm | 1 - Source/HBIOS/pcf.asm | 60 +++-------------------------------- Source/HBIOS/std.asm | 15 +++++++++ 26 files changed, 25 insertions(+), 81 deletions(-) diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm index c8d3c792..431bcbb9 100644 --- a/Source/HBIOS/cfg_DUO.asm +++ b/Source/HBIOS/cfg_DUO.asm @@ -96,6 +96,8 @@ CTCOSC .SET (7372800/8) ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER PCFBASE .SET $56 ; PCF8584 BASE I/O ADDRESS +PCFCLK .SET PCFCLK_12 ; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12] +PCFTRNS .SET PCFTRNS_90 ; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15] ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm index 80b95152..2e7c2838 100644 --- a/Source/HBIOS/cfg_DYNO.asm +++ b/Source/HBIOS/cfg_DYNO.asm @@ -97,7 +97,6 @@ CTCBASE .SET $88 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm index e6bd05e0..ff80c150 100644 --- a/Source/HBIOS/cfg_EPITX.asm +++ b/Source/HBIOS/cfg_EPITX.asm @@ -92,7 +92,6 @@ CTCBASE .SET $88 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm index 577d25b4..6603d06c 100644 --- a/Source/HBIOS/cfg_EZZ80.asm +++ b/Source/HBIOS/cfg_EZZ80.asm @@ -95,7 +95,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_FZ80.asm b/Source/HBIOS/cfg_FZ80.asm index 8a14e828..492efe5d 100644 --- a/Source/HBIOS/cfg_FZ80.asm +++ b/Source/HBIOS/cfg_FZ80.asm @@ -95,7 +95,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm index 4671582e..99f5030c 100644 --- a/Source/HBIOS/cfg_GMZ180.asm +++ b/Source/HBIOS/cfg_GMZ180.asm @@ -91,7 +91,6 @@ CTCBASE .SET $88 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm index 177e0247..21f337d3 100644 --- a/Source/HBIOS/cfg_HEATH.asm +++ b/Source/HBIOS/cfg_HEATH.asm @@ -95,7 +95,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm index 470a523e..a117f480 100644 --- a/Source/HBIOS/cfg_MASTER.asm +++ b/Source/HBIOS/cfg_MASTER.asm @@ -128,8 +128,8 @@ CTCOSC .EQU 614400 ; CTC CLOCK FREQUENCY ; PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -PCFCLK .EQU 12 ; PCF CLOCK BASE -PCFTRNS .EQU 90 ; PCF TRANSFER SPEED +PCFCLK .EQU PCFCLK_12 ; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12] +PCFTRNS .EQU PCFTRNS_90 ; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15] ; EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm index 18b5f779..fe907a30 100644 --- a/Source/HBIOS/cfg_MBC.asm +++ b/Source/HBIOS/cfg_MBC.asm @@ -92,7 +92,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET (4915200/8) ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm index ee5183f6..a5de49b0 100644 --- a/Source/HBIOS/cfg_MK4.asm +++ b/Source/HBIOS/cfg_MK4.asm @@ -97,7 +97,6 @@ CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm index 99e65e2b..e8192fd6 100644 --- a/Source/HBIOS/cfg_MON.asm +++ b/Source/HBIOS/cfg_MON.asm @@ -92,7 +92,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm index 0fbda02b..5b948649 100644 --- a/Source/HBIOS/cfg_N8.asm +++ b/Source/HBIOS/cfg_N8.asm @@ -99,7 +99,6 @@ CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm index 443bc410..862e8234 100644 --- a/Source/HBIOS/cfg_NABU.asm +++ b/Source/HBIOS/cfg_NABU.asm @@ -95,7 +95,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm index 9e1472a8..5a33c933 100644 --- a/Source/HBIOS/cfg_RCEZ80.asm +++ b/Source/HBIOS/cfg_RCEZ80.asm @@ -93,7 +93,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm index 9511969c..7314bc00 100644 --- a/Source/HBIOS/cfg_RCZ180.asm +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -97,7 +97,6 @@ CTCBASE .SET $88 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm index 92ee15bd..6d56c86b 100644 --- a/Source/HBIOS/cfg_RCZ280.asm +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -97,7 +97,6 @@ CTCBASE .SET $88 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm index 77c0c6c3..729f96bb 100644 --- a/Source/HBIOS/cfg_RCZ80.asm +++ b/Source/HBIOS/cfg_RCZ80.asm @@ -96,8 +96,8 @@ CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS -PCFCLK .SET 8 ; PCF CLOCK BASE -PCFTRNS .SET 90 ; PCF TRANSFER SPEED +PCFCLK .SET PCFCLK_8 ; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12] +PCFTRNS .SET PCFTRNS_90 ; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15] ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm index fad70b2e..0998c00c 100644 --- a/Source/HBIOS/cfg_RPH.asm +++ b/Source/HBIOS/cfg_RPH.asm @@ -97,7 +97,6 @@ CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_S100.asm b/Source/HBIOS/cfg_S100.asm index 4cbf7df1..8df8b29f 100644 --- a/Source/HBIOS/cfg_S100.asm +++ b/Source/HBIOS/cfg_S100.asm @@ -97,7 +97,6 @@ CTCBASE .SET $88 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm index 75fa135b..5c536e04 100644 --- a/Source/HBIOS/cfg_SBC.asm +++ b/Source/HBIOS/cfg_SBC.asm @@ -92,7 +92,6 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) CTCOSC .SET 614400 ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm index e4322a3f..1fca8ac5 100644 --- a/Source/HBIOS/cfg_SCZ180.asm +++ b/Source/HBIOS/cfg_SCZ180.asm @@ -97,7 +97,6 @@ CTCBASE .SET $88 ; CTC BASE I/O ADDRESS CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm index fe1bd88d..a24a05dc 100644 --- a/Source/HBIOS/cfg_Z80RETRO.asm +++ b/Source/HBIOS/cfg_Z80RETRO.asm @@ -95,7 +95,6 @@ CTCTIMCH .SET 1 ; TIMER CHANNEL (0-3) CTCOSC .SET 7372800 ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm index e12885d4..c0d737b7 100644 --- a/Source/HBIOS/cfg_ZETA.asm +++ b/Source/HBIOS/cfg_ZETA.asm @@ -84,7 +84,6 @@ KIOBASE .SET $80 ; KIO BASE I/O ADDRESS CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm index 7981c6d5..4280d684 100644 --- a/Source/HBIOS/cfg_ZETA2.asm +++ b/Source/HBIOS/cfg_ZETA2.asm @@ -95,7 +95,6 @@ CTCTIMCH .SET 1 ; TIMER CHANNEL (0-3) CTCOSC .SET 921600 ; CTC CLOCK FREQUENCY ; PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS ; EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION ; diff --git a/Source/HBIOS/pcf.asm b/Source/HBIOS/pcf.asm index 0d5216c8..1a6789d2 100644 --- a/Source/HBIOS/pcf.asm +++ b/Source/HBIOS/pcf.asm @@ -66,62 +66,10 @@ PCF_BB .EQU 00000001B ; | 12MHz | | | | | | 90Khz | 120Khz | 138Khz | 150Khz | ; +----------------------------------------------------------------------------------+---------+ ; -; CLOCK CHIP FREQUENCIES -; -PCF_CLK3 .EQU 000H -PCF_CLK443 .EQU 010H -PCF_CLK6 .EQU 014H -PCF_CLK8 .EQU 018H -PCF_CLK12 .EQU 01CH -; -; TRANSMISSION FREQUENCIES -; -PCF_TRNS90 .EQU 000H ; 90 kHz */ -PCF_TRNS45 .EQU 001H ; 45 kHz */ -PCF_TRNS11 .EQU 002H ; 11 kHz */ -PCF_TRNS15 .EQU 003H ; 1.5 kHz */ -; -; BELOW VARIABLES CONTROL PCF CLOCK DIVISOR PROGRAMMING -; -#IF (PCFCLK = 3) -PCF_CLK .EQU PCF_CLK3 -#ELSE - #IF (PCFCLK = 443) -PCF_CLK .EQU PCF_CLK443 - #ELSE - #IF (PCFCLK = 6) -PCF_CLK .EQU PCF_CLK6 - #ELSE - #IF (PCFCLK = 8) -PCF_CLK .EQU PCF_CLK8 - #ELSE - #IF (PCFCLK = 12) -PCF_CLK .EQU PCF_CLK12 - #ELSE ***ERROR - .ERROR "PCFCLK UNDEFINED OR WRONG VALUE VALID VALUES ARE (3,443,6,8,12)" - #ENDIF - #ENDIF - #ENDIF - #ENDIF -#ENDIF -; -#IF (PCFTRNS = 90) -PCF_TRNS .EQU PCF_TRNS90 -#ELSE - #IF (PCFTRNS = 45) -PCF_TRNS .EQU PCF_TRNS45 - #ELSE - #IF (PCFTRNS = 11) -PCF_TRNS .EQU PCF_TRNS11 - #ELSE - #IF (PCFTRNS = 15) -PCF_TRNS .EQU PCF_TRNS15 - #ELSE ***ERROR - .ERROR "PCFTRNS UNDEFINED OR WRONG VALUE VALID VALUES ARE (90,45,11,15)" - #ENDIF - #ENDIF - #ENDIF -#ENDIF +; SEE STD.ASM FOR DEFINITIONS OF PCFCLK AND PCFTRNS VALUES +; +PCF_CLK .EQU PCFCLK +PCF_TRNS .EQU PCFTRNS ; ; TIMEOUT AND DELAY VALUES (ARBITRARY) ; diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 38e075fe..87bdd7f9 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -327,6 +327,21 @@ SYQMODE_NONE .EQU 0 ; NONE SYQMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP) SYQMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE ; +; PCF CLOCK CHIP FREQUENCIES +; +PCFCLK_3 .EQU $00 ; 3 MHz +PCFCLK_443 .EQU $10 ; 4.43 MHz +PCFCLK_6 .EQU $14 ; 6 MHz +PCFCLK_8 .EQU $18 ; 8 MHz +PCFCLK_12 .EQU $1C ; 12 MHz +; +; PCF TRANSMISSION FREQUENCIES +; +PCFTRNS_90 .EQU $00 ; 90 KHZ +PCFTRNS_45 .EQU $01 ; 45 KHZ +PCFTRNS_11 .EQU $02 ; 11 KHZ +PCFTRNS_15 .EQU $03 ; 1.5 KHZ +; ; GDC MONITOR SELECTIONS ; GDCMON_NONE .EQU 0 From 77d201f9d3c62295c97a6b136c73662afb5a3dfb Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sat, 24 May 2025 16:10:39 -0700 Subject: [PATCH 002/162] CPU Speed LCD Dynamic Update, Issue #520 - Enable dynamic update of CPU speed display on LCD. --- Source/HBIOS/hbios.asm | 31 +++++++++++++------------ Source/HBIOS/lcd.asm | 51 +++++++++++++++++++++++++----------------- 2 files changed, 46 insertions(+), 36 deletions(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 07ff95d8..9150d836 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -6222,12 +6222,12 @@ SYS_SETCPUSPD1: LD A,(HB_RTCVAL) AND ~%00001000 ; CLEAR SPEED BIT OR C ; IMPLEMENT NEW SPEED BIT -#IF (PLATFORM == PLT_SBC) + #IF (PLATFORM == PLT_SBC) ; SBC SPEED BIT IS INVERTED, ADJUST IT LD A,C XOR %00001000 LD C,A -#ENDIF + #ENDIF LD (HB_RTCVAL),A ; SAVE IN SHADOW REGISTER OUT (RTCIO),A ; UPDATE HARDWARE REGISTER ; @@ -6255,15 +6255,11 @@ SYS_SETCPUSPD2: ADC A,C ; C -> A; ADD CF FOR ROUNDING LD (CB_CPUMHZ),A ; SAVE IT ; -#IF (CPUFAM != CPU_EZ80) + #IF (CPUFAM != CPU_EZ80) ; REINIT DELAY ROUTINE LD A,(CB_CPUMHZ) ; CPU SPEED TO ACCUM AND INIT CALL DELAY_INIT ; .. SPEED COMPENSATED DELAY -#ENDIF -; -SYS_SETCPUSPD3: - XOR A - RET + #ENDIF #ENDIF ; #IF (PLATFORM == PLT_HEATH) @@ -6302,14 +6298,11 @@ SYS_SETCPUSPD2: ADC A,C ; C -> A; ADD CF FOR ROUNDING LD (CB_CPUMHZ),A ; SAVE IT ; -#IF (CPUFAM != CPU_EZ80) + #IF (CPUFAM != CPU_EZ80) ; REINIT DELAY ROUTINE LD A,(CB_CPUMHZ) ; CPU SPEED TO ACCUM AND INIT CALL DELAY_INIT ; .. SPEED COMPENSATED DELAY -#ENDIF -; - XOR A ; SIGNAL SUCCESS - RET + #ENDIF #ENDIF ; #IF (CPUFAM == CPU_Z180) @@ -6441,11 +6434,11 @@ SYS_SETCPUSPD4: LD A,L ; WORKING VALUE TO A OUT0 (Z180_DCNTL),A ; IMPLEMENT NEW VALUE ; -#IF (CPUFAM != CPU_EZ80) + #IF (CPUFAM != CPU_EZ80) ; REINIT DELAY ROUTINE LD A,(CB_CPUMHZ) ; CPU SPEED TO ACCUM AND INIT CALL DELAY_INIT ; .. SPEED COMPENSATED DELAY -#ENDIF + #ENDIF ; #IF ((INTMODE == 2) & (Z180_TIMER)) ; THE Z180 TIMER IS BASED ON CPU SPEED. SO HERE @@ -6473,10 +6466,16 @@ SYS_SETCPUSPD4: LD IY,ASCI1_CFG CALL ASCI_INITDEV #ENDIF +#ENDIF +; +SYS_SETCPUSPD_OK: +; + LD B,BF_DSKYEVENT + LD C,DSKY_EVT_CPUSPD + CALL DSKY_DISPATCH ; XOR A RET -#ENDIF ; SYS_SETCPUSPD_ERR: OR $FF ; NOT SUPPORTED diff --git a/Source/HBIOS/lcd.asm b/Source/HBIOS/lcd.asm index 0a49df9b..05e0becd 100644 --- a/Source/HBIOS/lcd.asm +++ b/Source/HBIOS/lcd.asm @@ -90,21 +90,7 @@ LCD_PREINIT: LD DE,LCD_STR_XPU CALL LCD_OUTDS ; - ; "12.345 MHz" RIGHT JUSTIFIED - LD HL,$010A ; ROW 2, COL 10 - CALL LCD_GOTORC - LD HL,(CB_CPUKHZ) - PUSH HL - LD BC,10000 ; 10 MHZ - SBC HL,BC ; SUBTRACT - JR NC,LCD_PREINIT1 - LD A,' ' ; EXTRA PAD - CALL LCD_OUTD -LCD_PREINIT1: - POP HL - CALL LCD_PRTD3M ; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA - LD DE,LCD_STR_MHZ - CALL LCD_OUTDS + CALL LCD_EVT_CPUSPD ; ; THIRD LINE LD HL,$0200 ; ROW 2, COL 0 @@ -228,7 +214,22 @@ LCD_EVENT: ; CPU SPEED CHANGE ; LCD_EVT_CPUSPD: - XOR A + ; "12.345 MHz" RIGHT JUSTIFIED + LD HL,$010A ; ROW 2, COL 10 + CALL LCD_GOTORC + LD HL,(CB_CPUKHZ) + PUSH HL + LD BC,10000 ; 10 MHZ + SBC HL,BC ; SUBTRACT + JR NC,LCD_PREINIT1 + LD A,' ' ; EXTRA PAD + CALL LCD_OUTD +LCD_PREINIT1: + POP HL + CALL LCD_PRTD3M ; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA + LD DE,LCD_STR_MHZ + CALL LCD_OUTDS +; RET ; ; FORMAT: "Disk #99 R:12345678" @@ -342,16 +343,23 @@ LCD_DELAY: CALL DELAY ; 16US JP DELAY ; 16US, TOTAL 48US ; +; DELAY USED DURING NORMAL I/O +; REQUIRED FOR HIGH SPEED CPU OPERATION +; +#DEFINE LCD_XDELAY EX (SP),HL \ EX (SP),HL +; ; SEND FUNCTION CODE IN A ; LCD_OUTF: PUSH AF ; SAVE CODE LCD_OUTF1: + LCD_XDELAY EZ80_IO IN A,(LCD_STAT) ; GET STATUS AND $80 ; ISOLATE BUSY FLAG JR NZ,LCD_OUTF1 ; LOOP TILL NOT BUSY POP AF ; RECOVER CODE + LCD_XDELAY EZ80_IO OUT (LCD_FUNC),A ; SEND IT RET ; DONE @@ -372,11 +380,13 @@ LCD_OUTFS: LCD_OUTD: PUSH AF ; SAVE BYTE LCD_OUTD1: + LCD_XDELAY EZ80_IO IN A,(LCD_STAT) ; GET STATUS AND $80 ; ISOLATE BUSY FLAG JR NZ,LCD_OUTD1 ; LOOP TILL NOT BUSY POP AF ; RECOVER BYTE + LCD_XDELAY EZ80_IO OUT (LCD_DATA),A ; SEND IT RET ; DONE @@ -408,11 +418,13 @@ LCD_OUTDS: ; GET DATA BYTE INTO A ; LCD_IND: + LCD_XDELAY EZ80_IO IN A,(LCD_STAT) ; GET STATUS AND $80 ; ISOLATE BUSY FLAG JR NZ,LCD_IND ; LOOP TILL NOT BUSY POP AF ; RECOVER BYTE + LCD_XDELAY EZ80_IO IN A,(LCD_DATA) ; GET IT RET ; DONE @@ -483,10 +495,9 @@ LCD_INIT_SEQ: .DB $00 ; TERMINATOR ; LCD_STR_BAN .DB "RomWBW v", BIOSVER, 0 -LCD_STR_CFG .DB "Build: ", CONFIG, 0 +LCD_STR_CFG .DB CONFIG, 0 LCD_STR_IO .DB "Disk #", 0 LCD_STR_XPU .DB " CPU",0 -;;;LCD_STR_SPD .DB "12.345",0 LCD_STR_MHZ .DB " MHz",0 ; LCD_CPU .DW LCD_CPU_Z80 @@ -498,8 +509,8 @@ LCD_CPU .DW LCD_CPU_Z80 ; LCD_CPU_Z80 .DB "Z80",0 LCD_CPU_Z180 .DB "Z180",0 -LCD_CPU_Z180K .DB "Z180-K",0 -LCD_CPU_Z180N .DB "Z180-N",0 +LCD_CPU_Z180K .DB "Z180K",0 +LCD_CPU_Z180N .DB "Z180N",0 LCD_CPU_Z280 .DB "Z280",0 LCD_CPU_EZ80 .DB "eZ80",0 ; From ed4ced1ab65a9761fdc607d86e71ebdce443a493 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sat, 24 May 2025 16:26:23 -0700 Subject: [PATCH 003/162] Update hbios.asm - Missed one label change in previous commit. --- Source/HBIOS/hbios.asm | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 9150d836..2effdae7 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -6210,7 +6210,7 @@ SYS_SETCPUSPD: ; LD A,L ; CLK SPD TO ACCUM CP $FF ; NO CHANGE? - JR Z,SYS_SETCPUSPD3 ; DONE IF SO + JR Z,SYS_SETCPUSPD_OK ; DONE IF SO LD C,%00000000 ; HALF SPEED CP 0 JR Z,SYS_SETCPUSPD1 From 2ffd248eb5fba05de7690d785d943c91b01a1a36 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 25 May 2025 14:42:06 -0700 Subject: [PATCH 004/162] LPT Driver Boot Messages, Issue #555 LPT driver will now display hardware that is not detected. Thanks and credit to @robbbates. --- Doc/ChangeLog.txt | 2 ++ Source/HBIOS/lpt.asm | 46 ++++++++++++++++++-------------------------- 2 files changed, 21 insertions(+), 27 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index cf1bdd7b..dfec5a68 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -2,6 +2,8 @@ Version 3.6 ----------- - MGG: Added COBOL language disk image - WDC: Added config options to PCF driver +- WBW: Enabled dynamic CPU speed update on LCD screen +- WBW: Improve LPT driver boot messaging when not detected (per Robb Bates) Version 3.5.1 ------------- diff --git a/Source/HBIOS/lpt.asm b/Source/HBIOS/lpt.asm index 0445b269..c8e57d11 100644 --- a/Source/HBIOS/lpt.asm +++ b/Source/HBIOS/lpt.asm @@ -95,10 +95,18 @@ LPT_INIT: LD IY,LPT_CFG ; POINT TO START OF CFG TABLE LPT_INIT0: PUSH BC ; SAVE LOOP CONTROL + CALL LPT_PRTCFG ; PRINT CONFIG CALL LPT_INITUNIT ; HAND OFF TO UNIT INIT CODE POP BC ; RESTORE LOOP CONTROL ; - LD A,(IY+1) ; GET THE LPT TYPE DETECTED + JR Z,LPT_INIT1 ; IF DETECTED, CONTINUE INIT + CALL PC_SPACE ; FORMATTING + LD DE,LPT_STR_NOLPT ; NO LPT MESSAGE + CALL WRITESTR ; DISPLAY IT + JR LPT_INIT2 ; AND LOOP AS NEEDED +; +LPT_INIT1: + LD A,(IY+1) ; GET THE LPT TYPE OR A ; SET FLAGS JR Z,LPT_INIT2 ; SKIP IT IF NOTHING FOUND ; @@ -107,7 +115,6 @@ LPT_INIT0: POP DE ; ... TO DE LD BC,LPT_FNTBL ; BC := FUNCTION TABLE ADDRESS CALL NZ,CIO_ADDENT ; ADD ENTRY IF LPT FOUND, BC:DE - CALL LPT_PRTCFG ; PRINT IF NOT ZERO POP BC ; RESTORE LOOP CONTROL ; LPT_INIT2: @@ -123,9 +130,7 @@ LPT_INIT3: ; LPT_INITUNIT: CALL LPT_DETECT ; DETERMINE LPT TYPE - LD (IY+1),A ; SAVE IN CONFIG TABLE - OR A ; SET FLAGS - RET Z ; ABORT IF NOTHING THERE + RET NZ ; ABORT IF NOTHING THERE ; ; UPDATE WORKING LPT DEVICE NUM LD HL,LPT_DEV ; POINT TO CURRENT DEVICE NUM @@ -326,15 +331,7 @@ LPT_DETECT: ; LPT_DETECT: LD C,(IY+3) ; BASE PORT ADDRESS - CALL LPT_DETECT2 ; CHECK IT - JR Z,LPT_DETECT1 ; FOUND IT, RECORD IT - LD A,LPTMODE_NONE ; NOTHING FOUND - RET ; DONE -; -LPT_DETECT1: - ; LPT FOUND, RECORD IT - LD A,LPTMODE_SPP ; RETURN CHIP TYPE - RET ; DONE + JR LPT_DETECT2 ; CHECK IT ; LPT_DETECT2: ; LOOK FOR LPT AT BASE PORT ADDRESS IN C @@ -394,20 +391,13 @@ LPT_DETECT: CALL PRTHEXBYTE #ENDIF CP $A5 ; CHECK FOR TEST VALUE - JR Z,LPT_DETECT1 ; FOUND IT - LD A,LPTMODE_NONE ; NOT FOUND - RET -; -LPT_DETECT1: - ; LPT FOUND, RECORD IT - LD A,LPTMODE_MG014 ; RETURN CHIP TYPE - RET ; DONE + RET ; ZF SET IF DETECTED #ENDIF ; #IF (LPTMODE == LPTMODE_S100) LPT_DETECT: ; PORT ALWAYS EXISTS ON FPGA - LD A,LPTMODE_S100 ; RETURN CHIP TYPE + XOR A ; SIGNAL SUCCESS RET ; DONE #ENDIF ; @@ -417,7 +407,7 @@ LPT_PRTCFG: ; ANNOUNCE PORT CALL NEWLINE ; FORMATTING PRTS("LPT$") ; FORMATTING - LD A,(IY) ; DEVICE NUM + LD A,(IY+2) ; DEVICE NUM CALL PRTDECB ; PRINT DEVICE NUM PRTS(": IO=0x$") ; FORMATTING LD A,(IY+3) ; GET BASE PORT @@ -452,11 +442,13 @@ LPT_TYPE_MAP: .DW LPT_STR_MG014 .DW LPT_STR_S100 ; -LPT_STR_NONE .DB "$" +LPT_STR_NONE .DB "???$" LPT_STR_SPP .DB "SPP$" LPT_STR_MG014 .DB "MG014$" LPT_STR_S100 .DB "S100$" ; +LPT_STR_NOLPT .DB "NOT PRESENT$" +; ; WORKING VARIABLES ; LPT_DEV .DB 0 ; DEVICE NUM USED DURING INIT @@ -468,7 +460,7 @@ LPT_CFG: LPT0_CFG: ; LPT MODULE A CONFIG .DB 0 ; DEVICE NUMBER (SET DURING INIT) - .DB 0 ; LPT TYPE (SET DURING INIT) + .DB LPTMODE ; LPT MODE .DB 0 ; MODULE ID .DB LPT0BASE ; BASE PORT .DW 0 ; LINE CONFIGURATION @@ -494,7 +486,7 @@ LPT_CFGSIZ .EQU $ - LPT_CFG ; SIZE OF ONE CFG TABLE ENTRY LPT1_CFG: ; LPT MODULE B CONFIG .DB 0 ; DEVICE NUMBER (SET DURING INIT) - .DB 0 ; LPT TYPE (SET DURING INIT) + .DB LPTMODE ; LPT MODE .DB 1 ; MODULE ID .DB LPT1BASE ; BASE PORT .DW 0 ; LINE CONFIGURATION From 2f61c3fc8144f2ef9f08735f77495afc105fc508 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 25 May 2025 15:32:03 -0700 Subject: [PATCH 005/162] Correct DS1307 Boot Date/Time Display, Issue #556 DS1307 driver (ds7rtc.asm) was displaying an erroneous date/time in the boot messages. The HBIOS API data was OK. Credit and thanks to @tpycio for identifying this issue. --- Doc/ChangeLog.txt | 1 + Source/HBIOS/ds7rtc.asm | 12 ++++++------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index dfec5a68..7b1f0c48 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -4,6 +4,7 @@ Version 3.6 - WDC: Added config options to PCF driver - WBW: Enabled dynamic CPU speed update on LCD screen - WBW: Improve LPT driver boot messaging when not detected (per Robb Bates) +- WBW: Correct DS1307 boot date/time display (per Tadeusz Pycio) Version 3.5.1 ------------- diff --git a/Source/HBIOS/ds7rtc.asm b/Source/HBIOS/ds7rtc.asm index 4014b26e..aadc740b 100644 --- a/Source/HBIOS/ds7rtc.asm +++ b/Source/HBIOS/ds7rtc.asm @@ -418,12 +418,12 @@ DS7_CLP:LD C,(HL) RET ; DS7_CLKTBL: - .DB 04H, 00111111B, '/' - .DB 05H, 00011111B, '/' - .DB 06H, 11111111B, ' ' - .DB 02H, 00011111B, ':' - .DB 01H, 01111111B, ':' - .DB 00H, 01111111B, 00H + .DB 04H, 00111111B, '/' ; DD: 31 + .DB 05H, 00011111B, '/' ; MM: 12 + .DB 06H, 11111111B, ' ' ; YY: 99 + .DB 02H, 01111111B, ':' ; SS: 59 + .DB 01H, 01111111B, ':' ; MM: 59 + .DB 00H, 00111111B, 00H ; HH: 24 ; DS7_BCD:PUSH HL LD HL,DS7_BUF ; READ VALUE FROM From ed77b3ef8468bb4194377cbbef6c29c21d356b48 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Mon, 26 May 2025 13:10:00 -0700 Subject: [PATCH 006/162] Fix Char Device Name Display, Issue #557 An extraneous character device enumeration string had not been deleted as needed. This has been fixed. Thanks and credit to @PeterOGB. --- Source/HBIOS/hbios.asm | 1 - 1 file changed, 1 deletion(-) diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 2effdae7..5f2304e8 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -8802,7 +8802,6 @@ PS_SDLPT .TEXT "LPT$" PS_SDESPCON .TEXT "ESPCON$" PS_SDESPSER .TEXT "ESPSER$" PS_SDSCON .TEXT "SCON$" -PS_SDEF .TEXT "EF$" PS_SDSSER .TEXT "SSER$" PS_SDEZ80 .TEXT "EZ80$" ; From 52ea94161c9458069d75bd26dcd928dd905a4f79 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Wed, 28 May 2025 15:27:35 -0700 Subject: [PATCH 007/162] TUNE Delay Switch, Issue #558 - Add a -DELAY switch to the TUNE command line to force the use of delay mode for note pacing. Issue #558 Credit to @robbbates for suggesting this. - Add missing include file logic for DS1307, Issue #556. Credit to @tpycio. - Miscellaneous documentation improvements per Peter Onion and Petr Antos. --- Doc/ChangeLog.txt | 1 + Doc/RomWBW Applications.pdf | Bin 412718 -> 413038 bytes Doc/RomWBW Disk Catalog.pdf | Bin 226912 -> 226913 bytes Doc/RomWBW Hardware.pdf | Bin 361050 -> 361273 bytes Doc/RomWBW Introduction.pdf | Bin 92899 -> 92900 bytes Doc/RomWBW System Guide.pdf | Bin 628732 -> 630807 bytes Doc/RomWBW User Guide.pdf | Bin 571391 -> 571613 bytes ReadMe.md | 2 +- ReadMe.txt | 2 +- Source/Apps/Tune/cli.inc | 16 ++++++++++- Source/Apps/Tune/timing.inc | 6 ++++ Source/Apps/Tune/tune.asm | 9 ++++-- Source/Doc/Applications.md | 19 +++++++----- Source/Doc/Hardware.md | 5 ++++ Source/Doc/SystemGuide.md | 56 ++++++++++++++++++++++++++++++++++++ Source/Doc/UserGuide.md | 2 +- Source/HBIOS/hbios.asm | 9 ++++++ Source/ver.inc | 2 +- Source/ver.lib | 2 +- 19 files changed, 115 insertions(+), 16 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 7b1f0c48..33628d3d 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -5,6 +5,7 @@ Version 3.6 - WBW: Enabled dynamic CPU speed update on LCD screen - WBW: Improve LPT driver boot messaging when not detected (per Robb Bates) - WBW: Correct DS1307 boot date/time display (per Tadeusz Pycio) +- WBW: Add -DELAY option to TUNE app (per Robb Bates) Version 3.5.1 ------------- diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index f480fe7520ff13435de30b738e8691f07b6fbfc7..c26e152b6fc13d0808a105218eb4a9b34f782f7c 100644 GIT binary patch delta 28350 zcmahx2RN4P_nG07osyE3Xz=dmeU-A3t&oOPWTfoSFO4@+LX>1ggOs$a6ltj_Es;=0 zOR{MaQvdU)jQj4o{@-vRO}_WTl8QF&k&k}5RWRJNpBPyVg6#2U5jrKf%g@rTOsx`mxCx*yO_kNFa_ zKJ)(FLWL{#owqA{XWwq>{hEGjr+;>ISZY(QrPXU|9u2V>KB3=g?B*z!+302Puf0}tN|Dfp zbtYCOCl1}IbRVze7oPXCEGr~BhR#{b>Z4pIxjg?;y*8$`ev7^xQAbt7O@DdWyP_X_HySNTwtV?u`K2oln{GB; zeD->Uohf&re1302Y&nmNv3SRz%0Pe5_9xc@;s)EEmA>Ncl!`SgF{n7)8*DA_%ox1? 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