diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt
index 8416c3c4..2014093a 100644
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -17,6 +17,7 @@ Version 2.9.2
 - PMS: Added note playing ability to SPK driver
 - WBW: Support disk I/O to any memory bank
 - WBW: Fix floppy I/O error on slow CPUs w/ ints active (credit Jorge Rodrigues)
+- WBW: Support for KIO chip (based on board by Tom Szolyga)
 
 Version 2.9.1
 -------------
diff --git a/Doc/Z180 ASCI Baud Rate Options.pdf b/Doc/Z180 ASCI Baud Rate Options.pdf
new file mode 100644
index 00000000..0786fcbe
Binary files /dev/null and b/Doc/Z180 ASCI Baud Rate Options.pdf differ
diff --git a/ReadMe.txt b/ReadMe.txt
index 3434779e..2b3018a3 100644
--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -7,7 +7,7 @@
 ***********************************************************************
 
 Wayne Warthen (wwarthen@gmail.com)
-Version 2.9.2-pre.9, 2019-09-06
+Version 2.9.2-pre.10, 2019-09-15
 https://www.retrobrewcomputers.org/
 
 RomWBW is a ROM-based implementation of CP/M-80 2.2 and Z-System for 
diff --git a/Source/CBIOS/ver.inc b/Source/CBIOS/ver.inc
index 6cbfc90e..0f44e40e 100644
--- a/Source/CBIOS/ver.inc
+++ b/Source/CBIOS/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.9"
+#DEFINE BIOSVER	"2.9.2-pre.10"
diff --git a/Source/Doc/Z180 ASCI Baud Rate Options.xlsx b/Source/Doc/Z180 ASCI Baud Rate Options.xlsx
new file mode 100644
index 00000000..b808a5f9
Binary files /dev/null and b/Source/Doc/Z180 ASCI Baud Rate Options.xlsx differ
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index b2e9e885..256b8b40 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -37,6 +37,9 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 ;
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index df222c16..11f11006 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -55,6 +55,9 @@ RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 CTCBASE		.EQU	$20		; CTC BASE I/O ADDRESS
 ;
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index fa35a14b..1b374069 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -42,6 +42,9 @@ MK4_RTC		.EQU	$8A		; MK4: RTC LATCH REGISTER ADR
 ;
 RTCIO		.EQU	MK4_RTC		; RTC LATCH REGISTER ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index f95428d2..3dacdd9b 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -45,6 +45,9 @@ N8_DEFACR	.EQU	$1B		; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
 RTCIO		.EQU	N8_RTC		; RTC LATCH REGISTER ADR
 PPIBASE		.EQU	N8_PPI0		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 86a086da..ddcd94d3 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -42,6 +42,9 @@ Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 881d92c6..9bcc308c 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -36,7 +36,11 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 ;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 90879e8e..8e7fa1dd 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -34,6 +34,9 @@ MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
diff --git a/Source/HBIOS/cfg_sc126.asm b/Source/HBIOS/cfg_sc126.asm
index 282d0eed..a853fa45 100644
--- a/Source/HBIOS/cfg_sc126.asm
+++ b/Source/HBIOS/cfg_sc126.asm
@@ -37,6 +37,9 @@ Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 46e5bc02..1a791066 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -34,6 +34,9 @@ MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index f29ba8ce..175ce240 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -37,6 +37,9 @@ MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;
+KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+;
 CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
 CTCBASE		.EQU	$20		; CTC BASE I/O ADDRESS
 ;
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index f4077117..515f7470 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -992,6 +992,236 @@ HB_CPU1:
 	LD	A,L
 	LD	(HB_CPUTYPE),A
 ;
+#IF (KIOENABLE)
+	LD	A,%11111001	; RESET ALL DEVICES, SET DAISYCHAIN
+	OUT	(KIOBASE+$0E),A	; DO IT
+	CALL	DLY64		; WAIT A BIT FOR RESET TO COMPLETE
+#ENDIF  
+;
+; SETUP INTERRUPT VECTORS, AS APPROPRIATE
+;
+;#IF (INTMODE == 1)
+;	; OVERLAY $0038 WITH JP INT_IM1
+;	LD	A,$C3			; JP INSTRUCTION
+;	LD	($0038),A		; INSTALL IT
+;	LD	HL,INT_IM1		; DESTINATION ADDRESS
+;	LD	($0039),HL		; INSTALL IT
+;#ENDIF
+;
+#IF (INTMODE == 2)
+	; SETUP Z80 IVT AND INT MODE 2
+	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
+	LD	I,A			; ... AND PLACE IT IN I REGISTER
+
+  #IF (CPUFAM == CPU_Z180)
+	; SETUP Z180 IVT
+	XOR	A			; SETUP LO BYTE OF IVT ADDRESS
+	OUT0	(Z180_IL),A		; ... AND PLACE IN Z180 IL REGISTER
+  #ENDIF
+
+	IM	2			; SWITCH TO INT MODE 2
+#ENDIF
+
+#IF (PLATFORM == PLT_SBC)
+;
+  #IF (HTIMENABLE)			; SIMH TIMER
+;
+    #IF (INTMODE == 1)
+	LD	HL,HB_TIMINT
+	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
+    #ENDIF
+;
+    #IF (INTMODE == 2)
+	;LD	HL,HB_TIMINT
+	;LD	(HBX_IVT),HL
+    #ENDIF
+;
+  #ENDIF
+;
+#ENDIF
+;
+#IF (PLATFORM == PLT_ZETA2)
+;
+; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
+; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
+; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
+; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
+;
+  #IF (INTMODE == 2)
+;
+	; TIMER INTERRUPT IS ON CTCB, VECTOR IS SECOND IVT SLOT
+	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
+	LD	(IVT(INT_CTC0B)),HL	; IVT ENTRY FOR CTC0B
+;
+	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
+	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
+	; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
+	; IVT CORRESPOND TO CTC CHANNELS A-D
+	LD	A,0
+	OUT	(CTCA),A		; SETUP CTC BASE INT VECTOR
+;
+	; CTCA IS SLAVED (WIRED) TO TO CTCB TO ACT AS A PRESCALER
+	; CONFIGURE CHANNEL B FOR 50HZ PERIODIC INTERRUPTS
+	; CTC CLK = 921,200HZ
+	; CTCA TIME CONSTANT = 256
+	; CTCB TIME CONSTANT = 72
+	; INT FREQ IS CTC CLK / CTCA TC / CTCB TC
+	; WHICH IS 921,600HZ / 256 / 72 = 50HZ
+	LD	A,%01010111		; CTCA CONTROL WORD VALUE
+		;  |||||||+-- 1=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
+		;  |+-------- 1=COUNTER MODE
+		;  +--------- 0=NO INTERRUPTS
+	OUT	(CTCA),A		; SETUP CTCA
+	LD	A,0			; CTCA TIMER CONSTANT = 256, 0 MEANS 256
+	OUT	(CTCA),A		; SETUP CTCA TIMER CONSTANT
+	LD	A,%11010111		; CTCB CONTROL WORD VALUE
+		;  |||||||+-- 1=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
+		;  |+-------- 1=COUNTER MODE
+		;  +--------- 1=ENABLE INTERRUPTS
+	OUT	(CTCB),A		; SETUP CTCB
+	LD	A,72			; CTCB TIMER CONSTANT = 72
+	OUT	(CTCB),A		; SETUP CTCB TIMER CONSTANT
+  #ENDIF
+;
+#ENDIF
+;
+#IF (PLATFORM == PLT_EZZ80)
+;
+; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
+; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
+; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
+; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
+;
+  #IF (INTMODE == 2)
+;
+	; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT
+	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
+	LD	(IVT(INT_CTC0D)),HL	; IVT ENTRY FOR CTC0D
+;
+	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
+	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
+	; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
+	; IVT CORRESPOND TO CTC CHANNELS A-D
+	LD	A,0
+	OUT	(CTCA),A		; SETUP CTC BASE INT VECTOR
+;
+	; CTCC IS SLAVED (WIRED) TO CTCD TO ACT AS A PRESCALER
+	; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS
+	; CTC CLK = 921,200HZ
+	; CTCC TIME CONSTANT = 256
+	; CTCD TIME CONSTANT = 72
+	; INT FREQ IS CTC CLK / CTCC TC / CTCD TC
+	; WHICH IS 921,600HZ / 256 / 72 = 50HZ
+	LD	A,%01010111		; CTCC CONTROL WORD VALUE
+		;  |||||||+-- 1=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
+		;  |+-------- 1=COUNTER MODE
+		;  +--------- 0=NO INTERRUPTS
+	OUT	(CTCC),A		; SETUP CTCC
+	LD	A,0			; CTCC TIMER CONSTANT = 256, 0 MEANS 256
+	OUT	(CTCC),A		; SETUP CTCC TIMER CONSTANT
+	LD	A,%11010111		; CTCD CONTROL WORD VALUE
+		;  |||||||+-- 1=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
+		;  |+-------- 1=COUNTER MODE
+		;  +--------- 1=ENABLE INTERRUPTS
+	OUT	(CTCD),A		; SETUP CTCD
+	LD	A,72			; CTCD TIMER CONSTANT = 72
+	OUT	(CTCD),A		; SETUP CTCD TIMER CONSTANT
+  #ELSE
+	.ECHO	"*** ERROR: EZZ80 REQUIRES INTMODE 2!!!\n"
+	!!!	; FORCE AN ASSEMBLY ERROR
+  #ENDIF
+;
+#ENDIF
+;
+;
+#IF (PLATFORM == PLT_RCZ80)
+;
+; FOR NOW, THIS IS SPECIFICALLY FOR A CTC TO DRIVE AN SIO
+; AT 1:1 USING CTC CHANNELS A & B.  IN OTHER WORDS, IT JUST
+; PASSES THE INCOMING TRIGGER OUT AT 1:1.  NO INTERRUPTS.
+;
+  #IF (CTCENABLE == TRUE)
+;
+	LD	A,%01010111		; CTCC CONTROL WORD VALUE
+		;  |||||||+-- 1=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 0=PRESCALER OF 16 (NOT USED)
+		;  |+-------- 1=COUNTER MODE
+		;  +--------- 0=NO INTERRUPTS
+	OUT	(CTCA),A		; SETUP CTCC
+	LD	A,1			; CTCC TIMER CONSTANT = 1
+	OUT	(CTCA),A		; SETUP CTCC TIMER CONSTANT
+;
+	LD	A,%01010111		; CTCC CONTROL WORD VALUE
+		;  |||||||+-- 1=CONTROL WORD FLAG
+		;  ||||||+--- 1=SOFTWARE RESET
+		;  |||||+---- 1=TIME CONSTANT FOLLOWS
+		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
+		;  |||+------ 1=RISING EDGE TRIGGER
+		;  ||+------- 0=PRESCALER OF 16 (NOT USED)
+		;  |+-------- 1=COUNTER MODE
+		;  +--------- 0=NO INTERRUPTS
+	OUT	(CTCB),A		; SETUP CTCC
+	LD	A,1			; CTCC TIMER CONSTANT = 1
+	OUT	(CTCB),A		; SETUP CTCC TIMER CONSTANT
+;
+  #ENDIF
+;
+#ENDIF
+;
+#IF (CPUFAM == CPU_Z180)
+;
+  #IF (INTMODE == 2)
+;
+	; MASK ALL EXTERNAL INTERRUPTS FOR NOW
+	LD	A,$01			; INT0 ENABLED, INT1-2 DISABLED
+	OUT0	(Z180_ITC),A		; WRITE TO INT/TRAP CONTROL REGISTER
+;
+	; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT
+	LD	HL,HB_TIMINT
+	LD	(IVT(INT_TIM0)),HL	; Z180 TIMER 0
+
+	; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0
+	LD	HL,(CB_CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
+	LD	B,0
+	LD	C,Z180_RLDR0L		; INITIALIZE TIMER 0 RELOAD REGISTER
+	OUT	(C),L
+	INC	C
+	OUT	(C),H
+	LD	C,Z180_TMDR0L		; INITIALIZE TIMER 0 DATA REGISTER
+	OUT	(C),L
+	INC	C
+	OUT	(C),H
+	LD	A,%00010001		; ENABLE TIMER0 INT AND DOWN COUNTING
+	OUT0	(Z180_TCR),A
+;
+  #ENDIF
+;
+#ENDIF
+;
 #IF (CPUFAM == CPU_Z180)
 ;
 	; AT BOOT, Z180 PHI IS OSC / 2
@@ -1180,192 +1410,6 @@ PSCNX	.EQU	$ + 1
 	DJNZ	PSCN1
 #ENDIF
 ;
-; SETUP INTERRUPT VECTORS, AS APPROPRIATE
-;
-;#IF (INTMODE == 1)
-;	; OVERLAY $0038 WITH JP INT_IM1
-;	LD	A,$C3			; JP INSTRUCTION
-;	LD	($0038),A		; INSTALL IT
-;	LD	HL,INT_IM1		; DESTINATION ADDRESS
-;	LD	($0039),HL		; INSTALL IT
-;#ENDIF
-;
-#IF (INTMODE == 2)
-	; SETUP Z80 IVT AND INT MODE 2
-	LD	A,HBX_IVT >> 8		; SETUP HI BYTE OF IVT ADDRESS
-	LD	I,A			; ... AND PLACE IT IN I REGISTER
-
-  #IF (CPUFAM == CPU_Z180)
-	; SETUP Z180 IVT
-	XOR	A			; SETUP LO BYTE OF IVT ADDRESS
-	OUT0	(Z180_IL),A		; ... AND PLACE IN Z180 IL REGISTER
-  #ENDIF
-
-	IM	2			; SWITCH TO INT MODE 2
-#ENDIF
-
-#IF (PLATFORM == PLT_SBC)
-;
-  #IF (HTIMENABLE)			; SIMH TIMER
-;
-    #IF (INTMODE == 1)
-	LD	HL,HB_TIMINT
-	CALL	HB_ADDIM1		; ADD TO IM1 CALL LIST
-    #ENDIF
-;
-    #IF (INTMODE == 2)
-	;LD	HL,HB_TIMINT
-	;LD	(HBX_IVT),HL
-    #ENDIF
-;
-  #ENDIF
-;
-#ENDIF
-;
-#IF (PLATFORM == PLT_ZETA2)
-;
-; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
-; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
-; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
-; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
-;
-  #IF (INTMODE == 2)
-;
-	; TIMER INTERRUPT IS ON CTCB, VECTOR IS SECOND IVT SLOT
-	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
-	LD	(IVT(INT_CTC0B)),HL	; IVT ENTRY FOR CTC0B
-;
-	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
-	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
-	; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
-	; IVT CORRESPOND TO CTC CHANNELS A-D
-	LD	A,0
-	OUT	(CTCA),A		; SETUP CTC BASE INT VECTOR
-;
-	; CTCA IS SLAVED (WIRED) TO TO CTCB TO ACT AS A PRESCALER
-	; CONFIGURE CHANNEL B FOR 50HZ PERIODIC INTERRUPTS
-	; CTC CLK = 921,200HZ
-	; CTCA TIME CONSTANT = 256
-	; CTCB TIME CONSTANT = 72
-	; INT FREQ IS CTC CLK / CTCA TC / CTCB TC
-	; WHICH IS 921,600HZ / 256 / 72 = 50HZ
-	LD	A,%01010111		; CTCA CONTROL WORD VALUE
-		;  |||||||+-- 1=CONTROL WORD FLAG
-		;  ||||||+--- 1=SOFTWARE RESET
-		;  |||||+---- 1=TIME CONSTANT FOLLOWS
-		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
-		;  |||+------ 1=RISING EDGE TRIGGER
-		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
-		;  |+-------- 1=COUNTER MODE
-		;  +--------- 0=NO INTERRUPTS
-	OUT	(CTCA),A		; SETUP CTCA
-	LD	A,0			; CTCA TIMER CONSTANT = 256, 0 MEANS 256
-	OUT	(CTCA),A		; SETUP CTCA TIMER CONSTANT
-	LD	A,%11010111		; CTCB CONTROL WORD VALUE
-		;  |||||||+-- 1=CONTROL WORD FLAG
-		;  ||||||+--- 1=SOFTWARE RESET
-		;  |||||+---- 1=TIME CONSTANT FOLLOWS
-		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
-		;  |||+------ 1=RISING EDGE TRIGGER
-		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
-		;  |+-------- 1=COUNTER MODE
-		;  +--------- 1=ENABLE INTERRUPTS
-	OUT	(CTCB),A		; SETUP CTCB
-	LD	A,72			; CTCB TIMER CONSTANT = 72
-	OUT	(CTCB),A		; SETUP CTCB TIMER CONSTANT
-  #ENDIF
-;
-#ENDIF
-;
-#IF (PLATFORM == PLT_EZZ80)
-;
-; ONLY IM2 IMPLEMENTED BELOW.  I DON'T SEE ANY REASONABLE WAY TO
-; IMPLEMENT AN IM1 TIMER BECAUSE THE CTC PROVIDES NO WAY TO
-; DETERMINE IF IT WAS THE CAUSE OF AN INTERRUPT OR A WAY TO
-; DETERMINE WHICH CHANNEL CAUSED AN INTERRUPT.
-;
-  #IF (INTMODE == 2)
-;
-	; TIMER INTERRUPT IS ON CTCD, VECTOR IS FOURTH IVT SLOT
-	LD	HL,HB_TIMINT		; TIMER INT HANDLER ADR
-	LD	(IVT(INT_CTC0D)),HL	; IVT ENTRY FOR CTC0D
-;
-	; CTC USES 4 CONSECUTIVE VECTOR POSITIONS, ONE FOR
-	; EACH CHANNEL.  BELOW WE SET THE BASE VECTOR TO THE
-	; START OF THE IVT, SO THE FIRST FOUR ENTIRES OF THE
-	; IVT CORRESPOND TO CTC CHANNELS A-D
-	LD	A,0
-	OUT	(CTCA),A		; SETUP CTC BASE INT VECTOR
-;
-	; CTCC IS SLAVED (WIRED) TO CTCD TO ACT AS A PRESCALER
-	; CONFIGURE CHANNEL D FOR 50HZ PERIODIC INTERRUPTS
-	; CTC CLK = 921,200HZ
-	; CTCC TIME CONSTANT = 256
-	; CTCD TIME CONSTANT = 72
-	; INT FREQ IS CTC CLK / CTCC TC / CTCD TC
-	; WHICH IS 921,600HZ / 256 / 72 = 50HZ
-	LD	A,%01010111		; CTCC CONTROL WORD VALUE
-		;  |||||||+-- 1=CONTROL WORD FLAG
-		;  ||||||+--- 1=SOFTWARE RESET
-		;  |||||+---- 1=TIME CONSTANT FOLLOWS
-		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
-		;  |||+------ 1=RISING EDGE TRIGGER
-		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
-		;  |+-------- 1=COUNTER MODE
-		;  +--------- 0=NO INTERRUPTS
-	OUT	(CTCC),A		; SETUP CTCC
-	LD	A,0			; CTCC TIMER CONSTANT = 256, 0 MEANS 256
-	OUT	(CTCC),A		; SETUP CTCC TIMER CONSTANT
-	LD	A,%11010111		; CTCD CONTROL WORD VALUE
-		;  |||||||+-- 1=CONTROL WORD FLAG
-		;  ||||||+--- 1=SOFTWARE RESET
-		;  |||||+---- 1=TIME CONSTANT FOLLOWS
-		;  ||||+----- 0=AUTO TRIGGER WHEN TIME CONST LOADED
-		;  |||+------ 1=RISING EDGE TRIGGER
-		;  ||+------- 1=PRESCALER OF 16 (NOT USED)
-		;  |+-------- 1=COUNTER MODE
-		;  +--------- 1=ENABLE INTERRUPTS
-	OUT	(CTCD),A		; SETUP CTCD
-	LD	A,72			; CTCD TIMER CONSTANT = 72
-	OUT	(CTCD),A		; SETUP CTCD TIMER CONSTANT
-  #ELSE
-	.ECHO	"*** ERROR: EZZ80 REQUIRES INTMODE 2!!!\n"
-	!!!	; FORCE AN ASSEMBLY ERROR
-  #ENDIF
-  
-;
-#ENDIF
-;
-#IF (CPUFAM == CPU_Z180)
-;
-  #IF (INTMODE == 2)
-;
-	; MASK ALL EXTERNAL INTERRUPTS FOR NOW
-	LD	A,$01			; INT0 ENABLED, INT1-2 DISABLED
-	OUT0	(Z180_ITC),A		; WRITE TO INT/TRAP CONTROL REGISTER
-;
-	; SETUP Z180 TIMER0 INTERRUPT VECTOR IN IVT
-	LD	HL,HB_TIMINT
-	LD	(IVT(INT_TIM0)),HL	; Z180 TIMER 0
-
-	; SETUP PERIODIC TIMER INTERRUPT ON TIMER 0
-	LD	HL,(CB_CPUKHZ)		; 50HZ = 18432000 / 20 / 50 / X, SO X = CPU KHZ
-	LD	B,0
-	LD	C,Z180_RLDR0L		; INITIALIZE TIMER 0 RELOAD REGISTER
-	OUT	(C),L
-	INC	C
-	OUT	(C),H
-	LD	C,Z180_TMDR0L		; INITIALIZE TIMER 0 DATA REGISTER
-	OUT	(C),L
-	INC	C
-	OUT	(C),H
-	LD	A,%00010001		; ENABLE TIMER0 INT AND DOWN COUNTING
-	OUT0	(Z180_TCR),A
-;
-  #ENDIF
-;
-#ENDIF
-;
 #IF 0
 HB_SPDTST:
 	CALL	HB_CPUSPD		; CPU SPEED DETECTION
diff --git a/Source/HBIOS/ver.inc b/Source/HBIOS/ver.inc
index 6cbfc90e..0f44e40e 100644
--- a/Source/HBIOS/ver.inc
+++ b/Source/HBIOS/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	9
 #DEFINE	RUP	2
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.9.2-pre.9"
+#DEFINE BIOSVER	"2.9.2-pre.10"
diff --git a/Source/Images/hd_cpm3/s0/u0/BDOS3.SPR b/Source/Images/hd_cpm3/s0/u0/BDOS3.SPR
deleted file mode 100644
index 728fe2af..00000000
Binary files a/Source/Images/hd_cpm3/s0/u0/BDOS3.SPR and /dev/null differ
diff --git a/Source/Images/hd_cpm3/s0/u0/BNKBDOS3.SPR b/Source/Images/hd_cpm3/s0/u0/BNKBDOS3.SPR
deleted file mode 100644
index 97c8aee4..00000000
Binary files a/Source/Images/hd_cpm3/s0/u0/BNKBDOS3.SPR and /dev/null differ
diff --git a/Source/Images/hd_cpm3/s0/u0/CCP.COM b/Source/Images/hd_cpm3/s0/u0/CCP.COM
deleted file mode 100644
index 3934d840..00000000
Binary files a/Source/Images/hd_cpm3/s0/u0/CCP.COM and /dev/null differ
diff --git a/Source/Images/hd_cpm3/s0/u0/GENCPM.COM b/Source/Images/hd_cpm3/s0/u0/GENCPM.COM
deleted file mode 100644
index d9d67499..00000000
Binary files a/Source/Images/hd_cpm3/s0/u0/GENCPM.COM and /dev/null differ
diff --git a/Source/Images/hd_cpm3/s0/u0/INITDIR.COM b/Source/Images/hd_cpm3/s0/u0/INITDIR.COM
new file mode 100644
index 00000000..03cce335
Binary files /dev/null and b/Source/Images/hd_cpm3/s0/u0/INITDIR.COM differ
diff --git a/Source/Images/hd_cpm3/s0/u0/R.COM b/Source/Images/hd_cpm3/s0/u0/R.COM
deleted file mode 100644
index fecaa4ac..00000000
Binary files a/Source/Images/hd_cpm3/s0/u0/R.COM and /dev/null differ
diff --git a/Source/Images/hd_cpm3/s0/u0/README.1ST b/Source/Images/hd_cpm3/s0/u0/README.1ST
deleted file mode 100644
index 1277e897..00000000
--- a/Source/Images/hd_cpm3/s0/u0/README.1ST
+++ /dev/null
@@ -1,39 +0,0 @@
-CP/M 3
-======
-
-  This archive contains an almost complete build of CP/M 3.
-
-  If you have the source distribution, the file MAKING.DOC explains how to
-set up the build environment on your computer.
-
-Differences from Digital Research CP/M 3
-========================================
-
-  All the CP/M 3 patches described in the document CPM3FIX.PAT have been
-applied to the source code, except those to INITDIR. Patches 1-18 (except
-nos. 5 and 9) were applied.
-
-  CP/M 3 is now fully Year 2000 compliant. This affects the programs 
-DATE.COM, DIR.COM and SHOW.COM.
-
-  Dates can be displayed in US, UK or Year-Month-Day format. This is set by 
-SETDEF:
-
-      SETDEF [US]
-      SETDEF [UK]
-      SETDEF [YMD]  respectively.
-  
-  The CCP has a further bug fix: A command sequence such as:
-
-  C1
-  :C2
-  :C3
-
-  will now not execute the command C3 if the command C1 failed.
-
-What's missing?
-===============
-INITDIR.COM - because it is written in PL/I and I can't make the
-            PL/I compiler at <http://cdl.uta.edu/cpm> compile it.
-            Apparently a more recent version of the compiler is 
-            required.
\ No newline at end of file
diff --git a/Source/Images/hd_cpm3/s0/u0/RESBDOS3.SPR b/Source/Images/hd_cpm3/s0/u0/RESBDOS3.SPR
deleted file mode 100644
index a5f21969..00000000
Binary files a/Source/Images/hd_cpm3/s0/u0/RESBDOS3.SPR and /dev/null differ
diff --git a/Source/Images/hd_cpm3/s0/u0/W.COM b/Source/Images/hd_cpm3/s0/u0/W.COM
deleted file mode 100644
index 2e5ab12a..00000000
Binary files a/Source/Images/hd_cpm3/s0/u0/W.COM and /dev/null differ
diff --git a/Source/Images/hd_cpm3/s0/u0/WBW.TXT b/Source/Images/hd_cpm3/s0/u0/WBW.TXT
new file mode 100644
index 00000000..9bdf3827
--- /dev/null
+++ b/Source/Images/hd_cpm3/s0/u0/WBW.TXT
@@ -0,0 +1,16 @@
+With the following exceptions, the files in this directory
+came from the CP/M 3 binary distribution on "The Unofficial
+CP/M Web site" at http://www.cpm.z80.de/binary.html.
+
+As documented in the "README.1ST" file, the included
+files have been patched with all applicable DRI patches
+per CPM3FIX.PAT.
+
+In addition, the following have been added:
+
+- INITDIR.COM was not included.  The copy included is the
+  original DRI distribution, with both patches installed.
+
+- ZSID6.COM is the original DRI ZSID distribution, but
+  patched to use RST 6 instead of RST 7 to avoid conflicting
+  with mode 1 interrupts.
diff --git a/Source/Images/hd_cpm3/s0/u0/ZSID6.COM b/Source/Images/hd_cpm3/s0/u0/ZSID6.COM
new file mode 100644
index 00000000..686b3775
Binary files /dev/null and b/Source/Images/hd_cpm3/s0/u0/ZSID6.COM differ