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https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Finalize v2.9.1 Prerelease 9
Stability fixes.
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@@ -51,6 +51,8 @@ ACIA_RTSOFF .EQU %11010110 ; RCV INT, RTS DEASSERTED, 8N1, CLK/64 BAUD
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ACIA_PREINIT:
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;
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; SETUP THE DISPATCH TABLE ENTRIES
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; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST REMIAIN
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; DISABLED.
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;
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LD B,ACIA_CNT ; LOOP CONTROL
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LD C,0 ; PHYSICAL UNIT INDEX
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@@ -116,7 +118,9 @@ ACIA_INITUNIT:
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; SET DEFAULT CONFIG
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LD DE,-1 ; LEAVE CONFIG ALONE
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JP ACIA_INITDEV ; IMPLEMENT IT AND RETURN
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; CALL INITDEV TO IMPLEMENT CONFIG, BUT NOTE THAT WE CALL
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; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS!
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JP ACIA_INITDEVX ; IMPLEMENT IT AND RETURN
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;
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;
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;
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@@ -167,7 +171,8 @@ ACIAA_INT00:
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LD E,A ; SAVE BYTE READ
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LD A,(ACIAA_BUFCNT) ; GET CURRENT BUFFER USED COUNT
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CP ACIAA_BUFSZ ; COMPARE TO BUFFER SIZE
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RET Z ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
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;RET Z ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
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JR Z,ACIAA_INT2 ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
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INC A ; INCREMENT THE COUNT
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LD (ACIAA_BUFCNT),A ; AND SAVE IT
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CP ACIAA_BUFSZ - 5 ; BUFFER GETTING FULL?
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@@ -186,6 +191,7 @@ ACIAA_INT1:
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INC HL ; INCREMENT HEAD POINTER
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LD (ACIAA_HD),HL ; SAVE IT
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;
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ACIAA_INT2:
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; CHECK FOR MORE PENDING...
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IN A,(C) ; GET STATUS
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RRA ; READY BIT TO CF
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@@ -210,7 +216,8 @@ ACIAB_INT00:
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LD E,A ; SAVE BYTE READ
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LD A,(ACIAB_BUFCNT) ; GET CURRENT BUFFER USED COUNT
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CP ACIAB_BUFSZ ; COMPARE TO BUFFER SIZE
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RET Z ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
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;RET Z ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
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JR Z,ACIAB_INT2 ; BAIL OUT IF BUFFER FULL, RCV BYTE DISCARDED
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INC A ; INCREMENT THE COUNT
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LD (ACIAB_BUFCNT),A ; AND SAVE IT
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CP ACIAB_BUFSZ - 5 ; BUFFER GETTING FULL?
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@@ -229,6 +236,7 @@ ACIAB_INT1:
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INC HL ; INCREMENT HEAD POINTER
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LD (ACIAB_HD),HL ; SAVE IT
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;
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ACIAB_INT2:
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; CHECK FOR MORE PENDING...
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IN A,(C) ; GET STATUS
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RRA ; READY BIT TO CF
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@@ -396,6 +404,14 @@ ACIA_OST:
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;
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ACIA_INITDEV:
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HB_DI ; AVOID CONFLICTS
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CALL ACIA_INITDEVX ; DO THE REAL WORK
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HB_EI ; INTS BACK ON
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RET ; DONE
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;
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ACIA_INITDEVX:
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;
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; THIS ENTRY POINT BYPASSES DISABLING/ENABLING INTS WHICH IS REQUIRED BY
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; PREINIT ABOVE. PREINIT IS NOT ALLOWED TO ENABLE INTS!
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;
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; PROGRAM THE ACIA CHIP
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LD C,(IY+3) ; COMMAND PORT
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@@ -428,7 +444,6 @@ ACIA_INITDEV:
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;
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#ENDIF
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;
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HB_EI ; READY FOR INTS AGAIN
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XOR A ; SIGNAL SUCCESS
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RET ; RETURN
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;
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