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@ -1,6 +1,6 @@ |
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; |
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;================================================================================================== |
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; ROMWBW GLOBAL MASTER CONFIGURATION FILE |
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; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: XXXXXX |
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;================================================================================================== |
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; |
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; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
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@ -45,14 +45,16 @@ |
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#DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES |
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE |
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#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED |
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#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION |
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#DEFINE DEFSERCFG SER_9600_8N1 ; DEFAULT SERIAL CONFIGURATION |
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; |
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#INCLUDE "cfg_MASTER.asm" |
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; |
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PLATFORM .SET PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RC2014|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|SZ180|DUO|HEATH|EPITX|MON|STDZ180|NABU|SZ80|N8PC] |
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CPUFAM .SET CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] |
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TURBOZ80 .SET FALSE ; TRUE FOR TURBO Z80 BOOSTING TO 20MHZ |
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TURBOZ80DISPRT .SET $00 ; DUMMY I/O PORT ADDRESS TO READ FROM, TO DISABLE TURBO BOOST FOR NEXT 31 CLOCK TICKS |
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NMOSCPU .SET FALSE ; NMOS CPU (ENABLES INT STATUS BUG WORKAROUND) |
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BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
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BIOS .SET BIOS_NONE ; HARDWARE BIOS: BIOS_[WBW|UNA] |
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BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
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HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) |
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USELZSA2 .SET FALSE ; ENABLE FONT COMPRESSION |
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@ -129,6 +131,9 @@ CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) |
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CTCOSC .SET 614400 ; CTC CLOCK FREQUENCY |
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; |
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PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER |
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PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS |
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PCFCLK .SET PCFCLK_12 ; PCF CLOCK BASE: PCFCLK_[3|443|6|8|12] |
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PCFTRNS .SET PCFTRNS_90 ; PCF TRANSFER SPEED: PCFTRNS_[90|45|11|15] |
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; |
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EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION |
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; |
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@ -222,6 +227,14 @@ SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK |
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SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED |
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; |
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DLPSERENABLE .SET FALSE ; DLPSER: ENABLE DLP-USB SERIAL DRIVER (DLPSER.ASM) |
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DLPSERCNT .SET 1 ; DLPSER: NUMBER OF DEVICES TO DETECT (1-2) |
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DLPSER0STAT .SET $FF ; DLPSER0: STATUS PORT ADDRESS |
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DLPSER0DATA .SET $FF ; DLPSER0: DATA PORT ADDRESS |
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DLPSER1STAT .SET $FF ; DLPSER1: STATUS PORT ADDRESS |
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DLPSER1DATA .SET $FF ; DLPSER1: DATA PORT ADDRESS |
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; |
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TSERENABLE .SET FALSE ; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM) |
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TSERCFG .SET SER_9600_8N1 ; TSER: SERIAL LINE CONFIG |
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; |
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DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) |
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DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) |
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@ -304,6 +317,27 @@ SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG |
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SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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; |
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SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) |
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SCCDEBUG .SET FALSE ; SCC: ENABLE DEBUG OUTPUT |
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SCCBOOT .SET 0 ; SCC: REBOOT ON RCV CHAR (0=DISABLED) |
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SCCCNT .SET 2 ; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP |
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SCCINTS .SET FALSE ; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3 |
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SCCPCLK .SET FALSE ; SCC: USE PROCESSOR CLOCK AS BAUD CLOCK |
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SCC0MODE .SET SCCMODE_SZ80 ; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80] |
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SCC0BASE .SET $FF ; SCC 0: REGISTERS BASE ADR |
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SCC0ACLK .SET 4915200 ; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SCC0ACFG .SET DEFSERCFG ; SCC 0A: SERIAL LINE CONFIG |
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SCC0ACTCC .SET -1 ; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SCC0BCLK .SET 4915200 ; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SCC0BCFG .SET DEFSERCFG ; SCC 0B: SERIAL LINE CONFIG |
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SCC0BCTCC .SET -1 ; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SCC1MODE .SET SCCMODE_SZ80 ; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80] |
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SCC1BASE .SET $FF ; SCC 1: REGISTERS BASE ADR |
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SCC1ACLK .SET 4915200 ; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SCC1ACFG .SET DEFSERCFG ; SCC 1A: SERIAL LINE CONFIG |
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SCC1ACTCC .SET -1 ; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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SCC1BCLK .SET 4915200 ; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 |
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SCC1BCFG .SET DEFSERCFG ; SCC 1B: SERIAL LINE CONFIG |
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SCC1BCTCC .SET -1 ; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE |
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; |
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XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG |
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; |
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@ -316,7 +350,7 @@ GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) |
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GDCMODE .SET GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH] |
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GDCMON .SET GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA] |
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TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
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TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] |
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TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|N8PC] |
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TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 |
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TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) |
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VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
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@ -325,6 +359,9 @@ VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) |
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SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) |
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EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) |
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TVGAENABLE .SET FALSE ; TVGA: ENABLE TRION VGA VIDEO DRIVER (TVGA.ASM) |
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XOSENABLE .SET FALSE ; XOSERA: ENABLE XOSERA VIDEO DRIVERS (XOSERA.ASM) |
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XOS_BASE .SET $20 ; XOSERA: I/O BASE ADDRESS (REQUIRES 32 BYTES) |
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XOSSIZ .SET V80X30 ; XOSERA: DISPLAY FORMAT [V80X30|V80X60] |
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; |
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MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
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MDROM .SET TRUE ; MD: ENABLE ROM DISK |
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@ -344,6 +381,7 @@ RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
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RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) |
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; |
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IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
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IDEDETECTMEDIA .SET FALSE ; IDE: PROBE FOR MEDIA IN MASTER UNIT, IF NOT DETECTED THEN DON'T ENABLE DRIVER |
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IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH |
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IDE0MODE .SET IDEMODE_NONE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] |
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@ -452,13 +490,25 @@ SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ |
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SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ |
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; |
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ESPSDENABLE .SET FALSE ; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM) |
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ESPSDTRACE .SET 1 ; ESPSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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ESPSD_USECD .SET FALSE ; ESPSD: ENABLE CARD DETECT SIGNAL USAGE |
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ESPSDCNT .SET 1 ; ESPSD: NUMBER OF BOARDS TO DETECT (1-2), 1-2 DEVICES PER BOARD |
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ESPSD0BASE .SET $80 ; ESPSD 0: ESP32 INTERFACE IO BASE ADR |
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ESPSD0DUAL .SET TRUE ; ESPSD 0: DUAL INTERFACE BOARD (DUAL SD) |
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ESPSD1BASE .SET $82 ; ESPSD 1: ESP32 INTERFACE IO BASE ADR |
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ESPSD1DUAL .SET TRUE ; ESPSD 1: DUAL INTERFACE BOARD (DUAL SD) |
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; |
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SCSIENABLE .SET FALSE ; SCSI: ENABLE 3580-BASED SCSI INTERFACE (SCSI.ASM) |
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SCSITRACE .SET 1 ; SCSI: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
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SCSICNT .SET 2 ; SCSI: NUMBER OF TARGET DEVICES (1-2) |
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SCSI_TID .SET 0 ; SCSI: TARGET DEVICE ID (0-6) |
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SCSI0_LUN .SET 0 ; SCSI0: TARGET LUN |
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SCSI1_LUN .SET 1 ; SCSI1: TARGET LUN |
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SCSICNT .SET 1 ; SCSI: NUMBER OF TARGET DEVICES (1-4) |
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SCSI0_TGT .SET 0 ; SCSI 0: TARGET DEVICE ID (0-6) |
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SCSI0_LUN .SET 0 ; SCSI 0: TARGET LUN (0-7) |
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SCSI1_TGT .SET 1 ; SCSI 1: TARGET DEVICE ID (0-6) |
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SCSI1_LUN .SET 0 ; SCSI 1: TARGET LUN (0-7) |
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SCSI2_TGT .SET 2 ; SCSI 2: TARGET DEVICE ID (0-6) |
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SCSI2_LUN .SET 0 ; SCSI 2: TARGET LUN (0-7) |
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SCSI3_TGT .SET 3 ; SCSI 3: TARGET DEVICE ID (0-6) |
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SCSI3_LUN .SET 0 ; SCSI 3: TARGET LUN (0-7) |
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; |
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PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
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PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD |
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@ -484,7 +534,7 @@ AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT |
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SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
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SPKPORT .SET RTCIO ; SPK: THE PORT WITH THE SPEAKER IO BIT |
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SPKSHADOW .SET HB_RTCVAL ; SPK: THE SHADOW VALUE FOR THE PORT THAT HAS TO BE MAINTAINED |
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SPKMASK .SET 00000100b ; SPK: THE BIT MASK TO ACTUALLY TOGGLE |
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SPKMASK .SET %00000100 ; SPK: THE BIT MASK TO ACTUALLY TOGGLE |
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; |
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DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) |
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DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS |
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@ -495,32 +545,39 @@ VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) |
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; |
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; EZ80 SETTINGS |
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; |
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EZ80TMR_NONE .SET 0 ; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS |
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EZ80TMR_INT .SET 1 ; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS |
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EZ80TMR_FIRM .SET 2 ; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED) |
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EZ80TMR_NONE .SET 0 ; DO NOT USE ON-BOARD TIMER TO GENERATE TICKS |
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EZ80TMR_INT .SET 1 ; MARSHALL TIMER TICK INTERRUPTS FROM EZ80 TO HBIOS |
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EZ80TMR_FIRM .SET 2 ; DELEGATE SYS TIMER HBIOS CALL TO EZ80 FIRMWARE (TIMER TICK INTS DISABLED) |
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; |
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EZ80UARTENABLE .SET FALSE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM) |
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EZ80RTCENABLE .SET FALSE ; EZ80 ON CHIP RTC |
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EZ80TIMER .SET EZ80TMR_FIRM ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM] |
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EZ80IOBASE .SET $FF ; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO |
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EZ80UARTENABLE .SET FALSE ; EZ80 UART: ENABLE EZ80 UART0 DRIVER (EZ80UART.ASM) |
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EZ80RTCENABLE .SET FALSE ; EZ80 ON CHIP RTC |
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EZ80TIMER .SET EZ80TMR_FIRM ; EZ80: TIMER TICK MODEL: EZ80TMR_[INT|FIRM] |
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EZ80IOBASE .SET $FF ; EZ80 I/O BASE ADDRESS FOR EXTERNAL IO |
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; |
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; BUS TIMING FOR PAGED MEMORY ACCESS (CS3) |
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EZ80_MEM_CYCLES .SET 3 ; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES |
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EZ80_MEM_MIN_NS .SET 100 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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EZ80_MEM_WS .SET 5 ; MEMORY WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT |
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EZ80_MEM_MIN_WS .SET 0 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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EZ80_MEM_CYCLES .SET 3 ; MEMORY BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES |
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EZ80_MEM_MIN_NS .SET 100 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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EZ80_MEM_MIN_BC .SET 1 ; MINIMUM BUS CYCLES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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; |
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; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2) |
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EZ80_IO_CYCLES .SET 4 ; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES |
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EZ80_IO_WS .SET 5 ; IO WAIT STATES (0-7) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_WAIT |
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EZ80_IO_MIN_NS .SET 320 ; CALCULATE AT BOOT TIME THE REQUIRED W/S OR B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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EZ80_IO_MIN_WS .SET 6 ; MINIMUM WAIT STATES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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EZ80_IO_CYCLES .SET 4 ; IO BUS CYCLES (1-15) TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CYCLES |
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EZ80_IO_MIN_NS .SET 250 ; CALCULATE AT BOOT TIME THE REQUIRED B/C, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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EZ80_IO_MIN_BC .SET 4 ; MINIMUM BUS CYCLES TO APPLY, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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; |
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; APPLY CYCLES, W/S OR CALCULATE CYCLES BASED ON DESIRED PERIOD |
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EZ80_WSMD_TYP .SET EZ80WSMD_CALC ; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES|WAIT] |
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; APPLY BUS CYCLES OR CALCULATE CYCLES BASED ON DESIRED PERIOD |
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EZ80_WSMD_TYP .SET EZ80WSMD_CALC ; BUS WAIT STATE CONFIG: EZ80WSMD_[CALC|CYCLES] |
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; |
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; BUS TIMING FOR ON CHIP ROM |
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; |
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EZ80_FLSH_WS .SET 1 ; WAIT STATES FOR ON CHIP FLASH (0-7) |
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EZ80_FLSH_MIN_NS .SET 60 ; MINIMUM WAIT STATES TO APPLY TO ON-CHIP FLASH, IF EZ80_WSMD_TYP = EZ80WSMD_CALC |
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EZ80_FWSMD_TYP .SET EZ80WSMD_CALC ; WAIT STATE TYPE: EZ80RMMD_[CALC|WAIT] (CYCLES NOT ALLOWED) |
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; |
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CHNATIVEENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE USB DRIVER |
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CHSCSIENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE MASS STORAGE DEVICES (REQUIRES CHNATIVEENABLE) |
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CHUFIENABLE .SET FALSE ; CH376: ENABLE CH376 NATIVE UFI FLOPPY DISK DEVICES (REQUIRES CHNATIVEENABLE) |
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CHNATIVEFORCE .SET FALSE ; CH376: DISABLE AUTO-DETECTION OF MODULE - ASSUME ITS INSTALLED (REQUIRES CHNATIVEENABLE) |
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CHNATIVEEZ80 .SET FALSE ; CH376: DELEGATE USB DRIVERS TO EZ80'S FIRMWARE |
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; |
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_CH376_DATA_PORT .SET $FF88 ; CH376: DATA PORT |
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_CH376_COMMAND_PORT .SET $FF89 ; CH376: COMMAND PORT |
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_USB_MODULE_LEDS .SET $FF8A ; CH376: LED CONTROL PORT |
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