diff --git a/Source/HBIOS/cfg_rc.asm b/Source/HBIOS/cfg_rc.asm
index 148a3f42..5ceec867 100644
--- a/Source/HBIOS/cfg_rc.asm
+++ b/Source/HBIOS/cfg_rc.asm
@@ -23,10 +23,16 @@ DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	FALSE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
-SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO/2 SUPPORT
-SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
 ACIAENABLE	.EQU	TRUE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
+SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT									;PS 
+SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP							;PS
+DEFSIOACFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG								;PS
+DEFSIOBCFG	.EQU	DEFSERCFG	; DEFAULT SERIAL LINE CONFIG								;PS
+DEFSIODIV	.EQU	1			; 1=RC2014/SMB, 2/4/8/16/32/64/128/256=ZP depending on jumper X5    ;PS
+DEFSIOCLK	.EQU	CPUOSC		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY		;PS
+SIODEBUG	.EQU	FALSE		;PS
+;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index 2e0750fa..ad320eed 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -8,7 +8,7 @@
 CPUOSC		.EQU	8000000		; CPU OSC FREQ
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SHOULD MATCH ABOVE)
-INTMODE		.EQU	0		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
+INTMODE		.EQU	1		; 0=NONE, 1=INT MODE 1, 2=INT MODE 2
 ;
 CRTACT		.EQU	FALSE		; CRT ACTIVATION AT STARTUP
 VDAEMU		.EQU	EMUTYP_ANSI	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
@@ -23,10 +23,16 @@ DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTCMODE_STD, DSRTCMODE_MFPIC
 ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTOSC		.EQU	1843200		; UART OSC FREQUENCY
-SIOENABLE	.EQU	FALSE		; TRUE FOR ZILOG SIO/2 SUPPORT
-SIOMODE		.EQU	SIOMODE_RC	; SIOMODE_RC, SIOMODE_SMB
 ACIAENABLE	.EQU	FALSE		; TRUE FOR MOTOROLA 6850 ACIA SUPPORT
 ;
+SIOENABLE	.EQU	TRUE		; TRUE FOR ZILOG SIO SUPPORT									;PS 
+SIOMODE		.EQU	SIOMODE_ZP	; SIOMODE_RC, SIOMODE_SMB, SIOMODE_ZP							;PS
+DEFSIOACFG	.EQU	SER_9600_8N1	; DEFAULT SERIAL LINE CONFIG								;PS
+DEFSIOBCFG	.EQU	SER_9600_8N1	; DEFAULT SERIAL LINE CONFIG								;PS
+DEFSIODIV	.EQU	8			; 1=RC2014, SMB, 2/4/8/16/32/64/128/256 for ZP depending on jumper X5                    ;PS
+DEFSIOCLK	.EQU	4915200		; 2457600/4915200=ZP,7372800=RC/SMB - SIO FIXED OSC FREQUENCY		;PS
+SIODEBUG	.EQU	TRUE		;PS
+;
 VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
 CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
diff --git a/Source/HBIOS/plt_rc.inc b/Source/HBIOS/plt_rc.inc
index b9b1764e..49bd0aa1 100644
--- a/Source/HBIOS/plt_rc.inc
+++ b/Source/HBIOS/plt_rc.inc
@@ -8,3 +8,4 @@ MPGSEL_3	.EQU	$7B	; BANK_3 PAGE SELECT REGISTER (WRITE ONLY)
 MPGENA		.EQU	$7C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC	    	.EQU	$C0	; RTC PORT address
+SIOBASE 	.EQU 	$80 ; RC OR SMB SIO DEFAULT
diff --git a/Source/HBIOS/plt_sbc.inc b/Source/HBIOS/plt_sbc.inc
index e74806a2..d0795108 100644
--- a/Source/HBIOS/plt_sbc.inc
+++ b/Source/HBIOS/plt_sbc.inc
@@ -19,3 +19,4 @@ MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
+SIOBASE	.EQU	$B0				; ZILOG PERIPHERALS DEFAULT				;PS
diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index 842b54b7..bf26c114 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -10,26 +10,418 @@
 ;    F   E   D   C   B   A   9   8     7   6   5   4   3   2   1   0
 ;       -- MSB (D REGISTER) --           -- LSB (E REGISTER) --
 ;
-SIO_DEBUG	.EQU	FALSE
 ;               
 SIO_NONE	.EQU	0
 SIO_SIO		.EQU	1
 ;               
 #IF (SIOMODE == SIOMODE_RC)
-SIOA_CMD	.EQU	$80
-SIOA_DAT	.EQU	$81
-SIOB_CMD	.EQU	$82
-SIOB_DAT	.EQU	$83
+SIOA_CMD	.EQU	SIOBASE + $00      ;PS	
+SIOA_DAT	.EQU	SIOBASE + $01      ;PS 
+SIOB_CMD	.EQU	SIOBASE + $02      ;PS 
+SIOB_DAT	.EQU	SIOBASE + $03      ;PS
 #ENDIF
 ;
 #IF (SIOMODE == SIOMODE_SMB)
-SIOA_CMD	.EQU	$82
-SIOA_DAT	.EQU	$80
-SIOB_CMD	.EQU	$83
-SIOB_DAT	.EQU	$81
+SIOA_CMD	.EQU	SIOBASE + $02      ;PS
+SIOA_DAT	.EQU	SIOBASE + $00      ;PS
+SIOB_CMD	.EQU	SIOBASE + $03      ;PS
+SIOB_WR4	.EQU	SIOBASE + $01      ;PS
 #ENDIF
 ;
+#IF (SIOMODE == SIOMODE_ZP)	;PS	
+SIOA_CMD	.EQU	SIOBASE + $06		;PS
+SIOA_DAT	.EQU	SIOBASE + $04		;PS 
+SIOB_CMD	.EQU	SIOBASE + $07		;PS 
+SIOB_DAT	.EQU	SIOBASE + $05		;PS 
+#ENDIF						            ;PS 
 ;
+
+#IF (DEFSIOCLK/DEFSIODIV/1 ==     75) 
+SIOBAUD1 .EQU  0 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==    150) 
+SIOBAUD1 .EQU  1 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==    300) 
+SIOBAUD1  .EQU  2 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==    600) 
+SIOBAUD1  .EQU  3 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==   1200) 
+SIOBAUD1  .EQU  4 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==   2400) 
+SIOBAUD1  .EQU  5 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==   4800) 
+SIOBAUD1  .EQU  6 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==   9600) 
+SIOBAUD1  .EQU  7 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==  19200) 
+SIOBAUD1  .EQU  8 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==  38400) 
+SIOBAUD1  .EQU  9 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==  76800) 
+SIOBAUD1  .EQU 10 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 == 153600) 
+SIOBAUD1  .EQU 11 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 == 307200) 
+SIOBAUD1  .EQU 12 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 == 614400) 
+SIOBAUD1  .EQU 13 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 =1228800) 
+SIOBAUD1  .EQU 14 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 =2457600) 
+SIOBAUD1  .EQU 15 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==    225) 
+SIOBAUD1  .EQU 16 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==    450) 
+SIOBAUD1  .EQU 17 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==    900) 
+SIOBAUD1  .EQU 18 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==   1800) 
+SIOBAUD1  .EQU 19 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==   3600) 
+SIOBAUD1  .EQU 20 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==   7200) 
+SIOBAUD1  .EQU 21 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==  14400) 
+SIOBAUD1  .EQU 22 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==  28800) 
+SIOBAUD1  .EQU 23 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 ==  57600) 
+SIOBAUD1  .EQU 24 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 == 115200) 
+SIOBAUD1  .EQU 25 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 == 230400) 
+SIOBAUD1  .EQU 26 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 == 921600) 
+SIOBAUD1  .EQU 28 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 =1843200) 
+SIOBAUD1  .EQU 29 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 =3686400) 
+SIOBAUD1  .EQU 30 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/1 =7372800) 
+SIOBAUD1  .EQU 31 
+#ENDIF
+
+
+#IF (DEFSIOCLK/DEFSIODIV/16 ==     75) 
+SIOBAUD1 .EQU  0 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==    150) 
+SIOBAUD2  .EQU  1 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==    300) 
+SIOBAUD2  .EQU  2 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==    600) 
+SIOBAUD2  .EQU  3 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==   1200) 
+SIOBAUD2  .EQU  4 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==   2400) 
+SIOBAUD2  .EQU  5 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==   4800) 
+SIOBAUD2  .EQU  6 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==   9600) 
+SIOBAUD2  .EQU  7 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==  19200) 
+SIOBAUD2  .EQU  8 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==  38400) 
+SIOBAUD2  .EQU  9 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==  76800) 
+SIOBAUD2  .EQU 10 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 == 153600) 
+SIOBAUD2  .EQU 11 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 == 307200) 
+SIOBAUD2  .EQU 12 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 == 614400) 
+SIOBAUD2  .EQU 13 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 =1228800) 
+SIOBAUD2  .EQU 14 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 =2457600) 
+SIOBAUD2  .EQU 15 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==    225) 
+SIOBAUD2  .EQU 16 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==    450) 
+SIOBAUD2  .EQU 17 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==    900) 
+SIOBAUD2  .EQU 18 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==   1800) 
+SIOBAUD2  .EQU 19 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==   3600) 
+SIOBAUD2  .EQU 20 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==   7200) 
+SIOBAUD2  .EQU 21 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==  14400) 
+SIOBAUD2  .EQU 22 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==  28800) 
+SIOBAUD2  .EQU 23 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==  57600) 
+SIOBAUD2  .EQU 24 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 == 115200) 
+SIOBAUD2  .EQU 25 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 == 230400) 
+SIOBAUD2  .EQU 26 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 == 460800) 
+SIOBAUD2  .EQU 27 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 == 921600) 
+SIOBAUD2  .EQU 28 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==1843200) 
+SIOBAUD2  .EQU 29 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==3686400) 
+SIOBAUD2  .EQU 30 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/16 ==7372800) 
+SIOBAUD2  .EQU 31 
+#ENDIF
+
+#IF (DEFSIOCLK/DEFSIODIV/32==     75) 
+SIOBAUD3  .EQU  0 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==    150) 
+SIOBAUD3  .EQU  1 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==    300) 
+SIOBAUD3  .EQU  2 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==    600) 
+SIOBAUD3  .EQU  3 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==   1200) 
+SIOBAUD3  .EQU  4 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==   2400) 
+SIOBAUD3  .EQU  5 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==   4800) 
+SIOBAUD3  .EQU  6 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==   9600) 
+SIOBAUD3  .EQU  7 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==  19200) 
+SIOBAUD3  .EQU  8 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==  38400) 
+SIOBAUD3  .EQU  9 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==  76800) 
+SIOBAUD3  .EQU 10 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32== 153600) 
+SIOBAUD3  .EQU 11 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32== 307200) 
+SIOBAUD3  .EQU 12 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32== 614400) 
+SIOBAUD3  .EQU 13 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==1228800) 
+SIOBAUD3  .EQU 14 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==2457600) 
+SIOBAUD3  .EQU 15 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==    225) 
+SIOBAUD3  .EQU 16 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==    450) 
+SIOBAUD3  .EQU 17 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==    900) 
+SIOBAUD3  .EQU 18 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==   1800) 
+SIOBAUD3  .EQU 19 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==   3600) 
+SIOBAUD3  .EQU 20 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==   7200) 
+SIOBAUD3  .EQU 21 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==  14400) 
+SIOBAUD3  .EQU 22 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==  28800) 
+SIOBAUD3  .EQU 23 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==  57600) 
+SIOBAUD3  .EQU 24 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32= 115200) 
+SIOBAUD3  .EQU 25 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32= 230400) 
+SIOBAUD3  .EQU 26 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32== 460800) 
+SIOBAUD3  .EQU 27 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32== 921600) 
+SIOBAUD3  .EQU 28 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==1843200) 
+SIOBAUD3  .EQU 29 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==3686400) 
+SIOBAUD3  .EQU 30 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/32==7372800) 
+SIOBAUD3  .EQU 31 
+#ENDIF
+
+#IF (DEFSIOCLK/DEFSIODIV/64==     75) 
+SIOBAUD4  .EQU  0 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==    150) 
+SIOBAUD4  .EQU  1 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==    300) 
+SIOBAUD4  .EQU  2 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==    600) 
+SIOBAUD4  .EQU  3 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==   1200) 
+SIOBAUD4  .EQU  4 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==   2400) 
+SIOBAUD4  .EQU  5 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==   4800) 
+SIOBAUD4  .EQU  6 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==  9600) 
+SIOBAUD4  .EQU  7 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==  19200) 
+SIOBAUD4  .EQU  8 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==  38400) 
+SIOBAUD4  .EQU  9 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==  76800) 
+SIOBAUD4  .EQU 10 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64== 153600) 
+SIOBAUD4  .EQU 11 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64== 307200) 
+SIOBAUD4  .EQU 12 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64== 614400) 
+SIOBAUD4  .EQU 13 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==1228800) 
+SIOBAUD4  .EQU 14 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==2457600) 
+SIOBAUD4  .EQU 15 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==    225) 
+SIOBAUD4  .EQU 16 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==    450) 
+SIOBAUD4  .EQU 17 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==    900) 
+SIOBAUD4  .EQU 18 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==   1800) 
+SIOBAUD4  .EQU 19 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==   3600) 
+SIOBAUD4  .EQU 20 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==   7200) 
+SIOBAUD4  .EQU 21 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==  14400) 
+SIOBAUD4  .EQU 22 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==  28800) 
+SIOBAUD4  .EQU 23 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==  57600) 
+SIOBAUD4  .EQU 24 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64== 115200) 
+SIOBAUD4  .EQU 25 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64== 230400) 
+SIOBAUD4  .EQU 26 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64== 460800) 
+SIOBAUD4  .EQU 27 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64== 921600) 
+SIOBAUD4  .EQU 28 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==1843200) 
+SIOBAUD4  .EQU 29 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==3686400) 
+SIOBAUD4  .EQU 30 
+#ENDIF
+#IF (DEFSIOCLK/DEFSIODIV/64==7372800) 
+SIOBAUD4  .EQU 31 
+#ENDIF
+
 ;
 SIO_PREINIT:
 ;
@@ -98,7 +490,7 @@ SIO_INITUNIT:
 	LD	HL,SIO_DEV		; POINT TO CURRENT UART DEVICE NUM
 	LD	A,(HL)			; PUT IN ACCUM
 	INC	(HL)			; INCREMENT IT (FOR NEXT LOOP)
-	LD	(IY),A			; UDPATE UNIT NUM
+	LD	(IY),A			; UPDATE UNIT NUM
 	
 	; SET DEFAULT CONFIG
 	LD	DE,-1			; LEAVE CONFIG ALONE
@@ -314,6 +706,10 @@ SIO_OUT:
 #IF (SIOMODE == SIOMODE_SMB)
 	DEC C			; DECREMENT CMD PORT TWICE TO GET DATA PORT
 	DEC C
+#ENDIF
+#IF (SIOMODE == SIOMODE_ZP)
+	DEC C			; DECREMENT CMD PORT TWICE TO GET DATA PORT
+	DEC C
 #ENDIF
 	OUT	(C),E			; SEND CHAR FROM E
 	XOR	A			; SIGNAL SUCCESS
@@ -358,9 +754,155 @@ SIO_OST:
 ;
 ;
 SIO_INITDEV:
+;
+	; TEST FOR -1 WHICH MEANS USE CURRENT CONFIG (JUST REINIT)			; PS
+	LD	A,D			; TEST DE FOR										; PS
+	AND	E			; ... VALUE OF -1									; PS
+	INC	A			; ... SO Z SET IF -1								; PS
+	JR	NZ,SIO_INITDEV1	; IF DE == -1, REINIT CURRENT CONFIG		; PS
+;
+	; LOAD EXISTING CONFIG TO REINIT									;PS
+	LD	E,(IY + 4)		; LOW BYTE										;PS
+	LD	D,(IY + 5)		; HIGH BYTE ;PS
+
+; CHANGE INIT TABLE
+;
+SIO_INITDEV1:
+	PUSH	DE		; SAVE CONFIG
+
+	LD	A,D			; GET CONFIG MSB
+	AND	$1F			; ISOLATE ENCODED BAUD RATE
+
+#IF (SIODEBUG)
+	PUSH AF
+	PRTS(" ENCODE[$")
+	CALL	PRTHEXBYTE
+	PRTC(']')
+	POP AF
+#ENDIF
+	
+	CP SIOBAUD1		; We set the divider and the lower bit (d2) of the baud rate here
+	LD D,$04		; /1 N,8,1
+	JR Z,BROK
+	CP SIOBAUD2
+	LD D,$44		; /16 N,8,1
+	JR Z,BROK
+	CP SIOBAUD3
+	LD D,$84		; /32 N,8,1
+	JR Z,BROK
+	CP SIOBAUD4
+	LD D,$C4		; /64 N,8,1
+	JR Z,BROK		; RET NZ
+
+#IF (SIODEBUG)
+	PUSH AF
+	PRTS(" BR FAIL[$")	
+	CALL PRTHEXBYTE
+	PRTC(']')
+	POP AF
+#ENDIF
+;
+EXITINIT:
+	POP DE
+	RET				; NZ status here indicating fail / invalid baud rate.
+	
+BROK:
+	LD	A,E
+	AND $E0
+	JR NZ,EXITINIT	; NZ status here indicates dtr, xon, parity mark or space so return
+
+	LD A,E			;  set stop bit (d3) and add divider
+	AND $04
+	RLA
+	OR D			; carry gets reset here
+	LD D,A
+	
+	
+	LD A,E			; get the parity bits
+	SRL A			; move them to bottom two bits
+	SRL A			; we know top bits are zero from previous test
+	SRL A			; add stop bits
+	OR D 			; carry = 0
+	
+	LD	BC,SIO_INITVALS+3
+	LD (BC),A
+	
+#IF (SIODEBUG)
+	PUSH AF
+	PRTS(" MODE[$")
+	CALL	PRTHEXBYTE
+	PRTC(']')
+	POP AF
+#ENDIF
+
+; THE # DATA BITS NEED TO BE CONVERTED FROM THE 
+; ROMWBW REPRESENTATION TO THE SIO XILOG CODING
+	
+;	XOR A
+;	RR E			; d0 of bits into carry
+;	RR A			; d0 into msb
+;	RR E			; d1 of bits into carry
+;	RR A			; d1 into msb
+;;	SCF				; 1 into msb
+;	RR A
+;	OR $8a
+
+	LD A,E
+
+	#IF (SIODEBUG)
+	PUSH AF
+	PRTS(" BITS[$")
+	CALL	PRTHEXBYTE
+	PRTC(']')
+	POP AF
+#ENDIF	
+					; 112233445566d1d0 CC
+	RRA				; CC112233445566d1 d0
+	RRA				; d0CC112233445566 d1
+	RRA 			; d1d0CC1122334455 66
+	LD D,A
+	RRA				; 66d1d0CC11223344 55
+	AND $60			; 0011110000000000 00
+	OR $8a
+;	
+; SET TRANSMIT DATA BITS WR5	
+;
+	LD	BC,SIO_INITVALS+11
+	LD (BC),A	
+
+#IF (SIODEBUG)
+	PUSH AF
+	PRTS(" TXDATA[$")
+	CALL	PRTHEXBYTE
+	PRTC(']')
+	POP AF
+#ENDIF	
+;
+; SET RECEIVE DATA BITS WR3 
+;	
+	LD A,D
+	AND $C0
+	OR $01
+	
+	LD	BC,SIO_INITVALS+9
+	LD (BC),A	
+
+#IF (SIODEBUG)
+	PUSH AF
+	PRTS(" RXDATA[$")
+	CALL	PRTHEXBYTE
+	PRTC(']')
+	POP AF
+#ENDIF	
+	
+	POP	DE			; RESTORE CONFIG
+
+	LD	(IY + 4),E		; SAVE LOW WORD
+	LD	(IY + 5),D		; SAVE HI WORD
+	
 	HB_DI				; AVOID CONFLICTS
 ;
-	; PROGRAM THE SIO/2 CHIP CHANNEL
+	; PROGRAM THE SIO CHIP CHANNEL
 	LD	C,(IY + 3)		; COMMAND PORT
 	LD	HL,SIO_INITVALS		; POINT TO INIT VALUES
 	LD	B,SIO_INITLEN		; COUNT OF BYTES TO WRITE
@@ -393,11 +935,11 @@ SIO_INITDEV:
 ;
 SIO_INITVALS:
 	.DB	$00, $18	; WR0: CHANNEL RESET
-	.DB	$04, $C4	; WR4: CLK/64=115200 BAUD, NO PARITY, 1 STOP BIT
+	.DB	$04, $00	; WR4:  CLK BAUD PARITY STOP BIT ; PST
 	.DB	$01, $18	; WR1: INTERRUPT ON ALL RECEIVE CHARACTERS
 	.DB	$02, IVT_SER0	; WR2: INTERRUPT VECTOR OFFSET
 	.DB	$03, $C1	; WR3: 8 BIT RCV, RX ENABLE
-	.DB	$05, $EA	; WR5: DTR, 8 BITS SEND,  TX ENABLE, RTS
+	.DB	$05, $EA	; WR5: DTR, 8 BITS SEND,  TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc)
 SIO_INITLEN	.EQU	$ - SIO_INITVALS
 ;
 ;
@@ -503,20 +1045,20 @@ SIOB_BUFSZ	.EQU	$ - SIOB_BUF	; SIZE OF RING BUFFER
 ; SIO PORT TABLE
 ;
 SIO_CFG:
-	; SIO/2 CHANNEL A
+	; SIO CHANNEL A
 	.DB	0			; DEVICE NUMBER (SET DURING INIT)
 	.DB	0			; SIO TYPE (SET DURING INIT)
 	.DB	0			; SIO CHANNEL (A)
 	.DB	SIOA_CMD		; BASE PORT (CMD PORT)
-	.DW	DEFSERCFG		; LINE CONFIGURATION
+	.DW	DEFSIOACFG		; LINE CONFIGURATION
 	.DW	SIOA_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
-	; SIO/2 CHANNEL B
+	; SIO CHANNEL B
 	.DB	0			; DEVICE NUMBER (SET DURING INIT)
 	.DB	0			; SIO TYPE (SET DURING INIT)
 	.DB	1			; SIO CHANNEL (B)
 	.DB	SIOB_CMD		; BASE PORT (CMD PORT)
-	.DW	DEFSERCFG		; LINE CONFIGURATION
+	.DW	DEFSIOBCFG		; LINE CONFIGURATION
 	.DW	SIOB_RCVBUF		; POINTER TO RCV BUFFER STRUCT
 ;
 SIO_CNT	.EQU	($ - SIO_CFG) / 8
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 96cd946a..e2e497d5 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -139,6 +139,8 @@ SER_STOP2	.EQU	1 << 2
 ; SERIAL BAUD RATES ENCODED AS V = 75 * 2^X * 3^Y
 ; AND STORED AS 5 BITS: YXXXX
 ;
+SER_BAUD75	.EQU	$00 << 8														;PS
+SER_BAUD150	.EQU	$01 << 8														;PS
 SER_BAUD300	.EQU	$02 << 8
 SER_BAUD600	.EQU	$03 << 8
 SER_BAUD1200	.EQU	$04 << 8
@@ -148,14 +150,35 @@ SER_BAUD9600	.EQU	$07 << 8
 SER_BAUD19200	.EQU	$08 << 8
 SER_BAUD38400	.EQU	$09 << 8
 SER_BAUD76800	.EQU	$0A << 8
+SER_BAUD153600	.EQU	$0B << 8													;PS
+SER_BAUD307200	.EQU	$0C << 8													;PS
+SER_BAUD614400	.EQU	$0D << 8													;PS
+SER_BAUD1228800	.EQU	$0E << 8													;PS
+SER_BAUD2457600	.EQU	$0F << 8													;PS
+SER_BAUD225	.EQU	$10 << 8														;PS
+SER_BAUD450	.EQU	$11 << 8														;PS
+SER_BAUD900	.EQU	$12 << 8														;PS
+SER_BAUD1800	.EQU	$13 << 8													;PS
+SER_BAUD3600	.EQU	$14 << 8													;PS
+SER_BAUD7200	.EQU	$15 << 8													;PS
+SER_BAUD14400	.EQU	$16 << 8													;PS
+SER_BAUD28800	.EQU	$17 << 8													;PS
+SER_BAUD57600	.EQU	$18 << 8													;PS
+
 SER_BAUD115200	.EQU	$19 << 8
 SER_BAUD230400	.EQU	$1A << 8
 SER_BAUD460800	.EQU	$1B << 8
+SER_BAUD921600	.EQU	$1C << 8													;PS
+SER_BAUD1843200	.EQU	$1D << 8													;PS
+SER_BAUD3686400	.EQU	$1E << 8													;PS
+SER_BAUD7372800	.EQU	$1F << 8													;PS
 ;
 SER_XON		.EQU	1 << 6
 SER_DTR		.EQU	1 << 7
 SER_RTS		.EQU	1 << 13
 ;
+SER_75_8N1	.EQU	SER_BAUD75 | SER_DATA8 | SER_PARNONE | SER_STOP1				;PS
+SER_150_8N1	.EQU	SER_BAUD150 | SER_DATA8 | SER_PARNONE | SER_STOP1				;PS
 SER_300_8N1	.EQU	SER_BAUD300 | SER_DATA8 | SER_PARNONE | SER_STOP1
 SER_600_8N1	.EQU	SER_BAUD600 | SER_DATA8 | SER_PARNONE | SER_STOP1
 SER_1200_8N1	.EQU	SER_BAUD1200 | SER_DATA8 | SER_PARNONE | SER_STOP1
@@ -165,9 +188,27 @@ SER_9600_8N1	.EQU	SER_BAUD9600 | SER_DATA8 | SER_PARNONE | SER_STOP1
 SER_19200_8N1	.EQU	SER_BAUD19200 | SER_DATA8 | SER_PARNONE | SER_STOP1
 SER_38400_8N1	.EQU	SER_BAUD38400 | SER_DATA8 | SER_PARNONE | SER_STOP1
 SER_76800_8N1	.EQU	SER_BAUD76800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_153600_8N1	.EQU	SER_BAUD153600 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_307200_8N1	.EQU	SER_BAUD307200 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_614400_8N1	.EQU	SER_BAUD614400 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_1228800_8N1	.EQU	SER_BAUD1228800 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_2457600_8N1	.EQU	SER_BAUD2457600 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_225_8N1	.EQU	SER_BAUD225 | SER_DATA8 | SER_PARNONE | SER_STOP1				;PS
+SER_450_8N1	.EQU	SER_BAUD450 | SER_DATA8 | SER_PARNONE | SER_STOP1				;PS
+SER_900_8N1	.EQU	SER_BAUD900 | SER_DATA8 | SER_PARNONE | SER_STOP1				;PS
+SER_1800_8N1	.EQU	SER_BAUD1800 | SER_DATA8 | SER_PARNONE | SER_STOP1			;PS
+SER_3600_8N1	.EQU	SER_BAUD3600 | SER_DATA8 | SER_PARNONE | SER_STOP1			;PS
+SER_7200_8N1	.EQU	SER_BAUD7200 | SER_DATA8 | SER_PARNONE | SER_STOP1			;PS
+SER_14400_8N1	.EQU	SER_BAUD14400 | SER_DATA8 | SER_PARNONE | SER_STOP1			;PS
+SER_28800_8N1	.EQU	SER_BAUD28800 | SER_DATA8 | SER_PARNONE | SER_STOP1			;PS
+SER_57600_8N1	.EQU	SER_BAUD57600 | SER_DATA8 | SER_PARNONE | SER_STOP1			;PS
 SER_115200_8N1	.EQU	SER_BAUD115200 | SER_DATA8 | SER_PARNONE | SER_STOP1
 SER_230400_8N1	.EQU	SER_BAUD230400 | SER_DATA8 | SER_PARNONE | SER_STOP1
 SER_460800_8N1	.EQU	SER_BAUD460800 | SER_DATA8 | SER_PARNONE | SER_STOP1
+SER_921600_8N1	.EQU	SER_BAUD921600 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_1843200_8N1	.EQU	SER_BAUD1843200 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_3686400_8N1	.EQU	SER_BAUD3686400 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
+SER_7372800_8N1	.EQU	SER_BAUD7372800 | SER_DATA8 | SER_PARNONE | SER_STOP1		;PS
 ;
 ; INTERRUPT VECTOR TABLE ENTRY OFFSETS (Z180 COMPATIBLE)
 ;