Browse Source

Merge branch 'master' of https://github.com/lesbird/RomWBW

pull/409/head
Les Bird 1 year ago
parent
commit
17f1d1cb99
  1. 2
      Doc/ChangeLog.txt
  2. BIN
      Doc/Hard Disk Anatomy.pdf
  3. BIN
      Doc/RomWBW Applications.pdf
  4. BIN
      Doc/RomWBW Disk Catalog.pdf
  5. BIN
      Doc/RomWBW Errata.pdf
  6. BIN
      Doc/RomWBW System Guide.pdf
  7. BIN
      Doc/RomWBW User Guide.pdf
  8. 144
      Doc/Testing Notes.txt
  9. 2
      ReadMe.md
  10. 2
      ReadMe.txt
  11. BIN
      Source/Doc/Graphics/BankSwitchedMemory.pdf
  12. BIN
      Source/Doc/Graphics/BankSwitchedMemory.png
  13. 366
      Source/Doc/Graphics/BankSwitchedMemory.svg
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      Source/Doc/Graphics/BankSwitchedMemory.vsd
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      Source/Doc/Graphics/CharacterEmulationVideoServices.pdf
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      Source/Doc/Graphics/CharacterEmulationVideoServices.png
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      Source/Doc/Graphics/CharacterEmulationVideoServices.svg
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      Source/Doc/Graphics/CharacterEmulationVideoServices.vsd
  19. BIN
      Source/Doc/Graphics/Hard Disk Anatomy.vsd
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      Source/Doc/Graphics/Logo.pdf
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      Source/Doc/Graphics/Logo.png
  22. 59
      Source/Doc/Graphics/Logo.svg
  23. 0
      Source/Doc/Graphics/Logo.vsdx
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      Source/Doc/Graphics/Panel.pdf
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      Source/Doc/Graphics/Panel.png
  26. 369
      Source/Doc/Graphics/Panel.svg
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      Source/Doc/Graphics/hd1k.pdf
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      Source/Doc/Graphics/hd1k.png
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      Source/Doc/Graphics/hd1k.svg
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      Source/Doc/Graphics/hd512.pdf
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      Source/Doc/Graphics/hd512.png
  32. 236
      Source/Doc/Graphics/hd512.svg
  33. BIN
      Source/Doc/RomWBW Disk Layouts.xlsx
  34. 104
      Source/Doc/SystemGuide.md
  35. 220
      Source/Doc/UserGuide.md
  36. 13
      Source/FZ80/Build.cmd
  37. 21
      Source/FZ80/Makefile
  38. 46
      Source/HBIOS/Build.cmd
  39. 62
      Source/HBIOS/Build.sh
  40. 0
      Source/HBIOS/Config/RCZ180_ext_std.asm
  41. 0
      Source/HBIOS/Config/RCZ180_nat_std.asm
  42. 0
      Source/HBIOS/Config/RCZ180_z1rcc_std.asm
  43. 0
      Source/HBIOS/Config/RCZ280_ext_std.asm
  44. 0
      Source/HBIOS/Config/RCZ280_nat_std.asm
  45. 0
      Source/HBIOS/Config/RCZ280_zz80mb_std.asm
  46. 0
      Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm
  47. 0
      Source/HBIOS/Config/RCZ280_zzrcc_std.asm
  48. 0
      Source/HBIOS/Config/RCZ80_easy_std.asm
  49. 0
      Source/HBIOS/Config/RCZ80_kio_std.asm
  50. 0
      Source/HBIOS/Config/RCZ80_skz_std.asm
  51. 0
      Source/HBIOS/Config/RCZ80_tiny_std.asm
  52. 0
      Source/HBIOS/Config/RCZ80_zrc512_std.asm
  53. 0
      Source/HBIOS/Config/RCZ80_zrc_ram_std.asm
  54. 0
      Source/HBIOS/Config/RCZ80_zrc_std.asm
  55. 0
      Source/HBIOS/Config/SCZ180_sc126_std.asm
  56. 0
      Source/HBIOS/Config/SCZ180_sc130_std.asm
  57. 0
      Source/HBIOS/Config/SCZ180_sc131_std.asm
  58. 0
      Source/HBIOS/Config/SCZ180_sc140_std.asm
  59. 0
      Source/HBIOS/Config/SCZ180_sc503_std.asm
  60. 0
      Source/HBIOS/Config/SCZ180_sc700_std.asm
  61. 1
      Source/HBIOS/cfg_duo.asm
  62. 1
      Source/HBIOS/cfg_dyno.asm
  63. 1
      Source/HBIOS/cfg_epitx.asm
  64. 1
      Source/HBIOS/cfg_fz80.asm
  65. 1
      Source/HBIOS/cfg_heath.asm
  66. 1
      Source/HBIOS/cfg_master.asm
  67. 1
      Source/HBIOS/cfg_mbc.asm
  68. 1
      Source/HBIOS/cfg_mk4.asm
  69. 1
      Source/HBIOS/cfg_mon.asm
  70. 1
      Source/HBIOS/cfg_n8.asm
  71. 1
      Source/HBIOS/cfg_nabu.asm
  72. 1
      Source/HBIOS/cfg_rcz180.asm
  73. 1
      Source/HBIOS/cfg_rcz280.asm
  74. 1
      Source/HBIOS/cfg_rcz80.asm
  75. 1
      Source/HBIOS/cfg_s100.asm
  76. 1
      Source/HBIOS/cfg_sbc.asm
  77. 1
      Source/HBIOS/cfg_scz180.asm
  78. 1
      Source/HBIOS/cfg_z80retro.asm
  79. 1
      Source/HBIOS/hbios.asm
  80. 110
      Source/HBIOS/sd.asm
  81. 137
      Source/HBIOS/sio.asm
  82. 5
      Source/Images/Build.cmd
  83. BIN
      Source/Images/Common/Z3/u14/UMAP18.CFG
  84. BIN
      Source/Images/Common/Z3/u15/UMAP.COM
  85. 6
      Source/Images/Makefile
  86. 19
      Source/Images/d_msxroms1/ReadMe.txt
  87. BIN
      Source/Images/d_msxroms1/u0/10YAR000.ROM
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      Source/Images/d_msxroms1/u0/3DGOL002.ROM
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      Source/Images/d_msxroms1/u0/3DGOL003.ROM
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      Source/Images/d_msxroms1/u0/3DTEN004.ROM
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      Source/Images/d_msxroms1/u0/ACTMA007.ROM
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      Source/Images/d_msxroms1/u0/ADVEN008.ROM
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      Source/Images/d_msxroms1/u0/AEJAP005.ROM
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      Source/Images/d_msxroms1/u0/ALBAT009.ROM
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      Source/Images/d_msxroms1/u0/ALCAZ010.ROM
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      Source/Images/d_msxroms1/u0/ALIBA011.ROM
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      Source/Images/d_msxroms1/u0/ALIEN012.ROM
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      Source/Images/d_msxroms1/u0/ALPHA014.ROM
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      Source/Images/d_msxroms1/u0/ALPHA015.ROM
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      Source/Images/d_msxroms1/u0/AMERI016.ROM

2
Doc/ChangeLog.txt

@ -29,6 +29,8 @@ Version 3.5
- WBW: Added support for Les Bird's Dual 16C550 UART module - WBW: Added support for Les Bird's Dual 16C550 UART module
- WBW: Refactor UART driver for more flexible configuration - WBW: Refactor UART driver for more flexible configuration
- M?R: Added hour/minute/second display to timer app - M?R: Added hour/minute/second display to timer app
- WBW: Substantial customization of NZ-COM disk image
- WBW: Refactor build post-processing (ZRC, ZZRCC, etc.)
Version 3.4 Version 3.4
----------- -----------

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Doc/Hard Disk Anatomy.pdf

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Doc/RomWBW Applications.pdf

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Doc/RomWBW Disk Catalog.pdf

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Doc/RomWBW Errata.pdf

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Doc/RomWBW System Guide.pdf

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Doc/RomWBW User Guide.pdf

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144
Doc/Testing Notes.txt

@ -1,144 +0,0 @@
SIMH (X)
----
- Test UART driver
- Test HDSK driver
Zeta 1 (X)
------
- Test UART driver
- Test PPP detection (startup w/ and w/o PPP)
- Test boot to CRT
- Test PPPSD driver
- Test PPPCON driver (video & kbd)
- Test FD driver
- Test FDU app
Zeta 2 (X)
------
- Test UART driver
- Test PPP detection (startup w/ and w/o PPP)
- Test boot to CRT
- Test PPPSD driver
- Test PPPCON driver (video & kbd)
- Test FD driver
- Test FDU app
RCBus (X)
------
- Test SIO driver (Serial Module)
- Test ACIA driver (Dual Serial Module)
- Test IDE driver (Compact Flash Module)
- Test PPIDE driver (IDE Module)
- Test FD driver (SMC and WDC)
- Test FDU app (SMC and WDC)
N8-2312 (X)
-------
- Test ASCI driver
- Test SD driver (CSIO mode)
- Test FD driver
- Test FDU app
- Test TMS driver (video & kbd)
N8-2511 (X)
-------
- Test ASCI driver
- Test SD driver (Juha mode)
- Test FD driver
- Test FDU app
- Test TMS driver (video & kbd)
SBC (X)
---
- Test UART driver
- Test PPIDE driver
- Test PPISD driver
- Test PRP detection
- Test boot to CRT console
MK4 (X)
---
- Test ASCI driver
- Test IDE driver
- Test SD driver
- Test PRP detection
RAMF (X)
----
- Test RAMF driver
PRP (X)
---
- Test PRPSD driver
- Test PRPCON driver (video & kbd)
SCG (X)
---
- Test TMS driver (video)
VDU (X)
---
- Test CVDU driver (video & kbd)
CVDU (X)
----
- Test CVDU driver (video & kbd)
VGA (X)
---
- Test VGA driver (video & kbd)
DIO (X)
---
- Test FD driver
- Test FDU app
- Test IDE driver
DIO3 (X)
----
- Test FD driver
- Test FDU app
- Test PPIDE driver
DIDE (X)
----
- Test FD driver
- Test FDU app
- Test IDE driver
DSD (X)
---
- Test SD driver
4UART (X)
-----
- Test UART driver
UNA (X)
---
- General Startup
- Boot from disk functionality
- Image loading
- Monitor
- XM app
- ASSIGN app
- MODE app
- SYSCOPY app
- OSLDR app
- FDU app
- FDISK80 app
GENERAL (X)
-------
- Boot to ROM
- Boot to Disk
- Boot to Monitor
- XM app
- XM port auto-detect
- ASSIGN app
- MODE app
- SYSCOPY app
- FDU app
- FDISK80 app
- TUNE app

2
ReadMe.md

@ -3,7 +3,7 @@
**RomWBW ReadMe** \ **RomWBW ReadMe** \
Version 3.5 \ Version 3.5 \
Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \ Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
15 Jul 2024
21 Aug 2024
# Overview # Overview

2
ReadMe.txt

@ -1,6 +1,6 @@
RomWBW ReadMe RomWBW ReadMe
Wayne Warthen (wwarthen@gmail.com) Wayne Warthen (wwarthen@gmail.com)
15 Jul 2024
21 Aug 2024

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Source/Doc/RomWBW Disk Layouts.xlsx

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104
Source/Doc/SystemGuide.md

@ -126,6 +126,7 @@ execution.
![Bank Switched Memory Layout](Graphics/BankSwitchedMemory){ width=100% } ![Bank Switched Memory Layout](Graphics/BankSwitchedMemory){ width=100% }
## Bank Id ## Bank Id
RomWBW utilizes a specific assignment of memory banks for dedicated RomWBW utilizes a specific assignment of memory banks for dedicated
@ -262,6 +263,106 @@ Common Bank:
It is a fixed mapping that is never changed in normal RomWBW operation It is a fixed mapping that is never changed in normal RomWBW operation
hence the name "Common". hence the name "Common".
# Disk Layout
RomWBW supports two hard disk layouts: the Classic layout used by
RomWBW with 512 directory entries per slice and a Modern layout with
1024 directory entries per slice. These layouts are referred to as
hd512 and hd1k respectively.
WARNING: You **can not** mix the two hard disk layouts on one hard
disk device. You can use different layouts on different hard disk
devices in a single system though.
RomWBW determines which of the hard disk layouts to use for a given
hard disk device based on whether there is a RomWBW hard disk
partition on the disk containing the slices. If there is no RomWBW
partition, then RomWBW will assume the 512 directory entry format for
all slices and will assume the slices start at the first sector of
the hard disk. If there is a RomWBW partition on the hard disk
device, then RomWBW will assume the 1024 directory entry format for
all slices and will assume the slices are located in the defined
partition.
RomWBW supports up to 256 CP/M slices (0-255). Under hd512, the slices
begin at the start of the hard disk. Under hd1k, the slices reside
within partition type 0x2E.
RomWBW accesses all hard disks using Logical Block Addressing (pure
sector offset). When necessary, RomWBW simulates the following disk
geometry for operating systems:
- Sector = 512 Bytes
- Track = 16 Sectors (8KB per Track)
- Cylinder = 16 Tracks (256 Sectors per Cylinder, 128KB per Cylinder)
If one is used, the FAT Partition must not overlap the CP/M slices.
The FAT partition does not need to start immediately after the CP/M
slices nor does it need to extend to the end of the hard disk. Its
location and size are entirely determined by its corresponding
partition table entry.
Drive letters in CP/M are ASSIGNed to the numbered slices as desired.
At boot, RomWBW automatically assigns up to 8 slices to drive letters
starting with the first available drive letter (typically C:).
Microsoft Windows will assign a single drive letter to the FAT partition
when the CF/SD Card is inserted. The drive letter assigned has no
relationship to the CP/M drive letters assigned to CP/M slices.
In general, Windows, MacOS, or Linux know nothing about the CP/M slices
and CP/M knows nothing about the FAT partition. However, the FAT
application can be run under CP/M to access the FAT partition
programmatically.
A CP/M slice is (re)initialized using the CP/M command CLRDIR. A CP/M
slice can be made bootable by copying system image to the System Area
using SYSCOPY.
The FAT partition can be created from CP/M using the FDISK80 application.
The FAT partition can be initialized using the FAT application from CP/M
using the command `FAT FORMAT n:` where n is the RomWBW disk unit
number containing the FAT partition to be formatted.
## Modern Disk Layout (hd1k)
![Modern Disk Layout](Graphics/hd1k)
The CP/M filesystem on a Modern disk will accommodate 1,024 directory
entries.
The CP/M slices reside entirely within a hard disk partition of type
0x2E. The number of slices is determined by the number of slices that
fit within the partition spaces allocated up to the maximum of 256.
## Classic Disk Layout (hd512)
![Classic Disk Layout](Graphics/hd512)
The CP/M filesystem on a Classic disk will accommodate 512 directory
entries.
The CP/M slices reside on the hard disk starting at the first sector
of the hard disk. The number of CP/M slices is not explicitly recorded
anywhere on the hard disk. It is up to the system user to know how
many slices are being used based on the size of the hard disk media
and/or the start of a FAT partition.
A partition table may exist within the first sector of the first
slice. For Classic disks, the partition table defines only the
location and size of the FAT partition. The Partition Table does
not control the location or number of CP/M slices in any way.
The Partition Table resides in a sector that is shared with the System
Area of CP/M Slice 0. However, the RomWBW implementation of CP/M takes
steps to avoid changing or corrupting the Partition Table area.
The FAT partition can be created from CP/M using the FDISK80
application. The user is responsible for ensuring that the start of the
FAT partition does not overlap with the area they intend to use for
CP/M slices. FDISK80 has a Reserve option to assist with this.
# System Boot Process # System Boot Process
A multi-phase boot strategy is employed. This is necessary because at A multi-phase boot strategy is employed. This is necessary because at
@ -2409,6 +2510,9 @@ a double-word binary value. The frequency of the system timer in Hertz
is returned in Frequency (C). The returned Status (A) is a standard HBIOS is returned in Frequency (C). The returned Status (A) is a standard HBIOS
result code. result code.
The tick count is a 32 bit binary value. It will rollover to zero
if the maximum value for a 32 bit number is reached.
Note that not all hardware configuration have a system timer. You Note that not all hardware configuration have a system timer. You
can determine if a timer exists by calling this function repeatedly can determine if a timer exists by calling this function repeatedly
to see if it is incrementing. to see if it is incrementing.

220
Source/Doc/UserGuide.md

@ -222,46 +222,46 @@ by RomWBW along with the standard pre-built ROM image(s). RomWBW does
allow for the creation of ROM images with custom configurations. This allow for the creation of ROM images with custom configurations. This
is discussed in [Customizing RomWBW]. is discussed in [Customizing RomWBW].
| **Description** | **Bus** | **ROM Image File** | **Baud Rate** |
|----------------------------------------------------------------|---------|-----------------------|--------------:|
| [RetroBrew Z80 SBC]^1^ | ECB | SBC_std.rom | 38400 |
| [RetroBrew Z80 SimH]^1^ | - | SBC_simh.rom | 38400 |
| [RetroBrew N8 Z180 SBC]^1^ (date code >= 2312) | ECB | N8_std.rom | 38400 |
| [Zeta Z80 SBC]^2^, ParPortProp | - | ZETA_std.rom | 38400 |
| [Zeta V2 Z80 SBC]^2^, ParPortProp | - | ZETA2_std.rom | 38400 |
| [Mark IV Z180 SBC]^3^ | ECB | MK4_std.rom | 38400 |
| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 |
| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM, KIO | RCBus | RCZ80_kio.rom | 115200 |
| [RCBus Z180 CPU Module]^4^ w/ external banking | RCBus | RCZ180_ext.rom | 115200 |
| [RCBus Z180 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat.rom | 115200 |
| [RCBus Z280 CPU Module]^4^ w/ external banking | RCBus | RCZ180_ext.rom | 115200 |
| [RCBus Z280 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat.rom | 115200 |
| [Easy Z80 SBC]^2^ | RCBus | RCZ80_easy.rom | 115200 |
| [Tiny Z80 SBC]^2^ | RCBus | RCZ80_tiny.rom | 115200 |
| [Z80-512K CPU/RAM/ROM Module]^2^ | RCBus | RCZ80_skz.rom | 115200 |
| [Small Computer SC126 Z180 SBC]^5^ | BP80 | SCZ180_sc126.rom | 115200 |
| [Small Computer SC130 Z180 SBC]^5^ | RCBus | SCZ180_sc130.rom | 115200 |
| [Small Computer SC131 Z180 Pocket Computer]^5^ | - | SCZ180_sc131.rom | 115200 |
| [Small Computer SC140 Z180 CPU Module]^5^ | Z50 | SCZ180_sc140.rom | 115200 |
| [Small Computer SC503 Z180 CPU Module]^5^ | Z50 | SCZ180_sc503.rom | 115200 |
| [Small Computer SC700 Z180 CPU Module]^5^ | RCBus | SCZ180_sc700.rom | 115200 |
| [Dyno Z180 SBC]^6^ | Dyno | DYNO_std.rom | 38400 |
| [Nhyodyne Z80 MBC]^1^ | MBC | MBC_std.rom | 38400 |
| [Rhyophyre Z180 SBC]^1^ | - | RPH_std.rom | 38400 |
| [Z80 ZRC CPU Module]^7^ | RCBus | RCZ80_zrc.rom | 115200 |
| [Z80 ZRC CPU Module]^7^ ROMless | RCBus | RCZ80_zrc_ram.rom | 115200 |
| [Z80 ZRC512 CPU Module]^7^ | RCBus | RCZ80_zrc512.rom | 115200 |
| [Z180 Z1RCC CPU Module]^7^ | RCBus | RCZ180_z1rcc.rom | 115200 |
| [Z280 ZZRCC CPU Module]^7^ | RCBus | RCZ280_zzrcc.rom | 115200 |
| [Z280 ZZRCC CPU Module]^7^ ROMless | RCBus | RCZ280_zzrcc_ram.rom | 115200 |
| [Z280 ZZ80MB SBC]^7^ | RCBus | RCZ280_zz80mb.rom | 115200 |
| [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 |
| [S100 Computers Z180]^9^ | S100 | S100_std.rom | 57600 |
| [Duodyne Z80 System]^1^ | Duo | DUO_std.rom | 38400 |
| [Heath H8 Z80 System]^10^ | H8 | HEATH_std.rom | 115200 |
| [EP Mini-ITX Z180]^11^ | RCBus? | EPITX_std.rom | 115200 |
| [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 |
| [S100 FPGA Z80]^9^ | S100 | FZ80_std.rom | 9600 |
| **Description** | **Bus** | **ROM Image File** | **Baud Rate** |
|-------------------------------------------------------------|---------|------------------------------|--------------:|
| [RetroBrew Z80 SBC]^1^ | ECB | SBC_std.rom | 38400 |
| [RetroBrew Z80 SimH]^1^ | - | SBC_simh.rom | 38400 |
| [RetroBrew N8 Z180 SBC]^1^ (date >= 2312) | ECB | N8_std.rom | 38400 |
| [Zeta Z80 SBC]^2^, ParPortProp | - | ZETA_std.rom | 38400 |
| [Zeta V2 Z80 SBC]^2^, ParPortProp | - | ZETA2_std.rom | 38400 |
| [Mark IV Z180 SBC]^3^ | ECB | MK4_std.rom | 38400 |
| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 |
| [RCBus Z80 CPU Module]^4^, 512K w/KIO | RCBus | RCZ80_kio_std.rom | 115200 |
| [RCBus Z180 CPU Module]^4^ w/ ext banking | RCBus | RCZ180_ext_std.rom | 115200 |
| [RCBus Z180 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat_std.rom | 115200 |
| [RCBus Z280 CPU Module]^4^ w/ ext banking | RCBus | RCZ180_ext_std.rom | 115200 |
| [RCBus Z280 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat_std.rom | 115200 |
| [Easy Z80 SBC]^2^ | RCBus | RCZ80_easy_std.rom | 115200 |
| [Tiny Z80 SBC]^2^ | RCBus | RCZ80_tiny_std.rom | 115200 |
| [Z80-512K CPU/RAM/ROM Module]^2^ | RCBus | RCZ80_skz_std.rom | 115200 |
| [Small Computer SC126 Z180 SBC]^5^ | BP80 | SCZ180_sc126_std.rom | 115200 |
| [Small Computer SC130 Z180 SBC]^5^ | RCBus | SCZ180_sc130_std.rom | 115200 |
| [Small Computer SC131 Z180 Pocket Comp]^5^ | - | SCZ180_sc131_std.rom | 115200 |
| [Small Computer SC140 Z180 CPU Module]^5^ | Z50 | SCZ180_sc140_std.rom | 115200 |
| [Small Computer SC503 Z180 CPU Module]^5^ | Z50 | SCZ180_sc503_std.rom | 115200 |
| [Small Computer SC700 Z180 CPU Module]^5^ | RCBus | SCZ180_sc700_std.rom | 115200 |
| [Dyno Z180 SBC]^6^ | Dyno | DYNO_std.rom | 38400 |
| [Nhyodyne Z80 MBC]^1^ | MBC | MBC_std.rom | 38400 |
| [Rhyophyre Z180 SBC]^1^ | - | RPH_std.rom | 38400 |
| [Z80 ZRC CPU Module]^7^ | RCBus | RCZ80_zrc_std.rom | 115200 |
| [Z80 ZRC CPU Module]^7^ ROMless | RCBus | RCZ80_zrc_ram_std.rom | 115200 |
| [Z80 ZRC512 CPU Module]^7^ | RCBus | RCZ80_zrc512_std.rom | 115200 |
| [Z180 Z1RCC CPU Module]^7^ | RCBus | RCZ180_z1rcc_std.rom | 115200 |
| [Z280 ZZRCC CPU Module]^7^ | RCBus | RCZ280_zzrcc_std.rom | 115200 |
| [Z280 ZZRCC CPU Module]^7^ ROMless | RCBus | RCZ280_zzrcc_ram_std.rom | 115200 |
| [Z280 ZZ80MB SBC]^7^ | RCBus | RCZ280_zz80mb_std.rom | 115200 |
| [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 |
| [S100 Computers Z180]^9^ | S100 | S100_std.rom | 57600 |
| [Duodyne Z80 System]^1^ | Duo | DUO_std.rom | 38400 |
| [Heath H8 Z80 System]^10^ | H8 | HEATH_std.rom | 115200 |
| [EP Mini-ITX Z180]^11^ | RCBus? | EPITX_std.rom | 115200 |
| [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 |
| [S100 FPGA Z80]^9^ | S100 | FZ80_std.rom | 9600 |
| ^1^Designed by Andrew Lynch | ^1^Designed by Andrew Lynch
| ^2^Designed by Sergey Kiselev | ^2^Designed by Sergey Kiselev
@ -783,23 +783,62 @@ the [Disk Images] section of this document.
### Auto-Submit Batch Files ### Auto-Submit Batch Files
All of the operating systems supplied with RomWBW have the ability to
execute a "batch" of commands by creating a batch submission file
containing the commands to be executed. The specifics of using
batch files in a specific operating system is covered in its specific
documentation.
All of the operating systems supplied with RomWBW have the ability to
execute a "batch" of commands by creating a batch submission file
containing the commands to be executed. The mechanism for running
commands automatically at startup varies by operating system. In some
cases, it was built into the original operating system. In other cases,
I have added this capability in the RomWBW BIOS of the operating
system.
At boot, the operating system will look for a specific batch file
(`PROFILE.SUB` for CP/M 2.2 and 3) on the boot drive and execute that
batch file automatically. This allows you to automatically customize
your operating system with any commands desired at boot. CP/M 2.2 did
not originally have the ability to automatically excute a batch file at
boot, but the CBIOS in RomWBW has added this capability.
In all cases, the file containing the commands to run at startup must
be on the boot drive (A:). RomWBW automatically assigns A: to the
disk slice you choose to boot. Adding a startup command file to the
ROM Disk is not recommended because it would require customizing and
building a new ROM. Use of bootable disk slices is preferred since
the startup command files can be added/edited without any special
system customization.
Here is an overview for each operating system:
- **CP/M 2.2** - Will run PROFILE.SUB as a SUBMIT file if it exists in
A: at startup. Note that original CP/M 2.2 itself did not have this
ability -- it was added to the RomWBW CP/M 2.2 BIOS. The use of SUBMIT
files is documented in Section 1.6.7 SUBMIT Command of the CPM Manual
included in the Doc/CPM folder of the RomWBW distribution.
- **Z-System (ZSDOS 1.1)** - Will run run PROFILE.SUB as a SUBMIT file
if it exists in A: at startup. Works exactly the same as CP/M 2.2.
The original Z-System ZSDOS 1.1 did not have this ability -- it was
added to the RomWBW Z-System BIOS. The Z-System documentation does
not cover the use of SUBMIT files -- please refer to the CP/M 2.2
documentation.
- **NZCOM** - Will run the command STARTZCM at startup. This is
normally an alias file. You use SALIAS to edit such files. Please see
Section 3.1 Creating an Alias of the NZCOM Users Manual included in the
Doc/CPM folder of the RomWBW distribution. Note that the NZCOM
distribution includes a PROFILE.SUB file. NZCOM itself is launched from
ZSDOS. The included PROFILE.SUB accomplishes this. Do not modify this
file unless you fully understand the NZCOM boot process.
- **CP/M 3** - Will run PROFILE.SUB as a SUBMIT file if it exists in A:
at startup. This mechanism is built into the CP/M 3 operating system.
Please see Section 4.5 Executing Multiple Commands and Section 5.2.74
Executing the SUBMIT Command of the CPM3 Users Guide included in the
Doc/CPM folder of the RomWBW distribution.
- **ZPM3** - Will run the command STARTZPM at startup. This is normally
an alias file. You use SALIAS to edit such files. ZPM3 has no real
documentation. The NZCOM documentation of STARTZCM is generally correct
for ZPM3.
Since RomWBW can utilize many disk slices, it is very easy to create Since RomWBW can utilize many disk slices, it is very easy to create
slices for specific workflows (editing, software development, games, slices for specific workflows (editing, software development, games,
etc.). You can then just boot to the slice that is optimized for the etc.). You can then just boot to the slice that is optimized for the
task you want to perform.
task you want to perform. Each such slice may have its own startup
command batch file that customizes the environment for the specific
workflow desired.
## System Management ## System Management
@ -1946,13 +1985,38 @@ new combo disk image.
#### Custom Hard Disk Image #### Custom Hard Disk Image
If you want to use specific slices in a specific order, you can easily
generate a custom hard disk image file.
For hard disks, each .img file represents a single slice (CP/M For hard disks, each .img file represents a single slice (CP/M
filesystem). Since a hard disk can contain many slices, you can just filesystem). Since a hard disk can contain many slices, you can just
concatenate the slices (.img files) together to create your desired hard concatenate the slices (.img files) together to create your desired hard
disk image. For example, if you want to create a hard disk image that
disk image.
If you look in the Binary directory of the distribution, you will see
that there are more disk (slice) images than the 6 that are included
in the "combo" disk images. These images are identified by looking
for the files that start with hd1k_ or hd512_.
You can add slices to the combo disk images simply by tacking
slices onto the end. For example, if you want to add a slice
containing the MSX ROMs to the end of the combo image, you could
use one of the following command lines depending on your operating
system:
Windows:
`COPY /B hd1k_combo.img + hd1k_msxroms.img my_hd.img`
Linus/MaxOS:
`cat hd1k_combo.img hd1k_msxroms.img >my_hd.img`
Note that you **must** be sure to use either the hd1k_ or hd512_
prefixed files together. You cannot mix them.
If you want to create a completely custom hard disk image that is not
based on the existing combo image, you can generate a disk image entirely
from scratch using whatever slices you want in whatever order you like.
For example, if you want to create a hard disk image that
has slices for CP/M 2.2, CP/M 3, and WordStar in the hd512 format, you has slices for CP/M 2.2, CP/M 3, and WordStar in the hd512 format, you
would use the command line of your modern computer to create the final would use the command line of your modern computer to create the final
image: image:
@ -4609,7 +4673,7 @@ the RomWBW HBIOS configuration.
`\clearpage`{=latex} `\clearpage`{=latex}
#### ROM Image File: RCZ80_kio.rom
#### ROM Image File: RCZ80_kio_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4652,7 +4716,7 @@ the RomWBW HBIOS configuration.
### RCBus Z180 CPU Module ### RCBus Z180 CPU Module
#### ROM Image File: RCZ180_ext.rom
#### ROM Image File: RCZ180_ext_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4697,7 +4761,7 @@ the RomWBW HBIOS configuration.
`\clearpage`{=latex} `\clearpage`{=latex}
#### ROM Image File: RCZ180_nat.rom
#### ROM Image File: RCZ180_nat_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4744,7 +4808,7 @@ the RomWBW HBIOS configuration.
### RCBus Z280 CPU Module ### RCBus Z280 CPU Module
#### ROM Image File: RCZ280_ext.rom
#### ROM Image File: RCZ280_ext_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4787,7 +4851,7 @@ the RomWBW HBIOS configuration.
`\clearpage`{=latex} `\clearpage`{=latex}
#### ROM Image File: RCZ280_nat.rom
#### ROM Image File: RCZ280_nat_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4831,7 +4895,7 @@ the RomWBW HBIOS configuration.
### Easy Z80 SBC ### Easy Z80 SBC
#### ROM Image File: RCZ80_easy.rom
#### ROM Image File: RCZ80_easy_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4876,7 +4940,7 @@ the RomWBW HBIOS configuration.
### Tiny Z80 SBC ### Tiny Z80 SBC
#### ROM Image File: RCZ80_tiny.rom
#### ROM Image File: RCZ80_tiny_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4920,7 +4984,7 @@ the RomWBW HBIOS configuration.
### Z80-512K CPU/RAM/ROM Module ### Z80-512K CPU/RAM/ROM Module
#### ROM Image File: RCZ80_skz.rom
#### ROM Image File: RCZ80_skz_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -4965,7 +5029,7 @@ the RomWBW HBIOS configuration.
### Small Computer SC126 Z180 SBC ### Small Computer SC126 Z180 SBC
#### ROM Image File: SCZ180_sc126.rom
#### ROM Image File: SCZ180_sc126_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5013,7 +5077,7 @@ the RomWBW HBIOS configuration.
### Small Computer SC130 Z180 SBC ### Small Computer SC130 Z180 SBC
#### ROM Image File: SCZ180_sc130.rom
#### ROM Image File: SCZ180_sc130_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5059,9 +5123,9 @@ the RomWBW HBIOS configuration.
`\clearpage`{=latex} `\clearpage`{=latex}
### Small Computer SC131 Z180 Pocket Computer
### Small Computer SC131 Z180 Pocket Comp
#### ROM Image File: SCZ180_sc131.rom
#### ROM Image File: SCZ180_sc131_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5088,7 +5152,7 @@ the RomWBW HBIOS configuration.
### Small Computer SC140 Z180 CPU Module ### Small Computer SC140 Z180 CPU Module
#### ROM Image File: SCZ180_sc140.rom
#### ROM Image File: SCZ180_sc140_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5135,7 +5199,7 @@ the RomWBW HBIOS configuration.
### Small Computer SC503 Z180 CPU Module ### Small Computer SC503 Z180 CPU Module
#### ROM Image File: SCZ180_sc503.rom
#### ROM Image File: SCZ180_sc503_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5182,7 +5246,7 @@ the RomWBW HBIOS configuration.
### Small Computer SC700 Z180 CPU Module ### Small Computer SC700 Z180 CPU Module
#### ROM Image File: SCZ180_sc700.rom
#### ROM Image File: SCZ180_sc700_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5342,7 +5406,7 @@ S- MD: TYPE=RAM
### Z80 ZRC CPU Module ### Z80 ZRC CPU Module
#### ROM Image File: RCZ80_zrc.rom
#### ROM Image File: RCZ80_zrc_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5389,7 +5453,7 @@ S- MD: TYPE=RAM
`\clearpage`{=latex} `\clearpage`{=latex}
#### ROM Image File: RCZ80_zrc_ram.rom
#### ROM Image File: RCZ80_zrc_ram_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5436,7 +5500,7 @@ S- MD: TYPE=RAM
### Z80 ZRC512 CPU Module ### Z80 ZRC512 CPU Module
#### ROM Image File: RCZ80_zrc512.rom
#### ROM Image File: RCZ80_zrc512_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5483,7 +5547,7 @@ S- MD: TYPE=RAM
### Z180 Z1RCC CPU Module ### Z180 Z1RCC CPU Module
#### ROM Image File: RCZ180_z1rcc.rom
#### ROM Image File: RCZ180_z1rcc_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5529,7 +5593,7 @@ S- MD: TYPE=RAM
### Z280 ZZRCC CPU Module ### Z280 ZZRCC CPU Module
#### ROM Image File: RCZ280_zzrcc.rom
#### ROM Image File: RCZ280_zzrcc_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5575,7 +5639,7 @@ S- MD: TYPE=RAM
`\clearpage`{=latex} `\clearpage`{=latex}
#### ROM Image File: RCZ280_zzrcc_ram.rom
#### ROM Image File: RCZ280_zzrcc_ram_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|
@ -5621,7 +5685,7 @@ S- MD: TYPE=RAM
### Z280 ZZ80MB SBC ### Z280 ZZ80MB SBC
#### ROM Image File: RCZ280_zz80mb.rom
#### ROM Image File: RCZ280_zz80mb_std.rom
| | | | | |
|-------------------|---------------| |-------------------|---------------|

13
Source/FZ80/Build.cmd

@ -5,17 +5,20 @@ set TOOLS=../../Tools
set PATH=%TOOLS%\srecord;%PATH% set PATH=%TOOLS%\srecord;%PATH%
if exist ..\..\Binary\FZ80_std.rom call :build_fz80
for %%f in (..\..\Binary\FZ80_*.rom) do call :build %%~nf
goto :eof goto :eof
:build_fz80
:build
echo.
echo Creating %1 disk image...
echo.
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\FZ80_std.rom -binary -offset 0x80000 -o temp.dat -binary
move temp.dat ..\..\Binary\hd1k_fz80_prefix.dat
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\%1.rom -binary -offset 0x80000 -o temp.dat -binary
move temp.dat ..\..\Binary\%1_hd1k_prefix.dat
copy /b ..\..\Binary\hd1k_fz80_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_fz80_combo.img || exit /b
copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b
goto :eof goto :eof

21
Source/FZ80/Makefile

@ -1,12 +1,13 @@
HD1KFZ80PREFIX = hd1k_fz80_prefix.dat
HD1KFZ80COMBOIMG = hd1k_fz80_combo.img
FZ80ROM = ../../Binary/FZ80_std.rom
HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img
DEST=../../Binary
OBJECTS := $(HD1KFZ80PREFIX) $(HD1KFZ80COMBOIMG)
HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \
$(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img
DEST=../../Binary
ROMS := $(wildcard $(DEST)/FZ80_*.rom)
ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS))
OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS))
OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS))
TOOLS = ../../Tools TOOLS = ../../Tools
@ -14,11 +15,11 @@ include $(TOOLS)/Makefile.inc
DIFFPATH = $(DIFFTO)/Binary DIFFPATH = $(DIFFTO)/Binary
$(HD1KFZ80PREFIX):
%_hd1k_prefix.dat: $(DEST)/%.rom
srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $(FZ80ROM) -binary -offset 0x80000 -o temp.dat -binary
srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $< -binary -offset 0x80000 -o temp.dat -binary
mv temp.dat $@ mv temp.dat $@
$(HD1KFZ80COMBOIMG): $(HD1KFZ80PREFIX) $(HD1KIMGS)
%_hd1k_combo.img: %_hd1k_prefix.dat $(HD1KIMGS)
cat $^ > $@ cat $^ > $@

46
Source/HBIOS/Build.cmd

@ -211,31 +211,28 @@ call Build ZETA2 std || exit /b
call Build N8 std || exit /b call Build N8 std || exit /b
call Build MK4 std || exit /b call Build MK4 std || exit /b
call Build RCZ80 std || exit /b call Build RCZ80 std || exit /b
call Build RCZ80 kio || exit /b
call Build RCZ80 easy || exit /b
call Build RCZ80 tiny || exit /b
call Build RCZ80 skz || exit /b
:: call Build RCZ80 mt || exit /b
:: call Build RCZ80 duart || exit /b
call Build RCZ80 zrc || exit /b
call Build RCZ80 zrc_ram || exit /b
call Build RCZ80 zrc512 || exit /b
call Build RCZ180 ext || exit /b
call Build RCZ180 nat || exit /b
call Build RCZ180 z1rcc || exit /b
call Build RCZ280 ext || exit /b
call Build RCZ280 nat || exit /b
call Build RCZ280 zz80mb || exit /b
call Build RCZ280 zzrcc || exit /b
call Build RCZ280 zzrcc_ram || exit /b
call Build SCZ180 sc126 || exit /b
call Build SCZ180 sc130 || exit /b
call Build SCZ180 sc131 || exit /b
call Build SCZ180 sc140 || exit /b
call Build SCZ180 sc503 || exit /b
call Build SCZ180 sc700 || exit /b
call Build RCZ80 kio_std || exit /b
call Build RCZ80 easy_std || exit /b
call Build RCZ80 tiny_std || exit /b
call Build RCZ80 skz_std || exit /b
call Build RCZ80 zrc_std || exit /b
call Build RCZ80 zrc_ram_std || exit /b
call Build RCZ80 zrc512_std || exit /b
call Build RCZ180 ext_std || exit /b
call Build RCZ180 nat_std || exit /b
call Build RCZ180 z1rcc_std || exit /b
call Build RCZ280 ext_std || exit /b
call Build RCZ280 nat_std || exit /b
call Build RCZ280 zz80mb_std || exit /b
call Build RCZ280 zzrcc_std || exit /b
call Build RCZ280 zzrcc_ram_std || exit /b
call Build SCZ180 sc126_std || exit /b
call Build SCZ180 sc130_std || exit /b
call Build SCZ180 sc131_std || exit /b
call Build SCZ180 sc140_std || exit /b
call Build SCZ180 sc503_std || exit /b
call Build SCZ180 sc700_std || exit /b
call Build DYNO std || exit /b call Build DYNO std || exit /b
call Build UNA std || exit /b
call Build RPH std || exit /b call Build RPH std || exit /b
call Build Z80RETRO std || exit /b call Build Z80RETRO std || exit /b
call Build S100 std || exit /b call Build S100 std || exit /b
@ -245,5 +242,6 @@ call Build EPITX std || exit /b
:: call Build MON std || exit /b :: call Build MON std || exit /b
call Build NABU std || exit /b call Build NABU std || exit /b
call Build FZ80 std || exit /b call Build FZ80 std || exit /b
call Build UNA std || exit /b
goto :eof goto :eof

62
Source/HBIOS/Build.sh

@ -11,48 +11,46 @@ export CPUFAM
if [ "${ROM_PLATFORM}" == "dist" ] ; then if [ "${ROM_PLATFORM}" == "dist" ] ; then
echo "!!!DISTRIBUTION BUILD!!!" echo "!!!DISTRIBUTION BUILD!!!"
ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext"; bash Build.sh
ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat"; bash Build.sh
ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_ram"; bash Build.sh
# ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; bash Build.sh
# ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="easy"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="tiny"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512"; bash Build.sh
ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh
ROM_PLATFORM="MBC"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="MBC"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc126"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc130"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700"; bash Build.sh
ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio_std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="easy_std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="tiny_std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz_std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram_std"; bash Build.sh
ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512_std"; bash Build.sh
ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext_std"; bash Build.sh
ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat_std"; bash Build.sh
ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc_std"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext_std"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat_std"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb_std"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_std"; bash Build.sh
ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_ram_std"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc126_std"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc130_std"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131_std"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140_std"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503_std"; bash Build.sh
ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700_std"; bash Build.sh
ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh
# ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh # ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="FZ80"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="FZ80"; ROM_CONFIG="std"; bash Build.sh
ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
exit exit
fi fi

0
Source/HBIOS/Config/RCZ180_ext.asm → Source/HBIOS/Config/RCZ180_ext_std.asm

0
Source/HBIOS/Config/RCZ180_nat.asm → Source/HBIOS/Config/RCZ180_nat_std.asm

0
Source/HBIOS/Config/RCZ180_z1rcc.asm → Source/HBIOS/Config/RCZ180_z1rcc_std.asm

0
Source/HBIOS/Config/RCZ280_ext.asm → Source/HBIOS/Config/RCZ280_ext_std.asm

0
Source/HBIOS/Config/RCZ280_nat.asm → Source/HBIOS/Config/RCZ280_nat_std.asm

0
Source/HBIOS/Config/RCZ280_zz80mb.asm → Source/HBIOS/Config/RCZ280_zz80mb_std.asm

0
Source/HBIOS/Config/RCZ280_zzrcc_ram.asm → Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm

0
Source/HBIOS/Config/RCZ280_zzrcc.asm → Source/HBIOS/Config/RCZ280_zzrcc_std.asm

0
Source/HBIOS/Config/RCZ80_easy.asm → Source/HBIOS/Config/RCZ80_easy_std.asm

0
Source/HBIOS/Config/RCZ80_kio.asm → Source/HBIOS/Config/RCZ80_kio_std.asm

0
Source/HBIOS/Config/RCZ80_skz.asm → Source/HBIOS/Config/RCZ80_skz_std.asm

0
Source/HBIOS/Config/RCZ80_tiny.asm → Source/HBIOS/Config/RCZ80_tiny_std.asm

0
Source/HBIOS/Config/RCZ80_zrc512.asm → Source/HBIOS/Config/RCZ80_zrc512_std.asm

0
Source/HBIOS/Config/RCZ80_zrc_ram.asm → Source/HBIOS/Config/RCZ80_zrc_ram_std.asm

0
Source/HBIOS/Config/RCZ80_zrc.asm → Source/HBIOS/Config/RCZ80_zrc_std.asm

0
Source/HBIOS/Config/SCZ180_sc126.asm → Source/HBIOS/Config/SCZ180_sc126_std.asm

0
Source/HBIOS/Config/SCZ180_sc130.asm → Source/HBIOS/Config/SCZ180_sc130_std.asm

0
Source/HBIOS/Config/SCZ180_sc131.asm → Source/HBIOS/Config/SCZ180_sc131_std.asm

0
Source/HBIOS/Config/SCZ180_sc140.asm → Source/HBIOS/Config/SCZ180_sc140_std.asm

0
Source/HBIOS/Config/SCZ180_sc503.asm → Source/HBIOS/Config/SCZ180_sc503_std.asm

0
Source/HBIOS/Config/SCZ180_sc700.asm → Source/HBIOS/Config/SCZ180_sc700_std.asm

1
Source/HBIOS/cfg_duo.asm

@ -169,6 +169,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $60 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $60 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU (7372800/4) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU (7372800/4) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_dyno.asm

@ -183,6 +183,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_epitx.asm

@ -185,6 +185,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_fz80.asm

@ -188,6 +188,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_heath.asm

@ -188,6 +188,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_master.asm

@ -227,6 +227,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_mbc.asm

@ -166,6 +166,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_mk4.asm

@ -176,6 +176,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_mon.asm

@ -183,6 +183,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_n8.asm

@ -178,6 +178,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_nabu.asm

@ -188,6 +188,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_rcz180.asm

@ -189,6 +189,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_rcz280.asm

@ -193,6 +193,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_rcz80.asm

@ -188,6 +188,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_s100.asm

@ -183,6 +183,7 @@ SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_sbc.asm

@ -166,6 +166,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_scz180.asm

@ -183,6 +183,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/cfg_z80retro.asm

@ -169,6 +169,7 @@ SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
SIO0MODE .EQU SIOMODE_Z80R ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0MODE .EQU SIOMODE_Z80R ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
SIO0ACLK .EQU CPUOSC/2 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACLK .EQU CPUOSC/2 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800

1
Source/HBIOS/hbios.asm

@ -8640,6 +8640,7 @@ HB_APPBOOT2:
LD DE,STR_APPBOOT ; POINT TO MESSAGE LD DE,STR_APPBOOT ; POINT TO MESSAGE
LD C,9 ; BDOS FUNC 9: WRITE STR LD C,9 ; BDOS FUNC 9: WRITE STR
CALL $0005 ; DO IT CALL $0005 ; DO IT
CALL LDELAY ; SERIAL PORT FLUSH TIME
JR HB_APPBOOT3 ; AND CONTINUE JR HB_APPBOOT3 ; AND CONTINUE
; ;
STR_APPBOOT .DB "\r\n\r\n*** Launching RomWBW HBIOS v", BIOSVER, ", ", TIMESTAMP, " for" STR_APPBOOT .DB "\r\n\r\n*** Launching RomWBW HBIOS v", BIOSVER, ", ", TIMESTAMP, " for"

110
Source/HBIOS/sd.asm

@ -446,6 +446,7 @@ SD_CMD_READ_SNGL_BLK .EQU $40 + 17 ; $51, CMD17 -> R1
SD_CMD_WRITE_BLOCK .EQU $40 + 24 ; $58, CMD24 -> R1 SD_CMD_WRITE_BLOCK .EQU $40 + 24 ; $58, CMD24 -> R1
SD_CMD_APP_CMD .EQU $40 + 55 ; $77, CMD55 -> R1 SD_CMD_APP_CMD .EQU $40 + 55 ; $77, CMD55 -> R1
SD_CMD_READ_OCR .EQU $40 + 58 ; $7A, CMD58 -> R3 SD_CMD_READ_OCR .EQU $40 + 58 ; $7A, CMD58 -> R3
SD_CMD_CRC_ON_OFF .EQU $40 + 59 ; $7B, CMD59 -> R1
; ;
; SD CARD APPLICATION COMMANDS (PRECEDED BY APP_CMD COMMAND) ; SD CARD APPLICATION COMMANDS (PRECEDED BY APP_CMD COMMAND)
; ;
@ -941,19 +942,12 @@ SD_IO:
OR A ; SET FLAGS OR A ; SET FLAGS
RET Z ; ZERO SECTOR I/O, RETURN W/ E=0 & A=0 RET Z ; ZERO SECTOR I/O, RETURN W/ E=0 & A=0
; ;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
; CONSIDER CAPTURING CURRENT CNTR VALUE HERE AND USE IT
; IN SD_CSIO_DEF
; SET CSIO FOR HIGH SPEED OPERATION ; SET CSIO FOR HIGH SPEED OPERATION
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT
XOR A ; ZERO MEANS MAX SPEED
OUT0 (SD_CNTR),A ; NOW SET CSIO PORT
CALL SD_SPD_FAST
;
; HOOK RETURN TO RESTORE CSIO TO DEFAULT SPEED ; HOOK RETURN TO RESTORE CSIO TO DEFAULT SPEED
LD HL,SD_CSIO_DEF ; ROUTE RETURN
LD HL,SD_SPD_STD ; ROUTE RETURN
PUSH HL ; ... THRU CSIO RESTORE PUSH HL ; ... THRU CSIO RESTORE
#ENDIF
; ;
#IF (SDTRACE == 1) #IF (SDTRACE == 1)
LD HL,SD_PRTERR ; SET UP SD_PRTERR LD HL,SD_PRTERR ; SET UP SD_PRTERR
@ -1045,6 +1039,9 @@ SD_MEDIA:
JR NZ,SD_MEDIA1 ; ERROR ACTIVE, GO RIGHT TO RESET JR NZ,SD_MEDIA1 ; ERROR ACTIVE, GO RIGHT TO RESET
; ;
; USE SEND_CSD TO CHECK CARD ; USE SEND_CSD TO CHECK CARD
;;;LD A,'C' ;;;
;;;CALL COUT ;;;
CALL SD_SPD_FAST ; GO FAST FOR COMPATIBILITY
CALL SD_SELUNIT ; SET CUR UNIT CALL SD_SELUNIT ; SET CUR UNIT
LD A,SD_CMD_SEND_CSD ; SEND_CSD LD A,SD_CMD_SEND_CSD ; SEND_CSD
CALL SD_INITCMD ; SETUP COMMAND BUFFER CALL SD_INITCMD ; SETUP COMMAND BUFFER
@ -1057,9 +1054,14 @@ SD_MEDIA:
JR Z,SD_MEDIA2 ; IF SUCCESS, BYPASS RESET JR Z,SD_MEDIA2 ; IF SUCCESS, BYPASS RESET
; ;
SD_MEDIA1: SD_MEDIA1:
;;;LD A,'R' ;;;
;;;CALL COUT ;;;
CALL SD_RESET ; RESET CARD CALL SD_RESET ; RESET CARD
; ;
SD_MEDIA2: SD_MEDIA2:
;;;LD A,'D' ;;;
;;;CALL COUT ;;;
CALL SD_SPD_STD ; BACK TO STD SPEED
LD A,(IY+SD_STAT) ; GET STATUS LD A,(IY+SD_STAT) ; GET STATUS
OR A ; SET FLAGS OR A ; SET FLAGS
LD D,0 ; NO MEDIA CHANGE DETECTED LD D,0 ; NO MEDIA CHANGE DETECTED
@ -1072,7 +1074,6 @@ SD_MEDIA2:
; ;
; ;
; ;
;
SD_SEEK: SD_SEEK:
BIT 7,D ; CHECK FOR LBA FLAG BIT 7,D ; CHECK FOR LBA FLAG
CALL Z,HB_CHS2LBA ; CLEAR MEANS CHS, CONVERT TO LBA CALL Z,HB_CHS2LBA ; CLEAR MEANS CHS, CONVERT TO LBA
@ -1120,14 +1121,7 @@ SD_INITCARD:
CALL SD_CHKCD ; CHECK CARD DETECT CALL SD_CHKCD ; CHECK CARD DETECT
JP Z,SD_NOMEDIA ; Z=NO MEDIA, HANDLE IF SO JP Z,SD_NOMEDIA ; Z=NO MEDIA, HANDLE IF SO
; ;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
CALL SD_CSIO_DEF ; ENSURE CSIO AT DEFAULT SPEED
#ENDIF
;
#IF (SDMODE == SDMODE_FZ80)
;;; FORCE SLOW SPEED HERE?
;;; CALL SD_SELECT?
#ENDIF
CALL SD_SPD_SLOW ; SET SLOW SPEED FOR INIT
; ;
; WAKE UP THE CARD, KEEP DIN HI (ASSERTED) AND /CS HI (DEASSERTED) ; WAKE UP THE CARD, KEEP DIN HI (ASSERTED) AND /CS HI (DEASSERTED)
LD B,$10 ; MIN 74 CLOCKS REQUIRED, WE USE 128 ($10 * 8) LD B,$10 ; MIN 74 CLOCKS REQUIRED, WE USE 128 ($10 * 8)
@ -1138,8 +1132,8 @@ SD_INITCARD1:
POP BC ; RESTORE LOOP CONTROL POP BC ; RESTORE LOOP CONTROL
DJNZ SD_INITCARD1 ; LOOP AS NEEDED DJNZ SD_INITCARD1 ; LOOP AS NEEDED
; ;
; MAKE SURE WE FINISH SENDING
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
; MAKE SURE CSIO IS DONE SENDING DATA
CALL SD_WAITTX ; WAIT FOR TE TO CLEAR CALL SD_WAITTX ; WAIT FOR TE TO CLEAR
CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT
#ENDIF #ENDIF
@ -1234,9 +1228,28 @@ SD_INITCARD4:
CALL SD_INITCMD ; SETUP COMMAND BUFFER CALL SD_INITCMD ; SETUP COMMAND BUFFER
CALL SD_EXECCMD ; EXECUTE COMMAND CALL SD_EXECCMD ; EXECUTE COMMAND
RET NZ ; ABORT ON ERROR RET NZ ; ABORT ON ERROR
; CMD58 WORKED, GET OCR DATA AND SET CARD TYPE
CALL SD_GET ; BITS 31-24
; CMD58 WORKED, GET OCR DATA
LD B,4 ; 4 BYTES OF OCR
LD HL,SD_BUF ; PUT IN OUR PRIVATE BUFFER
SD_INITCARD4B:
PUSH BC ; SAVE LOOP CONTROL
CALL SD_GET ; GET NEXT BYTE
POP BC ; RESTORE LOOP CONTROL
LD (HL),A ; SAVE IT
INC HL ; BUMP BUF PTR
DJNZ SD_INITCARD4B ; LOOP AS NEEDED
CALL SD_DONE ; FINISH THE TRANSACTION CALL SD_DONE ; FINISH THE TRANSACTION
;
#IF (SDTRACE >= 3)
; IF TRACING, DUMP THE OCR CONTENTS
CALL SD_PRTPREFIX
LD DE,SD_STR_OCR
CALL WRITESTR
LD DE,SD_BUF
LD A,4
CALL PRTHEXBUF
#ENDIF
LD A,(SD_BUF) ; FIRST BYTE OF BUF (BITS 31-24 OF OCR)
AND $40 ; ISOLATE BIT 30 (CCS) AND $40 ; ISOLATE BIT 30 (CCS)
LD C,SD_TYPESDSC ; ASSUME V1 CARD LD C,SD_TYPESDSC ; ASSUME V1 CARD
JR Z,SD_INITCARD5 ; IF BIT NOT SET, THIS IS SDSC CARD JR Z,SD_INITCARD5 ; IF BIT NOT SET, THIS IS SDSC CARD
@ -1746,8 +1759,11 @@ SD_GETDATA3:
LD A,D LD A,D
OR E OR E
JR NZ,SD_GETDATA3 ; LOOP FOR ALL BYTES JR NZ,SD_GETDATA3 ; LOOP FOR ALL BYTES
;;;CALL PC_SPACE
CALL SD_GET ; DISCARD CRC BYTE 1 CALL SD_GET ; DISCARD CRC BYTE 1
;;;CALL PRTHEXBYTE
CALL SD_GET ; DISCARD CRC BYTE 2 CALL SD_GET ; DISCARD CRC BYTE 2
;;;CALL PRTHEXBYTE
#ENDIF #ENDIF
XOR A ; RESULT IS ZERO XOR A ; RESULT IS ZERO
SD_GETDATA4: SD_GETDATA4:
@ -1858,6 +1874,11 @@ SD_DONE:
PUSH AF PUSH AF
LD A,$FF LD A,$FF
CALL SD_PUT CALL SD_PUT
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
; MAKE SURE CSIO IS DONE SENDING DATA
CALL SD_WAITTX ; WAIT FOR TE TO CLEAR
CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT
#ENDIF
CALL SD_DESELECT CALL SD_DESELECT
POP AF POP AF
RET RET
@ -2052,7 +2073,7 @@ SD_DESELECT:
#ENDIF #ENDIF
; ;
#IF (SDMODE == SDMODE_FZ80) #IF (SDMODE == SDMODE_FZ80)
CALL SD_WAITBSY
;;;CALL SD_WAITBSY
#ENDIF #ENDIF
; ;
LD A,(SD_OPRVAL) LD A,(SD_OPRVAL)
@ -2188,7 +2209,7 @@ SD_PUT1:
#ENDIF #ENDIF
; ;
#IF (SDMODE == SDMODE_FZ80) #IF (SDMODE == SDMODE_FZ80)
CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY
;;;CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY
OUT (SD_DATA),A ; POST THE VALUE OUT (SD_DATA),A ; POST THE VALUE
OUT (SD_ACTION),A ; INITIATE THE WRITE OUT (SD_ACTION),A ; INITIATE THE WRITE
;;;CALL PC_SPACE ; *DEBUG* ;;;CALL PC_SPACE ; *DEBUG*
@ -2299,21 +2320,33 @@ SD_GET1:
#ENDIF #ENDIF
; ;
#IF (SDMODE == SDMODE_FZ80) #IF (SDMODE == SDMODE_FZ80)
CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY
;;;CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY
IN A,(SD_ACTION) ; INITIATE READ IN A,(SD_ACTION) ; INITIATE READ
CALL SD_WAITBSY ; WAIT FOR DONE
;;;CALL SD_WAITBSY ; WAIT FOR DONE
IN A,(SD_DATA) ; GET THE VALUE IN A,(SD_DATA) ; GET THE VALUE
;;;CALL PC_SPACE ; *DEBUG*
;;;CALL PC_LT ; *DEBUG*
;;;CALL PRTHEXBYTE ; *DEBUG*
#ENDIF #ENDIF
RET RET
; ;
; SET CSIO TO DEFAULT SPEED
; SET STANDARD SPEED (RESTORE SPI INTERFACE TO DEFAULTS)
;
SD_SPD_STD:
; ;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
; SET CSIO FOR DEFAULT OPERATION
PUSH AF ; PRESERVE AF
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT
LD A,Z180_CNTR_DEF ; DIV 1280, 14KHZ @ 18MHZ CLK
OUT0 (SD_CNTR),A ; DO IT
POP AF ; RESTORE AF
#ENDIF
RET
;
; SET SLOW SPEED
; ;
SD_CSIO_DEF:
SD_SPD_SLOW:
;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
; SET CSIO FOR DEFAULT OPERATION ; SET CSIO FOR DEFAULT OPERATION
PUSH AF ; PRESERVE AF PUSH AF ; PRESERVE AF
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
@ -2321,9 +2354,23 @@ SD_CSIO_DEF:
LD A,Z180_CNTR_DEF ; DIV 1280, 14KHZ @ 18MHZ CLK LD A,Z180_CNTR_DEF ; DIV 1280, 14KHZ @ 18MHZ CLK
OUT0 (SD_CNTR),A ; DO IT OUT0 (SD_CNTR),A ; DO IT
POP AF ; RESTORE AF POP AF ; RESTORE AF
#ENDIF
RET RET
; ;
; SET FAST SPEED
;
SD_SPD_FAST:
;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX))
; SET CSIO FOR HIGH SPEED OPERATION
PUSH AF ; PRESERVE AF
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT
XOR A ; 0 IS HIGHEST CLOCK SPEED
OUT0 (SD_CNTR),A ; DO IT
POP AF ; RESTORE AF
#ENDIF #ENDIF
RET
; ;
; ;
;============================================================================= ;=============================================================================
@ -2513,6 +2560,7 @@ SD_STR_TOK .TEXT " TOK=$"
SD_STR_CSD .TEXT " CSD =$" SD_STR_CSD .TEXT " CSD =$"
SD_STR_CID .TEXT " CID =$" SD_STR_CID .TEXT " CID =$"
SD_STR_SCR .TEXT " SCR =$" SD_STR_SCR .TEXT " SCR =$"
SD_STR_OCR .TEXT " OCR =$"
SD_STR_SDTYPE .TEXT " SD CARD TYPE ID=$" SD_STR_SDTYPE .TEXT " SD CARD TYPE ID=$"
; ;
SD_STR_STOK .TEXT "OK$" SD_STR_STOK .TEXT "OK$"

137
Source/HBIOS/sio.asm

@ -24,13 +24,13 @@ SIO_SIO .EQU 1
SIO_RTSON .EQU $EA SIO_RTSON .EQU $EA
SIO_RTSOFF .EQU $E8 SIO_RTSOFF .EQU $E8
; ;
#IF (INTMODE == 0)
SIO_WR1VAL .EQU $00 ; WR1 VALUE FOR NO INTS
#ELSE
#IF ((SIOINTS) & (INTMODE > 0))
SIO_WR1VAL .EQU $18 ; WR1 VALUE FOR INT ON RECEIVED CHARS SIO_WR1VAL .EQU $18 ; WR1 VALUE FOR INT ON RECEIVED CHARS
#ELSE
SIO_WR1VAL .EQU $00 ; WR1 VALUE FOR NO INTS
#ENDIF #ENDIF
; ;
#IF ((INTMODE == 2) | (INTMODE == 3))
#IF ((SIOINTS) & (INTMODE >= 2))
; ;
SIO0_IVT .EQU IVT(INT_SIO0) SIO0_IVT .EQU IVT(INT_SIO0)
SIO1_IVT .EQU IVT(INT_SIO1) SIO1_IVT .EQU IVT(INT_SIO1)
@ -146,7 +146,7 @@ SIO_PREINIT2:
ADD IY,DE ; BUMP IY TO NEXT ENTRY ADD IY,DE ; BUMP IY TO NEXT ENTRY
DJNZ SIO_PREINIT0 ; LOOP UNTIL DONE DJNZ SIO_PREINIT0 ; LOOP UNTIL DONE
; ;
#IF (INTMODE >= 1)
#IF ((SIOINTS) & (INTMODE > 0))
; SETUP INT VECTORS AS APPROPRIATE ; SETUP INT VECTORS AS APPROPRIATE
LD A,(SIO_DEV) ; GET DEVICE COUNT LD A,(SIO_DEV) ; GET DEVICE COUNT
OR A ; SET FLAGS OR A ; SET FLAGS
@ -223,7 +223,7 @@ SIO_INIT1:
; ;
; RECEIVE INTERRUPT HANDLER ; RECEIVE INTERRUPT HANDLER
; ;
#IF (INTMODE > 0)
#IF ((SIOINTS) & (INTMODE > 0))
; ;
; IM1 ENTRY POINT ; IM1 ENTRY POINT
; ;
@ -354,17 +354,7 @@ SIO_FNTBL:
; ;
; ;
; ;
#IF (INTMODE == 0)
;
SIO_IN:
CALL SIO_IST ; CHAR WAITING?
JR Z,SIO_IN ; LOOP IF NOT
LD C,(IY+4) ; DATA PORT
IN E,(C) ; GET CHAR
XOR A ; SIGNAL SUCCESS
RET
;
#ELSE
#IF ((SIOINTS) & (INTMODE > 0))
; ;
SIO_IN: SIO_IN:
CALL SIO_IST ; SEE IF CHAR AVAILABLE CALL SIO_IST ; SEE IF CHAR AVAILABLE
@ -411,6 +401,17 @@ SIO_IN2:
HB_EI ; INTERRUPTS OK AGAIN HB_EI ; INTERRUPTS OK AGAIN
XOR A ; SIGNAL SUCCESS XOR A ; SIGNAL SUCCESS
RET ; AND DONE RET ; AND DONE
;
#ELSE
;
SIO_IN:
CALL SIO_IST ; CHAR WAITING?
JR Z,SIO_IN ; LOOP IF NOT
LD C,(IY+4) ; DATA PORT
IN E,(C) ; GET CHAR
XOR A ; SIGNAL SUCCESS
RET
;
#ENDIF #ENDIF
; ;
; ;
@ -425,7 +426,17 @@ SIO_OUT:
; ;
; ;
; ;
#IF (INTMODE == 0)
#IF ((SIOINTS) & (INTMODE > 0))
;
SIO_IST:
LD L,(IY+7) ; GET ADDRESS
LD H,(IY+8) ; ... OF RECEIVE BUFFER
LD A,(HL) ; BUFFER UTILIZATION COUNT
OR A ; SET FLAGS
JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING
RET
;
#ELSE
; ;
SIO_IST: SIO_IST:
LD C,(IY+3) ; CMD PORT LD C,(IY+3) ; CMD PORT
@ -438,16 +449,6 @@ SIO_IST:
INC A ; ASCCUM := 1 TO SIGNAL 1 CHAR WAITING INC A ; ASCCUM := 1 TO SIGNAL 1 CHAR WAITING
RET ; DONE RET ; DONE
; ;
#ELSE
;
SIO_IST:
LD L,(IY+7) ; GET ADDRESS
LD H,(IY+8) ; ... OF RECEIVE BUFFER
LD A,(HL) ; BUFFER UTILIZATION COUNT
OR A ; SET FLAGS
JP Z,CIO_IDLE ; NOT READY, RETURN VIA IDLE PROCESSING
RET
;
#ENDIF #ENDIF
; ;
; ;
@ -853,7 +854,7 @@ SIO_INITGO:
; ;
; SET INTERRUPT VECTOR OFFSET WR2 ; SET INTERRUPT VECTOR OFFSET WR2
; ;
#IF ((INTMODE == 2) | (INTMODE == 3))
#IF ((SIOINTS) & (INTMODE >= 2))
LD A,(IY+2) ; CHIP / CHANNEL LD A,(IY+2) ; CHIP / CHANNEL
SRL A ; SHIFT AWAY CHANNEL BIT SRL A ; SHIFT AWAY CHANNEL BIT
LD L,SIO0_VEC ; ASSUME CHIP 0 LD L,SIO0_VEC ; ASSUME CHIP 0
@ -893,7 +894,7 @@ SIO_INITPRT:
LD B,SIO_INITLEN ; COUNT OF BYTES TO WRITE LD B,SIO_INITLEN ; COUNT OF BYTES TO WRITE
OTIR ; WRITE ALL VALUES OTIR ; WRITE ALL VALUES
; ;
#IF (INTMODE > 0)
#IF ((SIOINTS) & (INTMODE > 0))
; ;
; RESET THE RECEIVE BUFFER ; RESET THE RECEIVE BUFFER
LD E,(IY+7) LD E,(IY+7)
@ -1108,17 +1109,7 @@ SIO_STR_SIO .DB "SIO$"
SIO_DEV .DB 0 ; DEVICE NUM USED DURING INIT SIO_DEV .DB 0 ; DEVICE NUM USED DURING INIT
SIO_MAP .DB 0 ; CHIP PRESENCE BITMAP SIO_MAP .DB 0 ; CHIP PRESENCE BITMAP
; ;
#IF (INTMODE == 0)
;
SIO0A_RCVBUF .EQU 0
SIO0B_RCVBUF .EQU 0
;
#IF (SIOCNT >= 2)
SIO1A_RCVBUF .EQU 0
SIO1B_RCVBUF .EQU 0
#ENDIF
;
#ELSE
#IF ((SIOINTS) & (INTMODE > 0))
; ;
; SIO0 CHANNEL A RECEIVE BUFFER ; SIO0 CHANNEL A RECEIVE BUFFER
SIO0A_RCVBUF: SIO0A_RCVBUF:
@ -1152,6 +1143,16 @@ SIO1B_BUF .FILL SIO_BUFSZ,0 ; RECEIVE RING BUFFER
; ;
#ENDIF #ENDIF
; ;
#ELSE
;
SIO0A_RCVBUF .EQU 0
SIO0B_RCVBUF .EQU 0
;
#IF (SIOCNT >= 2)
SIO1A_RCVBUF .EQU 0
SIO1B_RCVBUF .EQU 0
#ENDIF
;
#ENDIF #ENDIF
; ;
; SIO PORT TABLE ; SIO PORT TABLE
@ -1191,9 +1192,9 @@ SIO0A_CFG:
DEVECHO ", IO=" DEVECHO ", IO="
DEVECHO SIO0BASE DEVECHO SIO0BASE
DEVECHO ", CHANNEL A" DEVECHO ", CHANNEL A"
#IF (INTMODE > 0)
#IF ((SIOINTS) & (INTMODE > 0))
DEVECHO ", INTERRUPTS ENABLED" DEVECHO ", INTERRUPTS ENABLED"
#ENDIF
#ENDIF
DEVECHO "\n" DEVECHO "\n"
; ;
SIO_CFGSIZ .EQU $ - SIO_CFG ; SIZE OF ONE CFG TABLE ENTRY SIO_CFGSIZ .EQU $ - SIO_CFG ; SIZE OF ONE CFG TABLE ENTRY
@ -1231,9 +1232,9 @@ SIO0B_CFG:
DEVECHO ", IO=" DEVECHO ", IO="
DEVECHO SIO0BASE DEVECHO SIO0BASE
DEVECHO ", CHANNEL B" DEVECHO ", CHANNEL B"
#IF (INTMODE > 0)
#IF ((SIOINTS) & (INTMODE > 0))
DEVECHO ", INTERRUPTS ENABLED" DEVECHO ", INTERRUPTS ENABLED"
#ENDIF
#ENDIF
DEVECHO "\n" DEVECHO "\n"
; ;
#IF (SIOCNT >= 2) #IF (SIOCNT >= 2)
@ -1253,26 +1254,26 @@ SIO1A_CFG:
.DB SIO1MODE ; MODE .DB SIO1MODE ; MODE
; ;
DEVECHO "SIO MODE=" DEVECHO "SIO MODE="
#IF (SIO1MODE == SIOMODE_STD)
#IF (SIO1MODE == SIOMODE_STD)
DEVECHO "STD" DEVECHO "STD"
#ENDIF
#IF (SIO1MODE == SIOMODE_RC)
#ENDIF
#IF (SIO1MODE == SIOMODE_RC)
DEVECHO "RC" DEVECHO "RC"
#ENDIF
#IF (SIO1MODE == SIOMODE_SMB)
#ENDIF
;
#IF (SIO1MODE == SIOMODE_SMB)
DEVECHO "SMB" DEVECHO "SMB"
#ENDIF
#IF (SIO1MODE == SIOMODE_ZP)
#ENDIF
#IF (SIO1MODE == SIOMODE_ZP)
DEVECHO "ZP" DEVECHO "ZP"
#ENDIF
#IF (SIO1MODE == SIOMODE_Z80R)
#ENDIF
#IF (SIO1MODE == SIOMODE_Z80R)
DEVECHO "Z80R" DEVECHO "Z80R"
#ENDIF
#ENDIF
DEVECHO ", IO=" DEVECHO ", IO="
DEVECHO SIO1BASE DEVECHO SIO1BASE
DEVECHO ", CHANNEL A" DEVECHO ", CHANNEL A"
#IF (INTMODE > 0)
#IF ((SIOINTS) & (INTMODE > 0))
DEVECHO ", INTERRUPTS ENABLED" DEVECHO ", INTERRUPTS ENABLED"
#ENDIF #ENDIF
DEVECHO "\n" DEVECHO "\n"
@ -1292,25 +1293,25 @@ SIO1B_CFG:
.DB SIO1MODE ; MODE .DB SIO1MODE ; MODE
; ;
DEVECHO "SIO MODE=" DEVECHO "SIO MODE="
#IF (SIO1MODE == SIOMODE_STD)
#IF (SIO1MODE == SIOMODE_STD)
DEVECHO "STD" DEVECHO "STD"
#ENDIF
#IF (SIO1MODE == SIOMODE_RC)
#ENDIF
#IF (SIO1MODE == SIOMODE_RC)
DEVECHO "RC" DEVECHO "RC"
#ENDIF
#IF (SIO1MODE == SIOMODE_SMB)
#ENDIF
#IF (SIO1MODE == SIOMODE_SMB)
DEVECHO "SMB" DEVECHO "SMB"
#ENDIF
#IF (SIO1MODE == SIOMODE_ZP)
#ENDIF
#IF (SIO1MODE == SIOMODE_ZP)
DEVECHO "ZP" DEVECHO "ZP"
#ENDIF
#IF (SIO1MODE == SIOMODE_Z80R)
#ENDIF
#IF (SIO1MODE == SIOMODE_Z80R)
DEVECHO "Z80R" DEVECHO "Z80R"
#ENDIF
#ENDIF
DEVECHO ", IO=" DEVECHO ", IO="
DEVECHO SIO1BASE DEVECHO SIO1BASE
DEVECHO ", CHANNEL B" DEVECHO ", CHANNEL B"
#IF (INTMODE > 0)
#IF ((SIOINTS) & (INTMODE > 0))
DEVECHO ", INTERRUPTS ENABLED" DEVECHO ", INTERRUPTS ENABLED"
#ENDIF #ENDIF
DEVECHO "\n" DEVECHO "\n"

5
Source/Images/Build.cmd

@ -24,7 +24,6 @@ call BuildDisk.cmd fortran hd wbw_fd144 || exit /b
call BuildDisk.cmd games hd wbw_fd144 || exit /b call BuildDisk.cmd games hd wbw_fd144 || exit /b
call BuildDisk.cmd cowgol hd wbw_fd144 || exit /b call BuildDisk.cmd cowgol hd wbw_fd144 || exit /b
echo. echo.
echo Building Hard Disk Images (512 directory entry format)... echo Building Hard Disk Images (512 directory entry format)...
echo. echo.
@ -45,6 +44,8 @@ call BuildDisk.cmd bascomp hd wbw_hd512 || exit /b
call BuildDisk.cmd fortran hd wbw_hd512 || exit /b call BuildDisk.cmd fortran hd wbw_hd512 || exit /b
call BuildDisk.cmd games hd wbw_hd512 || exit /b call BuildDisk.cmd games hd wbw_hd512 || exit /b
call BuildDisk.cmd cowgol hd wbw_hd512 || exit /b call BuildDisk.cmd cowgol hd wbw_hd512 || exit /b
call BuildDisk.cmd msxroms1 hd wbw_hd512 || exit /b
call BuildDisk.cmd msxroms2 hd wbw_hd512 || exit /b
echo. echo.
echo Building Combo Disk (512 directory entry format) Image... echo Building Combo Disk (512 directory entry format) Image...
@ -69,6 +70,8 @@ call BuildDisk.cmd bascomp hd wbw_hd1k || exit /b
call BuildDisk.cmd fortran hd wbw_hd1k || exit /b call BuildDisk.cmd fortran hd wbw_hd1k || exit /b
call BuildDisk.cmd games hd wbw_hd1k || exit /b call BuildDisk.cmd games hd wbw_hd1k || exit /b
call BuildDisk.cmd cowgol hd wbw_hd1k || exit /b call BuildDisk.cmd cowgol hd wbw_hd1k || exit /b
call BuildDisk.cmd msxroms1 hd wbw_hd1k || exit /b
call BuildDisk.cmd msxroms2 hd wbw_hd1k || exit /b
if exist ..\BPBIOS\bp*.rel call BuildDisk.cmd bp hd wbw_hd1k ..\zsdos\zsys_wbw.sys || exit /b if exist ..\BPBIOS\bp*.rel call BuildDisk.cmd bp hd wbw_hd1k ..\zsdos\zsys_wbw.sys || exit /b

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Source/Images/Common/Z3/u14/UMAP18.CFG

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Source/Images/Common/Z3/u15/UMAP.COM

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6
Source/Images/Makefile

@ -13,13 +13,15 @@ HD512IMGS = hd512_cpm22.img hd512_zsdos.img hd512_nzcom.img \
HD512XIMGS = hd512_z80asm.img hd512_aztecc.img hd512_hitechc.img \ HD512XIMGS = hd512_z80asm.img hd512_aztecc.img hd512_hitechc.img \
hd512_bascomp.img hd512_fortran.img hd512_games.img \ hd512_bascomp.img hd512_fortran.img hd512_games.img \
hd512_tpascal.img hd512_dos65.img hd512_qpm.img \ hd512_tpascal.img hd512_dos65.img hd512_qpm.img \
hd512_cowgol.img hd512_blank.img
hd512_cowgol.img hd512_msxroms1.img hd512_msxroms2.img \
hd512_blank.img
HD1KIMGS = hd1k_cpm22.img hd1k_zsdos.img hd1k_nzcom.img \ HD1KIMGS = hd1k_cpm22.img hd1k_zsdos.img hd1k_nzcom.img \
hd1k_cpm3.img hd1k_zpm3.img hd1k_ws4.img hd1k_cpm3.img hd1k_zpm3.img hd1k_ws4.img
HD1KXIMGS = hd1k_z80asm.img hd1k_aztecc.img hd1k_hitechc.img \ HD1KXIMGS = hd1k_z80asm.img hd1k_aztecc.img hd1k_hitechc.img \
hd1k_bascomp.img hd1k_fortran.img hd1k_games.img \ hd1k_bascomp.img hd1k_fortran.img hd1k_games.img \
hd1k_tpascal.img hd1k_qpm.img \ hd1k_tpascal.img hd1k_qpm.img \
hd1k_cowgol.img hd1k_blank.img
hd1k_cowgol.img hd1k_msxroms1.img hd1k_msxroms2.img \
hd1k_blank.img
HD1KXIMGS += hd1k_bp.img HD1KXIMGS += hd1k_bp.img
HD512PREFIX = HD512PREFIX =

19
Source/Images/d_msxroms1/ReadMe.txt

@ -0,0 +1,19 @@
===== MSX ROMs Disk for RomWBW =====
This is disk 1 of 2 of the collection of MSX ROMs as provided by Les
Bird (ROM filenames A-K). These ROMs are "run" by using the
appropriate variant of Les' MSX8 ROM loader. You can download the
loader binaries from https://github.com/lesbird/MSX8. You will need
appropriate hardware to run the loader.
Please review the file ROMLIST.TXT for information on the current
operational status of the ROM and it's long file name/description.
This disk (RomWBW slice) is not automatically included with the
RomWBW "combo" disk images. You can simply add it to a combo
image by appending it to the end. After booting your system,
you can use the ASSIGN command to map the slice to a drive letter.
Refer to the RomWBW User Guide for more information on this
process.
-- WBW 11:15 AM 8/21/2024

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Source/Images/d_msxroms1/u0/10YAR000.ROM

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Source/Images/d_msxroms1/u0/3DGOL002.ROM

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Source/Images/d_msxroms1/u0/3DGOL003.ROM

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Source/Images/d_msxroms1/u0/3DTEN004.ROM

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Source/Images/d_msxroms1/u0/ACTMA007.ROM

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Source/Images/d_msxroms1/u0/ADVEN008.ROM

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Source/Images/d_msxroms1/u0/AEJAP005.ROM

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Source/Images/d_msxroms1/u0/ALBAT009.ROM

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Source/Images/d_msxroms1/u0/ALCAZ010.ROM

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Source/Images/d_msxroms1/u0/ALIBA011.ROM

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Source/Images/d_msxroms1/u0/ALIEN012.ROM

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Source/Images/d_msxroms1/u0/ALPHA014.ROM

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Source/Images/d_msxroms1/u0/ALPHA015.ROM

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Source/Images/d_msxroms1/u0/AMERI016.ROM

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