MirrorRepos/RomWBW
1
0
Fork 1
mirror of https://github.com/wwarthen/RomWBW.git synced 2026-02-06 22:13:13 -06:00
Code Issues Projects Releases Wiki Activity

Update uart.asm

Browse Source 
Fixed some stuff in 16C2552 support
- Concurrent write was being enabled unintentionally
- Swapped the EPDSER UART base ports to match the boards annotations
This commit is contained in:
Wayne Warthen
2020-05-22 09:58:04 -07:00
parent d331fcbdef
commit 180b7fddec
1 changed files with 25 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

34
Source/HBIOS/uart.asm
View File

@@ -230,11 +230,23 @@ UART_INITDEV1:
LD A,C
UART_OUTP(UART_DLL) ; SET DIVISOR (LS)
;
; SETUP FCR (DLAB MUST STILL BE ON FOR ACCESS TO BIT 5)
LD A,%00100111 ; FIFO ENABLE & RESET, 64 BYTE FIFO ENABLE ON 750+
; FOR 750+, WE ENABLE THE 64-BYTE FIFO
; DLAB MUST STILL BE ON FOR ACCESS TO BIT 5
; WE DO *NOT* ENABLE ANY OTHER FCR BITS HERE
; BEACAUSE IT WILL SCREW UP THE 2552!!!
LD A,%00100000
UART_OUTP(UART_FCR) ; DO IT
;
; SETUP LCR FROM SECOND CONFIG BYTE (DLAB IS CLEARED)
XOR A ; DLAB OFF NOW
UART_OUTP(UART_LCR) ; DO IT
;
; SETUP FCR, BIT 5 IS KEPT ON EVEN THOUGH IT IS PROBABLY
; IRRELEVANT BECAUSE IT ONLY APPLIES TO 750 AND DLAB IS
; NOW OFF, BUT DOESN'T HURT.
LD A,%00100111 ; FIFO ENABLE & RESET
UART_OUTP(UART_FCR) ; DO IT
;
; SETUP LCR FROM SECOND CONFIG BYTE
LD A,(IY + 4) ; GET CONFIG BYTE
AND ~$C0 ; ISOLATE PARITY, STOP/DATA BITS
UART_OUTP(UART_LCR) ; SAVE IT
@@ -364,8 +376,9 @@ UART_DETECT:
CP $5A ; SPR STILL THERE?
JR NZ,UART_DETECT1 ; NOPE, HIDDEN, MUST BE 16650/850
;
; RESET LCR TO DEFAULT
LD A,$80 ; DLAB BIT ON
; RESET LCR TO DEFAULT (DLAB OFF)
;LD A,$80 ; DLAB BIT ON
XOR A ; DLAB BIT OFF
UART_OUTP(UART_LCR) ; RESET LCR
;
; TEST FCR TO ISOLATE 16450/550/550A
@@ -381,6 +394,9 @@ UART_DETECT:
JR UART_DETECT_16750 ; ONLY THING LEFT IS 16750
;
UART_DETECT1: ; PICK BETWEEN 16650/850
; RESET LCR TO DEFAULT (DLAB OFF)
XOR A ; DLAB BIT OFF
UART_OUTP(UART_LCR) ; RESET LCR
; NOT SURE HOW TO DIFFERENTIATE 16650 FROM 16850 YET
JR UART_DETECT_16650 ; ASSUME 16650
RET
@@ -630,15 +646,15 @@ UART_CFG:
; UARTRC SERIAL PORT A
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB $A0 ; IO PORT BASE (RBR, THR)
.DB $A0 + UART_LSR ; LINE STATUS PORT (LSR)
.DB $A8 ; IO PORT BASE (RBR, THR)
.DB $A8 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
; UARTRC SERIAL PORT B
.DB 0 ; DEVICE NUMBER (UPDATED DURING INIT)
.DB 0 ; UART TYPE
.DB $A8 ; IO PORT BASE (RBR, THR)
.DB $A8 + UART_LSR ; LINE STATUS PORT (LSR)
.DB $A0 ; IO PORT BASE (RBR, THR)
.DB $A0 + UART_LSR ; LINE STATUS PORT (LSR)
.DW UARTCFG ; LINE CONFIGURATION
.FILL 2,$FF ; FILLER
#ENDIF