Configuration File Improvements

- Modified configuration files so that all configurations now inherit from the Master Config file.

Source/HBIOS/Config/DUO_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   DUODYNE STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR DUODYNE
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/DYNO_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   DYNO STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR DYNO
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/EPITX_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   Z180 Mini ITX STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR Z180 MINI ITX
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	PLATFORM_NAME	"Z180 MiniITX"
 ;

Source/HBIOS/Config/FZ80_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   S100 FPGZ Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR S100 FPGA Z80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/GMZ180_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   STD Z180 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR GENESIS STD Z180
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/HEATH_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   HEATH H8 Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR HEATH H8 Z80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/MBC_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   MBC CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR NHYODYNE
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/MK4_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   MARK IV STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR MARK IV
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/MON_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   MONSPUTER Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR MONSPUTER Z80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/N8_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   N8 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR N8
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/NABU_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   NABU Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR NABU Z80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ180_ext_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z180 STANDARD CONFIGURATION (EXTERNAL MMU ON 512K RAM/ROM BANKED MEMORY MODULE)
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 W/ EXTERNAL Z2 MMU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ180_nat_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z180 STANDARD CONFIGURATION (NATIVE Z180 MMU W/ LINEAR MEMORY MODULE)
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 W/ NATIVE Z180 MMU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ180_z1rcc_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z180 Z1RCC CONFIGURATION (ROMLESS)
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 ROMLESS Z1RCC
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Z1RCC", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ280_ext_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z280 STANDARD CONFIGURATION (EXTERNAL MMU ON 512K RAM/ROM BANKED MEMORY MODULE)
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 W/ EXTERNAL Z2 MMU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ280_nat_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY)
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 W/ NATIVE Z280 MMU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ280_zz80mb_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZ80MB)
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS ZZ80MB Z280 W/ NATIVE Z280 MMU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "ZZ80MB", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z280 ZZRCC CONFIGURATION (ROMLESS)
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 ROMLESS ZZRCC W/ NATIVE Z280 MMU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ280_zzrcc_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z280 ZZRCC CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 ZZRCC W/ NATIVE Z280 MMU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ80_easy_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   EASY Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR EASY Z80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Easy-Z80", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ80_kio_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z80 STANDARD CONFIGURATION W/ KIO
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ KIO
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ80_skz_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z80 STANDARD CONFIGURATION W/ SERGEY KISELEV Z80 + 512K CPU
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ SERGEY KISELEL Z80+512K CPU
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ80_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/RCZ80_tiny_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   TINY Z80 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR TINY Z80
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Tiny-Z80", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ80_user.asm

@@ -0,0 +1,57 @@
+;
+;==================================================================================================
+;   ROMWBW CUSTOM USER BUILD SETTINGS EXAMPLE FOR RCBUS Z80
+;==================================================================================================
+;
+; THIS FILE IS AN EXAMPLE OF A CUSTOM USER SETTINGS FILE.  THESE
+; SETTINGS OVERRIDE THE DEFAULT SETTINGS OF THE INHERITED FILES AS
+; DESIRED BY A USER.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; THIS FILE EXEMPLIFIES THE IDEAL WAY TO CREATE A USER SPECIFIC BUILD
+; CONFIGURATION.  NOTICE THAT IT INCLUDES THE DEFAULT BUILD SETTINGS
+; FILE AND OVERRIDES SOME DESIRED SETTINGS.
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+; THIS EXAMPLE CUSTOM USER SETTINGS FILE DOES THE FOLLOWING:
+;
+; 1. SETS A CUSTOM NAME USED IN THE BOOT LOADER BANNER
+; 2. BOOTS ZSDOS BY DEFAULT AFTER 10 SECOND DELAY
+; 3. ENABLES LPT PRINTER SUPPORT
+;
+#DEFINE PLATFORM_NAME "My Custom RCBus Computer", " [", CONFIG, "]"
+#DEFINE	BOOT_DEFAULT "Z"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+BOOT_TIMEOUT	.SET	10		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+;
+LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)

Source/HBIOS/Config/RCZ80_zrc512_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z80 ZRC512 CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ZRC512
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "ZRC512", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ80_zrc_ram_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z80 ZRC CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ROMLESS ZRC
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RCZ80_zrc_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RCBUS Z80 ZRC CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ZRC
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/RPH_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   RHYOPHYRE STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR RHYOPHYRE
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/S100_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   S100 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR S100
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/SBC_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   SBC STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR N8VEM SBC
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/SCZ180_sc126_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   SC126 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR SC126
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Small Computer SC126", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/SCZ180_sc130_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   SC130 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR SC130
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Small Computer SC130", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/SCZ180_sc131_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   SC131 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR SC131
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Small Computer SC131", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/SCZ180_sc140_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   SC140 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR PLATFORM: SBC
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Small Computer SC140", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/SCZ180_sc503_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   SC503 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR SC503
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Small Computer SC503", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/SCZ180_sc700_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   SC700 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR SC700
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Small Computer SC700", " [", CONFIG, "]"
 ;

Source/HBIOS/Config/UNA_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   UNA STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR UNA
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/Z80RETRO_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   ZETA2 STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR Z80 RETRO
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/ZETA2_std.asm

@@ -1,26 +1,93 @@
 ;
 ;==================================================================================================
-;   ZETA2 STANDARD CONFIGURATION
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ280
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
+;
+
+
+
+;
+;==================================================================================================
+;   ROMWBW DEFAULT BUILD SETTINGS FOR ZETA2
+;==================================================================================================
+;
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/Config/ZETA_std.asm

@@ -1,26 +1,46 @@
 ;
 ;==================================================================================================
-;   ZETA STANDARD CONFIGURATION
+;   ROMWBW DEFAULT BUILD SETTINGS FOR ZETA
 ;==================================================================================================
 ;
-; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
-; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
-; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
-; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
-; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
-; YOUR FILE IN THE BUILD PROCESS.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE.  THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS
+; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES.
 ;
-; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
-; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
-; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
-; SETTINGS.
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
 ;
-; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
-; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
-; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
 ;
-; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
-; DIRECTORIES ABOVE THIS ONE).
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.
+;
+; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE
+; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE).
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
 ;

Source/HBIOS/cfg_duo.asm

@@ -1,350 +1,381 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR DUODYNE
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: DUO
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_DUO		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	FALSE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	FALSE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_UNSUP	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$50		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$51		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$52		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$53		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$54		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$50		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$51		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$52		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$53		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$54		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$94		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$94		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$60		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	(7372800/8)	; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$60		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	(7372800/8)	; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$56		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$56		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$42		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$42		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$42		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$42		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$88		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$88		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$88		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	TRUE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$88		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	7372800		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$58		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$A8		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$70		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$78		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	7372800		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$58		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$A8		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$70		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$78		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$60		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(7372800/4)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$60		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	(7372800/4)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	0		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	(7372800/4)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
-CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_DUO	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_DUO	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
-FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_DUO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_DUO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
-RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$88		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$88		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$20		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$14		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	TRUE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	TRUE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$4E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	TRUE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$FF		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	FALSE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	1		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$4E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	TRUE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$FF		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	FALSE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
-ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.SET	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
-HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKTRACE	.SET	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$68		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$6C		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$68		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$6C		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$48		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$48		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$EC		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_SPP	; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_SPP	; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_SPP	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_SPP	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_SPP	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_SPP	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
-UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_DUO	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_DUO	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO]
 ;
-AY38910ENABLE	.EQU	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_DUO	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$40		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_DUO	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	TRUE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$40		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_DUO	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_dyno.asm

@@ -1,330 +1,361 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR DYNO
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: DYNO
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Dyno", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_DYNO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$0C		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	TRUE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	TRUE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_DYNO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_DYNO	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$4C		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$4C		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_NONE	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_epitx.asm

@@ -1,362 +1,387 @@
 ;
 ;==================================================================================================
-;   ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: EPITX
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "MiniITX"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_EPITX	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
-Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR - TODO
+RTCIO		.SET	$0C		; RTC LATCH REGISTER ADR - TODO
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
-FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
-DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
-;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
 ; TODO - ADD PS/2 BITBANGER
-VDAEMU_SERKBD	.EQU	$00		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+VDAEMU_SERKBD	.SET	$00		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	2		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	2		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	2		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$A0		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$A8		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	2		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$A0		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$A8		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_EPFDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_EPFDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$40		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
-SDTRACE		.EQU	2		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_EPITX	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$40		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
+SDTRACE		.SET	2		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_fz80.asm

@@ -1,365 +1,396 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 FPGA Z80
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: FZ80
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_FZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_FZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
-SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
-WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6E		; WATCHDOG REGISTER ADR
 ;
-FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$FF		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$FF		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	TRUE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	TRUE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$34		; SSER: STATUS PORT
-SSERDATA	.EQU	$35		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	TRUE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$34		; SSER: STATUS PORT
+SSERDATA	.SET	$35		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	TRUE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	TRUE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	TRUE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	TRUE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	FALSE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	FALSE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$30		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$30		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_FZ80	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_FZ80	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_gmz180.asm

@@ -1,362 +1,393 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR GENESIS MODULES STD BUS BASED Z180 VARIANTS 
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: GMZ180
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_GMZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-RTCIO		.EQU	$84		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$84		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	TRUE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
-GM7303BASE	.EQU	$30		; BASE ADDRESS FOR GM3703 BOARD  
-GM7303DSKACT	.EQU	TRUE		; ENABLE DISK ACTIVITY OF GM7303 LCD DISPLAY
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	TRUE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+GM7303BASE	.SET	$30		; BASE ADDRESS FOR GM3703 BOARD  
+GM7303DSKACT	.SET	TRUE		; ENABLE DISK ACTIVITY OF GM7303 LCD DISPLAY
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	TRUE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	TRUE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_GIDE	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
-IDE0BASE	.EQU	$20   		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_GIDE	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE0BASE	.SET	$20   		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_GM	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$18		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$18		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_heath.asm

@@ -1,355 +1,386 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR HEATHKIT Z80
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: HEATH
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "HEATHKIT", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_HEATH	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	16384000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	16384000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
-SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
-WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6E		; WATCHDOG REGISTER ADR
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	TRUE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	FALSE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	TRUE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$E8		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$E0		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$D8		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$D0		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$E8		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$E0		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$D8		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$D0		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_MSX	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_master.asm

@@ -1,12 +1,46 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION MASTER
+;   ROMWBW GLOBAL MASTER CONFIGURATION FILE
 ;==================================================================================================
 ;
-; THIS FILE IS *NOT* A REAL CONFIGURATION FILE.	 IT IS A MASTER TEMPLATE FILE
-; CONTAINING ALL POSSIBLE CONFIGURATION SETTINGS ACROSS ALL PLATFORMS.	IT IS
-; USED ONLY AS A REFERENCE TO HELP MANAGE THE FULL SET OF POSSIBLE SETTINGS AND
-; KEEP THINGS CONSISTENT.
+; THIS FILE IS THE GLOBAL MASTER CONFIGURATION FILE FOR THE ROMWBW
+; BUILD PROCESS.  IT DEFINES ALL POSSIBLE CONFIGURATION SETTINGS
+; AVAILABLE WITHIN ROMWBW.  MANY SETTINGS WILL NOT BE APPLICABLE TO
+; ALL OF THE DIFFERENT ROMWBW PLATFORMS.
+;
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; EACH FILE BELOW THIS TOP MASTER CONFIGURATION FILE INHERITS THE
+; CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY OVERRIDE THESE
+; SETTINGS AS DESIRED.
+;
+; OTHER THAN THIS TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE.  THE TOP TWO FILES SHOULD NOT BE MODIFIED.  TO CUSTOMIZE YOUR
+; BUILD SETTINGS, YOU SHOULD MODIFY THE DEFAULT BUILD SETTINGS
+; (Config/<platform>_std.asm) OR PREFERABLY CREATE AN OPTIONAL CUSTOM
+; USER SETTINGS FILE THAT INCLUDES THE DEFAULT BUILD SETTINGS FILE (SEE
+; EXAMPLE Config/SBC_custom.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** NOTE: THIS FILE USES ".EQU" TO DEFINE ALL SETTINGS.  ALL OTHER
+; CONFIGURATION FILES BELOW THIS FILE MUST USE ".SET" TO OVERRIDE
+; SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT TO USE ".EQU"
+; TO REDEFINE A PREVIOUS DEFINITION.
 ;
 #DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]"
 ;

Source/HBIOS/cfg_mbc.asm

@@ -1,337 +1,368 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR MBC
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MBC
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_MBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_HILO	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_LOW		; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
-MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_MBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPCL_RAM	.SET	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
+MPCL_ROM	.SET	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
-RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$70		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	(4915200/8)	; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	(4915200/8)	; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	3		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$80		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$88		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	3		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$80		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$88		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$B0		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	TRUE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-CVDUMODE	.EQU	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
-CVDUMON		.EQU	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	TRUE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_MBC	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_CGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MBC	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_MBC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
-RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$20		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$14		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
-ESPCONENABLE	.EQU	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPCONENABLE	.SET	TRUE		; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
-HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKTRACE	.SET	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	TRUE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_SPP	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$E8		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$EC		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_SPP	; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_SPP	; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_SPP	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_SPP	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_SPP	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_SPP	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
-UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_MBC	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	TRUE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_MBC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_mk4.asm

@@ -1,333 +1,364 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION FOR MARK IV
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MK4
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Mark IV", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_MK4		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
-Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-MK4_IDE		.EQU	$80		; MK4: IDE REGISTERS BASE ADR
-MK4_XAR		.EQU	$88		; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
-MK4_SD		.EQU	$89		; MK4: SD CARD CONTROL REGISTER ADR
-MK4_RTC		.EQU	$8A		; MK4: RTC LATCH REGISTER ADR
+MK4_IDE		.SET	$80		; MK4: IDE REGISTERS BASE ADR
+MK4_XAR		.SET	$88		; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR
+MK4_SD		.SET	$89		; MK4: SD CARD CONTROL REGISTER ADR
+MK4_RTC		.SET	$8A		; MK4: RTC LATCH REGISTER ADR
 ;
-RTCIO		.EQU	MK4_RTC		; RTC LATCH REGISTER ADR
+RTCIO		.SET	MK4_RTC		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	6		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	TRUE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$18		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$80		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$C0		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$C8		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$D0		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$D8		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	6		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	TRUE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$18		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$80		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$C0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$C8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$D0		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$D8		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$B0		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
-CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_DIDE	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
-RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
 ;
-IDEENABLE	.EQU	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_MK4	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$80		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_DIDE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$20		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$28		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$28		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	FALSE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	FALSE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_DIDE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$30		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$38		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$38		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	FALSE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	FALSE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_MK4	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$80		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_DIDE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$20		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$28		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$28		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	FALSE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	FALSE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_DIDE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$30		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$38		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$38		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	FALSE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	FALSE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	2		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$14		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	2		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$14		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$20		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MK4	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	TRUE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
-PPPBASE		.EQU	$60		; PPP: PPI REGISTERS BASE ADDRESS
-PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
-PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.SET	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.SET	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_NONE	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$E8		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$EC		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_NONE	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$E8		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$EC		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
-UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_mon.asm

@@ -1,360 +1,391 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR MONSPUTER Z80
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MON
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_MON		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	4000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	4000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_MON		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_MON		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
 ;
-RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
-SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
-WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6E		; WATCHDOG REGISTER ADR
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_n8.asm

@@ -1,326 +1,357 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION FOR N8
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: N8
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RetroBrew N8", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_N8		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
-Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-N8_PPI0		.EQU	$80		; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
-N8_PPI1		.EQU	$84		; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
-N8_RTC		.EQU	$88		; N8: RTC LATCH REGISTER ADR
-N8_ACR		.EQU	$94		; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
-N8_RMAP		.EQU	$96		; N8: ROM PAGE REGISTER ADR
-N8_DEFACR	.EQU	$1B		; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+N8_PPI0		.SET	$80		; N8: FIRST PARALLEL PORT REGISTERS BASE ADR
+N8_PPI1		.SET	$84		; N8: SECOND PARALLEL PORT REGISTERS BASE ADR
+N8_RTC		.SET	$88		; N8: RTC LATCH REGISTER ADR
+N8_ACR		.SET	$94		; N8: AUXILLARY CONTROL REGISTER (ACR) ADR
+N8_RMAP		.SET	$96		; N8: ROM PAGE REGISTER ADR
+N8_DEFACR	.SET	$1B		; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
 ;
-RTCIO		.EQU	N8_RTC		; RTC LATCH REGISTER ADR
+RTCIO		.SET	N8_RTC		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	N8_PPI0		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	N8_PPI0		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	5		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	TRUE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$C0		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$C8		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$D0		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$D8		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	5		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	TRUE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$C0		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$C8		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$D0		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$D8		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$B0		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
-CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
-RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	N8_PPI0		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	N8_PPI0		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	N8_PPI0		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	N8_PPI0		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	N8_PPI0		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
-FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_nabu.asm

@@ -1,365 +1,396 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR NABU Z80 W/ OPTION BOARD
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: NABU
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "NABU Personal Computer", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_NABU	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	3580000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	3580000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
-SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
-WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6E		; WATCHDOG REGISTER ADR
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	FALSE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_NABU	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$00		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_NABU	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$00		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$48		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$48		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NABU	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	TRUE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	TRUE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_NABU	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	TRUE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	TRUE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_NABU	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	TRUE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_NABU	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rcz180.asm

@@ -1,366 +1,391 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ180
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_RCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$0C		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPENABLE	.EQU	FALSE		; ENABLES FRONT PANEL SWITCHES
-FPBASE		.EQU	$00		; FRONT PANEL I/O PORT BASE ADDRESS
-DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
-DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
-DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+CHENABLE	.SET	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
-;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rcz280.asm

@@ -1,370 +1,401 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ280
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_RCZ280	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z280	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	24000000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z280_MEMLOWAIT	.EQU	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
-Z280_MEMHIWAIT	.EQU	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
-Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)
-Z280_TIMER	.EQU	TRUE		; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
+Z280_MEMLOWAIT	.SET	0		; Z280: LOW 8MB MEMORY WAIT STATES (0-3)
+Z280_MEMHIWAIT	.SET	0		; Z280: HIGH 8MB MEMORY WAIT STATES (0-3)
+Z280_IOWAIT	.SET	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z280_INTWAIT	.SET	0		; Z280: INT ACK WAIT STATUS (0-3)
+Z280_TIMER	.SET	TRUE		; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER
 ;
-RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
-Z2UOSC		.EQU	1843200		; Z2U: OSC FREQUENCY IN MHZ
-Z2UOSCEXT	.EQU	TRUE		; Z2U: USE EXTERNAL OSCILLATOR
-Z2U0BASE	.EQU	$10		; Z2U 0: BASE I/O ADDRESS
-Z2U0CFG		.EQU	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
-Z2U0HFC		.EQU	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UOSC		.SET	1843200		; Z2U: OSC FREQUENCY IN MHZ
+Z2UOSCEXT	.SET	TRUE		; Z2U: USE EXTERNAL OSCILLATOR
+Z2U0BASE	.SET	$10		; Z2U 0: BASE I/O ADDRESS
+Z2U0CFG		.SET	DEFSERCFG	; Z2U 0: SERIAL LINE CONFIG
+Z2U0HFC		.SET	FALSE		; Z2U 0: ENABLE HARDWARE FLOW CONTROL
 ;
-ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.EQU	7372800		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.EQU	7372800		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	7372800		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	7372800		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z280	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rcz80.asm

@@ -1,365 +1,396 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ80
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_RCZ80	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	7372800		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$C0		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_TIM16	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	CPUOSC		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
-SKZDIV		.EQU	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZDIV		.SET	DIV_1		; UART CLK (CLK2) DIVIDER FOR Z80-512K
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
-WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.SET	$6E		; WATCHDOG REGISTER ADR
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
-ACIADEBUG	.EQU	FALSE		; ACIA: ENABLE DEBUG OUTPUT
-ACIACNT		.EQU	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
-ACIA0BASE	.EQU	$80		; ACIA 0: REGISTERS BASE ADR
-ACIA0CLK	.EQU	CPUOSC		; ACIA 0: OSC FREQ IN HZ
-ACIA0DIV	.EQU	1		; ACIA 0: SERIAL CLOCK DIVIDER
-ACIA0CFG	.EQU	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
-ACIA1BASE	.EQU	$40		; ACIA 1: REGISTERS BASE ADR
-ACIA1CLK	.EQU	CPUOSC		; ACIA 1: OSC FREQ IN HZ
-ACIA1DIV	.EQU	1		; ACIA 1: SERIAL CLOCK DIVIDER
-ACIA1CFG	.EQU	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIADEBUG	.SET	FALSE		; ACIA: ENABLE DEBUG OUTPUT
+ACIACNT		.SET	1		; ACIA: NUMBER OF CHIPS TO DETECT (1-2)
+ACIA0BASE	.SET	$80		; ACIA 0: REGISTERS BASE ADR
+ACIA0CLK	.SET	CPUOSC		; ACIA 0: OSC FREQ IN HZ
+ACIA0DIV	.SET	1		; ACIA 0: SERIAL CLOCK DIVIDER
+ACIA0CFG	.SET	DEFSERCFG	; ACIA 0: SERIAL LINE CONFIG  (SEE STD.ASM)
+ACIA1BASE	.SET	$40		; ACIA 1: REGISTERS BASE ADR
+ACIA1CLK	.SET	CPUOSC		; ACIA 1: OSC FREQ IN HZ
+ACIA1DIV	.SET	1		; ACIA 1: SERIAL CLOCK DIVIDER
+ACIA1CFG	.SET	DEFSERCFG	; ACIA 1: SERIAL LINE CONFIG  (SEE STD.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_MT	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	2		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$0C		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$0C		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ80	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_RC	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_rph.asm

@@ -1,314 +1,345 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION FOR RHYOPHYRE
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RPH
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Rhyophyre", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_RPH		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	TRUE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_RPH		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
-Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-RPH_PPI0	.EQU	$88		; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
-RPH_RTC		.EQU	$84		; RPH: RTC LATCH REGISTER ADR
-RPH_ACR		.EQU	$80		; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
-RPH_DEFACR	.EQU	$20		; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
+RPH_PPI0	.SET	$88		; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR
+RPH_RTC		.SET	$84		; RPH: RTC LATCH REGISTER ADR
+RPH_ACR		.SET	$80		; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR
+RPH_DEFACR	.SET	$20		; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE)
 ;
-RTCIO		.EQU	RPH_RTC		; RTC LATCH REGISTER ADR
+RTCIO		.SET	RPH_RTC		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	RPH_PPI0	; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	RPH_PPI0	; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	RPH_PPI0	; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
-CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-GDCENABLE	.EQU	TRUE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-GDCMODE		.EQU	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
-GDCMON		.EQU	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	TRUE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+GDCMODE		.SET	GDCMODE_RPH	; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH]
+GDCMON		.SET	GDCMON_EGA      ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA]
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_N8	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_N8	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
-RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	RPH_PPI0	; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	RPH_PPI0	; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_CSIO	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	RPH_PPI0	; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	FALSE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	FALSE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	RPH_PPI0	; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	RPH_PPI0	; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
-FIFO_BASE	.EQU	$0C		; UF: REGISTERS BASE ADR
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_NONE	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_N8	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_s100.asm

@@ -1,350 +1,381 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 Z180
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: S100
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_S100	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_57600_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	1		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	2		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	1		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	2		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$0C		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	TRUE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$18		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$18		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_sbc.asm

@@ -1,315 +1,346 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SBC
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: SBC
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "RetroBrew SBC", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_SBC		; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
-MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPCL_RAM	.SET	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
+MPCL_ROM	.SET	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
-RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$70		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$B0		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	2		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	3		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	614400		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	7		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	TRUE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$80		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$18		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$C0		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$C8		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$D0		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$D8		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	7		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	TRUE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$80		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$18		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$C0		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$C8		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$D0		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$D8		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$B0		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_ZP	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$B0		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	(4915200/8)	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	(4915200/8)	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-VDUSIZ		.EQU	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-CVDUMODE	.EQU	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
-CVDUMON		.EQU	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VGASIZ		.EQU	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+VDUSIZ		.SET	V80X25		; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+CVDUMODE	.SET	CVDUMODE_ECB	; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
+CVDUMON		.SET	CVDUMON_EGA	; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_SCG	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VGASIZ		.SET	V80X25		; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_DIO3	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
-RFCNT		.EQU	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFCNT		.SET	1		; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$20		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	FALSE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	FALSE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_DIO	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$20		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$20		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$28		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	FALSE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	FALSE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$20		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$14		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$20		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$14		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_JUHA	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
-HDSKTRACE	.EQU	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKTRACE	.SET	1		; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO4BASE	.EQU	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIOZBASE	.EQU	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO4BASE	.SET	$90		; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIOZBASE	.SET	$88		; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
-UFBASE		.EQU	$0C		; UF: REGISTERS BASE ADR
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFBASE		.SET	$0C		; UF: REGISTERS BASE ADR
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_VGM	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_ECB	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_scz180.asm

@@ -1,360 +1,391 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.)
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: SCZ180
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Small Computer", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_SCZ180	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z180	; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	18432000	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	18432000	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_115200_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-RAMBIAS		.EQU	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+RAMBIAS		.SET	ROMSIZE		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
-Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
-Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)
-Z180_IOWAIT	.EQU	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
-Z180_TIMER	.EQU	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
+Z180_BASE	.SET	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
+Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
+Z180_MEMWAIT	.SET	0		; Z180: MEMORY WAIT STATES (0-3)
+Z180_IOWAIT	.SET	1		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
+Z180_TIMER	.SET	TRUE		; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
 ;
-RTCIO		.EQU	$0C		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$0C		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$88		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	TRUE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED (SINGLE LED)
-LEDMODE		.EQU	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$0E		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED (SINGLE LED)
+LEDMODE		.SET	LEDMODE_SC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$0E		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	TRUE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	TRUE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$AA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
-DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
-DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
-DUART0ACFG	.EQU	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
-DUART0BCFG	.EQU	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
-DUART1BASE	.EQU	$40		; DUART 1: BASE ADDRESS OF CHIP
-DUART1ACFG	.EQU	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
-DUART1BCFG	.EQU	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
+DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
+DUART0ACFG	.SET	DEFSERCFG	; DUART 0A: SERIAL LINE CONFIG
+DUART0BCFG	.SET	DEFSERCFG	; DUART 0B: SERIAL LINE CONFIG
+DUART1BASE	.SET	$40		; DUART 1: BASE ADDRESS OF CHIP
+DUART1ACFG	.SET	DEFSERCFG	; DUART 1A: SERIAL LINE CONFIG
+DUART1BCFG	.SET	DEFSERCFG	; DUART 1B: SERIAL LINE CONFIG
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$80		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$88		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$A0		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$A8		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	4		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$80		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$88		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$A0		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$A8		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
-ASCIINTS	.EQU	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-ASCISWAP	.EQU	FALSE		; ASCI: SWAP CHANNELS
-ASCIBOOT	.EQU	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
-ASCI0CFG	.EQU	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
-ASCI1CFG	.EQU	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
+ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIINTS	.SET	TRUE		; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+ASCISWAP	.SET	FALSE		; ASCI: SWAP CHANNELS
+ASCIBOOT	.SET	0		; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
+ASCI0CFG	.SET	DEFSERCFG	; ASCI 0: SERIAL LINE CONFIG
+ASCI1CFG	.SET	DEFSERCFG	; ASCI 1: SERIAL LINE CONFIG
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	2		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_RC	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	7372800		; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	SER_115200_8N1	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	7372800		; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	SER_115200_8N1	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_RC	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	7372800		; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	SER_115200_8N1	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	7372800		; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	SER_115200_8N1	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	2		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
-IDETRACE	.EQU	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IDECNT		.EQU	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
-IDE0MODE	.EQU	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE0BASE	.EQU	$10		; IDE 0: IO BASE ADDRESS
-IDE0DATLO	.EQU	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
-IDE0DATHI	.EQU	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
-IDE0A8BIT	.EQU	TRUE		; IDE 0A (MASTER): 8 BIT XFER
-IDE0B8BIT	.EQU	TRUE		; IDE 0B (MASTER): 8 BIT XFER
-IDE1MODE	.EQU	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE1BASE	.EQU	$00		; IDE 1: IO BASE ADDRESS
-IDE1DATLO	.EQU	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
-IDE1DATHI	.EQU	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
-IDE1A8BIT	.EQU	TRUE		; IDE 1A (MASTER): 8 BIT XFER
-IDE1B8BIT	.EQU	TRUE		; IDE 1B (MASTER): 8 BIT XFER
-IDE2MODE	.EQU	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
-IDE2BASE	.EQU	$00		; IDE 2: IO BASE ADDRESS
-IDE2DATLO	.EQU	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
-IDE2DATHI	.EQU	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
-IDE2A8BIT	.EQU	TRUE		; IDE 2A (MASTER): 8 BIT XFER
-IDE2B8BIT	.EQU	TRUE		; IDE 2B (MASTER): 8 BIT XFER
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDETRACE	.SET	1		; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IDECNT		.SET	1		; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
+IDE0MODE	.SET	IDEMODE_RC	; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE0BASE	.SET	$10		; IDE 0: IO BASE ADDRESS
+IDE0DATLO	.SET	$00		; IDE 0: DATA LO PORT FOR 16-BIT I/O
+IDE0DATHI	.SET	$00		; IDE 0: DATA HI PORT FOR 16-BIT I/O
+IDE0A8BIT	.SET	TRUE		; IDE 0A (MASTER): 8 BIT XFER
+IDE0B8BIT	.SET	TRUE		; IDE 0B (MASTER): 8 BIT XFER
+IDE1MODE	.SET	IDEMODE_NONE	; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE1BASE	.SET	$00		; IDE 1: IO BASE ADDRESS
+IDE1DATLO	.SET	$00		; IDE 1: DATA LO PORT FOR 16-BIT I/O
+IDE1DATHI	.SET	$00		; IDE 1: DATA HI PORT FOR 16-BIT I/O
+IDE1A8BIT	.SET	TRUE		; IDE 1A (MASTER): 8 BIT XFER
+IDE1B8BIT	.SET	TRUE		; IDE 1B (MASTER): 8 BIT XFER
+IDE2MODE	.SET	IDEMODE_NONE	; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
+IDE2BASE	.SET	$00		; IDE 2: IO BASE ADDRESS
+IDE2DATLO	.SET	$00		; IDE 2: DATA LO PORT FOR 16-BIT I/O
+IDE2DATHI	.SET	$00		; IDE 2: DATA HI PORT FOR 16-BIT I/O
+IDE2A8BIT	.SET	TRUE		; IDE 2A (MASTER): 8 BIT XFER
+IDE2B8BIT	.SET	TRUE		; IDE 2B (MASTER): 8 BIT XFER
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$20		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE1BASE	.EQU	$00		; PPIDE 1: PPI REGISTERS BASE ADR
-PPIDE1A8BIT	.EQU	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
-PPIDE1B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
-PPIDE2BASE	.EQU	$00		; PPIDE 2: PPI REGISTERS BASE ADR
-PPIDE2A8BIT	.EQU	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
-PPIDE2B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$20		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE1BASE	.SET	$00		; PPIDE 1: PPI REGISTERS BASE ADR
+PPIDE1A8BIT	.SET	FALSE		; PPIDE 1A (MASTER): 8 BIT XFER
+PPIDE1B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDE2BASE	.SET	$00		; PPIDE 2: PPI REGISTERS BASE ADR
+PPIDE2A8BIT	.SET	FALSE		; PPIDE 2A (MASTER): 8 BIT XFER
+PPIDE2B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_SC	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
-CHTRACE		.EQU	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHUSBTRACE	.EQU	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHSDTRACE	.EQU	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-CHCNT		.EQU	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
-CH0BASE		.EQU	$3E		; CH 0: BASE I/O ADDRESS
-CH0USBENABLE	.EQU	TRUE		; CH 0: ENABLE USB DISK
-CH0SDENABLE	.EQU	FALSE		; CH 0: ENABLE SD DISK
-CH1BASE		.EQU	$3C		; CH 1: BASE I/O ADDRESS
-CH1USBENABLE	.EQU	TRUE		; CH 1: ENABLE USB DISK
-CH1SDENABLE	.EQU	FALSE		; CH 1: ENABLE SD DISK
+CHENABLE	.SET	TRUE		; CH: ENABLE CH375/376 USB SUPPORT
+CHTRACE		.SET	1		; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHUSBTRACE	.SET	1		; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHSDTRACE	.SET	1		; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+CHCNT		.SET	2		; CH: NUMBER OF BOARDS TO DETECT (1-2)
+CH0BASE		.SET	$3E		; CH 0: BASE I/O ADDRESS
+CH0USBENABLE	.SET	TRUE		; CH 0: ENABLE USB DISK
+CH0SDENABLE	.SET	FALSE		; CH 0: ENABLE SD DISK
+CH1BASE		.SET	$3C		; CH 1: BASE I/O ADDRESS
+CH1USBENABLE	.SET	TRUE		; CH 1: ENABLE USB DISK
+CH1SDENABLE	.SET	FALSE		; CH 1: ENABLE SD DISK
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
-PRPSDENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
-PRPSDTRACE	.EQU	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PRPCONENABLE	.EQU	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPSDENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
+PRPSDTRACE	.SET	1		; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PRPCONENABLE	.SET	TRUE		; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
-PIOCNT		.EQU	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-PIO0BASE	.EQU	$B8		; PIO 0: REGISTERS BASE ADR
-PIO1BASE	.EQU	$BC		; PIO 1: REGISTERS BASE ADR
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOCNT		.SET	2		; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+PIO0BASE	.SET	$B8		; PIO 0: REGISTERS BASE ADR
+PIO1BASE	.SET	$BC		; PIO 1: REGISTERS BASE ADR
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
-LPTMODE		.EQU	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
-LPTCNT		.EQU	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
-LPTTRACE	.EQU	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-LPT0BASE	.EQU	$18		; LPT 0: REGISTERS BASE ADR
-LPT1BASE	.EQU	$00		; LPT 1: REGISTERS BASE ADR
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTMODE		.SET	LPTMODE_MG014	; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
+LPTCNT		.SET	1		; LPT: NUMBER OF CHIPS TO DETECT (1-2)
+LPTTRACE	.SET	1		; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+LPT0BASE	.SET	$18		; LPT 0: REGISTERS BASE ADR
+LPT1BASE	.SET	$00		; LPT 1: REGISTERS BASE ADR
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
-PPACNT		.EQU	1		; PPA: NUMBER OF PPA DEVICES (1-2)
-PPATRACE	.EQU	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPAMODE		.EQU	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
-PPA0BASE	.EQU	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
-PPA1BASE	.EQU	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPACNT		.SET	1		; PPA: NUMBER OF PPA DEVICES (1-2)
+PPATRACE	.SET	1		; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPAMODE		.SET	PPAMODE_MG014	; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
+PPA0BASE	.SET	LPT0BASE	; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
+PPA1BASE	.SET	LPT1BASE	; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
-IMMCNT		.EQU	1		; IMM: NUMBER OF IMM DEVICES (1-2)
-IMMTRACE	.EQU	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-IMMMODE		.EQU	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
-IMM0BASE	.EQU	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
-IMM1BASE	.EQU	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMCNT		.SET	1		; IMM: NUMBER OF IMM DEVICES (1-2)
+IMMTRACE	.SET	1		; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+IMMMODE		.SET	IMMMODE_MG014	; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
+IMM0BASE	.SET	LPT0BASE	; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
+IMM1BASE	.SET	LPT1BASE	; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
-SYQCNT		.EQU	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
-SYQTRACE	.EQU	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SYQMODE		.EQU	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
-SYQ0BASE	.EQU	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
-SYQ1BASE	.EQU	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQCNT		.SET	1		; SYQ: NUMBER OF SYQ DEVICES (1-2)
+SYQTRACE	.SET	1		; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SYQMODE		.SET	IMMMODE_MG014	; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
+SYQ0BASE	.SET	LPT0BASE	; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
+SYQ1BASE	.SET	LPT1BASE	; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
-AUDIOTRACE	.EQU	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
-SN7CLK		.EQU	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
-SNMODE		.EQU	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
+SN76489ENABLE	.SET	FALSE		; SN: ENABLE SN76489 SOUND DRIVER
+AUDIOTRACE	.SET	FALSE		; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
+SN7CLK		.SET	3579545		; SN: PSG CLOCK FREQ, ASSUME MSX STD
+SNMODE		.SET	SNMODE_RC	; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
 ;
-AY38910ENABLE	.EQU	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
-AY_CLK		.EQU	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
-AYMODE		.EQU	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
+AY38910ENABLE	.SET	FALSE		; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
+AY_CLK		.SET	1789772		; AY: PSG CLOCK FREQ, ASSUME MSX STD
+AYMODE		.SET	AYMODE_RCZ180	; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU]
 ;
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_Z180	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_z80retro.asm

@@ -1,281 +1,312 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: Z80RETRO
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_Z80RETRO	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	14745600	; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	14745600	; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$62		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$63		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$64		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$60		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$61		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$62		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$63		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$64		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$70		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$40		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
-CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$40		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	FALSE		; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now)
+CTCMODE		.SET	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	0		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	1		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	7372800		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	$00		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	$00		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$FF		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$FF		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	DEFSERCFG	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
-SIODEBUG	.EQU	FALSE		; SIO: ENABLE DEBUG OUTPUT
-SIOBOOT		.EQU	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
-SIOCNT		.EQU	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
-SIOINTS		.EQU	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
-SIO0MODE	.EQU	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO0BASE	.EQU	$80		; SIO 0: REGISTERS BASE ADR
-SIO0ACLK	.EQU	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0ACFG	.EQU	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
-SIO0ACTCC	.EQU	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO0BCLK	.EQU	CPUOSC/2	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO0BCFG	.EQU	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
-SIO0BCTCC	.EQU	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1MODE	.EQU	SIOMODE_Z80R	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
-SIO1BASE	.EQU	$84		; SIO 1: REGISTERS BASE ADR
-SIO1ACLK	.EQU	CPUOSC/2	; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1ACFG	.EQU	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
-SIO1ACTCC	.EQU	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
-SIO1BCLK	.EQU	CPUOSC/2	; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
-SIO1BCFG	.EQU	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
-SIO1BCTCC	.EQU	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIODEBUG	.SET	FALSE		; SIO: ENABLE DEBUG OUTPUT
+SIOBOOT		.SET	0		; SIO: REBOOT ON RCV CHAR (0=DISABLED)
+SIOCNT		.SET	1		; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SIOINTS		.SET	TRUE		; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3
+SIO0MODE	.SET	SIOMODE_Z80R	; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO0BASE	.SET	$80		; SIO 0: REGISTERS BASE ADR
+SIO0ACLK	.SET	CPUOSC/2	; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0ACFG	.SET	DEFSERCFG	; SIO 0A: SERIAL LINE CONFIG
+SIO0ACTCC	.SET	-1		; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO0BCLK	.SET	CPUOSC/2	; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO0BCFG	.SET	DEFSERCFG	; SIO 0B: SERIAL LINE CONFIG
+SIO0BCTCC	.SET	-1		; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1MODE	.SET	SIOMODE_Z80R	; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
+SIO1BASE	.SET	$84		; SIO 1: REGISTERS BASE ADR
+SIO1ACLK	.SET	CPUOSC/2	; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1ACFG	.SET	DEFSERCFG	; SIO 1A: SERIAL LINE CONFIG
+SIO1ACTCC	.SET	-1		; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SIO1BCLK	.SET	CPUOSC/2	; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
+SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	TRUE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_Z80R	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
-PPPBASE		.EQU	$60		; PPP: PPI REGISTERS BASE ADDRESS
-PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
-PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.SET	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.SET	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
-AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SN76489ENABLE	.SET	FALSE		; SN76489 SOUND DRIVER
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_zeta.asm

@@ -1,251 +1,282 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V1
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Zeta", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_ZETA	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; BIOS_[WBW|UNA]: HARDWARE BIOS
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
-MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPCL_RAM	.SET	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
+MPCL_ROM	.SET	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
-RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$70		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
+CTCENABLE	.SET	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_RTC	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_ZETA	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
-PPPBASE		.EQU	$60		; PPP: PPI REGISTERS BASE ADDRESS
-PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
-PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.SET	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.SET	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
-AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SN76489ENABLE	.SET	FALSE		; SN76489 SOUND DRIVER
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/HBIOS/cfg_zeta2.asm

@@ -1,262 +1,293 @@
 ;
 ;==================================================================================================
-;   ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V2
+;   ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA2
 ;==================================================================================================
 ;
-; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
-; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD, YOU SHOULD
-; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
-; UNDER THIS DIRECTORY.
+; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
+; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.	INSTEAD,
+; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN
+; THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
 ;
-; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
-; FOR THE PLATFORM.
+; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED.  IT IS MAINTAINED BY THE
+; AUTHORS OF ROMWBW.  TO OVERRIDE SETTINGS YOU SHOULD USE A
+; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY.
+;
+; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW:
+;
+; cfg_master.asm			- MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+; |
+; +-> cfg_<platform>.asm		- PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+;     |
+;     +-> Config/<plt>_std.asm		- DEFAULT BUILD SETTINGS FOR PLATFORM
+;         |
+;         +-> Config/<plt>_<cust>.asm	- OPTIONAL CUSTOM USER SETTINGS
+;
+; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW
+; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE
+; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY
+; OVERRIDE THESE SETTINGS AS DESIRED.
+;
+; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT
+; FILE (SEE #INCLUDE STATEMENT BELOW).  THE TOP TWO FILES SHOULD NOT BE
+; MODIFIED.  TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE
+; DEFAULT BUILD SETTINGS (Config/<platform>_std.asm) OR PREFERABLY
+; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT
+; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm).
+;
+; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE
+; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL ONLY BE INHERITING MOST
+; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES.
+;
+; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE
+; ".SET" TO OVERRIDE SETTINGS.  THE ASSEMBLER WILL ERROR IF YOU ATTEMPT
+; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU".
 ;
 #DEFINE PLATFORM_NAME "Zeta 2", " [", CONFIG, "]"
 ;
-#INCLUDE "hbios.inc"
+#INCLUDE "cfg_master.asm"
 ;
-PLATFORM	.EQU	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
-CPUFAM		.EQU	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
-BIOS		.EQU	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
-BATCOND		.EQU	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
-HBIOS_MUTEX	.EQU	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
-USELZSA2	.EQU	TRUE		; ENABLE FONT COMPRESSION
-TICKFREQ	.EQU	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
+PLATFORM	.SET	PLT_ZETA2	; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80]
+CPUFAM		.SET	CPU_Z80		; CPU FAMILY: CPU_[Z80|Z180|Z280]
+BIOS		.SET	BIOS_WBW	; HARDWARE BIOS: BIOS_[WBW|UNA]
+BATCOND		.SET	FALSE		; ENABLE LOW BATTERY WARNING MESSAGE
+HBIOS_MUTEX	.SET	FALSE		; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
+USELZSA2	.SET	TRUE		; ENABLE FONT COMPRESSION
+TICKFREQ	.SET	50		; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
 ;
-BOOT_TIMEOUT	.EQU	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
-BOOT_DELAY	.EQU	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
-AUTOCON		.EQU	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
+BOOT_TIMEOUT	.SET	-1		; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
+BOOT_DELAY	.SET	0		; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
+AUTOCON		.SET	TRUE		; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT
 ;
-CPUSPDCAP	.EQU	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
-CPUSPDDEF	.EQU	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
-CPUOSC		.EQU	8000000		; CPU OSC FREQ IN MHZ
-INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
-DEFSERCFG	.EQU	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
+CPUSPDCAP	.SET	SPD_FIXED	; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
+CPUSPDDEF	.SET	SPD_HIGH	; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
+CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
+INTMODE		.SET	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
+DEFSERCFG	.SET	SER_38400_8N1 | SER_RTS	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
-RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-ROMSIZE		.EQU	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
-APP_BNKS	.EQU	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
-MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
-MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
-MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
+RAMSIZE		.SET	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+ROMSIZE		.SET	512		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
+APP_BNKS	.SET	$FF		; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING)
+MEMMGR		.SET	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON]
+MPGSEL_0	.SET	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_1	.SET	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_2	.SET	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
+MPGSEL_3	.SET	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
+MPGENA		.SET	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
-RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
+RTCIO		.SET	$70		; RTC LATCH REGISTER ADR
 ;
-KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
-KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
+KIOENABLE	.SET	FALSE		; ENABLE ZILOG KIO SUPPORT
+KIOBASE		.SET	$80		; KIO BASE I/O ADDRESS
 ;
-CTCENABLE	.EQU	TRUE		; ENABLE ZILOG CTC SUPPORT
-CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
-CTCBASE		.EQU	$20		; CTC BASE I/O ADDRESS
-CTCTIMER	.EQU	TRUE		; ENABLE CTC PERIODIC TIMER
-CTCMODE		.EQU	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
-CTCPRE		.EQU	256		; PRESCALE CONSTANT (1-256)
-CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
-CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
-CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
+CTCENABLE	.SET	TRUE		; ENABLE ZILOG CTC SUPPORT
+CTCDEBUG	.SET	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
+CTCBASE		.SET	$20		; CTC BASE I/O ADDRESS
+CTCTIMER	.SET	TRUE		; ENABLE CTC PERIODIC TIMER
+CTCMODE		.SET	CTCMODE_CTR	; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
+CTCPRE		.SET	256		; PRESCALE CONSTANT (1-256)
+CTCPRECH	.SET	0		; PRESCALE CHANNEL (0-3)
+CTCTIMCH	.SET	1		; TIMER CHANNEL (0-3)
+CTCOSC		.SET	921600		; CTC CLOCK FREQUENCY
 ;
-PCFENABLE	.EQU	FALSE		; ENABLE PCF8584 I2C CONTROLLER
-PCFBASE		.EQU	$F0		; PCF8584 BASE I/O ADDRESS
+PCFENABLE	.SET	FALSE		; ENABLE PCF8584 I2C CONTROLLER
+PCFBASE		.SET	$F0		; PCF8584 BASE I/O ADDRESS
 ;
-EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+EIPCENABLE	.SET	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
-SKZENABLE	.EQU	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
+SKZENABLE	.SET	FALSE		; ENABLE SERGEY'S Z80-512K FEATURES
 ;
-WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGMODE	.SET	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
 ;
-FPLED_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL LEDS
-FPLED_IO	.EQU	$00		; FP: PORT ADDRESS FOR FP LEDS
-FPLED_INV	.EQU	FALSE		; FP: LED BITS ARE INVERTED
-FPLED_DSKACT	.EQU	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
-FPSW_ENABLE	.EQU	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
-FPSW_IO		.EQU	$00		; FP: PORT ADDRESS FOR FP SWITCHES
-FPSW_INV	.EQU	FALSE		; FP: SWITCH BITS ARE INVERTED
+FPLED_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL LEDS
+FPLED_IO	.SET	$00		; FP: PORT ADDRESS FOR FP LEDS
+FPLED_INV	.SET	FALSE		; FP: LED BITS ARE INVERTED
+FPLED_DSKACT	.SET	TRUE		; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
+FPSW_ENABLE	.SET	FALSE		; FP: ENABLES FRONT PANEL SWITCHES
+FPSW_IO		.SET	$00		; FP: PORT ADDRESS FOR FP SWITCHES
+FPSW_INV	.SET	FALSE		; FP: SWITCH BITS ARE INVERTED
 ;
-DIAGLVL		.EQU	DL_CRITICAL	; ERROR LEVEL REPORTING
+DIAGLVL		.SET	DL_CRITICAL	; ERROR LEVEL REPORTING
 ;
-LEDENABLE	.EQU	FALSE		; ENABLES STATUS LED
-LEDMODE		.EQU	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
-LEDPORT		.EQU	RTCIO		; STATUS LED PORT ADDRESS
-LEDDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
+LEDENABLE	.SET	FALSE		; ENABLES STATUS LED
+LEDMODE		.SET	LEDMODE_STD	; LEDMODE_[STD|SC|RTC|NABU]
+LEDPORT		.SET	RTCIO		; STATUS LED PORT ADDRESS
+LEDDISKIO	.SET	TRUE		; ENABLES DISK I/O ACTIVITY ON STATUS LED
 ;
-DSKYENABLE	.EQU	FALSE		; ENABLES DSKY FUNCTIONALITY
-DSKYDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
-ICMENABLE	.EQU	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
-ICMPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF ICM PPI
-PKDENABLE	.EQU	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
-PKDPPIBASE	.EQU	$60		; BASE I/O ADDRESS OF PKD PPI
-PKDOSC		.EQU	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
-H8PENABLE	.EQU	FALSE		; ENABLES HEATH H8 FRONT PANEL
-LCDENABLE	.EQU	FALSE		; ENABLE LCD DISPLAY
-LCDBASE		.EQU	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
-LCDDSKACT	.EQU	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
-GM7303ENABLE	.EQU	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
+DSKYENABLE	.SET	FALSE		; ENABLES DSKY FUNCTIONALITY
+DSKYDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON DSKY DISPLAY
+ICMENABLE	.SET	FALSE		; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
+ICMPPIBASE	.SET	$60		; BASE I/O ADDRESS OF ICM PPI
+PKDENABLE	.SET	FALSE		; ENABLES DSKY NG PKD DRIVER (8259)
+PKDPPIBASE	.SET	$60		; BASE I/O ADDRESS OF PKD PPI
+PKDOSC		.SET	3000000		; OSCILLATOR FREQ FOR PKD (IN HZ)
+H8PENABLE	.SET	FALSE		; ENABLES HEATH H8 FRONT PANEL
+LCDENABLE	.SET	FALSE		; ENABLE LCD DISPLAY
+LCDBASE		.SET	$DA		; BASE I/O ADDRESS OF LCD CONTROLLER
+LCDDSKACT	.SET	TRUE		; ENABLES DISK ACTIVITY ON LCD DISPLAY
+GM7303ENABLE	.SET	FALSE		; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD
 ;
-BOOTCON		.EQU	0		; BOOT CONSOLE DEVICE
-SECCON		.EQU	$FF		; SECONDARY CONSOLE DEVICE
-CRTACT		.EQU	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
-VDAEMU		.EQU	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
-VDAEMU_SERKBD	.EQU	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
-ANSITRACE	.EQU	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPKTRACE	.EQU	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDTRACE	.EQU	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-KBDKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
-PPKKBLOUT	.EQU	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
-MKYKBLOUT	.EQU	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+BOOTCON		.SET	0		; BOOT CONSOLE DEVICE
+SECCON		.SET	$FF		; SECONDARY CONSOLE DEVICE
+CRTACT		.SET	FALSE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
+VDAEMU		.SET	EMUTYP_ANSI	; VDA EMULATION: EMUTYP_[TTY|ANSI]
+VDAEMU_SERKBD	.SET	$FF		; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
+ANSITRACE	.SET	1		; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPKTRACE	.SET	1		; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDTRACE	.SET	1		; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+KBDKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
+PPKKBLOUT	.SET	KBD_US		; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
+MKYKBLOUT	.SET	KBD_US		; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
 ;
-DSRTCENABLE	.EQU	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
-DSRTCMODE	.EQU	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
-DSRTCCHG	.EQU	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
+DSRTCENABLE	.SET	TRUE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
+DSRTCMODE	.SET	DSRTCMODE_STD	; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W]
+DSRTCCHG	.SET	FALSE		; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
 ;
-DS1501RTCENABLE	.EQU	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
-DS1501RTC_BASE	.EQU	$50		; DS1501RTC: I/O BASE ADDRESS
+DS1501RTCENABLE	.SET	FALSE		; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
+DS1501RTC_BASE	.SET	$50		; DS1501RTC: I/O BASE ADDRESS
 ;
-BQRTCENABLE	.EQU	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
-BQRTC_BASE	.EQU	$50		; BQRTC: I/O BASE ADDRESS
+BQRTCENABLE	.SET	FALSE		; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
+BQRTC_BASE	.SET	$50		; BQRTC: I/O BASE ADDRESS
 ;
-INTRTCENABLE	.EQU	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
+INTRTCENABLE	.SET	FALSE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
-RP5RTCENABLE	.EQU	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
+RP5RTCENABLE	.SET	FALSE		; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
 ;
-HTIMENABLE	.EQU	FALSE		; ENABLE SIMH TIMER SUPPORT
-SIMRTCENABLE	.EQU	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
+HTIMENABLE	.SET	FALSE		; ENABLE SIMH TIMER SUPPORT
+SIMRTCENABLE	.SET	FALSE		; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
 ;
-DS7RTCENABLE	.EQU	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
-DS7RTCMODE	.EQU	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
+DS7RTCENABLE	.SET	FALSE		; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
+DS7RTCMODE	.SET	DS7RTCMODE_PCF	; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
 ;
-DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
+DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.EQU	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERCFG		.EQU	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
-SSERSTATUS	.EQU	$FF		; SSER: STATUS PORT
-SSERDATA	.EQU	$FF		; SSER: DATA PORT
-SSERIRDY	.EQU	%00000001	; SSER: INPUT READY BIT MASK
-SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
+SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
+SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
+SSERDATA	.SET	$FF		; SSER: DATA PORT
+SSERIRDY	.SET	%00000001	; SSER: INPUT READY BIT MASK
+SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
+SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
+SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
-DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
+DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
-UARTENABLE	.EQU	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
-UARTCNT		.EQU	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
-UARTOSC		.EQU	1843200		; UART: OSC FREQUENCY IN MHZ
-UARTINTS	.EQU	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
-UART4UART	.EQU	FALSE		; UART: SUPPORT 4UART ECB BOARD
-UART4UARTBASE	.EQU	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
-UART0BASE	.EQU	$68		; UART 0: REGISTERS BASE ADR
-UART0CFG	.EQU	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
-UART1BASE	.EQU	$FF		; UART 1: REGISTERS BASE ADR
-UART1CFG	.EQU	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
-UART2BASE	.EQU	$FF		; UART 2: REGISTERS BASE ADR
-UART2CFG	.EQU	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
-UART3BASE	.EQU	$FF		; UART 3: REGISTERS BASE ADR
-UART3CFG	.EQU	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
-UART4BASE	.EQU	$FF		; UART 4: REGISTERS BASE ADR
-UART4CFG	.EQU	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
-UART5BASE	.EQU	$FF		; UART 5: REGISTERS BASE ADR
-UART5CFG	.EQU	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
-UART6BASE	.EQU	$FF		; UART 6: REGISTERS BASE ADR
-UART6CFG	.EQU	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
-UART7BASE	.EQU	$FF		; UART 7: REGISTERS BASE ADR
-UART7CFG	.EQU	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+UARTCNT		.SET	1		; UART: NUMBER OF CHIPS TO DETECT (1-8)
+UARTOSC		.SET	1843200		; UART: OSC FREQUENCY IN MHZ
+UARTINTS	.SET	FALSE		; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
+UART4UART	.SET	FALSE		; UART: SUPPORT 4UART ECB BOARD
+UART4UARTBASE	.SET	$C0		; UART: BASE IO ADDRESS OF 4UART ECB BOARD
+UART0BASE	.SET	$68		; UART 0: REGISTERS BASE ADR
+UART0CFG	.SET	DEFSERCFG	; UART 0: SERIAL LINE CONFIG
+UART1BASE	.SET	$FF		; UART 1: REGISTERS BASE ADR
+UART1CFG	.SET	SER_300_8N1	; UART 1: SERIAL LINE CONFIG
+UART2BASE	.SET	$FF		; UART 2: REGISTERS BASE ADR
+UART2CFG	.SET	DEFSERCFG	; UART 2: SERIAL LINE CONFIG
+UART3BASE	.SET	$FF		; UART 3: REGISTERS BASE ADR
+UART3CFG	.SET	DEFSERCFG	; UART 3: SERIAL LINE CONFIG
+UART4BASE	.SET	$FF		; UART 4: REGISTERS BASE ADR
+UART4CFG	.SET	DEFSERCFG	; UART 4: SERIAL LINE CONFIG
+UART5BASE	.SET	$FF		; UART 5: REGISTERS BASE ADR
+UART5CFG	.SET	DEFSERCFG	; UART 5: SERIAL LINE CONFIG
+UART6BASE	.SET	$FF		; UART 6: REGISTERS BASE ADR
+UART6CFG	.SET	DEFSERCFG	; UART 6: SERIAL LINE CONFIG
+UART7BASE	.SET	$FF		; UART 7: REGISTERS BASE ADR
+UART7CFG	.SET	DEFSERCFG	; UART 7: SERIAL LINE CONFIG
 ;
-ASCIENABLE	.EQU	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
+ASCIENABLE	.SET	FALSE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 ;
-Z2UENABLE	.EQU	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
+Z2UENABLE	.SET	FALSE		; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
 ;
-ACIAENABLE	.EQU	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+ACIAENABLE	.SET	FALSE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 ;
-SIOENABLE	.EQU	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SIOENABLE	.SET	FALSE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
 ;
-XIOCFG		.EQU	DEFSERCFG	; XIO: SERIAL LINE CONFIG
+XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
-VDUENABLE	.EQU	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
-CVDUENABLE	.EQU	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
-GDCENABLE	.EQU	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
-TMSENABLE	.EQU	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
-TMSMODE		.EQU	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
-TMS80COLS	.EQU	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
-TMSTIMENABLE	.EQU	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
-VGAENABLE	.EQU	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
-VRCENABLE	.EQU	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
-SCONENABLE	.EQU	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
-EFENABLE	.EQU	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
-FVENABLE	.EQU	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
+VDUENABLE	.SET	FALSE		; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
+CVDUENABLE	.SET	FALSE		; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
+GDCENABLE	.SET	FALSE		; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSMODE		.SET	TMSMODE_NONE	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU]
+TMS80COLS	.SET	FALSE		; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+VGAENABLE	.SET	FALSE		; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
+VRCENABLE	.SET	FALSE		; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
+SCONENABLE	.SET	FALSE		; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM)
+EFENABLE	.SET	FALSE		; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM)
+FVENABLE	.SET	FALSE		; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM)
 ;
-MDENABLE	.EQU	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
-MDROM		.EQU	TRUE		; MD: ENABLE ROM DISK
-MDRAM		.EQU	TRUE		; MD: ENABLE RAM DISK
-MDTRACE		.EQU	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-MDFFENABLE	.EQU	FALSE		; MD: ENABLE FLASH FILE SYSTEM
+MDENABLE	.SET	TRUE		; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
+MDROM		.SET	TRUE		; MD: ENABLE ROM DISK
+MDRAM		.SET	TRUE		; MD: ENABLE RAM DISK
+MDTRACE		.SET	1		; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+MDFFENABLE	.SET	FALSE		; MD: ENABLE FLASH FILE SYSTEM
 ;
-FDENABLE	.EQU	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
-FDMODE		.EQU	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
-FDCNT		.EQU	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
-FDTRACE		.EQU	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
-FDMAUTO		.EQU	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
-FD0TYPE		.EQU	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
-FD1TYPE		.EQU	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FDENABLE	.SET	TRUE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_ZETA2	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
+FDCNT		.SET	1		; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
+FDTRACE		.SET	1		; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
+FDMAUTO		.SET	TRUE		; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
+FD0TYPE		.SET	FDT_3HD		; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
+FD1TYPE		.SET	FDT_3HD		; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
 ;
-RFENABLE	.EQU	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
+RFENABLE	.SET	FALSE		; RF: ENABLE RAM FLOPPY DRIVER
 ;
-IDEENABLE	.EQU	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+IDEENABLE	.SET	FALSE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
 ;
-PPIDEENABLE	.EQU	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
-PPIDETRACE	.EQU	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPIDECNT	.EQU	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
-PPIDE0BASE	.EQU	$60		; PPIDE 0: PPI REGISTERS BASE ADR
-PPIDE0A8BIT	.EQU	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
-PPIDE0B8BIT	.EQU	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
+PPIDEENABLE	.SET	FALSE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+PPIDETRACE	.SET	1		; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPIDECNT	.SET	1		; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
+PPIDE0BASE	.SET	$60		; PPIDE 0: PPI REGISTERS BASE ADR
+PPIDE0A8BIT	.SET	FALSE		; PPIDE 0A (MASTER): 8 BIT XFER
+PPIDE0B8BIT	.SET	FALSE		; PPIDE 0B (SLAVE): 8 BIT XFER
 ;
-SDENABLE	.EQU	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
-SDMODE		.EQU	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
-SDPPIBASE	.EQU	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
-SDCNT		.EQU	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
-SDTRACE		.EQU	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-SDCSIOFAST	.EQU	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
-SDMTSWAP	.EQU	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
+SDENABLE	.SET	FALSE		; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
+SDMODE		.SET	SDMODE_PPI	; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80]
+SDPPIBASE	.SET	$60		; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
+SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
+SDTRACE		.SET	1		; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+SDCSIOFAST	.SET	FALSE		; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
+SDMTSWAP	.SET	FALSE		; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
 ;
-CHENABLE	.EQU	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
+CHENABLE	.SET	FALSE		; CH: ENABLE CH375/376 USB SUPPORT
 ;
-PRPENABLE	.EQU	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
 ;
-PPPENABLE	.EQU	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
-PPPBASE		.EQU	$60		; PPP: PPI REGISTERS BASE ADDRESS
-PPPSDENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
-PPPSDTRACE	.EQU	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
-PPPCONENABLE	.EQU	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
+PPPENABLE	.SET	FALSE		; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
+PPPBASE		.SET	$60		; PPP: PPI REGISTERS BASE ADDRESS
+PPPSDENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER SD CARD SUPPORT
+PPPSDTRACE	.SET	1		; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
+PPPCONENABLE	.SET	TRUE		; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT
 ;
-ESPENABLE	.EQU	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
+ESPENABLE	.SET	FALSE		; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM)
 ;
-HDSKENABLE	.EQU	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
+HDSKENABLE	.SET	FALSE		; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
 ;
-PIOENABLE	.EQU	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
+PIOENABLE	.SET	FALSE		; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
 ;
-LPTENABLE	.EQU	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
+LPTENABLE	.SET	FALSE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
-PPAENABLE	.EQU	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
+PPAENABLE	.SET	FALSE		; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
 ;
-IMMENABLE	.EQU	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
+IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
-SYQENABLE	.EQU	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
+SYQENABLE	.SET	FALSE		; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
 ;
-PIO_4P		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
-PIO_ZP		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
-PIO_SBC		.EQU	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
-PIOSBASE	.EQU	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
+PIO_4P		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
+PIO_ZP		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
+PIO_SBC		.SET	FALSE		; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
+PIOSBASE	.SET	$60		; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
 ;
-UFENABLE	.EQU	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
+UFENABLE	.SET	FALSE		; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
 ;
-SN76489ENABLE	.EQU	FALSE		; SN76489 SOUND DRIVER
-AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
-SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
+SN76489ENABLE	.SET	FALSE		; SN76489 SOUND DRIVER
+AY38910ENABLE	.SET	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
+SPKENABLE	.SET	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
 ;
-DMAENABLE	.EQU	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
-DMABASE		.EQU	$E0		; DMA: DMA BASE ADDRESS
-DMAMODE		.EQU	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
+DMAENABLE	.SET	FALSE		; DMA: ENABLE DMA DRIVER (DMA.ASM)
+DMABASE		.SET	$E0		; DMA: DMA BASE ADDRESS
+DMAMODE		.SET	DMAMODE_NONE	; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO)
 ;
-YM2612ENABLE	.EQU	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
-VGMBASE		.EQU	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)
+YM2612ENABLE	.SET	FALSE		; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
+VGMBASE		.SET	$C0		; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC)

Source/ReadMe.txt

@@ -140,9 +140,33 @@ Each of the 4 steps above is described in more detail below.
 -----------------------------------
 
 The options for a build are primarily controlled by a configuration 
-file that is included in the build process.  In order to customize 
-your settings, it is easiest to make a copy of an existing 
-configuration file and make your changes there.
+file that is included in the build process.
+
+RomWBW uses cascading configuration files as indicated below:
+
+  cfg_master.asm - MASTER CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS
+    |
+    +-- cfg_<platform>.asm - PLATFORM SPECIFIC DEFAULT CONFIGURATION SETTINGS
+          |
+          +-- Config/<platform>_std.asm - DEFAULT BUILD SETTINGS FOR PLATFORM
+                |
+                +-- Config/<platform>_<custom>.asm - OPTIONAL CUSTOM USER SETTINGS
+
+The top (master configuration) file defines all possible RomWBW
+configuration settings. Each file below the master configuration file
+inherits the cumulative settings of the files above it and may
+override these settings as desired.
+
+Other than the top master file, each file must "#INCLUDE" its parent 
+file.  The top two files should not be modified.  To customize your 
+build settings you should modify the default build settings 
+(config/<platform>_std.asm) or preferably create an optional custom 
+user settings file that includes the default build settings file (see 
+example Config/SBC_user.asm).
+
+By creating a custom user settings file, you are less likely to be
+impacted by future changes because you will only be inheriting most
+of your settings which will be updated by authors as RomWBW evolves.
 
 RomWBW uses the concept of a "platform" and "configuration" to
 define the settings for a build.  Platform refers to one of the core
@@ -153,23 +177,29 @@ defaults as desired.
 The platform names are predefined.  Refer to the following table 
 to determine the <plt> component of the configuration filename:
 
-	SBC		Retrocomputing ECB Z80 SBC V1/V2
-	N8		RetroComputing N8 SBC
-	MK4		RetroComputing Mark IV Z180
-	ZETA		Sergey Kiselev's Zeta Z80
-	ZETA2		Sergey Kiselev's Zeta V2 Z80
-	RCZ80		RCBus Z80
-	RCZ180		RCBus Z180
-	SCZ180		Stephen Cousins' Z180 Systems
-	RCZ280		RCBus Z280
-	EZZ80		Sergey Kiselev's Easy/Tiny Z80
-	DYNO		Dyno Z180 Single Board Computer
-	MBC		Andrew Lynch's Nhyodyne Z80 MBC
-	RPH		Andrew Lynch's Rhyophyre Z180 SBC
+	SBC		Z80 SBC (v1 or v2) w/ ECB interface
+	ZETA		Standalone Z80 SBC w/ SBC compatibility
+	ZETA2		Second version of ZETA with enhanced memory bank switching
+	N8		MSX-ish Z180 SBC w/ onboard video and sound
+	MK4		Mark IV Z180 based SBC w/ ECB interface
+	UNA		Any Z80/Z180 computer with UNA BIOS
+	RCZ80		RCBUS based system with 512K banked RAM/ROM card
+	RCZ180		RCBUS based system with Z180 CPU
+	EZZ80		Easy Z80, Z80 SBC w/ RCBUS and CTC
+	SCZ180		Steve Cousins Z180 based system
+	DYNO		Steve Garcia's Dyno Micro-ATX Motherboard
+	RCZ280		Z280 CPU on RCBUS or ZZ80MB
+	MBC		Andrew Lynch's Multi Board Computer
+	RPH		Andrew Lynch's RHYOPHYRE Graphics Computer
 	Z80RETRO	Peter Wilson's Z80-Retro Computer
 	S100		S100 Computers Z180-based System
 	DUO		Andrew Lynch's Duodyne Computer
-	UNA		John Coffman's UNA System
+	HEATH		Les Bird's Heath Z80 Board
+	EPITX		Alan Cox' Mini-ITX System
+	MON		Jacques Pelletier's Monsputer
+	GMZ180		Doug Jacksons' Genesis Z180 System
+	NABU		NABU w/ Les Bird's RomWBW Option Board
+	FZ80		S100 Computers FPGA Z80
 
 Configuration files are found in the Source\HBIOS\Config 
 directory.  If you look in the this directory, you will see a 
@@ -194,11 +224,11 @@ and easily revert back to the original if you have problems.
 
 It is important to understand how configuration files are processed.
 They start by inheriting all of the default settings for the
-platform.  This is accomplished via the "#include" directive near
+platform.  This is accomplished via the "#INCLUDE" directive near
 the top of the file.  For the "MK4_std.asm" configuration file,
 this line reads:
 
-#include "cfg_mk4.asm"
+#INCLUDE "cfg_mk4.asm"
 
 When the configuration file (MK4_std.asm) is processed, it will first
 read in all the default platform settings from "cfg_mk4.asm".  All of