From 1e5e4eeb6bc664f0912418e36f40bd6ac931a8c7 Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Tue, 13 Jan 2026 17:50:19 -0800
Subject: [PATCH] Support SCC on RCBus

- Updated SCC driver and RCZ80 config
- Completed and tested IM1 support
- IM2 should work, but needs to be tested
- Not enabled by default
---
 Source/HBIOS/Config/RCZ80_std.asm |  1 +
 Source/HBIOS/cfg_MASTER.asm       |  1 +
 Source/HBIOS/cfg_RCZ80.asm        | 21 ++++++++++++
 Source/HBIOS/cfg_SZ180.asm        |  1 +
 Source/HBIOS/cfg_SZ80.asm         |  1 +
 Source/HBIOS/scc.asm              | 54 +++++++++++++++++++++++--------
 Source/HBIOS/std.asm              |  2 ++
 7 files changed, 67 insertions(+), 14 deletions(-)

diff --git a/Source/HBIOS/Config/RCZ80_std.asm b/Source/HBIOS/Config/RCZ80_std.asm
index c8c8974f..3404bd30 100644
--- a/Source/HBIOS/Config/RCZ80_std.asm
+++ b/Source/HBIOS/Config/RCZ80_std.asm
@@ -70,6 +70,7 @@ DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
 ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
 SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
 ;
 TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
 TMSMODE		.SET	TMSMODE_MSX	; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU|MSXUKY]
diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm
index 519dbd7d..22f7d83e 100644
--- a/Source/HBIOS/cfg_MASTER.asm
+++ b/Source/HBIOS/cfg_MASTER.asm
@@ -321,6 +321,7 @@ SCCDEBUG	.EQU	FALSE		; SCC: ENABLE DEBUG OUTPUT
 SCCBOOT		.EQU	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
 SCCCNT		.EQU	2		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SCCINTS		.EQU	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCCPCLK		.EQU	FALSE		; SCC: USE PROCESSOR CLOCK AS BAUD CLOCK
 SCC0MODE	.EQU	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
 SCC0BASE	.EQU	$FF		; SCC 0: REGISTERS BASE ADR
 SCC0ACLK	.EQU	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm
index 48cd25c5..734bc2fc 100644
--- a/Source/HBIOS/cfg_RCZ80.asm
+++ b/Source/HBIOS/cfg_RCZ80.asm
@@ -265,6 +265,27 @@ SIO1BCFG	.SET	DEFSERCFG	; SIO 1B: SERIAL LINE CONFIG
 SIO1BCTCC	.SET	-1		; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 SCCENABLE	.SET	FALSE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
+SCCDEBUG	.SET	FALSE		; SCC: ENABLE DEBUG OUTPUT
+SCCBOOT		.SET	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
+SCCCNT		.SET	1		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
+SCCINTS		.SET	TRUE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCCPCLK		.SET	TRUE		; SCC: USE PROCESSOR CLOCK AS BAUD CLOCK
+SCC0MODE	.SET	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
+SCC0BASE	.SET	$A0		; SCC 0: REGISTERS BASE ADR
+SCC0ACLK	.SET	CPUOSC		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0ACFG	.SET	DEFSERCFG	; SCC 0A: SERIAL LINE CONFIG
+SCC0ACTCC	.SET	-1		; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC0BCLK	.SET	CPUOSC		; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC0BCFG	.SET	DEFSERCFG	; SCC 0B: SERIAL LINE CONFIG
+SCC0BCTCC	.SET	-1		; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1MODE	.SET	SCCMODE_SZ80	; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80]
+SCC1BASE	.SET	$FF		; SCC 1: REGISTERS BASE ADR
+SCC1ACLK	.SET	CPUOSC		; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1ACFG	.SET	DEFSERCFG	; SCC 1A: SERIAL LINE CONFIG
+SCC1ACTCC	.SET	-1		; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
+SCC1BCLK	.SET	CPUOSC		; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
+SCC1BCFG	.SET	DEFSERCFG	; SCC 1B: SERIAL LINE CONFIG
+SCC1BCTCC	.SET	-1		; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
 ;
 XIOCFG		.SET	DEFSERCFG	; XIO: SERIAL LINE CONFIG
 ;
diff --git a/Source/HBIOS/cfg_SZ180.asm b/Source/HBIOS/cfg_SZ180.asm
index 43ac53b7..cd855b4e 100644
--- a/Source/HBIOS/cfg_SZ180.asm
+++ b/Source/HBIOS/cfg_SZ180.asm
@@ -236,6 +236,7 @@ SCCDEBUG	.SET	FALSE		; SCC: ENABLE DEBUG OUTPUT
 SCCBOOT		.SET	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
 SCCCNT		.SET	1		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SCCINTS		.SET	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCCPCLK		.SET	FALSE		; SCC: USE PROCESSOR CLOCK AS BAUD CLOCK
 SCC0MODE	.SET	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
 SCC0BASE	.SET	$A0		; SCC 0: REGISTERS BASE ADR
 SCC0ACLK	.SET	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/cfg_SZ80.asm b/Source/HBIOS/cfg_SZ80.asm
index a9265573..70be3f69 100644
--- a/Source/HBIOS/cfg_SZ80.asm
+++ b/Source/HBIOS/cfg_SZ80.asm
@@ -225,6 +225,7 @@ SCCDEBUG	.SET	FALSE		; SCC: ENABLE DEBUG OUTPUT
 SCCBOOT		.SET	0		; SCC: REBOOT ON RCV CHAR (0=DISABLED)
 SCCCNT		.SET	1		; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
 SCCINTS		.SET	FALSE		; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3
+SCCPCLK		.SET	FALSE		; SCC: USE PROCESSOR CLOCK AS BAUD CLOCK
 SCC0MODE	.SET	SCCMODE_SZ80	; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80]
 SCC0BASE	.SET	$A0		; SCC 0: REGISTERS BASE ADR
 SCC0ACLK	.SET	4915200		; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
diff --git a/Source/HBIOS/scc.asm b/Source/HBIOS/scc.asm
index 357d6eac..ec1ee76e 100644
--- a/Source/HBIOS/scc.asm
+++ b/Source/HBIOS/scc.asm
@@ -11,12 +11,7 @@
 ;       -- MSB (D REGISTER) --           -- LSB (E REGISTER) --
 ;
 ; TODO:
-;   - IMPLEMENT INTERRUPT DRIVEN BUFFER AND FLOW CONTROL
-;
-#IF ((SCCINTS) & (INTMODE > 0))
-	.ECHO	"*** ERROR: SCC DRIVER DOES NOT YET SUPPORT IONTERRUPTS!!!\n"
-	!!!	; FORCE AN ASSEMBLY ERROR
-#ENDIF
+;   - INTERRUPT MODE 2 IS UNTESTED
 ;
 SCC_BUFSZ	.EQU	32		; RECEIVE RING BUFFER SIZE
 ;
@@ -31,9 +26,11 @@ SCC_RTSON	.EQU	$EA
 SCC_RTSOFF	.EQU	$E8
 ;
 #IF ((SCCINTS) & (INTMODE > 0))
-SCC_WR1VAL	.EQU	$18		; WR1 VALUE FOR INT ON RECEIVED CHARS
+SCC_WR1VAL	.EQU	$10		; WR1 VALUE FOR INT ON RECEIVED CHARS
+SCC_WR9VAL	.EQU	$08		; WR9 VALUE FOR MASTER INTERRUPTS ENABLED
 #ELSE
 SCC_WR1VAL	.EQU	$00		; WR1 VALUE FOR NO INTS
+SCC_WR9VAL	.EQU	$00		; WR9 VALUE FOR MASTER INTERRUPTS DISABLED
 #ENDIF
 ;
 #IF ((SCCINTS) & (INTMODE >= 2))
@@ -251,8 +248,8 @@ SCC_INTRCV:
 	; CHECK TO SEE IF SOMETHING IS ACTUALLY THERE
 	LD	C,(IY+3)		; CMD/STAT PORT TO C
 	XOR	A			; A := 0
-	OUT	(C),A			; ADDRESS RD0
-	IN	A,(C)			; GET RD0
+	OUT	(C),A			; ADDRESS RR0
+	IN	A,(C)			; GET RR0
 	AND	$01			; ISOLATE RECEIVE READY BIT
 	RET	Z			; NOTHING AVAILABLE ON CURRENT CHANNEL
 ;
@@ -261,7 +258,7 @@ SCC_INTRCV1:
 	LD	C,(IY+4)		; DATA PORT TO C
 	IN	A,(C)			; READ PORT
   #IF (SCCBOOT != 0)
-	CP	SCCBOOT		; REBOOT REQUEST?
+	CP	SCCBOOT			; REBOOT REQUEST?
 	JP	Z,SYS_RESCOLD		; IF SO, DO IT, NO RETURN
   #ENDIF
 	LD	B,A			; SAVE BYTE READ
@@ -312,6 +309,26 @@ SCC_INTRCV3:
 	RRA				; READY BIT TO CF
 	JR	C,SCC_INTRCV1		; IF SET, DO SOME MORE
 SCC_INTRCV4:
+	; CHECK FOR ANY PENDING SPECIAL CONDITIONS
+	; IF AN ERROR OCCURS, THE RECEIVER WILL BE LOCKED UNTIL YOU
+	; CLEAR IT BY READ RR1
+	LD	C,(IY+3)		; CMD/STAT PORT TO C
+	LD	A,1			; RR1
+	OUT	(C),A			; SELECT IT
+	IN	A,(C)			; READ IT
+	AND	%0111000		; ISOLATE ERROR BITS
+	JR	Z,SCC_INTRCV5		; DONE IF NO BITS SET
+	;CALL	PRTHEXBYTE		; *DEBUG*
+;
+	; ERROR RESET
+	LD	A,%00110000		; ERROR RESET
+	OUT	(C),A			; SEND IT
+;
+SCC_INTRCV5:
+	; RESET INTERRUPT UNDER SERVICE
+	LD	A,%00111000		; RESET HIGHEST IUS
+	OUT	(C),A			; DO IT
+;
 	OR	$FF			; NZ SET TO INDICATE INT HANDLED
 	RET				; AND RETURN
 ;
@@ -643,9 +660,9 @@ SCC_INITPRT:
 #ENDIF
 ;
 	; RESET THE CHANNEL
-	LD	C,(IY+3)
-	XOR	A
-	OUT	(C),A			; SELECT WR0
+	LD	C,(IY+3)		; CONTROL PORT
+	LD	A,9			; REGISTER WR9
+	OUT	(C),A			; SELECT IT
 	LD	A,%10000000		; CHANNEL A RESET CMD
 	BIT	0,(IY+2)		; TEST CHANNEL NUM
 	JR	Z,SCC_INITGO1		; SKIP AHEAD IF CHANNEL 0
@@ -701,15 +718,22 @@ SCC_INITGO1:
 ;
 SCC_INITDEFS:
 	.DB	4,  $44			; ASYNC MODE, X16, 1 STOP, NO PARITY	; 0100 0100
+	.DB	1,  SCC_WR1VAL		; CONFIGURE INTERRUPTS
 	.DB	3,  $C0			; RX 8 BITS PER CHAR			; 1100 0000
 	.DB	5,  $E2			; TX 8 BITS PER CHAR			; 1110 0010
 	.DB	11, $56			; RTxC VIA BRG				; 0101 0110
 	.DB	12, SCC_DEFDIV & $FF	; BAUD RATE DIVISOR LO BYTE
 	.DB	13, SCC_DEFDIV >> 8	; BAUD RATE DIVISOR HI BYTE
+#IF (SCCPCLK)
+	.DB	14, $02			; BRG SOURCE PCLK			; 0000 0000
+	.DB	14, $03			; ENABLE BRG				; 0000 0001
+#ELSE
 	.DB	14, $00			; BRG SOURCE RTxC			; 0000 0000
 	.DB	14, $01			; ENABLE BRG				; 0000 0001
+#ENDIF
 	.DB	3,  $C1			; ENABLE RECEIVER 			; 1100 0001
 	.DB	5,  $EA			; ENABLE TRANSMITTER 			; 1110 1010
+	.DB	9,  SCC_WR9VAL		; MASTER INTERRUPT CONTROL
 ;
 SCC_INITLEN	.EQU	$ - SCC_INITDEFS
 ;
@@ -719,7 +743,8 @@ SCC_INITVALS	.FILL	SCC_INITLEN,0
 ; *** MUST SYNC WITH SCC_INITDEFS !!!
 ;
 SCC_WR4		.EQU	SCC_INITVALS + 1
-SCC_WR3		.EQU	SCC_WR4 + 2
+SCC_WR1		.EQU	SCC_WR4 + 2
+SCC_WR3		.EQU	SCC_WR1 + 2
 SCC_WR5		.EQU	SCC_WR3 + 2
 SCC_WR11	.EQU	SCC_WR5 + 2
 SCC_WR12	.EQU	SCC_WR11 + 2
@@ -728,6 +753,7 @@ SCC_WR14	.EQU	SCC_WR13 + 2
 SCC_WR14A	.EQU	SCC_WR14 + 2
 SCC_WR3A	.EQU	SCC_WR14A + 2
 SCC_WR5A	.EQU	SCC_WR3A + 2
+SCC_WR9		.EQU	SCC_WR5A + 2
 ;
 ;
 ;
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index 81b4e1f4..3126140f 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -1075,6 +1075,8 @@ INT_PIO0A	.EQU	9	; ZILOG PIO 0, CHANNEL A
 INT_PIO0B	.EQU	10	; ZILOG PIO 0, CHANNEL B
 INT_PIO1A	.EQU	11	; ZILOG PIO 1, CHANNEL A
 INT_PIO1B	.EQU	12	; ZILOG PIO 1, CHANNEL B
+INT_SCC0	.EQU	13	; ZILOG SCC 0, CHANNEL A & B
+INT_SCC1	.EQU	14	; ZILOG SCC 1, CHANNEL A & B
   #ENDIF
 
 #ENDIF