mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
Add S100 and DUO Platforms
This commit is contained in:
Wayne Warthen
@@ -629,6 +629,9 @@ CFGTBL: ; PLT RSEL RDAT RIN Z180 ACR
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;
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.DB 13, $A0, $A1, $A0, $FF, $A2 ; MBC
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.DW HWSTR_MBC
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;
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.DB 17, $A0, $A1, $A0, $FF, $A2 ; DUODYNE
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.DW HWSTR_DUO
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;
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.DB $FF ; END OF TABLE MARKER
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;
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@@ -682,6 +685,7 @@ HWSTR_RCEB6 .DB "RCBus Sound Module (EBv6)",0
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HWSTR_RCMF .DB "RCBus Sound Module (MF)",0
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HWSTR_LINC .DB "Z50 LiNC Sound Module",0
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HWSTR_MBC .DB "NHYODYNE Sound Module",0
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HWSTR_DUO .DB "DUODYNE Sound Module",0
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MSGUNSUP .db "MYM files not supported with HBIOS yet!\r\n", 0
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@@ -31,6 +31,8 @@
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;
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;[2022/03/27] v1.8 Support RHYOPHYRE
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;
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;[2023/07/07] v1.9 Support DUODYNE
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;
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; Constants
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;
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mask_data .EQU %10000000 ; RTC data line
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@@ -49,6 +51,7 @@ PORT_DYNO .EQU $0C ; RTC port for DYNO
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PORT_RCZ280 .EQU $C0 ; RTC port for RCZ280
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PORT_MBC .EQU $70 ; RTC port for MBC
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PORT_RPH .EQU $84 ; RTC port for RHYOPHYRE
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PORT_DUO .EQU $70 ; RTC port for DUODYNE
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BDOS .EQU 5 ; BDOS invocation vector
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@@ -1079,61 +1082,66 @@ HINIT:
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LD C,PORT_SBC
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LD DE,PLT_SBC
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CP $01 ; SBC
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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CP $02 ; ZETA
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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CP $03 ; ZETA 2
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_N8
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LD DE,PLT_N8
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CP $04 ; N8
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_MK4
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LD DE,PLT_MK4
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CP $05 ; Mark IV
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_RCZ80
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LD DE,PLT_RCZ80
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CP $07 ; RCBus w/ Z80
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_RCZ180
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LD DE,PLT_RCZ180
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CP $08 ; RCBus w/ Z180
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_EZZ80
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LD DE,PLT_EZZ80
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CP $09 ; Easy Z80
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_SCZ180
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LD DE,PLT_SCZ180
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CP $0A ; SCZ180
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_DYNO
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LD DE,PLT_DYNO
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CP 11 ; DYNO
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_RCZ280
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LD DE,PLT_RCZ280
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CP 12 ; RCZ280
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_MBC
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LD DE,PLT_MBC
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CP 13 ; MBC
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_RPH
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LD DE,PLT_RPH
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CP 14 ; RHYOPHYRE
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JR Z,RTC_INIT2
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JP Z,RTC_INIT2
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;
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LD C,PORT_DUO
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LD DE,PLT_DUO
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CP 13 ; DUODYNE
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JP Z,RTC_INIT2
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;
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; Unknown platform
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LD DE,PLTERR ; BIOS error message
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@@ -1630,7 +1638,7 @@ TESTING_BIT_DELAY_OVER:
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RTC_HELP_MSG:
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.DB 0Ah, 0Dh ; line feed and carriage return
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.TEXT "RTC: Version 1.8"
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.TEXT "RTC: Version 1.9"
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.DB 0Ah, 0Dh ; line feed and carriage return
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.TEXT "Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot W)arm-start H)elp"
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.DB 0Ah, 0Dh ; line feed and carriage return
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@@ -1760,6 +1768,7 @@ PLT_DYNO .TEXT ", DYNO RTC Module Latch Port 0x0C\r\n$"
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PLT_RCZ280 .TEXT ", RCBus Z280 RTC Module Latch Port 0xC0\r\n$"
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PLT_MBC .TEXT ", MBC RTC Latch Port 0x70\r\n$"
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PLT_RPH .TEXT ", RHYOPHYRE RTC Latch Port 0x84\r\n$"
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PLT_DUO .TEXT ", DUODYNE RTC Latch Port 0x70\r\n$"
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;
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; Generic FOR-NEXT loop algorithm
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@@ -1952,6 +1952,9 @@ The hardware Platform (L) is identified as follows:
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| PLT_RCZ280 |12 | RCBUS W/ Z280 |
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| PLT_MBC |13 | NHYODYNE MULTI-BOARD COMPUTER |
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| PLT_RPH |14 | RHYOPHYRE GRAPHICS SBC |
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| PLT_Z80RETRO |15 | Z80 RETRO COMPUTER |
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| PLT_S100 |16 | S100 COMPUTERS Z180 |
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| PLT_DUO |17 | DUODYNE Z80 SYSTEM |
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### Function 0xF2 -- System Set Bank (SYSSETBNK)
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@@ -202,6 +202,8 @@ below, **carefully** pick the appropriate ROM image for your hardware.
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| [Z280 ZZRCC CPU Module]^7^ | RCBus | RCZ280_zzrc.rom | 115200 |
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| [Z280 ZZ80MB SBC]^7^ | RCBus | RCZ280_zz80mb.rom | 115200 |
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| [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 |
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| [S100 Computers Z180]^9^ | S100 | S100_std.rom | 38400 |
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| [Duodyne Z80 System]^1^ | Duo | DUO_std.rom | 38400 |
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| ^1^Designed by Andrew Lynch
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| ^2^Designed by Sergey Kiselev
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@@ -211,6 +213,7 @@ below, **carefully** pick the appropriate ROM image for your hardware.
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| ^6^Designed by Steve Garcia
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| ^7^Designed by Bill Shen
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| ^8^Designed by Peter Wilson
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| ^9^Designed by John Monahan
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RCBus refers to Spencer Owen's RC2014 bus specification and derivatives
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including RC26, RC40, RC80, and BP80.
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@@ -3927,6 +3930,52 @@ the RomWBW HBIOS configuration.
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`\clearpage`{=latex}
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### S100 Computers Z180
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| | |
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|-------------------|---------------|
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| ROM Image File | S100_std.rom |
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| Console Baud Rate | 38400 |
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| Interrupts | Mode 2 |
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- CPU speed assumed to be 18.432 MHz
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- System timer is generated by Z180 CPU
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- Hardware auto-detected:
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- Interrupt-driven RTC
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- Z180 ASCI Serial Ports
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- Onboard SD Card Interface
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`\clearpage`{=latex}
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### Duodyne Z80 System
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| | |
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|-------------------|---------------|
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| ROM Image File | DUO_std.rom |
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| Console Baud Rate | 38400 |
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| Interrupts | None |
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- CPU speed is detected at startup if DS1302 RTC is active
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- Otherwise 8.000 MHz assumed
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- System timer is generated by CTC if available
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- Hardware auto-detected:
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- DS1302 RTC
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- Zilog CTC
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- Zilog DMA Module
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- UART Serial Adapter
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- SIO Serial Interface
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- LPT Printer Interface
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- Zilog Parallel Interface
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- CVDU Display Adapter
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- TMS9938/58 Display Adapter
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- PS/2 Keyboard Interface
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- AY-3-8910/YM2149 Sound Module
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- Floppy Disk Controller w/ 3.5" HD Drives
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- PPIDE Hard Disk Interface
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- Interrupts may be enabled in build options
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`\clearpage`{=latex}
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## Appendix B - Device Summary
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The table below briefly describes each of the possible devices that
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@@ -93,7 +93,14 @@ call :asm imgpad2 || exit /b
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copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin + ..\cpm22\cpm_wbw.bin osimg.bin || exit /b
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copy /b ..\Forth\camel80.bin + nascom.bin + ..\tastybasic\src\tastybasic.bin + game.bin + eastaegg.bin + netboot.mod + updater.bin + usrrom.bin osimg1.bin || exit /b
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copy /b imgpad2.bin osimg2.bin || exit /b
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if %Platform%==S100 (
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zxcc slr180 -s100mon/fh
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zxcc mload25 -s100mon || exit /b
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copy /b s100mon.com osimg2.bin || exit /b
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) else (
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copy /b imgpad2.bin osimg2.bin || exit /b
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)
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copy /b romldr.bin + dbgmon.bin + ..\zsdos\zsys_wbw.bin osimg_small.bin || exit /b
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@@ -224,5 +231,7 @@ call Build DYNO std || exit /b
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call Build UNA std || exit /b
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call Build RPH std || exit /b
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call Build Z80RETRO std || exit /b
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call Build S100 std || exit /b
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call Build DUO std || exit /b
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goto :eof
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@@ -27,8 +27,8 @@ $ErrorAction = 'Stop'
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# UNA BIOS is simply imbedded, it is not built here.
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#
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$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "UNA"
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$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH"
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$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA"
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$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100"
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$PlatformListZ280 = "RCZ280"
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#
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@@ -32,11 +32,13 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then
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ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh
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ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh
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ROM_PLATFORM="MBC"; ROM_CONFIG="std"; bash Build.sh
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ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh
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ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc126"; bash Build.sh
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ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc130"; bash Build.sh
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ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131"; bash Build.sh
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ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh
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ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh
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ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh
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ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh
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ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh
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ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh
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@@ -11,6 +11,7 @@ if exist *.exp del *.exp
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if exist *.tmp del *.tmp
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if exist *.mrk del *.mrk
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if exist *.sys del *.sys
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if exist *.hex del *.hex
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if exist build.inc del build.inc
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if exist font*.asm del font*.asm
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if exist build_env.cmd del build_env.cmd
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58
Source/HBIOS/Config/DUO_std.asm
Normal file
58
Source/HBIOS/Config/DUO_std.asm
Normal file
@@ -0,0 +1,58 @@
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;
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;==================================================================================================
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; DUODYNE STANDARD CONFIGURATION
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;==================================================================================================
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;
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
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; YOUR FILE IN THE BUILD PROCESS.
|
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;
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
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; DIRECTORIES ABOVE THIS ONE).
|
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;
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#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
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;
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#include "cfg_duo.asm"
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;
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CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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;
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INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
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;
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DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
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;
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BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
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;
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CPUSPDDEF .SET SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
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;
|
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ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
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RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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;
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MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
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;
|
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DSKYENABLE .SET TRUE ; ENABLES DSKY FUNCTIONALITY
|
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ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
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PKDENABLE .SET TRUE ; ENABLES DSKY NG PKD DRIVER (8259)
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;
|
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UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
;UARTCFG .SET UARTCFG | SER_RTS
|
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;
|
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LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
;
|
||||
CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
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;
|
||||
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
;
|
||||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
49
Source/HBIOS/Config/S100_std.asm
Normal file
49
Source/HBIOS/Config/S100_std.asm
Normal file
@@ -0,0 +1,49 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; S100 STANDARD CONFIGURATION
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
|
||||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
|
||||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
|
||||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
|
||||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
|
||||
; YOUR FILE IN THE BUILD PROCESS.
|
||||
;
|
||||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
|
||||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
|
||||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
|
||||
; SETTINGS.
|
||||
;
|
||||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
|
||||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
|
||||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
|
||||
;
|
||||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
|
||||
; DIRECTORIES ABOVE THIS ONE).
|
||||
;
|
||||
#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
|
||||
;
|
||||
#include "cfg_s100.asm"
|
||||
;
|
||||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
|
||||
;
|
||||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
;
|
||||
DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
;
|
||||
ASCI0CFG .SET SER_57600_8N1 ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR]
|
||||
SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
|
||||
@@ -6,7 +6,7 @@ MOREDIFF = game.bin hbios_rom.bin nascom.bin usrrom.bin \
|
||||
SUBDIRS =
|
||||
DEST = ../../Binary
|
||||
TOOLS =../../Tools
|
||||
OTHERS = *.img *.rom *.com *.upd *.bin *.z80 cpm.sys zsys.sys Build.inc font*.asm *.dat hbios_env.sh
|
||||
OTHERS = *.img *.rom *.com *.upd *.bin *.hex cpm.sys zsys.sys Build.inc font*.asm *.dat hbios_env.sh
|
||||
|
||||
# DIFFMAKE = 1
|
||||
|
||||
@@ -58,7 +58,13 @@ $(OBJECTS) : $(ROMDEPS)
|
||||
cat romldr.bin dbgmon.bin ../ZSDOS/zsys_$(BIOS).bin >osimg_small.bin
|
||||
if [ $(ROM_PLATFORM) != UNA ] ; then \
|
||||
cat camel80.bin nascom.bin tastybasic.bin game.bin eastaegg.bin netboot.mod updater.bin usrrom.bin >osimg1.bin ; \
|
||||
cat imgpad2.bin >osimg2.bin ; \
|
||||
if [ $(ROM_PLATFORM) = S100 ] ; then \
|
||||
$(ZXCC) slr180 -s100mon/fh ; \
|
||||
$(ZXCC) mload25 -s100mon ; \
|
||||
cat s100mon.com >osimg2.bin ; \
|
||||
else \
|
||||
cat imgpad2.bin >osimg2.bin ; \
|
||||
fi ; \
|
||||
if [ $(ROMSIZE) -gt 0 ] ; then \
|
||||
for f in hbios_rom.bin osimg.bin osimg1.bin osimg2.bin ; do \
|
||||
srec_cat $$f -Binary -Crop 0 0x7FFF -Checksum_Negative_Big_Endian 0x7FFF 1 1 -o $$f -Binary ; \
|
||||
|
||||
298
Source/HBIOS/cfg_duo.asm
Normal file
298
Source/HBIOS/cfg_duo.asm
Normal file
@@ -0,0 +1,298 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR DUODYNE
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_HILO ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VERIFICATION (0=DISABLED)
|
||||
MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
RTCIO .EQU $70 ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER
|
||||
CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256]
|
||||
CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256)
|
||||
CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3)
|
||||
CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3)
|
||||
CTCOSC .EQU (4915200/8) ; CTC CLOCK FREQUENCY
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU TRUE ; ENABLES STATUS LED
|
||||
LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|RTC]
|
||||
LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY
|
||||
DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY
|
||||
ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218)
|
||||
ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI
|
||||
PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259)
|
||||
PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI
|
||||
PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ)
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS
|
||||
UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED
|
||||
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
|
||||
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
|
||||
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
|
||||
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
|
||||
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
|
||||
UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART
|
||||
UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART
|
||||
;
|
||||
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30]
|
||||
CVDUENABLE .EQU TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
CVDUMODE .EQU CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC]
|
||||
CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA]
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MBC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43]
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_MBC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4)
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
;
|
||||
PIOENABLE .EQU TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $E8 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
UFBASE .EQU $0C ; UF: REGISTERS BASE ADR
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
|
||||
;
|
||||
SPKENABLE .EQU TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -12,7 +12,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU TRUE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
303
Source/HBIOS/cfg_s100.asm
Normal file
303
Source/HBIOS/cfg_s100.asm
Normal file
@@ -0,0 +1,303 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR S100 Z180
|
||||
;==================================================================================================
|
||||
;
|
||||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
|
||||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
|
||||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
|
||||
; UNDER THIS DIRECTORY.
|
||||
;
|
||||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
|
||||
; FOR THE PLATFORM.
|
||||
;
|
||||
#DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]"
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD)
|
||||
USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION
|
||||
TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
|
||||
;
|
||||
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
|
||||
BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT
|
||||
;
|
||||
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
|
||||
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
|
||||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
|
||||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
|
||||
DEFSERCFG .EQU SER_115200_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
|
||||
;
|
||||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
|
||||
ROMSIZE_CHK .EQU 0 ; ROMSIZE VALUE VERIFICATION (0=DISABLED)
|
||||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH]
|
||||
RAMLOC .EQU 19 ; START OF RAM AS POWER OF 2 (2^N) IN PHYSICAL ADDRESS SPACE
|
||||
RAMBIAS .EQU (1 << (RAMLOC - 10)) ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
|
||||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
|
||||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
|
||||
;
|
||||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
|
||||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
|
||||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
|
||||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
|
||||
Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER
|
||||
;
|
||||
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
|
||||
;
|
||||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
|
||||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
|
||||
;
|
||||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
|
||||
CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT
|
||||
CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS
|
||||
CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER
|
||||
;
|
||||
EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
|
||||
;
|
||||
SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES
|
||||
;
|
||||
WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
|
||||
;
|
||||
FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS
|
||||
FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS
|
||||
FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS
|
||||
FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES
|
||||
FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES
|
||||
;
|
||||
DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING
|
||||
;
|
||||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
|
||||
LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|RTC]
|
||||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
|
||||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
|
||||
;
|
||||
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
|
||||
;
|
||||
BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE
|
||||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
|
||||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
|
||||
VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD
|
||||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER)
|
||||
MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE]
|
||||
;
|
||||
DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
|
||||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
|
||||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
|
||||
;
|
||||
DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM)
|
||||
DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS
|
||||
;
|
||||
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
|
||||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
|
||||
;
|
||||
INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
|
||||
;
|
||||
RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM)
|
||||
;
|
||||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
|
||||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
;
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
|
||||
DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP
|
||||
DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG
|
||||
DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG
|
||||
DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP
|
||||
DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG
|
||||
DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG
|
||||
;
|
||||
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
|
||||
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
|
||||
UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS
|
||||
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
|
||||
UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH)
|
||||
UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART
|
||||
UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART
|
||||
UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART
|
||||
UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART
|
||||
UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART
|
||||
;
|
||||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
|
||||
ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3
|
||||
ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS
|
||||
ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
|
||||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
|
||||
;
|
||||
Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM)
|
||||
;
|
||||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
|
||||
;
|
||||
SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
|
||||
SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT
|
||||
SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED)
|
||||
SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR
|
||||
SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG
|
||||
SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG
|
||||
SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R]
|
||||
SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR
|
||||
SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG
|
||||
SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800
|
||||
SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG
|
||||
SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE
|
||||
;
|
||||
XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG
|
||||
;
|
||||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
|
||||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
|
||||
GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM)
|
||||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
|
||||
TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO]
|
||||
TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
|
||||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
|
||||
VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM)
|
||||
;
|
||||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
|
||||
MDROM .EQU TRUE ; MD: ENABLE ROM DISK
|
||||
MDRAM .EQU TRUE ; MD: ENABLE RAM DISK
|
||||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM
|
||||
;
|
||||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
|
||||
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]
|
||||
FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2)
|
||||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
|
||||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
|
||||
FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8]
|
||||
;
|
||||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
|
||||
;
|
||||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
|
||||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH
|
||||
IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS
|
||||
IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER
|
||||
IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER
|
||||
IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS
|
||||
IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER
|
||||
IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER
|
||||
IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC]
|
||||
IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS
|
||||
IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O
|
||||
IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O
|
||||
IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER
|
||||
IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER
|
||||
;
|
||||
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
|
||||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP
|
||||
PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR
|
||||
PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER
|
||||
PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR
|
||||
PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER
|
||||
PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR
|
||||
PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER
|
||||
PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER
|
||||
;
|
||||
SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
|
||||
SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR]
|
||||
SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE
|
||||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY
|
||||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
|
||||
SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011
|
||||
;
|
||||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
|
||||
PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT
|
||||
PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT
|
||||
;
|
||||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
|
||||
;
|
||||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
|
||||
;
|
||||
PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM)
|
||||
PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP
|
||||
PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR
|
||||
PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR
|
||||
;
|
||||
LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
|
||||
LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014]
|
||||
LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2)
|
||||
LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR
|
||||
LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR
|
||||
;
|
||||
PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM)
|
||||
PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2)
|
||||
PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014]
|
||||
PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA
|
||||
;
|
||||
IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
|
||||
IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2)
|
||||
IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014]
|
||||
IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM
|
||||
;
|
||||
SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM)
|
||||
SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2)
|
||||
SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
|
||||
SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014]
|
||||
SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ
|
||||
;
|
||||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
|
||||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
|
||||
PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
|
||||
;
|
||||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)
|
||||
;
|
||||
SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER
|
||||
AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER
|
||||
SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM]
|
||||
;
|
||||
AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER
|
||||
AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD
|
||||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC]
|
||||
;
|
||||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
|
||||
;
|
||||
DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM)
|
||||
DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS
|
||||
DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC)
|
||||
;
|
||||
YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB)
|
||||
VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76469s/CTC)
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "../UBIOS/ubios.inc"
|
||||
;
|
||||
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
;
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
;
|
||||
#INCLUDE "hbios.inc"
|
||||
;
|
||||
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO]
|
||||
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO]
|
||||
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280]
|
||||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
|
||||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
|
||||
|
||||
@@ -1373,6 +1373,22 @@ Z280_INITZ:
|
||||
LD (HB_CURBNK),A ; RESTORE HB_CURBNK
|
||||
#ENDIF
|
||||
;
|
||||
; S100 ROM CONTAINS A HARDWARE LEVEL MONITOR IN BANK ID 3 OF ROM.
|
||||
; IF PORT $65 BIT 1 IS SET (SET IS ZERO), THEN WE IMMEDIATELY
|
||||
; TRANSITION TO THIS MONITOR.
|
||||
;
|
||||
#IF ((PLATFORM == PLT_S100) & TRUE)
|
||||
IN A,($65) ; READ SWITCHES
|
||||
BIT 1,A ; CHECK BIT 1
|
||||
JR NZ,S100MON_SKIP ; IF NOT SET, BYPASS
|
||||
LD A,BID_IMG2 ; S100 MONITOR BANK
|
||||
LD IX,0 ; EXECUTION RESUMES HERE
|
||||
CALL HBX_BNKCALL ; CONTINUE IN RAM BANK, DO NOT RETURN
|
||||
HALT ; WE SHOULD NOT COME BACK HERE!
|
||||
;
|
||||
S100MON_SKIP:
|
||||
#ENDIF
|
||||
;
|
||||
; SAVE CURRENT BANKID
|
||||
;
|
||||
; THIS IS NOT GOING TO WORK IF THE APP BOOT IMAGE IS LOADED
|
||||
|
||||
@@ -150,6 +150,8 @@ PLT_RCZ280 .EQU 12 ; RCBUS W/ Z280
|
||||
PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER
|
||||
PLT_RPH .EQU 14 ; RHYOPHYRE GRAPHICS COMPUTER
|
||||
PLT_Z80RETRO .EQU 15 ; Z80 RETRO COMPUTER
|
||||
PLT_S100 .EQU 16 ; S100 COMPUTERS Z180 SYSTEM
|
||||
PLT_DUO .EQU 17 ; DUODYNE Z80 SYSTEM
|
||||
;
|
||||
; HBIOS GLOBAL ERROR RETURN VALUES
|
||||
;
|
||||
|
||||
3053
Source/HBIOS/s100mon.z80
Normal file
3053
Source/HBIOS/s100mon.z80
Normal file
File diff suppressed because it is too large
Load Diff
@@ -17,6 +17,8 @@
|
||||
; 13. MBC Andrew Lynch's Multi Board Computer
|
||||
; 14. RPH Andrew Lynch's RHYOPHYRE Graphics Computer
|
||||
; 15. Z80RETRO Peter Wilson's Z80-Retro Computer
|
||||
; 16. S100 S100 Computers Z180-based System
|
||||
; 17. DUO Andrew Lynch's Duodyne Computer
|
||||
|
||||
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
|
||||
;
|
||||
|
||||
@@ -142,6 +142,9 @@ to determine the <plt> component of the configuration filename:
|
||||
DYNO Dyno Z180 Single Board Computer
|
||||
MBC Andrew Lynch's Nhyodyne Z80 MBC
|
||||
RPH Andrew Lynch's Rhyophyre Z180 SBC
|
||||
Z80RETRO Peter Wilson's Z80-Retro Computer
|
||||
S100 S100 Computers Z180-based System
|
||||
DUO Andrew Lynch's Duodyne Computer
|
||||
UNA John Coffman's UNA System
|
||||
|
||||
Configuration files are found in the Source\HBIOS\Config
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
#DEFINE RMN 3
|
||||
#DEFINE RUP 0
|
||||
#DEFINE RTP 0
|
||||
#DEFINE BIOSVER "3.3.0-dev.29"
|
||||
#DEFINE BIOSVER "3.3.0-dev.30"
|
||||
#define rmj RMJ
|
||||
#define rmn RMN
|
||||
#define rup RUP
|
||||
|
||||
@@ -3,5 +3,5 @@ rmn equ 3
|
||||
rup equ 0
|
||||
rtp equ 0
|
||||
biosver macro
|
||||
db "3.3.0-dev.29"
|
||||
db "3.3.0-dev.30"
|
||||
endm
|
||||
|
||||
Reference in New Issue
Block a user