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Merge trunk -> dgg

import/raw
wayne 13 years ago
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  1. 369
      branches/dgg/LSource/Makefile
  2. BIN
      branches/dgg/LSource/bin/CPMCHATTR
  3. BIN
      branches/dgg/LSource/bin/CPMCHMOD
  4. BIN
      branches/dgg/LSource/bin/CPMCP
  5. BIN
      branches/dgg/LSource/bin/CPMLS
  6. BIN
      branches/dgg/LSource/bin/CPMRM
  7. BIN
      branches/dgg/LSource/bin/CVT2LINUX
  8. BIN
      branches/dgg/LSource/bin/TASM
  9. 215
      branches/dgg/LSource/bin/TASM05.TAB
  10. 205
      branches/dgg/LSource/bin/TASM3210.TAB
  11. 456
      branches/dgg/LSource/bin/TASM3225.TAB
  12. 281
      branches/dgg/LSource/bin/TASM48.TAB
  13. 285
      branches/dgg/LSource/bin/TASM51.TAB
  14. 222
      branches/dgg/LSource/bin/TASM65.TAB
  15. 348
      branches/dgg/LSource/bin/TASM68.TAB
  16. 290
      branches/dgg/LSource/bin/TASM70.TAB
  17. 594
      branches/dgg/LSource/bin/TASM80.TAB
  18. 257
      branches/dgg/LSource/bin/TASM85.TAB
  19. 393
      branches/dgg/LSource/bin/TASM96.TAB
  20. 594
      branches/dgg/LSource/bin/tasm180.tab

369
branches/dgg/LSource/Makefile
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# RomWBW/branches/dwg/LSource/Makefile 10/27/2012 dwg -
#
# GCC based makefile
#
# 10/27/2012 2.x dwg - updated for Linux
#
# 09/28/2012 2.2 dwg - updated for Mac OS X 10.8.2 Mountain Lion
#
# 06/18/2012 2.0 dgg - updated for v2.0
#
# 02/22/2012 1.5 dgg - modified for assembly under Linux
#
# 01/11/2011 1.4 wbw - added support for ZSDOS/ZDDOS/ZCPR
#
# 12/22/2011 1.3 wbw - removed all built-in config stuff, operation is now entirely
# dependent on variables CONFIG, ROMSIZE, and CPU
#
# 12/02/2011 1.3 wbw - replaced makever functionality with built-in makefile stuff
#
# 11/29/2011 1.3 dwg - uses makever to generate stdincl.inc from the version.hpp file
#
# 11/19/2011 1.3 dwg - added n8vem_vdu to "usage" and "all" rules
# enhanced clean to get files in $(OUTDIR)
# added custom to "all" rule
#
# The operation of this makefile is entirely dependent on the setting
# of three variables: CONFIG, ROMSIZE, and CPU:
#
# CONFIG determines which configuration to build which means that
# it will determine the config_xxx.asm config settings file to
# include as well as the output file names. So, for example,
# if CONFIG is "n8vem", the config_n8vem.asm file will be used
# for BIOS configuration settings and the output files will be
# n8vem.rom, n8vem.sys, and n8vem.com.
#
# ROMSIZE specifies the size of the ROM image to be produced and
# currently must be either "1024" for a 1MB ROM or "512" for a
# 512KB ROM.
#
# CPU specifies the instruction set to be used in assembly and
# must be either "80" for Z80 or "180" for Z180. Currently,
# you should use 180 for N8 ROMs and 80 for everything else.
#
# SYS specifies the system variant to build in. CPM will
# build traditional CP/M. ZSYS will build ZSystem which
# currently means ZSDOS 1.2 & ZCPR 1.0
#
# ROMNAME names the output file. It defaults to
# CONFIG. The output of the build will be:
# <ROMNAME>.rom, <ROMNAME>.sys, and <ROMNAME>.com.
#
# These variables can be passed into the makefile by the command
# line, hardcoded in this file, or set as environment variables
# in the OS. To use a command line, use the following format:
#
# make CONFIG=<config> ROMSIZE=<romsize> CPU=<cpu> SYS=<sys> ROMNAME=<romname>
#
# An example of this is:
#
# make CONFIG=n8vem ROMSIZE=512 CPU=80 SYS=CPM ROMNAME=n8vem
#
# Alternatively, you can specify the variables by hardcoding them
# in this file. To do so, uncomment the five lines after these
# comments and change the values as desired.
# If the variables are specified this way, you would then invoke
# the make by simply using "make"
#
# If you want to set them as environment variables, you can
# do this with commands like the following at an OS command
# prompt or in a batch file:
#
# SET CONFIG=zeta
# SET ROMSIZE=512
# SET CPU=80
# SET SYS=CPM
# SET ROMNAME=zeta
#
# Note: use "make clean" to delete temporary and output files
#
# A good idea is to do a clean with every build and this can be
# accomplished on one command line doing something like this:
#
# make clean all CONFIG=n8vem ROMSIZE=512 CPU=80 SYS=CPM ROMNAME=n8vem
#
# or, if you are using hard coded variables above:
#
# make clean all
#
# Uncomment and update values below to hardcode settings:
#
CONFIG := n8_2312
ROMSIZE := 512
CPU := 180
SYS := CPM
ROMNAME := n8_2312
ifndef ROMNAME
ROMNAME := $(CONFIG)
endif
CPMCP := bin/CPMCP
CVT := bin/CVT2LINUX
SRC := ../Source/
ROMDSKFILES := ../RomDsk/$(SYS)_$(ROMSIZE)KB/*.* ../RomDsk/cfg_$(CONFIG)/*.* ../Apps/core/*.*
ifeq "$(SYS)" "CPM"
DOSBIN := bdosb01.bin
CPBIN := ccpb03.bin
else
DOSBIN :s= zsdos.bin
CPBIN := zcprw.bin
endif
OUTDIR := ../Output
TASM := bin/TASM
TASMTABS := bin
export TASMTABS
ASMOPT80 := -t$(CPU) -g3
ASMOPT85 := -t85 -g3
ASM80 := $(TASM) $(ASMOPT80)
ASM85 := $(TASM) $(ASMOPT85)
ASMIMG := $(TASM) $(ASMOPT80) -b -fE5
NULL :=
SPACE := ${NULL} ${NULL}
%.bin: %.asm
$(ASM80) $< $@
%.com: %.asm
$(ASM80) $< $@
%.img: %.asm
$(ASMIMG) $< $@
%.exe: %.cpp
$(CC) $< -o $@
ifneq ($(MAKECMDGOALS),clean)
ifeq "$(and $(CONFIG), $(ROMSIZE), $(CPU), $(SYS), $(ROMNAME))" ""
$(error sage: make CONFIG=<config> ROMSIZE=[512|1024] CPU=[80|180] SYS=[CPM|ZSYS] ROMNAME=<romname>)
endif
endif
all: tasm80.tab tasm85.tab $(OUTDIR)/$(ROMNAME).rom $(OUTDIR)/$(ROMNAME).sys $(OUTDIR)/$(ROMNAME).com
tasm80.tab: bin/TASM80.TAB
cp bin/TASM80.TAB tasm80.tab
tasm85.tab: bin/TASM85.TAB
cp bin/TASM85.TAB tasm85.tab
build.inc:
/bin/echo ';' >$@
/bin/echo -n '; RomWBW Configured for '$(CONFIG)' ' >>$@
date >> $@
/bin/echo ; >>$@
/bin/echo -n '#DEFINE TIMESTAMP "' >>$@
date '+%Y %m %d %H%M"' >>$@
/bin/echo ; >>$@
/bin/echo '#DEFINE VARIANT "WBW-$(USERNAME)"' >>$@
/bin/echo ; >>$@
/bin/echo ROMSIZE .EQU $(ROMSIZE) >>$@
/bin/echo ; >>$@
/bin/echo '#INCLUDE "config_'$(CONFIG)'.asm"' >>$@
/bin/echo ; >>$@
bootrom.bin : bootrom.asm std.asm build.inc ver.inc memmgr.asm config_$(CONFIG).asm
$(TASM) $(ASMOPT80) $< $@
bootapp.bin: bootapp.asm std.asm build.inc ver.inc
$(TASM) $(ASMOPT80) $< $@
pgzero.bin: pgzero.asm std.asm build.inc ver.inc
$(TASM) $(ASMOPT80) $< $@
zcprw.bin: zcprw.asm zcpr.asm
$(TASM) $(ASMOPT85) $< $@
zsdos.bin: zsdos.asm zsdos.lib zsdos-gp.z80
$(TASM) $(ASMOPT80) $< $@
cbios.bin: cbios.asm fd_data.asm ide_data.asm ppide_data.asm sd_data.asm prp_data.asm ppp_data.asm uart.asm vdu.asm std.asm ver.inc build.inc infolist.inc
$(TASM) $(ASMOPT80) -dBLD_SYS=SYS_$(SYS) $< $@
dbgmon.bin: dbgmon.asm std.asm ver.inc build.inc
syscfg.bin: syscfg.asm std.asm build.inc ver.inc
os.bin: $(CPBIN) $(DOSBIN) cbios.bin
cat $(CPBIN) $(DOSBIN) cbios.bin >>$@
rom0.bin: pgzero.bin bootrom.bin syscfg.bin loader.bin romfill.bin dbgmon.bin os.bin hbfill.bin
cat pgzero.bin bootrom.bin syscfg.bin loader.bin romfill.bin dbgmon.bin os.bin hbfill.bin >>$@
rom1.bin: pgzero.bin bootrom.bin syscfg.bin loader.bin bnk1.bin
cat pgzero.bin bootrom.bin syscfg.bin loader.bin bnk1.bin >>$@
$(OUTDIR)/$(ROMNAME).rom: rom0.bin rom1.bin $(ROMDISKFILES) $(OUTDIR)/$(ROMNAME).sys diskdefs
cp $(SRC)blank$(ROMSIZE)KB.dat RomDisk.tmp
$(CPMCP) -f rom$(ROMSIZE)KB RomDisk.tmp $(ROMDSKFILES) 0:
$(CPMCP) -f rom$(ROMSIZE)KB RomDisk.tmp ../Output/$(ROMNAME).sys 0:$(SYS).sys
cat rom0.bin rom1.bin RomDisk.tmp >>$@
$(OUTDIR)/$(ROMNAME).com: bootapp.bin syscfg.bin loader.bin bnk1.bin dbgmon.bin os.bin
cat bootapp.bin syscfg.bin loader.bin bnk1.bin dbgmon.bin os.bin >>$@
$(OUTDIR)/$(ROMNAME).sys: prefix.bin os.bin
cat prefix.bin os.bin >>$@
ansi.asm: $(SRC)ansi.asm
cp $< $@
$(CVT) $@
bdosb01.asm: $(SRC)bdosb01.asm
cp $< $@
$(CVT) $@
bnk1.asm: $(SRC)bnk1.asm fd.asm ppide.asm n8v.asm ppk.asm sd.asm tty.asm ansi.asm
cp $(SRC)bnk1.asm $@
$(CVT) $@
bootapp.asm: $(SRC)bootapp.asm
cp $< $@
$(CVT) $@
bootrom.asm: $(SRC)bootrom.asm
cp $< $@
$(CVT) $@
cbios.asm: $(SRC)cbios.asm
cp $< $@
$(CVT) $@
ccpb03.asm: $(SRC)ccpb03.asm
cp $< $@
$(CVT) $@
cnfgdata.inc: $(SRC)cnfgdata.inc
cp $< $@
$(CVT) $@
##config_zeta.asm: $(SRC)config_zeta.asm
## cp $< $@
## $(CVT) $@
config_$(CONFIG).asm: $(SRC)config_$(CONFIG).asm
cp $< $@
$(CVT) $@
dbgmon.asm: $(SRC)dbgmon.asm
cp $< $@
$(CVT) $@
diskdefs: $(SRC)diskdefs
cp $< $@
$(CVT) $@
fd.asm: $(SRC)fd.asm
cp $< $@
$(CVT) $@
fd_data.asm: $(SRC)fd_data.asm
cp $< $@
$(CVT) $@
hbfill.asm: $(SRC)hbfill.asm
cp $< $@
$(CVT) $@
ide_data.asm: $(SRC)ide_data.asm
cp $< $@
$(CVT) $@
infolist.inc: $(SRC)infolist.inc
cp $< $@
$(CVT) $@
loader.asm: $(SRC)loader.asm util.asm
cp $(SRC)loader.asm $@
$(CVT) $@
memmgr.asm: $(SRC)memmgr.asm
cp $< $@
$(CVT) $@
n8v.asm: $(SRC)n8v.asm
cp $< $@
$(CVT) $@
pgzero.asm: $(SRC)pgzero.asm
cp $< $@
$(CVT) $@
ppide.asm: $(SRC)ppide.asm
cp $< $@
$(CVT) $@
ppide_data.asm: $(SRC)ppide_data.asm
cp $< $@
$(CVT) $@
ppk.asm: $(SRC)ppk.asm
cp $< $@
$(CVT) $@
ppp_data.asm: $(SRC)ppp_data.asm
cp $< $@
$(CVT) $@
prefix.asm: $(SRC)prefix.asm
cp $< $@
$(CVT) $@
prp_data.asm: $(SRC)prp_data.asm
cp $< $@
$(CVT) $@
romfill.asm: $(SRC)romfill.asm
cp $< $@
$(CVT) $@
sd.asm: $(SRC)sd.asm
cp $< $@
$(CVT) $@
sd_data.asm: $(SRC)sd_data.asm
cp $< $@
$(CVT) $@
std.asm: $(SRC)std.asm
cp $< $@
$(CVT) $@
syscfg.asm: $(SRC)syscfg.asm config_$(CONFIG).asm cnfgdata.inc
cp $< $@
$(CVT) $@
tty.asm: $(SRC)tty.asm
cp $< $@
$(CVT) $@
uart.asm: $(SRC)uart.asm
cp $< $@
$(CVT) $@
util.asm: $(SRC)util.asm
cp $< $@
$(CVT) $@
vdu.asm: $(SRC)vdu.asm
cp $< $@
$(CVT) $@
ver.inc: $(SRC)ver.inc
cp $< $@
$(CVT) $@
clean:
rm -f *.tab *.TAB *.inc *.asm *.bin *.com *.img *.rom *.lst *.exp *.tmp
rm -f build.inc diskdefs
rm -f $(OUTDIR)/*.*

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"TASM 6805 Assembler. "
/***************************************************************************
/* $Id
/***************************************************************************
/* This is the instruction set definition table for the 6805 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, April 1988.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ADC #* A9 2 NOP 1
ADC ,X F9 1 NOP 1
ADC *,X D9 3 MZERO 1
ADC * C9 3 MZERO 1
ADD #* AB 2 NOP 1
ADD ,X FB 1 NOP 1
ADD *,X DB 3 MZERO 1
ADD * CB 3 MZERO 1
AND #* A4 2 NOP 1
AND ,X F4 1 NOP 1
AND *,X D4 3 MZERO 1
AND * C4 3 MZERO 1
ASLA "" 48 1 NOP 1
ASLX "" 58 1 NOP 1
ASL ,X 78 1 NOP 1
ASL *,X 68 2 NOP 1
ASL * 38 2 NOP 1
ASRA "" 47 1 NOP 1
ASRX "" 57 1 NOP 1
ASR ,X 77 1 NOP 1
ASR *,X 67 2 NOP 1
ASR * 37 2 NOP 1
BCC * 24 2 R1 1
BCLR *,* 11 2 MBIT 1
BCS * 25 2 R1 1
BEQ * 27 2 R1 1
BHCC * 28 2 R1 1
BHCS * 29 2 R1 1
BHI * 22 2 R1 1
BHS * 24 2 R1 1
BIH * 2F 2 R1 1
BIL * 2E 2 R1 1
BIT #* A5 2 NOP 1
BIT ,X F5 1 NOP 1
BIT *,X D5 3 MZERO 1
BIT * C5 3 MZERO 1
BLO * 25 2 R1 1
BLS * 23 2 R1 1
BMC * 2C 2 R1 1
BMI * 2B 2 R1 1
BMS * 2D 2 R1 1
BNE * 26 2 R1 1
BPL * 2A 2 R1 1
BRA * 20 2 R1 1
BRCLR *,*,* 01 3 MBIT 1
BRN * 21 2 R1 1
BRSET *,*,* 00 3 MBIT 1
BSET *,* 10 2 MBIT 1
BSR * AD 2 R1 1
CLC "" 98 1 NOP 1
CLI "" 9A 1 NOP 1
CLRA "" 4F 1 NOP 1
CLRX "" 5F 1 NOP 1
CLR ,X 7F 1 NOP 1
CLR *,X 6F 2 NOP 1
CLR * 3F 2 NOP 1
CMP #* A1 2 NOP 1
CMP ,X F1 1 NOP 1
CMP *,X D1 3 MZERO 1
CMP * C1 3 MZERO 1
CMPX #* A3 2 NOP 1 /* equivalent to CPX */
CMPX ,X F3 1 NOP 1
CMPX *,X D3 3 MZERO 1
CMPX * C3 3 MZERO 1
COMA "" 43 1 NOP 1
COMX "" 53 1 NOP 1
COM ,X 73 1 NOP 1
COM *,X 63 2 NOP 1
COM * 33 2 NOP 1
CPX #* A3 2 NOP 1
CPX ,X F3 1 NOP 1
CPX *,X D3 3 MZERO 1
CPX * C3 3 MZERO 1
DECA "" 4A 1 NOP 1
DECX "" 5A 1 NOP 1
DEX "" 5A 1 NOP 1
DEC ,X 7A 1 NOP 1
DEC *,X 6A 2 NOP 1
DEC * 3A 2 NOP 1
EOR #* A8 2 NOP 1
EOR ,X F8 1 NOP 1
EOR *,X D8 3 MZERO 1
EOR * C8 3 MZERO 1
INCA "" 4C 1 NOP 1
INCX "" 5C 1 NOP 1
INX "" 5C 1 NOP 1
INC ,X 7C 1 NOP 1
INC *,X 6C 2 NOP 1
INC * 3C 2 NOP 1
JMP ,X FC 1 NOP 1
JMP *,X DC 3 MZERO 1
JMP * CC 3 MZERO 1
JSR ,X FD 1 NOP 1
JSR *,X DD 3 MZERO 1
JSR * CD 3 MZERO 1
LDA #* A6 2 NOP 1
LDA ,X F6 1 NOP 1
LDA *,X D6 3 MZERO 1
LDA * C6 3 MZERO 1
LDX #* AE 2 NOP 1
LDX ,X FE 1 NOP 1
LDX *,X DE 3 MZERO 1
LDX * CE 3 MZERO 1
LSLA "" 48 1 NOP 1
LSLX "" 58 1 NOP 1
LSL ,X 78 1 NOP 1
LSL *,X 68 2 NOP 1
LSL * 38 2 NOP 1
LSRA "" 44 1 NOP 1
LSRX "" 54 1 NOP 1
LSR ,X 74 1 NOP 1
LSR *,X 64 2 NOP 1
LSR * 34 2 NOP 1
MUL "" 42 1 NOP 4 /* HC05C4 only */
NEGA "" 40 1 NOP 1
NEGX "" 50 1 NOP 1
NEG ,X 70 1 NOP 1
NEG *,X 60 2 NOP 1
NEG * 30 2 NOP 1
NOP "" 9D 1 NOP 1
ORA #* AA 2 NOP 1
ORA ,X FA 1 NOP 1
ORA *,X DA 3 MZERO 1
ORA * CA 3 MZERO 1
ROLA "" 49 1 NOP 1
ROLX "" 59 1 NOP 1
ROL ,X 79 1 NOP 1
ROL *,X 69 2 NOP 1
ROL * 39 2 NOP 1
RORA "" 46 1 NOP 1
RORX "" 56 1 NOP 1
ROR ,X 76 1 NOP 1
ROR *,X 66 2 NOP 1
ROR * 36 2 NOP 1
RSP "" 9C 1 NOP 1
RTI "" 80 1 NOP 1
RTS "" 81 1 NOP 1
SBC #* A2 2 NOP 1
SBC ,X F2 1 NOP 1
SBC *,X D2 3 MZERO 1
SBC * C2 3 MZERO 1
SEC "" 99 1 NOP 1
SEI "" 9B 1 NOP 1
STA ,X F7 1 NOP 1
STA *,X D7 3 MZERO 1
STA * C7 3 MZERO 1
STOP "" 8E 1 NOP 2 /* M146805 CMOS only */
STX ,X FF 1 NOP 1
STX *,X DF 3 MZERO 1
STX * CF 3 MZERO 1
SUB #* A0 2 NOP 1
SUB ,X F0 1 NOP 1
SUB *,X D0 3 MZERO 1
SUB * C0 3 MZERO 1
SWI "" 83 1 NOP 1
TAX "" 97 1 NOP 1
TSTA "" 4D 1 NOP 1
TSTX "" 5D 1 NOP 1
TST ,X 7D 1 NOP 1
TST *,X 6D 2 NOP 1
TST * 3D 2 NOP 1
TXA "" 9F 1 NOP 1
WAIT "" 8F 1 NOP 2 /* M146805 CMOS only */

205
branches/dgg/LSource/bin/TASM3210.TAB
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"TASM TMS32010 Assembler."
/****************************************************************************
/* $Id: tasm3210.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the TMS32010 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/*
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT MASK */
/*-------------------------------------------*/
/* Generate opcodes high byte first */
.MSFIRST
/* Don't use '*' as the wild card since it is used for indirect addressing */
/* In this table '@' is the wild card indicating where expression may appear*/
.ALTWILD
/* Use word addressing (not byte addressing)
.WORDADDRS
/* All shift/and stuff applies to opcodes, not args
.NOARGSHIFT
.REGSET *+ A0 1
.REGSET *- 90 1
.REGSET * 80 1
ABS "" 7F88 2 NOP 1
ADD !,@,@ 0000 2 T1 1 8 0F00
ADD !,@ 0008 2 T1 1 8 0F00
ADD ! 0008 2 NOP 1
ADD @,@ 0000 2 TDMA 1 8 0F00
ADD @ 0000 2 T1 1 0 007F
ADDH !,@ 6000 2 T1 1 0 01
ADDH ! 6008 2 NOP 1
ADDH @ 6000 2 T1 1 0 007F
ADDS !,@ 6100 2 T1 1 0 01
ADDS ! 6108 2 NOP 1
ADDS @ 6100 2 T1 1 0 007F
AND !,@ 7900 2 T1 1 0 01
AND ! 7908 2 NOP 1
AND @ 7900 2 T1 1 0 7F
APAC "" 7F8F 2 NOP 1
B @ F900 4 SWAP 1
BANZ @ F400 4 SWAP 1
BGEZ @ FD00 4 SWAP 1
BGZ @ FC00 4 SWAP 1
BIOZ @ F600 4 SWAP 1
BLEZ @ FB00 4 SWAP 1
BLZ @ FA00 4 SWAP 1
BNZ @ FE00 4 SWAP 1
BV @ F500 4 SWAP 1
BZ @ FF00 4 SWAP 1
CALA "" 7F8C 2 NOP 1
CALL @ F800 4 SWAP 1
DINT "" 7F81 2 NOP 1
DMOV !,@ 6900 2 T1 1 0 01
DMOV ! 6908 2 NOP 1
DMOV @ 6900 2 T1 1 0 007F
EINT "" 7F82 2 NOP 1
IN !,@,@ 4000 2 T1 1 8 0700
IN !,@ 4008 2 T1 1 8 0700
IN @,@ 4000 2 TDMA 1 8 0700
LAC !,@,@ 2000 2 T1 1 8 0F00
LAC !,@ 2008 2 T1 1 8 0F00
LAC ! 2008 2 NOP 1
LAC @,@ 2000 2 TDMA 1 8 0F00
LAC @ 2000 2 T1 1 0 007F
LACK @ 7E00 2 T1 1 0 00FF
LAR @,!,@ 3800 2 TAR 1 0 0001
LAR @,! 3808 2 TAR 1 0 0001
LAR @,@ 3800 2 TAR 1 0 007F
LARK @,@ 7000 2 TAR 1 0 00FF
LARP @ 6880 2 T1 1 0 0001
LDP !,@ 6F00 2 T1 1 0 01
LDP ! 6F08 2 NOP 1
LDP @ 6F00 2 T1 1 0 007F
LDPK @ 6E00 2 T1 1 0 01
LST !,@ 7B00 2 T1 1 0 01
LST ! 7B08 2 NOP 1
LST @ 7B00 2 T1 1 0 007F
LT !,@ 6A00 2 T1 1 0 01
LT ! 6A08 2 NOP 1
LT @ 6A00 2 T1 1 0 007F
LTA !,@ 6C00 2 T1 1 0 01
LTA ! 6C08 2 NOP 1
LTA @ 6C00 2 T1 1 0 007F
LTD !,@ 6B00 2 T1 1 0 01
LTD ! 6B08 2 NOP 1
LTD @ 6B00 2 T1 1 0 007F
MAR !,@ 6800 2 T1 1 0 01
MAR ! 6808 2 NOP 1
MAR @ 6800 2 T1 1 0 007F
MPY !,@ 6D00 2 T1 1 0 01
MPY ! 6D08 2 NOP 1
MPY @ 6D00 2 T1 1 0 007F
MPYK @ 8000 2 T1 1 0 1FFF
NOP "" 7F80 2 NOP 1
OR !,@ 7A00 2 T1 1 0 01
OR ! 7A08 2 NOP 1
OR @ 7A00 2 T1 1 0 007F
OUT !,@,@ 4800 2 T1 1 8 0700
OUT !,@ 4808 2 T1 1 8 0700
OUT @,@ 4800 2 TDMA 1 8 0700
PAC "" 7F8E 2 NOP 1
POP "" 7F9D 2 NOP 1
PUSH "" 7F9C 2 NOP 1
RET "" 7F8D 2 NOP 1
ROVM "" 7F8A 2 NOP 1
/* shift count for SACH can only be 0,1, or 4. The mask allows */
/* 0,1,4, or 5. Let the user beware */
SACH !,@,@ 5800 2 T1 1 8 0500
SACH !,@ 5808 2 T1 1 8 0500
SACH ! 5808 2 NOP 1
SACH @,@ 5800 2 TDMA 1 8 0500
SACH @ 5800 2 T1 1 0 007F
/* The data book shows a shift field for SACL but states it must be 0.
/* The previous version of this table left the shift field out
/* for simplicity, but here I have put it back for compatibility.
/* The AND mask is set to zero in this case so a error message
/* will result from non-zero shifts.
SACL !,@,@ 5000 2 T1 1 8 0000
SACL !,@ 5008 2 T1 1 8 0000
SACL ! 5008 2 NOP 1
SACL @,@ 5000 2 TDMA 1 8 0000
SACL @ 5000 2 T1 1 0 007F
SAR @,!,@ 3000 2 TAR 1 0 0001
SAR @,! 3008 2 TAR 1 0 0001
SAR @,@ 3000 2 TAR 1 0 007F
SOVM "" 7F8B 2 NOP 1
SPAC "" 7F90 2 NOP 1
SST !,@ 7C00 2 T1 1 0 0001
SST ! 7C08 2 NOP 1
SST @ 7C00 2 T1 1 0 007F
SUB !,@,@ 1000 2 T1 1 8 0F00
SUB !,@ 1008 2 T1 1 8 0F00
SUB ! 1008 2 NOP 1
SUB @,@ 1000 2 TDMA 1 8 0F00
SUB @ 1000 2 T1 1 0 007F
SUBC !,@ 6400 2 T1 1 0 01
SUBC ! 6408 2 NOP 1
SUBC @ 6400 2 T1 1 0 007F
SUBH !,@ 6200 2 T1 1 0 01
SUBH ! 6208 2 NOP 1
SUBH @ 6200 2 T1 1 0 007F
SUBS !,@ 6300 2 T1 1 0 01
SUBS ! 6308 2 NOP 1
SUBS @ 6300 2 T1 1 0 007F
TBLR !,@ 6700 2 T1 1 0 01
TBLR ! 6708 2 NOP 1
TBLR @ 6700 2 T1 1 0 007F
TBLW !,@ 7D00 2 T1 1 0 01
TBLW ! 7D08 2 NOP 1
TBLW @ 7D00 2 T1 1 0 007F
XOR !,@ 7800 2 T1 1 0 01
XOR ! 7808 2 NOP 1
XOR @ 7800 2 T1 1 0 007F
ZAC "" 7F89 2 NOP 1
ZALH !,@ 6500 2 T1 1 0 01
ZALH ! 6508 2 NOP 1
ZALH @ 6500 2 T1 1 0 007F
ZALS !,@ 6600 2 T1 1 0 01
ZALS ! 6608 2 NOP 1
ZALS @ 6600 2 T1 1 0 007F

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"TASM TMS32025 Assembler."
/****************************************************************************
/* $Id: tasm3225.tab 1.2 1997/09/28 22:16:44 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the TMS32025 version of TASM.
/* Bob Stricklin
/*
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT MASK */
/*-------------------------------------------*/
/* Generate opcodes high byte first */
.MSFIRST
/* Don't use '*' as the wild card since it is used for indirect addressing */
/* In this table '@' is the wild card indicating where expression may appear*/
.ALTWILD
.WORDADDRS
.NOARGSHIFT
/* Addressing mode definitions.
/* Value gets OR'd in to the opcode if the
/* addressing mode is recognized
/* Note: no special classes are defined, so if this
/* table is used for TMS32020, invalid instructions
/* will not result in errors (no BR0+/- addressing mode (for example)
/* The ! character can match any of the patterns in the REGSET:
.REGSET *BR0+ F0 1
.REGSET *BR0- C0 1
.REGSET *0+ E0 1
.REGSET *0- D0 1
.REGSET *+ A0 1
.REGSET *- 90 1
.REGSET * 80 1
ABS "" CE1B 2 NOP 1
ADD !,@,@ 0088 2 T1 1 8 0F00
ADD !,@ 0080 2 T1 1 8 0F00
ADD ! 0080 2 NOP 1
ADD @,@ 0000 2 TDMA 1 8 0F00
ADD @ 0000 2 T1 1 0 007F
ADDC !,@ 4388 2 T1 1 0 0007
ADDC ! 4380 2 NOP 1
ADDC @ 4300 2 T1 1 0 007F
ADDH !,@ 4888 2 T1 1 0 0007
ADDH ! 4880 2 NOP 1
ADDH @ 4800 2 T1 1 0 007F
ADDK @ CC00 2 T1 1 0 00FF ;8 bit constant
ADDS !,@ 4988 2 T1 1 0 0007
ADDS ! 4980 2 NOP 1
ADDS @ 4900 2 T1 1 0 007F
ADDT !,@ 4A88 2 T1 1 0 0007
ADDT ! 4A80 2 NOP 1
ADDT @ 4A00 2 T1 1 0 007F
ADLK @,@ D002 4 TLK 1 8 0F00
ADLK @ D002 4 TLK 1
ADRK @ 7E00 2 T1 1 0 00FF ;8 bit constant
AND !,@ 4E88 2 T1 1 0 0007
AND ! 4E80 2 NOP 1
AND @ 4E00 2 T1 1 0 007F
ANDK @,@ D004 4 TLK 1 8 0F00
ANDK @ D004 4 TLK 1
APAC "" CE15 2 NOP 1
B @,!,@ FF88 4 TLK 1 0 07
B @,! FF80 4 SWAP 1
B @ FF80 4 SWAP 1
BACC "" CE25 2 NOP 1
BANZ @,!,@ FB88 4 TLK 1 0 07
BANZ @,! FB80 4 SWAP 1
BANZ @ FB90 4 SWAP 1 ; Default to the equivalent of
; BANZ loop,*- (as per spec) for
; TMS32010 compatibility.
BBNZ @,!,@ F988 4 TLK 1 0 07
BBNZ @,! F980 4 SWAP 1
BBNZ @ F980 4 SWAP 1
BBZ @,!,@ F888 4 TLK 1 0 07
BBZ @,! F880 4 SWAP 1
BBZ @ F880 4 SWAP 1
BC @,!,@ 5E88 4 TLK 1 0 07
BC @,! 5E80 4 SWAP 1
BC @ 5E80 4 SWAP 1
BGEZ @,!,@ F488 4 TLK 1 0 07
BGEZ @,! F480 4 SWAP 1
BGEZ @ F480 4 SWAP 1
BGZ @,!,@ F188 4 TLK 1 0 07
BGZ @,! F180 4 SWAP 1
BGZ @ F180 4 SWAP 1
BIOZ @,!,@ FA88 4 TLK 1 0 07
BIOZ @,! FA80 4 SWAP 1
BIOZ @ FA80 4 SWAP 1
BIT !,@,@ 9088 2 T1 1 8 0F00 ;8 bit shift
BIT !,@ 9080 2 T1 1 8 0F00
BIT @,@ 9000 2 TDMA 1 8 0F00
BITT !,@ 5788 2 T1 1 0 07
BITT ! 5780 2 T1 1
BITT @ 5700 2 T1 1 0 7F
BLEZ @,!,@ F288 4 TLK 1 0 07
BLEZ @,! F280 4 SWAP 1
BLEZ @ F280 4 SWAP 1
BLKD @,!,@ FD88 4 TLK 1 0 07
BLKD @,! FD80 4 TLK 1 0 07
BLKD @,@ FD00 4 TLK 1 0 FF
BLKP @,!,@ FC88 4 TLK 1 0 07
BLKP @,! FC80 4 TLK 1 0 07
BLKP @,@ FC00 4 TLK 1 0 FF
BLZ @,!,@ F388 4 TLK 1 0 07
BLZ @,! F380 4 SWAP 1
BLZ @ F380 4 SWAP 1
BNC @,!,@ 5F88 4 TLK 1 0 07
BNC @,! 5F80 4 SWAP 1
BNC @ 5F80 4 SWAP 1
BNV @,!,@ F788 4 TLK 1 0 07
BNV @,! F780 4 SWAP 1
BNV @ F780 4 SWAP 1
BNZ @,!,@ F588 4 TLK 1 0 07
BNZ @,! F580 4 SWAP 1
BNZ @ F580 4 SWAP 1
BV @,!,@ F088 4 TLK 1 0 07
BV @,! F080 4 SWAP 1
BV @ F080 4 SWAP 1
BZ @,!,@ F688 4 TLK 1 0 07
BZ @,! F680 4 SWAP 1
BZ @ F680 4 SWAP 1
CALA "" CE24 2 NOP 1
CALL @,!,@ FE88 4 TLK 1 0 07
CALL @,! FE80 4 SWAP 1
CALL @ FE80 4 SWAP 1
CMPL "" CE27 2 NOP 1
CMPR @ CE50 2 T1 1 0 03 ;2 BIT CONTANT
CNFD "" CE04 2 NOP 1
CNFP "" CE05 2 NOP 1
CONF "" CE3C 2 T1 4 0 03 ; c26 ONLY
DINT "" CE01 2 NOP 1
DMOV !,@ 5688 2 T1 1 0 07
DMOV ! 5680 2 NOP 1
DMOV @ 5600 2 T1 1 0 007F
EINT "" CE00 2 NOP 1
FORT @ CE0E 2 T1 1 0 01
IDLE "" CE1F 2 NOP 1
IN !,@,@ 8088 2 T1 1 8 0F00
IN !,@ 8080 2 T1 1 8 0F00
IN @,@ 8000 2 TDMA 1 8 0F00
LAC !,@,@ 2088 2 T1 1 8 0F00
LAC !,@ 2080 2 T1 1 8 0F00
LAC ! 2080 2 NOP 1
LAC @,@ 2000 2 TDMA 1 8 0F00
LAC @ 2000 2 T1 1 0 007F
LACK @ CA00 2 T1 1 0 00FF ;tested for -25
LACT !,@ 4288 2 T1 1 0 07
LACT ! 4280 2 NOP 1
LACT @ 4200 2 T1 1 0 007F
LALK @,@ D001 4 TLK 1 8 0F00
LALK @ D001 4 TLK 1
LAR @,!,@ 3088 2 TAR 1 0 07
LAR @,! 3080 2 TAR 1 0 07
LAR @,@ 3000 2 TAR 1 0 7F
LARK @,@ C000 2 TAR 1 0 00FF
LARP @ 5588 2 T1 1 0 0007
LDP !,@ 5288 2 T1 1 0 07
LDP ! 5280 2 NOP 1
LDP @ 5200 2 T1 1 0 007F
LDPK @ C800 2 T1 1 0 01FF ;9 bit constant
LPH !,@ 5388 2 T1 1 0 07
LPH ! 5380 2 NOP 1
LPH @ 5300 2 T1 1 0 7F
LRLK @,@ D000 4 T5 1 8 0700 ;<arp>, <const16>
LST !,@ 5088 2 T1 1 0 07
LST ! 5080 2 NOP 1
LST @ 5000 2 T1 1 0 7F
LST1 !,@ 5188 2 T1 1 0 07
LST1 ! 5180 2 NOP 1
LST1 @ 5100 2 T1 1 0 7F
LT !,@ 3C88 2 T1 1 0 07
LT ! 3C80 2 NOP 1
LT @ 3C00 2 T1 1 0 7F
LTA !,@ 3D88 2 T1 1 0 07
LTA ! 3D80 2 NOP 1
LTA @ 3D00 2 T1 1 0 7F
LTD !,@ 3F88 2 T1 1 0 07
LTD ! 3F80 2 NOP 1
LTD @ 3F00 2 T1 1 0 7F
LTP !,@ 3E88 2 T1 1 0 07
LTP ! 3E80 2 NOP 1
LTP @ 3E00 2 T1 1 0 7F
LTS !,@ 5B88 2 T1 1 0 07
LTS ! 5B80 2 NOP 1
LTS @ 5B00 2 T1 1 0 7F
MAC @,!,@ 5D88 4 TLK 1 0 07
MAC @,! 5D80 4 TLK 1 0 07
MAC @,@ 5D00 4 TLK 1 0 7F
MACD @,!,@ 5C88 4 TLK 1 0 07
MACD @,! 5C80 4 TLK 1 0 07
MACD @,@ 5C00 4 TLK 1 0 7F
MAR !,@ 5588 2 T1 1 0 07
MAR ! 5580 2 NOP 1
MAR @ 5500 2 T1 1 0 7F
MPY !,@ 3888 2 T1 1 0 07
MPY ! 3880 2 NOP 1
MPY @ 3800 2 T1 1 0 7F
MPYA !,@ 3A88 2 T1 1 0 07
MPYA ! 3A80 2 NOP 1
MPYA @ 3A00 2 T1 1 0 7F
MPYK @ A000 2 T1 1 0 1FFF ;13 BIT CONTSTANT
MPYS !,@ 3B88 2 T1 1 0 07
MPYS ! 3B80 2 NOP 1
MPYS @ 3B00 2 T1 1 0 7F
MPYU !,@ CF88 2 T1 1 0 07
MPYU ! CF80 2 NOP 1
MPYU @ CF00 2 T1 1 0 7F
NEG "" CE23 2 NOP 1
NOP "" 5500 2 NOP 1
NORM ! CE82 2 NOP 1 ; C25
NORM "" CEA2 2 NOP 1 ; C20
OR !,@ 4D88 2 T1 1 0 07
OR ! 4D80 2 NOP 1
OR @ 4D00 2 T1 1 0 7F
ORK @,@ D005 4 TLK 1 8 0F00
ORK @ D005 4 TLK 1
OUT !,@,@ E088 2 T1 1 8 0F00
OUT !,@ E080 2 T1 1 8 0F00
OUT @,@ E000 2 TDMA 1 8 0F00
PAC "" CE14 2 NOP 1
POP "" CE1D 2 NOP 1
POPD !,@ 7A88 2 T1 1 0 07
POPD ! 7A80 2 NOP 1
POPD @ 7A00 2 T1 1 0 7F
PSHD !,@ 5488 2 T1 1 0 07
PSHD ! 5480 2 NOP 1
PSHD @ 5400 2 T1 1 0 7F
PUSH "" CE1C 2 NOP 1
RC "" CE30 2 NOP 1
RET "" CE26 2 NOP 1
RFSM "" CE36 2 NOP 1
RHM "" CE38 2 NOP 1
ROL "" CE34 2 NOP 1
ROR "" CE35 2 NOP 1
ROVM "" CE02 2 NOP 1
RPT !,@ 4B88 2 T1 1 0 07
RPT ! 4B80 2 NOP 1
RPT @ 4B00 2 T1 1 0 7F
RPTK @ CB00 2 T1 1 0 00FF ;8 bit constant
RSXM "" CE06 2 NOP 1
RTC "" CE32 2 NOP 1
RTXM "" CE20 2 NOP 1
RXF "" CE0C 2 NOP 1
/* shift count for SACH can only be 0,1, or 4 FOR 32020
/* 0-7 FOR 320c25. For now, build the table specifically for the 320C25
SACH !,@,@ 6888 2 T1 1 8 0700
SACH !,@ 6880 2 T1 1 8 0700
SACH ! 6880 2 NOP 1
SACH @,@ 6800 2 TDMA 1 8 0700
SACH @ 6800 2 T1 1 0 007F
SACL !,@,@ 6088 2 T1 1 8 0700
SACL !,@ 6080 2 T1 1 8 0700
SACL ! 6080 2 NOP 1
SACL @,@ 6000 2 TDMA 1 8 0700
SACL @ 6000 2 T1 1 0 007F
SAR @,!,@ 7088 2 TAR 1 0 0007
SAR @,! 7080 2 TAR 1 0 0007
SAR @,@ 7000 2 TAR 1 0 007F
SBLK @,@ D003 4 TLK 1 8 0F00
SBLK @ D003 4 TLK 1
SBRK @ 7F00 2 T1 1 0 00FF
SC "" CE31 2 NOP 1
SFL "" CE18 2 NOP 1
SFR "" CE19 2 NOP 1
SFSM "" CE37 2 NOP 1
SHM "" CE39 2 NOP 1
SOVM "" CE03 2 NOP 1
SPAC "" CE16 2 NOP 1
SPH !,@ 7D88 2 T1 1 0 07
SPH ! 7D80 2 NOP 1
SPH @ 7D00 2 T1 1 0 7F
SPL !,@ 7C88 2 T1 1 0 07
SPL ! 7C80 2 NOP 1
SPL @ 7C00 2 T1 1 0 7F
SPM @ CE08 2 T1 1 0 03 ;2 bit constant
SQRA !,@ 3988 2 T1 1 0 07
SQRA ! 3980 2 NOP 1
SQRA @ 3900 2 T1 1 0 7F
SQRS !,@ 5A88 2 T1 1 0 07
SQRS ! 5A80 2 NOP 1
SQRS @ 5A00 2 T1 1 0 7F
SST !,@ 7888 2 T1 1 0 07
SST ! 7880 2 NOP 1
SST @ 7800 2 T1 1 0 7F
SST1 !,@ 7988 2 T1 1 0 07
SST1 ! 7980 2 NOP 1
SST1 @ 7900 2 T1 1 0 7F
SSXM "" CE07 2 NOP 1
STC "" CE33 2 NOP 1
STXM "" CE21 2 NOP 1
SUB !,@,@ 1088 2 T1 1 8 0F00
SUB !,@ 1080 2 T1 1 8 0F00
SUB ! 1080 2 NOP 1
SUB @,@ 1000 2 TDMA 1 8 0F00
SUB @ 1000 2 T1 1 0 007F
SUBB !,@ 4F88 2 T1 1 0 07
SUBB ! 4F80 2 NOP 1
SUBB @ 4F00 2 T1 1 0 7F
SUBC !,@ 4788 2 T1 1 0 07
SUBC ! 4780 2 NOP 1
SUBC @ 4700 2 T1 1 0 7F
SUBH !,@ 4488 2 T1 1 0 07
SUBH ! 4480 2 NOP 1
SUBH @ 4400 2 T1 1 0 7F
SUBK @ CD00 2 T1 1 0 00FF
SUBS !,@ 4588 2 T1 1 0 07
SUBS ! 4580 2 NOP 1
SUBS @ 4500 2 T1 1 0 7F
SUBT !,@ 4688 2 T1 1 0 07
SUBT ! 4680 2 NOP 1
SUBT @ 4600 2 T1 1 0 7F
SXF "" CE0D 2 NOP 1
TBLR !,@ 5888 2 T1 1 0 07
TBLR ! 5880 2 NOP 1
TBLR @ 5800 2 T1 1 0 7F
TBLW !,@ 5988 2 T1 1 0 07
TBLW ! 5980 2 NOP 1
TBLW @ 5900 2 T1 1 0 7F
TRAP "" CE1E 2 NOP 1
XOR !,@ 4C88 2 T1 1 0 07
XOR ! 4C80 2 NOP 1
XOR @ 4C00 2 T1 1 0 7F
XORK @,@ D006 4 TLK 1 8 0F00
XORK @ D006 4 TLK 1
ZAC "" CA00 2 NOP 1
ZALH !,@ 4088 2 T1 1 0 07
ZALH ! 4080 2 NOP 1
ZALH @ 4000 2 T1 1 0 7F
ZALR !,@ 7B88 2 T1 1 0 07
ZALR ! 7B80 2 NOP 1
ZALR @ 7B00 2 T1 1 0 7F
ZALS !,@ 4188 2 T1 1 0 07
ZALS ! 4180 2 NOP 1
ZALS @ 4100 2 T1 1 0 7F

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"TASM 8048 Assembler. "
/****************************************************************************
/* $Id: tasm48.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 8048 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, June 1987.
/* CLASS bits are assigned as follows:
/* bit 0 = 8X48, 8035, 8039, 8049 instructions
/* bit 1 = 8X41A
/* bit 2 = 8022
/* bit 3 = 8021
/* Note that some of the base instructions should be disabled for the
/* 8041, 8022, and 8021, but are not.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ADD A,R0 68 1 NOP 1
ADD A,R1 69 1 NOP 1
ADD A,R2 6A 1 NOP 1
ADD A,R3 6B 1 NOP 1
ADD A,R4 6C 1 NOP 1
ADD A,R5 6D 1 NOP 1
ADD A,R6 6E 1 NOP 1
ADD A,R7 6F 1 NOP 1
ADD A,@R0 60 1 NOP 1
ADD A,@R1 61 1 NOP 1
ADD A,#* 03 2 NOP 1
ADDC A,R0 78 1 NOP 1
ADDC A,R1 79 1 NOP 1
ADDC A,R2 7A 1 NOP 1
ADDC A,R3 7B 1 NOP 1
ADDC A,R4 7C 1 NOP 1
ADDC A,R5 7D 1 NOP 1
ADDC A,R6 7E 1 NOP 1
ADDC A,R7 7F 1 NOP 1
ADDC A,@R0 70 1 NOP 1
ADDC A,@R1 71 1 NOP 1
ADDC A,#* 13 2 NOP 1
ANL A,R0 58 1 NOP 1
ANL A,R1 59 1 NOP 1
ANL A,R2 5A 1 NOP 1
ANL A,R3 5B 1 NOP 1
ANL A,R4 5C 1 NOP 1
ANL A,R5 5D 1 NOP 1
ANL A,R6 5E 1 NOP 1
ANL A,R7 5F 1 NOP 1
ANL A,@R0 50 1 NOP 1
ANL A,@R1 51 1 NOP 1
ANL A,#* 53 2 NOP 1
ANL BUS,#* 98 2 NOP 1
ANL P1,#* 99 2 NOP 1
ANL P2,#* 9A 2 NOP 1
ANLD P4,A 9C 1 NOP 1
ANLD P5,A 9D 1 NOP 1
ANLD P6,A 9E 1 NOP 1
ANLD P7,A 9F 1 NOP 1
CALL * 14 2 JMP 1
CLR A 27 1 NOP 1
CLR C 97 1 NOP 1
CLR F0 85 1 NOP 1
CLR F1 A5 1 NOP 1
CPL A 37 1 NOP 1
CPL C A7 1 NOP 1
CPL F0 95 1 NOP 1
CPL F1 B5 1 NOP 1
DA A 57 1 NOP 1
DEC A 07 1 NOP 1
DEC R0 C8 1 NOP 1
DEC R1 C9 1 NOP 1
DEC R2 CA 1 NOP 1
DEC R3 CB 1 NOP 1
DEC R4 CC 1 NOP 1
DEC R5 CD 1 NOP 1
DEC R6 CE 1 NOP 1
DEC R7 CF 1 NOP 1
DIS I 15 1 NOP 1
DIS TCNTI 35 1 NOP 1
DJNZ R0,* E8 2 JTHISPAGE 1
DJNZ R1,* E9 2 JTHISPAGE 1
DJNZ R2,* EA 2 JTHISPAGE 1
DJNZ R3,* EB 2 JTHISPAGE 1
DJNZ R4,* EC 2 JTHISPAGE 1
DJNZ R5,* ED 2 JTHISPAGE 1
DJNZ R6,* EE 2 JTHISPAGE 1
DJNZ R7,* EF 2 JTHISPAGE 1
EN DMA E5 1 NOP 2 ;8041
EN FLAGS F5 1 NOP 2 ;8041
EN I 05 1 NOP 1
EN TCNTI 25 1 NOP 1
ENT0 CLK 75 1 NOP 1
IN A,DBB 22 1 NOP 2 ;8041
IN A,P0 08 1 NOP 8 ;8021
IN A,P1 09 1 NOP 1
IN A,P2 0A 1 NOP 1
INC A 17 1 NOP 1
INC R0 18 1 NOP 1
INC R1 19 1 NOP 1
INC R2 1A 1 NOP 1
INC R3 1B 1 NOP 1
INC R4 1C 1 NOP 1
INC R5 1D 1 NOP 1
INC R6 1E 1 NOP 1
INC R7 1F 1 NOP 1
INC @R0 10 1 NOP 1
INC @R1 11 1 NOP 1
INS A,BUS 08 1 NOP 1
JB0 * 12 2 JTHISPAGE 1
JB1 * 32 2 JTHISPAGE 1
JB2 * 52 2 JTHISPAGE 1
JB3 * 72 2 JTHISPAGE 1
JB4 * 92 2 JTHISPAGE 1
JB5 * B2 2 JTHISPAGE 1
JB6 * D2 2 JTHISPAGE 1
JB7 * F2 2 JTHISPAGE 1
JMP * 04 2 JMP 1
JC * F6 2 JTHISPAGE 1
JF0 * B6 2 JTHISPAGE 1
JF1 * 76 2 JTHISPAGE 1
JNC * E6 2 JTHISPAGE 1
JNI * 86 2 JTHISPAGE 1
JNIBF * D6 2 JTHISPAGE 2 ;8041
JNT0 * 26 2 JTHISPAGE 1
JNT1 * 46 2 JTHISPAGE 1
JNZ * 96 2 JTHISPAGE 1
JOBF * 86 2 JTHISPAGE 2 ;8041
JTF * 16 2 JTHISPAGE 1
JT0 * 36 2 JTHISPAGE 1
JT1 * 56 2 JTHISPAGE 1
JZ * C6 2 JTHISPAGE 1
JMPP @A B3 1 NOP 1
MOV A,PSW C7 1 NOP 1
MOV A,R0 F8 1 NOP 1
MOV A,R1 F9 1 NOP 1
MOV A,R2 FA 1 NOP 1
MOV A,R3 FB 1 NOP 1
MOV A,R4 FC 1 NOP 1
MOV A,R5 FD 1 NOP 1
MOV A,R6 FE 1 NOP 1
MOV A,R7 FF 1 NOP 1
MOV A,T 42 1 NOP 1
MOV A,@R0 F0 1 NOP 1
MOV A,@R1 F1 1 NOP 1
MOV A,#* 23 2 NOP 1
MOV PSW,A D7 1 NOP 1
MOV R0,A A8 1 NOP 1
MOV R1,A A9 1 NOP 1
MOV R2,A AA 1 NOP 1
MOV R3,A AB 1 NOP 1
MOV R4,A AC 1 NOP 1
MOV R5,A AD 1 NOP 1
MOV R6,A AE 1 NOP 1
MOV R7,A AF 1 NOP 1
MOV R0,#* B8 2 NOP 1
MOV R1,#* B9 2 NOP 1
MOV R2,#* BA 2 NOP 1
MOV R3,#* BB 2 NOP 1
MOV R4,#* BC 2 NOP 1
MOV R5,#* BD 2 NOP 1
MOV R6,#* BE 2 NOP 1
MOV R7,#* BF 2 NOP 1
MOV STS,A 90 1 NOP 2 ;8041
MOV T,A 62 1 NOP 1
MOV @R0,A A0 1 NOP 1
MOV @R1,A A1 1 NOP 1
MOV @R0,#* B0 2 NOP 1
MOV @R1,#* B1 2 NOP 1
MOVD A,P4 0C 1 NOP 1
MOVD A,P5 0D 1 NOP 1
MOVD A,P6 0E 1 NOP 1
MOVD A,P7 0F 1 NOP 1
MOVD P4,A 3C 1 NOP 1
MOVD P5,A 3D 1 NOP 1
MOVD P6,A 3E 1 NOP 1
MOVD P7,A 3F 1 NOP 1
MOVP A,@A A3 1 NOP 1
MOVP3 A,@A E3 1 NOP 1
MOVX A,@R0 80 1 NOP 1
MOVX A,@R1 81 1 NOP 1
MOVX @R0,A 90 1 NOP 1
MOVX @R1,A 91 1 NOP 1
NOP "" 00 1 NOP 1
ORL A,R0 48 1 NOP 1
ORL A,R1 49 1 NOP 1
ORL A,R2 4A 1 NOP 1
ORL A,R3 4B 1 NOP 1
ORL A,R4 4C 1 NOP 1
ORL A,R5 4D 1 NOP 1
ORL A,R6 4E 1 NOP 1
ORL A,R7 4F 1 NOP 1
ORL A,@R0 40 1 NOP 1
ORL A,@R1 41 1 NOP 1
ORL A,#* 43 2 NOP 1
ORL BUS,#* 88 2 NOP 1
ORL P1,#* 89 2 NOP 1
ORL P2,#* 8A 2 NOP 1
ORLD P4,A 8C 1 NOP 1
ORLD P5,A 8D 1 NOP 1
ORLD P6,A 8E 1 NOP 1
ORLD P7,A 8F 1 NOP 1
OUTL BUS,A 02 1 NOP 1
OUT DBB,A 02 1 NOP 2 ;8041
OUTL P0,A 90 1 NOP 8 ;8021
OUTL P1,A 39 1 NOP 1
OUTL P2,A 3A 1 NOP 1
RAD "" 80 1 NOP 4 ;8022
RET "" 83 1 NOP 1
RETI "" 93 1 NOP 4 ;8022
RETR "" 93 1 NOP 1
RL A E7 1 NOP 1
RLC A F7 1 NOP 1
RR A 77 1 NOP 1
RRC A 67 1 NOP 1
SEL AN0 85 1 NOP 4 ;8022
SEL AN1 95 1 NOP 4 ;8022
SEL MB0 E5 1 NOP 1
SEL MB1 F5 1 NOP 1
SEL RB0 C5 1 NOP 1
SEL RB1 D5 1 NOP 1
STOP TCNT 65 1 NOP 1
STRT CNT 45 1 NOP 1
STRT T 55 1 NOP 1
SWAP A 47 1 NOP 1
XCH A,R0 28 1 NOP 1
XCH A,R1 29 1 NOP 1
XCH A,R2 2A 1 NOP 1
XCH A,R3 2B 1 NOP 1
XCH A,R4 2C 1 NOP 1
XCH A,R5 2D 1 NOP 1
XCH A,R6 2E 1 NOP 1
XCH A,R7 2F 1 NOP 1
XCH A,@R0 20 1 NOP 1
XCH A,@R1 21 1 NOP 1
XCHD A,@R0 30 1 NOP 1
XCHD A,@R1 31 1 NOP 1
XRL A,R0 D8 1 NOP 1
XRL A,R1 D9 1 NOP 1
XRL A,R2 DA 1 NOP 1
XRL A,R3 DB 1 NOP 1
XRL A,R4 DC 1 NOP 1
XRL A,R5 DD 1 NOP 1
XRL A,R6 DE 1 NOP 1
XRL A,R7 DF 1 NOP 1
XRL A,@R0 D0 1 NOP 1
XRL A,@R1 D1 1 NOP 1
XRL A,#* D3 2 NOP 1

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"TASM 8051 Assembler. "
/****************************************************************************
/* $Id: tasm51.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 8051 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, June 1987.
/*
.NOARGSHIFT
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ACALL * 11 2 JMP 1 0 F800
ADD A,R0 28 1 NOP 1
ADD A,R1 29 1 NOP 1
ADD A,R2 2A 1 NOP 1
ADD A,R3 2B 1 NOP 1
ADD A,R4 2C 1 NOP 1
ADD A,R5 2D 1 NOP 1
ADD A,R6 2E 1 NOP 1
ADD A,R7 2F 1 NOP 1
ADD A,@R0 26 1 NOP 1
ADD A,@R1 27 1 NOP 1
ADD A,#* 24 2 NOP 1
ADD A,* 25 2 NOP 1
ADDC A,R0 38 1 NOP 1
ADDC A,R1 39 1 NOP 1
ADDC A,R2 3A 1 NOP 1
ADDC A,R3 3B 1 NOP 1
ADDC A,R4 3C 1 NOP 1
ADDC A,R5 3D 1 NOP 1
ADDC A,R6 3E 1 NOP 1
ADDC A,R7 3F 1 NOP 1
ADDC A,@R0 36 1 NOP 1
ADDC A,@R1 37 1 NOP 1
ADDC A,#* 34 2 NOP 1
ADDC A,* 35 2 NOP 1
AJMP * 01 2 JMP 1 0 F800
ANL A,R0 58 1 NOP 1
ANL A,R1 59 1 NOP 1
ANL A,R2 5A 1 NOP 1
ANL A,R3 5B 1 NOP 1
ANL A,R4 5C 1 NOP 1
ANL A,R5 5D 1 NOP 1
ANL A,R6 5E 1 NOP 1
ANL A,R7 5F 1 NOP 1
ANL A,@R0 56 1 NOP 1
ANL A,@R1 57 1 NOP 1
ANL A,#* 54 2 NOP 1
ANL A,* 55 2 NOP 1
ANL C,/* b0 2 NOP 1
ANL C,* 82 2 NOP 1
ANL *,A 52 2 NOP 1
ANL *,#* 53 3 COMBINE 1
CJNE A,#*,* b4 3 CR 1
CJNE A,*,* b5 3 CR 1
CJNE R0,#*,* b8 3 CR 1
CJNE R1,#*,* b9 3 CR 1
CJNE R2,#*,* ba 3 CR 1
CJNE R3,#*,* bb 3 CR 1
CJNE R4,#*,* bc 3 CR 1
CJNE R5,#*,* bd 3 CR 1
CJNE R6,#*,* be 3 CR 1
CJNE R7,#*,* bf 3 CR 1
CJNE @R0,#*,* b6 3 CR 1
CJNE @R1,#*,* b7 3 CR 1
CLR A e4 1 NOP 1
CLR C c3 1 NOP 1
CLR * c2 2 NOP 1
CPL A f4 1 NOP 1
CPL C b3 1 NOP 1
CPL * b2 2 NOP 1
DA A d4 1 NOP 1
DEC A 14 1 NOP 1
DEC R0 18 1 NOP 1
DEC R1 19 1 NOP 1
DEC R2 1A 1 NOP 1
DEC R3 1B 1 NOP 1
DEC R4 1C 1 NOP 1
DEC R5 1D 1 NOP 1
DEC R6 1E 1 NOP 1
DEC R7 1F 1 NOP 1
DEC @R0 16 1 NOP 1
DEC @R1 17 1 NOP 1
DEC * 15 2 NOP 1
DIV AB 84 1 NOP 1
DJNZ R0,* d8 2 R1 1
DJNZ R1,* d9 2 R1 1
DJNZ R2,* dA 2 R1 1
DJNZ R3,* dB 2 R1 1
DJNZ R4,* dC 2 R1 1
DJNZ R5,* dD 2 R1 1
DJNZ R6,* dE 2 R1 1
DJNZ R7,* dF 2 R1 1
DJNZ *,* d5 3 CR 1
INC A 04 1 NOP 1
INC R0 08 1 NOP 1
INC R1 09 1 NOP 1
INC R2 0A 1 NOP 1
INC R3 0B 1 NOP 1
INC R4 0C 1 NOP 1
INC R5 0D 1 NOP 1
INC R6 0E 1 NOP 1
INC R7 0F 1 NOP 1
INC @R0 06 1 NOP 1
INC @R1 07 1 NOP 1
INC DPTR a3 1 NOP 1
INC * 05 2 NOP 1
JB *,* 20 3 CR 1
JBC *,* 10 3 CR 1
JC * 40 2 R1 1
JMP @A+DPTR 73 1 NOP 1
JNB *,* 30 3 CR 1
JNC * 50 2 R1 1
JNZ * 70 2 R1 1
JZ * 60 2 R1 1
LCALL * 12 3 SWAP 1
LJMP * 02 3 SWAP 1
MOV A,R0 e8 1 NOP 1
MOV A,R1 e9 1 NOP 1
MOV A,R2 eA 1 NOP 1
MOV A,R3 eB 1 NOP 1
MOV A,R4 eC 1 NOP 1
MOV A,R5 eD 1 NOP 1
MOV A,R6 eE 1 NOP 1
MOV A,R7 eF 1 NOP 1
MOV A,@R0 e6 1 NOP 1
MOV A,@R1 e7 1 NOP 1
MOV A,#* 74 2 NOP 1
MOV A,* e5 2 NOP 1
MOV C,* a2 2 NOP 1
MOV DPTR,#* 90 3 SWAP 1
MOV R0,A f8 1 NOP 1
MOV R1,A f9 1 NOP 1
MOV R2,A fA 1 NOP 1
MOV R3,A fB 1 NOP 1
MOV R4,A fC 1 NOP 1
MOV R5,A fD 1 NOP 1
MOV R6,A fE 1 NOP 1
MOV R7,A fF 1 NOP 1
MOV R0,#* 78 2 NOP 1
MOV R1,#* 79 2 NOP 1
MOV R2,#* 7A 2 NOP 1
MOV R3,#* 7B 2 NOP 1
MOV R4,#* 7C 2 NOP 1
MOV R5,#* 7D 2 NOP 1
MOV R6,#* 7E 2 NOP 1
MOV R7,#* 7F 2 NOP 1
MOV R0,* a8 2 NOP 1
MOV R1,* a9 2 NOP 1
MOV R2,* aA 2 NOP 1
MOV R3,* aB 2 NOP 1
MOV R4,* aC 2 NOP 1
MOV R5,* aD 2 NOP 1
MOV R6,* aE 2 NOP 1
MOV R7,* aF 2 NOP 1
MOV @R0,A f6 1 NOP 1
MOV @R1,A f7 1 NOP 1
MOV @R0,#* 76 2 NOP 1
MOV @R1,#* 77 2 NOP 1
MOV @R0,* a6 2 NOP 1
MOV @R1,* a7 2 NOP 1
MOV *,A f5 2 NOP 1
MOV *,C 92 2 NOP 1
MOV *,R0 88 2 NOP 1
MOV *,R1 89 2 NOP 1
MOV *,R2 8A 2 NOP 1
MOV *,R3 8B 2 NOP 1
MOV *,R4 8C 2 NOP 1
MOV *,R5 8D 2 NOP 1
MOV *,R6 8E 2 NOP 1
MOV *,R7 8F 2 NOP 1
MOV *,@R0 86 2 NOP 1
MOV *,@R1 87 2 NOP 1
MOV *,#* 75 3 COMBINE 1
MOV *,* 85 3 CSWAP 1
MOVC A,@A+DPTR 93 1 NOP 1
MOVC A,@A+PC 83 1 NOP 1
MOVX A,@R0 e2 1 NOP 1
MOVX A,@R1 e3 1 NOP 1
MOVX A,@DPTR e0 1 NOP 1
MOVX @R0,A f2 1 NOP 1
MOVX @R1,A f3 1 NOP 1
MOVX @DPTR,A f0 1 NOP 1
MUL AB a4 1 NOP 1
NOP "" 00 1 NOP 1
ORL A,R0 48 1 NOP 1
ORL A,R1 49 1 NOP 1
ORL A,R2 4A 1 NOP 1
ORL A,R3 4B 1 NOP 1
ORL A,R4 4C 1 NOP 1
ORL A,R5 4D 1 NOP 1
ORL A,R6 4E 1 NOP 1
ORL A,R7 4F 1 NOP 1
ORL A,@R0 46 1 NOP 1
ORL A,@R1 47 1 NOP 1
ORL A,#* 44 2 NOP 1
ORL A,* 45 2 NOP 1
ORL C,/* a0 2 NOP 1
ORL C,* 72 2 NOP 1
ORL *,A 42 2 NOP 1
ORL *,#* 43 3 COMBINE 1
POP * d0 2 NOP 1
PUSH * c0 2 NOP 1
RET "" 22 1 NOP 1
RETI "" 32 1 NOP 1
RL A 23 1 NOP 1
RLC A 33 1 NOP 1
RR A 03 1 NOP 1
RRC A 13 1 NOP 1
SETB C d3 1 NOP 1
SETB * d2 2 NOP 1
SJMP * 80 2 R1 1
SUBB A,R0 98 1 NOP 1
SUBB A,R1 99 1 NOP 1
SUBB A,R2 9A 1 NOP 1
SUBB A,R3 9B 1 NOP 1
SUBB A,R4 9C 1 NOP 1
SUBB A,R5 9D 1 NOP 1
SUBB A,R6 9E 1 NOP 1
SUBB A,R7 9F 1 NOP 1
SUBB A,@R0 96 1 NOP 1
SUBB A,@R1 97 1 NOP 1
SUBB A,#* 94 2 NOP 1
SUBB A,* 95 2 NOP 1
SWAP A c4 1 NOP 1
XCH A,R0 c8 1 NOP 1
XCH A,R1 c9 1 NOP 1
XCH A,R2 cA 1 NOP 1
XCH A,R3 cB 1 NOP 1
XCH A,R4 cC 1 NOP 1
XCH A,R5 cD 1 NOP 1
XCH A,R6 cE 1 NOP 1
XCH A,R7 cF 1 NOP 1
XCH A,@R0 c6 1 NOP 1
XCH A,@R1 c7 1 NOP 1
XCH A,* c5 2 NOP 1
XCHD A,@R0 d6 1 NOP 1
XCHD A,@R1 d7 1 NOP 1
XRL A,R0 68 1 NOP 1
XRL A,R1 69 1 NOP 1
XRL A,R2 6A 1 NOP 1
XRL A,R3 6B 1 NOP 1
XRL A,R4 6C 1 NOP 1
XRL A,R5 6D 1 NOP 1
XRL A,R6 6E 1 NOP 1
XRL A,R7 6F 1 NOP 1
XRL A,@R0 66 1 NOP 1
XRL A,@R1 67 1 NOP 1
XRL A,#* 64 2 NOP 1
XRL A,* 65 2 NOP 1
XRL *,A 62 2 NOP 1
XRL *,#* 63 3 COMBINE 1

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"TASM 6502 Assembler. "
/****************************************************************************
/* $Id: tasm65.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 6502 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorported, June 1987.
/* Note that there are two classes of extended instructions beyond
/* the standard set. The classes are assigned bits as follows:
/* bit 0 = standard set
/* bit 1 = extended instructions for R65C02
/* bit 2 = extended instructions for R65C00/21
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
ADC #* 69 2 NOP 1
ADC (*,X) 61 2 NOP 1
ADC (*),Y 71 2 NOP 1
ADC (*) 72 2 NOP 2
ADC *,X 7D 3 ZP 1
ADC *,Y 79 3 NOP 1
ADC * 6D 3 ZP 1
AND #* 29 2 NOP 1
AND (*,X) 21 2 NOP 1
AND (*),Y 31 2 NOP 1
AND (*) 32 2 NOP 2
AND *,X 3D 3 ZP 1
AND *,Y 39 3 NOP 1
AND * 2D 3 ZP 1
ASL A 0A 1 NOP 1
ASL *,X 1E 3 ZP 1
ASL * 0E 3 ZP 1
BBR0 *,* 0f 3 CR 6
BBR1 *,* 1f 3 CR 6
BBR2 *,* 2f 3 CR 6
BBR3 *,* 3f 3 CR 6
BBR4 *,* 4f 3 CR 6
BBR5 *,* 5f 3 CR 6
BBR6 *,* 6f 3 CR 6
BBR7 *,* 7f 3 CR 6
BBS0 *,* 8f 3 CR 6
BBS1 *,* 9f 3 CR 6
BBS2 *,* af 3 CR 6
BBS3 *,* bf 3 CR 6
BBS4 *,* cf 3 CR 6
BBS5 *,* df 3 CR 6
BBS6 *,* ef 3 CR 6
BBS7 *,* ff 3 CR 6
BCC * 90 2 R1 1
BCS * B0 2 R1 1
BEQ * F0 2 R1 1
BMI * 30 2 R1 1
BNE * D0 2 R1 1
BPL * 10 2 R1 1
BRA * 80 2 R1 6
BVC * 50 2 R1 1
BVS * 70 2 R1 1
BIT #* 89 2 NOP 2
BIT *,X 3C 3 ZP 2
BIT * 2C 3 ZP 1
BRK "" 00 1 NOP 1
CLC "" 18 1 NOP 1
CLD "" D8 1 NOP 1
CLI "" 58 1 NOP 1
CLV "" B8 1 NOP 1
CMP #* C9 2 NOP 1
CMP (*,X) C1 2 NOP 1
CMP (*),Y D1 2 NOP 1
CMP (*) D2 2 NOP 2
CMP *,X DD 3 ZP 1
CMP *,Y D9 3 NOP 1
CMP * CD 3 ZP 1
CPX #* E0 2 NOP 1
CPX * EC 3 ZP 1
CPY #* C0 2 NOP 1
CPY * CC 3 ZP 1
DEC A 3A 1 NOP 2
DEC *,X DE 3 ZP 1
DEC * CE 3 ZP 1
DEX "" CA 1 NOP 1
DEY "" 88 1 NOP 1
EOR #* 49 2 NOP 1
EOR (*,X) 41 2 NOP 1
EOR (*),Y 51 2 NOP 1
EOR (*) 52 2 NOP 2
EOR *,X 5D 3 ZP 1
EOR *,Y 59 3 NOP 1
EOR * 4D 3 ZP 1
INC A 1A 1 NOP 2
INC *,X FE 3 ZP 1
INC * EE 3 ZP 1
INX "" E8 1 NOP 1
INY "" C8 1 NOP 1
JMP (*,X) 7C 3 NOP 2
JMP (*) 6C 3 NOP 1
JMP * 4C 3 NOP 1
JSR * 20 3 NOP 1
LDA #* A9 2 NOP 1
LDA (*,X) A1 2 NOP 1
LDA (*),Y B1 2 NOP 1
LDA (*) B2 2 NOP 2
LDA *,X BD 3 ZP 1
LDA *,Y B9 3 NOP 1
LDA * AD 3 ZP 1
LDX #* A2 2 NOP 1
LDX *,Y BE 3 ZP 1
LDX * AE 3 ZP 1
LDY #* A0 2 NOP 1
LDY *,X BC 3 ZP 1
LDY * AC 3 ZP 1
LSR A 4A 1 NOP 1
LSR *,X 5E 3 ZP 1
LSR * 4E 3 ZP 1
MUL "" 02 1 NOP 4 /* R65C00/21 only*/
NOP "" EA 1 NOP 1
ORA #* 09 2 NOP 1
ORA (*,X) 01 2 NOP 1
ORA (*),Y 11 2 NOP 1
ORA (*) 12 2 NOP 2
ORA *,X 1D 3 ZP 1
ORA *,Y 19 3 NOP 1
ORA * 0D 3 ZP 1
PHA "" 48 1 NOP 1
PHP "" 08 1 NOP 1
PHX "" DA 1 NOP 6
PHY "" 5A 1 NOP 6
PLA "" 68 1 NOP 1
PLP "" 28 1 NOP 1
PLX "" FA 1 NOP 6
PLY "" 7A 1 NOP 6
RMB0 * 07 2 NOP 6
RMB1 * 17 2 NOP 6
RMB2 * 27 2 NOP 6
RMB3 * 37 2 NOP 6
RMB4 * 47 2 NOP 6
RMB5 * 57 2 NOP 6
RMB6 * 67 2 NOP 6
RMB7 * 77 2 NOP 6
ROL A 2A 1 NOP 1
ROL *,X 3E 3 ZP 1
ROL * 2E 3 ZP 1
ROR A 6A 1 NOP 1
ROR *,X 7E 3 ZP 1
ROR * 6E 3 ZP 1
RTI "" 40 1 NOP 1
RTS "" 60 1 NOP 1
SBC #* E9 2 NOP 1
SBC (*,X) E1 2 NOP 1
SBC (*),Y F1 2 NOP 1
SBC (*) F2 2 NOP 2
SBC *,X FD 3 ZP 1
SBC *,Y F9 3 NOP 1
SBC * ED 3 ZP 1
SEC "" 38 1 NOP 1
SED "" F8 1 NOP 1
SEI "" 78 1 NOP 1
SMB0 * 87 2 NOP 6
SMB1 * 97 2 NOP 6
SMB2 * a7 2 NOP 6
SMB3 * b7 2 NOP 6
SMB4 * c7 2 NOP 6
SMB5 * d7 2 NOP 6
SMB6 * e7 2 NOP 6
SMB7 * f7 2 NOP 6
STA (*,X) 81 2 NOP 1
STA (*),Y 91 2 NOP 1
STA (*) 92 2 NOP 2
STA *,X 9D 3 ZP 1
STA *,Y 99 3 NOP 1
STA * 8D 3 ZP 1
STX *,Y 96 2 ZP 1
STX * 8E 3 ZP 1
STY *,X 94 2 NOP 1
STY * 8C 3 ZP 1
STZ *,X 9e 3 ZP 2
STZ * 9c 3 ZP 2
TAX "" AA 1 NOP 1
TAY "" A8 1 NOP 1
TRB * 1c 3 ZP 2
TSB * 0c 3 ZP 2
TSX "" BA 1 NOP 1
TXA "" 8A 1 NOP 1
TXS "" 9A 1 NOP 1
TYA "" 98 1 NOP 1

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"TASM 6800-6811 Assembler"
/****************************************************************************
/* $Id: tasm68.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* Originally submitted by Richard P. White, June 4,1989 */
/* Corrected and enhanced by T.N. Anderson, STI */
/* Enhanced for the 68HC11 by George Blat, Nov 3, 1990
/* Class bits defined as follows:
/*
/* bit 0 for 6800
/* bit 1 for 6801/6803
/* bit 2 for 68HC11
/*
/* Note that TASM deviates from motorola syntax for BCLR, BSET,
/* BRCLR, and BRSET instructions. TASM requires commas between
/* each arg. Motorola requires white space before the make and
/* label args.
.MSFIRST
ABA "" 1B 1 NOP 1
ABX "" 3A 1 NOP 2
ABY "" 183A 2 NOP 4
ADCA #* 89 2 NOP 1
ADCA *,Y 18A9 3 NOP 4
ADCA *,X A9 2 NOP 1
ADCA * B9 3 MZERO 1
ADCB #* C9 2 NOP 1
ADCB *,Y 18E9 3 NOP 4
ADCB *,X E9 2 NOP 1
ADCB * F9 3 MZERO 1
ADDA #* 8B 2 NOP 1
ADDA *,Y 18AB 3 NOP 4
ADDA *,X AB 2 NOP 1
ADDA * BB 3 MZERO 1
ADDB #* CB 2 NOP 1
ADDB *,Y 18EB 3 NOP 4
ADDB *,X EB 2 NOP 1
ADDB * FB 3 MZERO 1
ADDD #* C3 3 SWAP 2
ADDD *,Y 18E3 3 NOP 4
ADDD *,X E3 2 NOP 2
ADDD * F3 3 MZERO 2
ANDA #* 84 2 NOP 1
ANDA *,Y 18A4 3 NOP 4
ANDA *,X A4 2 NOP 1
ANDA * B4 3 MZERO 1
ANDB #* C4 2 NOP 1
ANDB *,Y 18E4 3 NOP 4
ANDB *,X E4 2 NOP 1
ANDB * F4 3 MZERO 1
ASL *,Y 1868 3 NOP 4
ASL *,X 68 2 NOP 1
ASL * 78 3 SWAP 1
ASLA "" 48 1 NOP 1
ASLB "" 58 1 NOP 1
ASLD "" 05 1 NOP 2
ASR *,Y 1867 3 NOP 4
ASR *,X 67 2 NOP 1
ASR * 77 3 SWAP 1
ASRA "" 47 1 NOP 1
ASRB "" 57 1 NOP 1
BCC * 24 2 R1 1
BCLR *,X,* 1D 3 COMB 4
BCLR *,Y,* 181D 4 COMB 4
BCLR *,#* 15 3 COMB 4 /* allow # since mask is immediate data
BCLR *,* 15 3 COMB 4
BCS * 25 2 R1 1
BEQ * 27 2 R1 1
BGE * 2C 2 R1 1
BGT * 2E 2 R1 1
BHI * 22 2 R1 1
BHS * 24 2 R1 1
BITA #* 85 2 NOP 1
BITA *,Y 18A5 3 NOP 4
BITA *,X A5 2 NOP 1
BITA * B5 3 MZERO 1
BITB #* C5 2 NOP 1
BITB *,Y 18E5 3 NOP 4
BITB *,X E5 2 NOP 1
BITB * F5 3 MZERO 1
BLE * 2F 2 R1 1
BLO * 25 2 R1 1
BLS * 23 2 R1 1
BLT * 2D 2 R1 1
BMI * 2B 2 R1 1
BNE * 26 2 R1 1
BPL * 2A 2 R1 1
BRA * 20 2 R1 1
BRCLR *,X,*,* 1F 4 3REL 4
BRCLR *,Y,*,* 181F 5 3REL 4
BRCLR *,*,* 13 4 3REL 4
BRN * 21 2 R1 2 /* NOT SURE ABOUT 6803 */
BRSET *,X,*,* 1E 4 3REL 4
BRSET *,Y,*,* 181E 5 3REL 4
BRSET *,*,* 12 4 3REL 4
BSET *,X,* 1C 3 COMB 4
BSET *,Y,* 181C 4 COMB 4
BSET *,#* 14 3 COMB 4 /* allow #
BSET *,* 14 3 COMB 4
BSR * 8D 2 R1 1
BVC * 28 2 R1 1
BVS * 29 2 R1 1
CBA "" 11 1 NOP 1
CLC "" 0C 1 NOP 1
CLI "" 0E 1 NOP 1
CLR *,Y 186F 3 NOP 4
CLR *,X 6F 2 NOP 1
CLR * 7F 3 SWAP 1
CLRA "" 4F 1 NOP 1
CLRB "" 5F 1 NOP 1
CLV "" 0A 1 NOP 1
CMPA #* 81 2 NOP 1
CMPA *,X A1 2 NOP 1
CMPA *,Y 18A1 3 NOP 4
CMPA * B1 3 MZERO 1
CMPB #* C1 2 NOP 1
CMPB *,Y 18E1 3 NOP 4
CMPB *,X E1 2 NOP 1
CMPB * F1 3 MZERO 1
CMPD #* 1A83 4 SWAP 4 /* alias for CPD */
CMPD *,X 1AA3 3 NOP 4
CMPD *,Y CDA3 3 NOP 4
CMPD * 1AB3 4 MZERO 4
COM *,X 63 2 NOP 1
COM *,Y 1863 3 NOP 4
COM * 73 3 SWAP 1
COMA "" 43 1 NOP 1
COMB "" 53 1 NOP 1
CPD #* 1A83 4 SWAP 4
CPD *,X 1AA3 3 NOP 4
CPD *,Y CDA3 3 NOP 4
CPD * 1AB3 4 MZERO 4
CPX #* 8C 3 SWAP 1
CPX *,X AC 2 NOP 1
CPX *,Y CDAC 3 NOP 4
CPX * BC 3 MZERO 1
CPY #* 188C 4 SWAP 4
CPY *,Y 18AC 3 NOP 4
CPY *,X 1AAC 3 NOP 4
CPY * 18BC 4 MZERO 4
DAA "" 19 1 NOP 1
DEC *,Y 186A 3 NOP 4
DEC *,X 6A 2 NOP 1
DEC * 7A 3 SWAP 1
DECA "" 4A 1 NOP 1
DECB "" 5A 1 NOP 1
DES "" 34 1 NOP 1
DEX "" 09 1 NOP 1
DEY "" 1809 2 NOP 4
EORA #* 88 2 NOP 1
EORA *,Y 18A8 3 NOP 4
EORA *,X A8 2 NOP 1
EORA * B8 3 MZERO 1
EORB #* C8 2 NOP 1
EORB *,Y 18E8 3 NOP 4
EORB *,X E8 2 NOP 1
EORB * F8 3 MZERO 1
FDIV "" 03 1 NOP 4
IDIV "" 02 1 NOP 4
INC *,Y 186C 3 NOP 4
INC *,X 6C 2 NOP 1
INC * 7C 3 SWAP 1
INCA "" 4C 1 NOP 1
INCB "" 5C 1 NOP 1
INS "" 31 1 NOP 1
INX "" 08 1 NOP 1
INY "" 1808 2 NOP 4
JMP *,Y 186E 3 NOP 4
JMP *,X 6E 2 NOP 1
JMP * 7E 3 SWAP 1
JSR *,Y 18AD 3 NOP 4
JSR *,X AD 2 NOP 1
JSR * BD 3 MZERO 1
LDAA #* 86 2 NOP 1
LDAA *,Y 18A6 3 NOP 4
LDAA *,X A6 2 NOP 1
LDAA >* B6 3 SWAP 1 /* Force EXT mode */
LDAA * B6 3 MZERO 1
LDAB #* C6 2 NOP 1
LDAB *,Y 18E6 3 NOP 4
LDAB *,X E6 2 NOP 1
LDAB >* F6 3 SWAP 1 /* Force EXT mode */
LDAB * F6 3 MZERO 1
LDD #* CC 3 SWAP 2
LDD *,Y 18EC 3 NOP 4
LDD *,X EC 2 NOP 2
LDD >* FC 3 SWAP 2 /* Force EXT mode */
LDD * FC 3 MZERO 2
LDS #* 8E 3 SWAP 1
LDS *,Y 18AE 3 NOP 4
LDS *,X AE 2 NOP 1
LDS >* BE 3 SWAP 1 /* Force EXT mode */
LDS * BE 3 MZERO 1
LDX #* CE 3 SWAP 1
LDX *,X EE 2 NOP 1
LDX *,Y CDEE 3 NOP 4
LDX >* FE 3 SWAP 1 /* Force EXT mode */
LDX * FE 3 MZERO 1
LDY #* 18CE 4 SWAP 4
LDY *,Y 18EE 3 NOP 4
LDY *,X 1AEE 3 NOP 4
LDY >* 18FE 4 SWAP 4 /* Force EXT mode */
LDY * 18FE 4 MZERO 4
LSL *,Y 1868 3 NOP 4
LSL *,X 68 2 NOP 1 /*SAME AS ASL */
LSL * 78 3 SWAP 1
LSLA "" 48 1 NOP 1
LSLB "" 58 1 NOP 1
LSLD "" 05 1 NOP 2
LSR *,Y 1864 3 NOP 4
LSR *,X 64 2 NOP 1
LSR * 74 3 SWAP 1
LSRA "" 44 1 NOP 1
LSRB "" 54 1 NOP 1
LSRD "" 04 1 NOP 2
MUL "" 3D 1 NOP 2
NEG *,Y 1860 3 NOP 4
NEG *,X 60 2 NOP 1
NEG * 70 3 SWAP 1
NEGA "" 40 1 NOP 1
NEGB "" 50 1 NOP 1
NOP "" 01 1 NOP 1
ORAA #* 8A 2 NOP 1
ORAA *,Y 18AA 3 NOP 4
ORAA *,X AA 2 NOP 1
ORAA * BA 3 MZERO 1
ORAB #* CA 2 NOP 1
ORAB *,Y 18EA 3 NOP 4
ORAB *,X EA 2 NOP 1
ORAB * FA 3 MZERO 1
PSHA "" 36 1 NOP 1
PSHB "" 37 1 NOP 1
PSHX "" 3C 1 NOP 2
PSHY "" 183C 2 NOP 4
PULA "" 32 1 NOP 1
PULB "" 33 1 NOP 1
PULX "" 38 1 NOP 2
PULY "" 1838 2 NOP 4
ROL *,Y 1869 3 NOP 4
ROL *,X 69 2 NOP 1
ROL * 79 3 SWAP 1
ROLA "" 49 1 NOP 1
ROLB "" 59 1 NOP 1
ROR *,Y 1866 3 NOP 4
ROR *,X 66 2 NOP 1
ROR * 76 3 SWAP 1
RORA "" 46 1 NOP 1
RORB "" 56 1 NOP 1
RTI "" 3B 1 NOP 1
RTS "" 39 1 NOP 1
SBA "" 10 1 NOP 1
SBCA #* 82 2 NOP 1
SBCA *,Y 18A2 3 NOP 4
SBCA *,X A2 2 NOP 1
SBCA * B2 3 MZERO 1
SBCB #* C2 2 NOP 1
SBCB *,Y 18E2 3 NOP 4
SBCB *,X E2 2 NOP 1
SBCB * F2 3 MZERO 1
SEC "" 0D 1 NOP 1
SEI "" 0F 1 NOP 1
SEV "" 0B 1 NOP 1
STAA *,Y 18A7 3 NOP 4
STAA *,X A7 2 NOP 1
STAA >* B7 3 SWAP 1 /* Force EXT mode */
STAA * B7 3 MZERO 1
STAB *,Y 18E7 3 NOP 4
STAB *,X E7 2 NOP 1
STAB >* F7 3 SWAP 1 /* Force EXT mode */
STAB * F7 3 MZERO 1
STD *,Y 18ED 3 NOP 4
STD *,X ED 2 NOP 2
STD >* FD 3 SWAP 2 /* Force EXT mode */
STD * FD 3 MZERO 2
STOP "" CF 1 NOP 1
STS *,X AF 2 NOP 1
STS *,Y 18AF 3 NOP 4
STS >* BF 3 SWAP 1 /* Force EXT mode */
STS * BF 3 MZERO 1
STX *,X EF 2 NOP 1
STX *,Y CDEF 3 NOP 4
STX >* FF 3 SWAP 1 /* Force EXT mode */
STX * FF 3 MZERO 1
STY *,Y 18EF 3 NOP 4
STY *,X 1AEF 3 NOP 4
STY >* 18FF 4 SWAP 4 /* Force EXT mode */
STY * 18FF 4 MZERO 4
SUBA #* 80 2 NOP 1
SUBA *,Y 18A0 3 NOP 4
SUBA *,X A0 2 NOP 1
SUBA * B0 3 MZERO 1
SUBB #* C0 2 NOP 1
SUBB *,Y 18E0 3 NOP 4
SUBB *,X E0 2 NOP 1
SUBB * F0 3 MZERO 1
SUBD #* 83 3 SWAP 2
SUBD *,Y 18A3 3 NOP 4
SUBD *,X A3 2 NOP 2
SUBD * B3 3 MZERO 2
SWI "" 3F 1 NOP 1
TAB "" 16 1 NOP 1
TAP "" 06 1 NOP 1
TBA "" 17 1 NOP 1
TEST "" 00 1 NOP 1
TPA "" 07 1 NOP 1
TST *,Y 186D 3 NOP 4
TST *,X 6D 2 NOP 1
TST * 7D 3 SWAP 1
TSTA "" 4D 1 NOP 1
TSTB "" 5D 1 NOP 1
TSX "" 30 1 NOP 1
TSY "" 1830 2 NOP 4
TXS "" 35 1 NOP 1
TYS "" 1835 2 NOP 4
WAI "" 3E 1 NOP 1
XGDX "" 8F 1 NOP 4
XGDY "" 188F 2 NOP 4
/* That's all folks */

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"TASM 7000 Assembler. "
/****************************************************************************
/* $Id: tasm70.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* Table for TMS7000 micros
/* Note that the table does not require the 'Rnn' nomenclature
/* for reference of locations in the register file. Any expression
/* will do, the value of which indicates the register. This is more
/* flexible then making an entry like "ADC R*,A".
/*
/* TASM has trouble with the MOVD +(B),+ instruction so
/* we convert it to MOVD +[B],+
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT OR */
/*-------------------------------------------*/
.ALTWILD+
ADC B,A 69 1 NOP 1
ADC %+,A 29 2 NOP 1
ADC %+,B 59 2 NOP 1
ADC %+,+ 79 3 COMB 1
ADC +,A 19 2 NOP 1
ADC +,B 39 2 NOP 1
ADC +,+ 49 3 COMB 1
ADD B,A 68 1 NOP 1
ADD %+,A 28 2 NOP 1
ADD %+,B 58 2 NOP 1
ADD %+,+ 78 3 COMB 1
ADD +,A 18 2 NOP 1
ADD +,B 38 2 NOP 1
ADD +,+ 48 3 COMB 1
AND B,A 63 1 NOP 1
AND %+,A 23 2 NOP 1
AND %+,B 53 2 NOP 1
AND %+,+ 73 3 COMB 1
AND +,A 13 2 NOP 1
AND +,B 33 2 NOP 1
AND +,+ 43 3 COMB 1
ANDP A,+ 83 2 NOP 1
ANDP B,+ 93 2 NOP 1
ANDP %+,+ A3 3 COMB 1
BTJO B,A,+ 66 2 R1 1
BTJO %+,A,+ 26 3 CREL 1
BTJO %+,B,+ 56 3 CREL 1
BTJO %+,+,+ 76 4 3REL 1
BTJO +,A,+ 16 3 CREL 1
BTJO +,B,+ 36 3 CREL 1
BTJO +,+,+ 46 4 3REL 1
BTJOP A,+,+ 86 3 CREL 1
BTJOP B,+,+ 96 3 CREL 1
BTJOP %+,+,+ A6 4 3REL 1
BTJZ B,A,+ 67 2 R1 1
BTJZ %+,A,+ 27 3 CREL 1
BTJZ %+,B,+ 57 3 CREL 1
BTJZ %+,+,+ 77 4 3REL 1
BTJZ +,A,+ 17 3 CREL 1
BTJZ +,B,+ 37 3 CREL 1
BTJZ +,+,+ 47 4 3REL 1
BTJZP A,+,+ 87 3 CREL 1
BTJZP B,+,+ 97 3 CREL 1
BTJZP %+,+,+ A7 4 3REL 1
BR @+(B) AC 3 SWAP 1
BR @+[B] AC 3 SWAP 1
BR @+ 8C 3 SWAP 1
BR *+ 9C 2 NOP 1
CALL @+(B) AE 3 SWAP 1
CALL @+[B] AE 3 SWAP 1
CALL @+ 8E 3 SWAP 1
CALL *+ 9E 2 NOP 1
CLR A B5 1 NOP 1
CLR B C5 1 NOP 1
CLR + D5 2 NOP 1
CLRC "" B0 1 NOP 1
CMP B,A 6D 1 NOP 1
CMP %+,A 2D 2 NOP 1
CMP %+,B 5D 2 NOP 1
CMP %+,+ 7D 3 COMB 1
CMP +,A 1D 2 NOP 1
CMP +,B 3D 2 NOP 1
CMP +,+ 4D 3 COMB 1
CMPA @+(B) AD 3 SWAP 1
CMPA @+[B] AD 3 SWAP 1
CMPA @+ 8D 3 SWAP 1
CMPA *+ 9D 2 NOP 1
DAC B,A 6E 1 NOP 1
DAC %+,A 2E 2 NOP 1
DAC %+,B 5E 2 NOP 1
DAC %+,+ 7E 3 COMB 1
DAC +,A 1E 2 NOP 1
DAC +,B 3E 2 NOP 1
DAC +,+ 4E 3 COMB 1
DEC A B2 1 NOP 1
DEC B C2 1 NOP 1
DEC + D2 2 NOP 1
DECD A BB 1 NOP 1
DECD B CB 1 NOP 1
DECD + DB 2 NOP 1
DINT "" 06 1 NOP 1
DJNZ A,+ BA 2 R1 1
DJNZ B,+ CA 2 R1 1
DJNZ +,+ DA 3 CREL 1
DSB B,A 6F 1 NOP 1
DSB %+,A 2F 2 NOP 1
DSB %+,B 5F 2 NOP 1
DSB %+,+ 7F 3 COMB 1
DSB +,A 1F 2 NOP 1
DSB +,B 3F 2 NOP 1
DSB +,+ 4F 3 COMB 1
EINT "" 05 1 NOP 1
IDLE "" 01 1 NOP 1
INC A B3 1 NOP 1
INC B C3 1 NOP 1
INC + D3 2 NOP 1
INV A B4 1 NOP 1
INV B C4 1 NOP 1
INV + D4 2 NOP 1
JMP + E0 2 R1 1
JC + E3 2 R1 1
JEQ + E2 2 R1 1
JGE + E5 2 R1 1
JGT + E4 2 R1 1
JHS + E3 2 R1 1
JL + E7 2 R1 1
JN + E1 2 R1 1 /+ ??
JNC + E7 2 R1 1
JNE + E6 2 R1 1
JNZ + E6 2 R1 1
JP + E4 2 R1 1
JPZ + E5 2 R1 1
JZ + E2 2 R1 1
LDA @+(B) AA 3 SWAP 1
LDA @+[B] AA 3 SWAP 1
LDA @+ 8A 3 SWAP 1
LDA *+ 9A 2 NOP 1
LDSP "" 0D 1 NOP 1
MOV A,B C0 1 NOP 1
MOV B,A 62 1 NOP 1
MOV A,+ D0 2 NOP 1
MOV B,+ D1 2 NOP 1
MOV %+,A 22 2 NOP 1
MOV %+,B 52 2 NOP 1
MOV %+,+ 72 3 COMB 1
MOV +,A 12 2 NOP 1
MOV +,B 32 2 NOP 1
MOV +,+ 42 3 COMB 1
MOVD %+[B],+ A8 4 CSWAP 1
MOVD %+,+ 88 4 CSWAP 1
MOVD +,+ 98 3 COMB 1
MOVP A,+ 82 2 NOP 1
MOVP B,+ 92 2 NOP 1
MOVP %+,+ A2 3 COMB 1
MOVP +,A 80 2 NOP 1
MOVP +,B 91 2 NOP 1
MPY B,A 6C 1 NOP 1
MPY %+,A 2C 2 NOP 1
MPY %+,B 5C 2 NOP 1
MPY %+,+ 7C 3 COMB 1
MPY +,A 1C 2 NOP 1
MPY +,B 3C 2 NOP 1
MPY +,+ 4C 3 COMB 1
NOP "" 00 1 NOP 1
OR B,A 64 1 NOP 1
OR %+,A 24 2 NOP 1
OR %+,B 54 2 NOP 1
OR %+,+ 74 3 COMB 1
OR +,A 14 2 NOP 1
OR +,B 34 2 NOP 1
OR +,+ 44 3 COMB 1
ORP A,+ 84 2 NOP 1
ORP B,+ 94 2 NOP 1
ORP %+,+ A4 3 COMB 1
POP A B9 1 NOP 1
POP B C9 1 NOP 1
POP ST 08 1 NOP 1
POP + D9 2 NOP 1
POPST "" 08 1 NOP 1
PUSH A B8 1 NOP 1
PUSH B C8 1 NOP 1
PUSH ST 0E 1 NOP 1
PUSH + D8 2 NOP 1
PUSHST "" 0E 1 NOP 1
RETI "" 0B 1 NOP 1
RETS "" 0A 1 NOP 1
RL A BE 1 NOP 1
RL B CE 1 NOP 1
RL + DE 2 NOP 1
RLC A BF 1 NOP 1
RLC B CF 1 NOP 1
RLC + DF 2 NOP 1
RR A BC 1 NOP 1
RR B CC 1 NOP 1
RR + DC 2 NOP 1
RRC A BD 1 NOP 1
RRC B CD 1 NOP 1
RRC + DD 2 NOP 1
SBB B,A 6B 1 NOP 1
SBB %+,A 2B 2 NOP 1
SBB %+,B 5B 2 NOP 1
SBB %+,+ 7B 3 COMB 1
SBB +,A 1B 2 NOP 1
SBB +,B 3B 2 NOP 1
SBB +,+ 4B 3 COMB 1
SETC "" 07 1 NOP 1
STA @+(B) AB 3 SWAP 1
STA @+[B] AB 3 SWAP 1
STA @+ 8B 3 SWAP 1
STA *+ 9B 2 NOP 1
STSP "" 09 1 NOP 1
SUB B,A 6A 1 NOP 1
SUB %+,A 2A 2 NOP 1
SUB %+,B 5A 2 NOP 1
SUB %+,+ 7A 3 COMB 1
SUB +,A 1A 2 NOP 1
SUB +,B 3A 2 NOP 1
SUB +,+ 4A 3 COMB 1
SWAP A B7 1 NOP 1
SWAP B C7 1 NOP 1
SWAP + D7 2 NOP 1
TRAP + FF 1 SUB 1
TST A B0 1 NOP 1
TSTA "" B0 1 NOP 1
TST B C1 1 NOP 1
TSTB "" C1 1 NOP 1
XCHB A B6 1 NOP 1
XCHB + D6 2 NOP 1
XOR B,A 65 1 NOP 1
XOR %+,A 25 2 NOP 1
XOR %+,B 55 2 NOP 1
XOR %+,+ 75 3 COMB 1
XOR +,A 15 2 NOP 1
XOR +,B 35 2 NOP 1
XOR +,+ 45 3 COMB 1
XORP A,+ 85 2 NOP 1
XORP B,+ 95 2 NOP 1
XORP %+,+ A5 3 COMB 1

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"TASM Z80 Assembler. "
/****************************************************************************
/* $Id: tasm80.tab 1.2 1998/02/28 14:31:22 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the Z80 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/* This table authored and submitted by Carl A. Wall, VE3APY.
/*
/* Class bits assigned as follows:
/* Bit-0 = Z80 (base instruction set)
/* Bit-1 = HD64180 (extended instructions)
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */
/*-------------------------------------------*/
ADC A,(HL) 8E 1 NOP 1
ADC A,(IX*) 8EDD 3 ZIX 1
ADC A,(IY*) 8EFD 3 ZIX 1
ADC A,A 8F 1 NOP 1
ADC A,B 88 1 NOP 1
ADC A,C 89 1 NOP 1
ADC A,D 8A 1 NOP 1
ADC A,E 8B 1 NOP 1
ADC A,H 8C 1 NOP 1
ADC A,L 8D 1 NOP 1
ADC A,* CE 2 NOP 1
ADC HL,BC 4AED 2 NOP 1
ADC HL,DE 5AED 2 NOP 1
ADC HL,HL 6AED 2 NOP 1
ADC HL,SP 7AED 2 NOP 1
ADD A,(HL) 86 1 NOP 1
ADD A,(IX*) 86DD 3 ZIX 1
ADD A,(IY*) 86FD 3 ZIX 1
ADD A,A 87 1 NOP 1
ADD A,B 80 1 NOP 1
ADD A,C 81 1 NOP 1
ADD A,D 82 1 NOP 1
ADD A,E 83 1 NOP 1
ADD A,H 84 1 NOP 1
ADD A,L 85 1 NOP 1
ADD A,* C6 2 NOP 1
ADD HL,BC 09 1 NOP 1
ADD HL,DE 19 1 NOP 1
ADD HL,HL 29 1 NOP 1
ADD HL,SP 39 1 NOP 1
ADD IX,BC 09DD 2 NOP 1
ADD IX,DE 19DD 2 NOP 1
ADD IX,IX 29DD 2 NOP 1
ADD IX,SP 39DD 2 NOP 1
ADD IY,BC 09FD 2 NOP 1
ADD IY,DE 19FD 2 NOP 1
ADD IY,IY 29FD 2 NOP 1
ADD IY,SP 39FD 2 NOP 1
AND (HL) A6 1 NOP 1
AND (IX*) A6DD 3 ZIX 1
AND (IY*) A6FD 3 ZIX 1
AND A A7 1 NOP 1
AND B A0 1 NOP 1
AND C A1 1 NOP 1
AND D A2 1 NOP 1
AND E A3 1 NOP 1
AND H A4 1 NOP 1
AND L A5 1 NOP 1
AND * E6 2 NOP 1
BIT *,(HL) 46CB 2 ZBIT 1
BIT *,(IX*) CBDD 4 ZBIT 1 0 4600
BIT *,(IY*) CBFD 4 ZBIT 1 0 4600
BIT *,A 47CB 2 ZBIT 1
BIT *,B 40CB 2 ZBIT 1
BIT *,C 41CB 2 ZBIT 1
BIT *,D 42CB 2 ZBIT 1
BIT *,E 43CB 2 ZBIT 1
BIT *,H 44CB 2 ZBIT 1
BIT *,L 45CB 2 ZBIT 1
CALL C,* DC 3 NOP 1
CALL M,* FC 3 NOP 1
CALL NC,* D4 3 NOP 1
CALL NZ,* C4 3 NOP 1
CALL P,* F4 3 NOP 1
CALL PE,* EC 3 NOP 1
CALL PO,* E4 3 NOP 1
CALL Z,* CC 3 NOP 1
CALL * CD 3 NOP 1
CCF "" 3F 1 NOP 1
CP (HL) BE 1 NOP 1
CP (IX*) BEDD 3 ZIX 1
CP (IY*) BEFD 3 ZIX 1
CP A BF 1 NOP 1
CP B B8 1 NOP 1
CP C B9 1 NOP 1
CP D BA 1 NOP 1
CP E BB 1 NOP 1
CP H BC 1 NOP 1
CP L BD 1 NOP 1
CP * FE 2 NOP 1
CPD "" A9ED 2 NOP 1
CPDR "" B9ED 2 NOP 1
CPIR "" B1ED 2 NOP 1
CPI "" A1ED 2 NOP 1
CPL "" 2F 1 NOP 1
DAA "" 27 1 NOP 1
DEC (HL) 35 1 NOP 1
DEC (IX*) 35DD 3 ZIX 1
DEC (IY*) 35FD 3 ZIX 1
DEC A 3D 1 NOP 1
DEC B 05 1 NOP 1
DEC BC 0B 1 NOP 1
DEC C 0D 1 NOP 1
DEC D 15 1 NOP 1
DEC DE 1B 1 NOP 1
DEC E 1D 1 NOP 1
DEC H 25 1 NOP 1
DEC HL 2B 1 NOP 1
DEC IX 2BDD 2 NOP 1
DEC IY 2BFD 2 NOP 1
DEC L 2D 1 NOP 1
DEC SP 3B 1 NOP 1
DI "" F3 1 NOP 1
DJNZ * 10 2 R1 1
EI "" FB 1 NOP 1
EX (SP),HL E3 1 NOP 1
EX (SP),IX E3DD 2 NOP 1
EX (SP),IY E3FD 2 NOP 1
EX AF,AF' 08 1 NOP 1
EX DE,HL EB 1 NOP 1
EXX "" D9 1 NOP 1
HALT "" 76 1 NOP 1
IM 0 46ED 2 NOP 1
IM 1 56ED 2 NOP 1
IM 2 5EED 2 NOP 1
/* Alternate form of above
IM0 46ED 2 NOP 1
IM1 56ED 2 NOP 1
IM2 5EED 2 NOP 1
IN A,(C) 78ED 2 NOP 1
IN B,(C) 40ED 2 NOP 1
IN C,(C) 48ED 2 NOP 1
IN D,(C) 50ED 2 NOP 1
IN E,(C) 58ED 2 NOP 1
IN H,(C) 60ED 2 NOP 1
IN L,(C) 68ED 2 NOP 1
IN A,(*) DB 2 NOP 1
IN0 A,(*) 38ED 3 NOP 2
IN0 B,(*) 00ED 3 NOP 2
IN0 C,(*) 08ED 3 NOP 2
IN0 D,(*) 10ED 3 NOP 2
IN0 E,(*) 18ED 3 NOP 2
IN0 H,(*) 20ED 3 NOP 2
IN0 L,(*) 28ED 3 NOP 2
INC (HL) 34 1 NOP 1
INC (IX*) 34DD 3 ZIX 1
INC (IY*) 34FD 3 ZIX 1
INC A 3C 1 NOP 1
INC B 04 1 NOP 1
INC BC 03 1 NOP 1
INC C 0C 1 NOP 1
INC D 14 1 NOP 1
INC DE 13 1 NOP 1
INC E 1C 1 NOP 1
INC H 24 1 NOP 1
INC HL 23 1 NOP 1
INC IX 23DD 2 NOP 1
INC IY 23FD 2 NOP 1
INC L 2C 1 NOP 1
INC SP 33 1 NOP 1
IND "" AAED 2 NOP 1
INDR "" BAED 2 NOP 1
INI "" A2ED 2 NOP 1
INIR "" B2ED 2 NOP 1
JP (HL) E9 1 NOP 1
JP (IX) E9DD 2 NOP 1
JP (IY) E9FD 2 NOP 1
JP C,* DA 3 NOP 1
JP M,* FA 3 NOP 1
JP NC,* D2 3 NOP 1
JP NZ,* C2 3 NOP 1
JP P,* F2 3 NOP 1
JP PE,* EA 3 NOP 1
JP PO,* E2 3 NOP 1
JP Z,* CA 3 NOP 1
JP * C3 3 NOP 1
JR C,* 38 2 R1 1
JR NC,* 30 2 R1 1
JR NZ,* 20 2 R1 1
JR Z,* 28 2 R1 1
JR * 18 2 R1 1
LD (BC),A 02 1 NOP 1
LD (DE),A 12 1 NOP 1
LD (HL),A 77 1 NOP 1
LD (HL),B 70 1 NOP 1
LD (HL),C 71 1 NOP 1
LD (HL),D 72 1 NOP 1
LD (HL),E 73 1 NOP 1
LD (HL),H 74 1 NOP 1
LD (HL),L 75 1 NOP 1
LD (HL),* 36 2 NOP 1
LD (IX*),A 77DD 3 ZIX 1
LD (IX*),B 70DD 3 ZIX 1
LD (IX*),C 71DD 3 ZIX 1
LD (IX*),D 72DD 3 ZIX 1
LD (IX*),E 73DD 3 ZIX 1
LD (IX*),H 74DD 3 ZIX 1
LD (IX*),L 75DD 3 ZIX 1
LD (IX*),* 36DD 4 ZIX 1
LD (IY*),A 77FD 3 ZIX 1
LD (IY*),B 70FD 3 ZIX 1
LD (IY*),C 71FD 3 ZIX 1
LD (IY*),D 72FD 3 ZIX 1
LD (IY*),E 73FD 3 ZIX 1
LD (IY*),H 74FD 3 ZIX 1
LD (IY*),L 75FD 3 ZIX 1
LD (IY*),* 36FD 4 ZIX 1
LD (*),A 32 3 NOP 1
LD (*),BC 43ED 4 NOP 1
LD (*),DE 53ED 4 NOP 1
LD (*),HL 22 3 NOP 1
LD (*),IX 22DD 4 NOP 1
LD (*),IY 22FD 4 NOP 1
LD (*),SP 73ED 4 NOP 1
LD A,(BC) 0A 1 NOP 1
LD A,(DE) 1A 1 NOP 1
LD A,(HL) 7E 1 NOP 1
LD A,(IX*) 7EDD 3 ZIX 1
LD A,(IY*) 7EFD 3 ZIX 1
LD A,A 7F 1 NOP 1
LD A,B 78 1 NOP 1
LD A,C 79 1 NOP 1
LD A,D 7A 1 NOP 1
LD A,E 7B 1 NOP 1
LD A,H 7C 1 NOP 1
LD A,I 57ED 2 NOP 1
LD A,L 7D 1 NOP 1
LD A,R 5FED 2 NOP 1
LD A,(*) 3A 3 NOP 1
LD A,* 3E 2 NOP 1
LD B,(HL) 46 1 NOP 1
LD B,(IX*) 46DD 3 ZIX 1
LD B,(IY*) 46FD 3 ZIX 1
LD B,A 47 1 NOP 1
LD B,B 40 1 NOP 1
LD B,C 41 1 NOP 1
LD B,D 42 1 NOP 1
LD B,E 43 1 NOP 1
LD B,H 44 1 NOP 1
LD B,L 45 1 NOP 1
LD B,* 06 2 NOP 1
LD BC,(*) 4BED 4 NOP 1
LD BC,* 01 3 NOP 1
LD C,(HL) 4E 1 NOP 1
LD C,(IX*) 4EDD 3 ZIX 1
LD C,(IY*) 4EFD 3 ZIX 1
LD C,A 4F 1 NOP 1
LD C,B 48 1 NOP 1
LD C,C 49 1 NOP 1
LD C,D 4A 1 NOP 1
LD C,E 4B 1 NOP 1
LD C,H 4C 1 NOP 1
LD C,L 4D 1 NOP 1
LD C,* 0E 2 NOP 1
LD D,(HL) 56 1 NOP 1
LD D,(IX*) 56DD 3 ZIX 1
LD D,(IY*) 56FD 3 ZIX 1
LD D,A 57 1 NOP 1
LD D,B 50 1 NOP 1
LD D,C 51 1 NOP 1
LD D,D 52 1 NOP 1
LD D,E 53 1 NOP 1
LD D,H 54 1 NOP 1
LD D,L 55 1 NOP 1
LD D,* 16 2 NOP 1
LD DE,(*) 5BED 4 NOP 1
LD DE,* 11 3 NOP 1
LD E,(HL) 5E 1 NOP 1
LD E,(IX*) 5EDD 3 ZIX 1
LD E,(IY*) 5EFD 3 ZIX 1
LD E,A 5F 1 NOP 1
LD E,B 58 1 NOP 1
LD E,C 59 1 NOP 1
LD E,D 5A 1 NOP 1
LD E,E 5B 1 NOP 1
LD E,H 5C 1 NOP 1
LD E,L 5D 1 NOP 1
LD E,* 1E 2 NOP 1
LD H,(HL) 66 1 NOP 1
LD H,(IX*) 66DD 3 ZIX 1
LD H,(IY*) 66FD 3 ZIX 1
LD H,A 67 1 NOP 1
LD H,B 60 1 NOP 1
LD H,C 61 1 NOP 1
LD H,D 62 1 NOP 1
LD H,E 63 1 NOP 1
LD H,H 64 1 NOP 1
LD H,L 65 1 NOP 1
LD H,* 26 2 NOP 1
LD HL,(*) 2A 3 NOP 1
LD HL,* 21 3 NOP 1
LD I,A 47ED 2 NOP 1
LD IX,(*) 2ADD 4 NOP 1
LD IX,* 21DD 4 NOP 1
LD IY,(*) 2AFD 4 NOP 1
LD IY,* 21FD 4 NOP 1
LD L,(HL) 6E 1 NOP 1
LD L,(IX*) 6EDD 3 ZIX 1
LD L,(IY*) 6EFD 3 ZIX 1
LD L,A 6F 1 NOP 1
LD L,B 68 1 NOP 1
LD L,C 69 1 NOP 1
LD L,D 6A 1 NOP 1
LD L,E 6B 1 NOP 1
LD L,H 6C 1 NOP 1
LD L,L 6D 1 NOP 1
LD L,* 2E 2 NOP 1
LD R,A 4FED 2 NOP 1
LD SP,(*) 7BED 4 NOP 1
LD SP,HL F9 1 NOP 1
LD SP,IX F9DD 2 NOP 1
LD SP,IY F9FD 2 NOP 1
LD SP,* 31 3 NOP 1
LDD "" A8ED 2 NOP 1
LDDR "" B8ED 2 NOP 1
LDI "" A0ED 2 NOP 1
LDIR "" B0ED 2 NOP 1
NEG "" 44ED 2 NOP 1
NOP "" 00 1 NOP 1
MLT BC 4CED 2 NOP 2
MLT DE 5CED 2 NOP 2
MLT HL 6CED 2 NOP 2
MLT SP 7CED 2 NOP 2
OR (HL) B6 1 NOP 1
OR (IX*) B6DD 3 ZIX 1
OR (IY*) B6FD 3 ZIX 1
OR A B7 1 NOP 1
OR B B0 1 NOP 1
OR C B1 1 NOP 1
OR D B2 1 NOP 1
OR E B3 1 NOP 1
OR H B4 1 NOP 1
OR L B5 1 NOP 1
OR * F6 2 NOP 1
OTDM "" 8BED 2 NOP 2
OTDMR "" 9BED 2 NOP 2
OTDR "" BBED 2 NOP 1
OTIM "" 83ED 2 NOP 2
OTIMR "" 93ED 2 NOP 2
OTIR "" B3ED 2 NOP 1
OUT (C),A 79ED 2 NOP 1
OUT (C),B 41ED 2 NOP 1
OUT (C),C 49ED 2 NOP 1
OUT (C),D 51ED 2 NOP 1
OUT (C),E 59ED 2 NOP 1
OUT (C),H 61ED 2 NOP 1
OUT (C),L 69ED 2 NOP 1
OUT (*),A D3 2 NOP 1
OUT0 (*),A 39ED 3 NOP 2
OUT0 (*),B 01ED 3 NOP 2
OUT0 (*),C 09ED 3 NOP 2
OUT0 (*),D 11ED 3 NOP 2
OUT0 (*),E 19ED 3 NOP 2
OUT0 (*),H 21ED 3 NOP 2
OUT0 (*),L 29ED 3 NOP 2
OUTD "" ABED 2 NOP 1
OUTI "" A3ED 2 NOP 1
POP AF F1 1 NOP 1
POP BC C1 1 NOP 1
POP DE D1 1 NOP 1
POP HL E1 1 NOP 1
POP IX E1DD 2 NOP 1
POP IY E1FD 2 NOP 1
PUSH AF F5 1 NOP 1
PUSH BC C5 1 NOP 1
PUSH DE D5 1 NOP 1
PUSH HL E5 1 NOP 1
PUSH IX E5DD 2 NOP 1
PUSH IY E5FD 2 NOP 1
RES *,(HL) 86CB 2 ZBIT 1
RES *,(IX*) CBDD 4 ZBIT 1 0 8600
RES *,(IY*) CBFD 4 ZBIT 1 0 8600
RES *,A 87CB 2 ZBIT 1
RES *,B 80CB 2 ZBIT 1
RES *,C 81CB 2 ZBIT 1
RES *,D 82CB 2 ZBIT 1
RES *,E 83CB 2 ZBIT 1
RES *,H 84CB 2 ZBIT 1
RES *,L 85CB 2 ZBIT 1
RET "" C9 1 NOP 1
RET C D8 1 NOP 1
RET M F8 1 NOP 1
RET NC D0 1 NOP 1
RET NZ C0 1 NOP 1
RET P F0 1 NOP 1
RET PE E8 1 NOP 1
RET PO E0 1 NOP 1
RET Z C8 1 NOP 1
RETI "" 4DED 2 NOP 1
RETN "" 45ED 2 NOP 1
RL (HL) 16CB 2 NOP 1
RL (IX*) CBDD 4 ZIX 1 0 1600
RL (IY*) CBFD 4 ZIX 1 0 1600
RL A 17CB 2 NOP 1
RL B 10CB 2 NOP 1
RL C 11CB 2 NOP 1
RL D 12CB 2 NOP 1
RL E 13CB 2 NOP 1
RL H 14CB 2 NOP 1
RL L 15CB 2 NOP 1
RLA "" 17 1 NOP 1
RLC (HL) 06CB 2 NOP 1
RLC (IX*) CBDD 4 ZIX 1 0 0600
RLC (IY*) CBFD 4 ZIX 1 0 0600
RLC A 07CB 2 NOP 1
RLC B 00CB 2 NOP 1
RLC C 01CB 2 NOP 1
RLC D 02CB 2 NOP 1
RLC E 03CB 2 NOP 1
RLC H 04CB 2 NOP 1
RLC L 05CB 2 NOP 1
RLCA "" 07 1 NOP 1
RLD "" 6FED 2 NOP 1
RR (HL) 1ECB 2 NOP 1
RR (IX*) CBDD 4 ZIX 1 0 1E00
RR (IY*) CBFD 4 ZIX 1 0 1E00
RR A 1FCB 2 NOP 1
RR B 18CB 2 NOP 1
RR C 19CB 2 NOP 1
RR D 1ACB 2 NOP 1
RR E 1BCB 2 NOP 1
RR H 1CCB 2 NOP 1
RR L 1DCB 2 NOP 1
RRA "" 1F 1 NOP 1
RRC (HL) 0ECB 2 NOP 1
RRC (IX*) CBDD 4 ZIX 1 0 0E00
RRC (IY*) CBFD 4 ZIX 1 0 0E00
RRC A 0FCB 2 NOP 1
RRC B 08CB 2 NOP 1
RRC C 09CB 2 NOP 1
RRC D 0ACB 2 NOP 1
RRC E 0BCB 2 NOP 1
RRC H 0CCB 2 NOP 1
RRC L 0DCB 2 NOP 1
RRCA "" 0F 1 NOP 1
RRD "" 67ED 2 NOP 1
RST 00H C7 1 NOP 1
RST 08H CF 1 NOP 1
RST 10H D7 1 NOP 1
RST 18H DF 1 NOP 1
RST 20H E7 1 NOP 1
RST 28H EF 1 NOP 1
RST 30H F7 1 NOP 1
RST 38H FF 1 NOP 1
/* Alternate form of above
RST 00 C7 1 NOP 1
RST 08 CF 1 NOP 1
RST 10 D7 1 NOP 1
RST 18 DF 1 NOP 1
RST 20 E7 1 NOP 1
RST 28 EF 1 NOP 1
RST 30 F7 1 NOP 1
RST 38 FF 1 NOP 1
SBC A,(HL) 9E 1 NOP 1
SBC A,(IX*) 9EDD 3 ZIX 1
SBC A,(IY*) 9EFD 3 ZIX 1
SBC A,A 9F 1 NOP 1
SBC A,B 98 1 NOP 1
SBC A,C 99 1 NOP 1
SBC A,D 9A 1 NOP 1
SBC A,E 9B 1 NOP 1
SBC A,H 9C 1 NOP 1
SBC A,L 9D 1 NOP 1
SBC HL,BC 42ED 2 NOP 1
SBC HL,DE 52ED 2 NOP 1
SBC HL,HL 62ED 2 NOP 1
SBC HL,SP 72ED 2 NOP 1
SBC A,* DE 2 NOP 1
SCF "" 37 1 NOP 1
SET *,(HL) C6CB 2 ZBIT 1
SET *,(IX*) CBDD 4 ZBIT 1 0 C600
SET *,(IY*) CBFD 4 ZBIT 1 0 C600
SET *,A C7CB 2 ZBIT 1
SET *,B C0CB 2 ZBIT 1
SET *,C C1CB 2 ZBIT 1
SET *,D C2CB 2 ZBIT 1
SET *,E C3CB 2 ZBIT 1
SET *,H C4CB 2 ZBIT 1
SET *,L C5CB 2 ZBIT 1
SLA (HL) 26CB 2 NOP 1
SLA (IX*) CBDD 4 ZIX 1 0 2600
SLA (IY*) CBFD 4 ZIX 1 0 2600
SLA A 27CB 2 NOP 1
SLA B 20CB 2 NOP 1
SLA C 21CB 2 NOP 1
SLA D 22CB 2 NOP 1
SLA E 23CB 2 NOP 1
SLA H 24CB 2 NOP 1
SLA L 25CB 2 NOP 1
SLP "" 76ED 2 NOP 2
SRA (HL) 2ECB 2 NOP 1
SRA (IX*) CBDD 4 ZIX 1 0 2E00
SRA (IY*) CBFD 4 ZIX 1 0 2E00
SRA A 2FCB 2 NOP 1
SRA B 28CB 2 NOP 1
SRA C 29CB 2 NOP 1
SRA D 2ACB 2 NOP 1
SRA E 2BCB 2 NOP 1
SRA H 2CCB 2 NOP 1
SRA L 2DCB 2 NOP 1
SRL (HL) 3ECB 2 NOP 1
SRL (IX*) CBDD 4 ZIX 1 0 3E00
SRL (IY*) CBFD 4 ZIX 1 0 3E00
SRL A 3FCB 2 NOP 1
SRL B 38CB 2 NOP 1
SRL C 39CB 2 NOP 1
SRL D 3ACB 2 NOP 1
SRL E 3BCB 2 NOP 1
SRL H 3CCB 2 NOP 1
SRL L 3DCB 2 NOP 1
SUB (HL) 96 1 NOP 1
SUB (IX*) 96DD 3 ZIX 1
SUB (IY*) 96FD 3 ZIX 1
SUB A 97 1 NOP 1
SUB B 90 1 NOP 1
SUB C 91 1 NOP 1
SUB D 92 1 NOP 1
SUB E 93 1 NOP 1
SUB H 94 1 NOP 1
SUB L 95 1 NOP 1
SUB * D6 2 NOP 1
TST A 3CED 2 NOP 2
TST B 04ED 2 NOP 2
TST C 0CED 2 NOP 2
TST D 14ED 2 NOP 2
TST E 1CED 2 NOP 2
TST H 24ED 2 NOP 2
TST L 2CED 2 NOP 2
TST (HL) 34ED 2 NOP 2
TST * 64ED 3 NOP 2
TSTIO * 74ED 3 NOP 2
XOR (HL) AE 1 NOP 1
XOR (IX*) AEDD 3 ZIX 1
XOR (IY*) AEFD 3 ZIX 1
XOR A AF 1 NOP 1
XOR B A8 1 NOP 1
XOR C A9 1 NOP 1
XOR D AA 1 NOP 1
XOR E AB 1 NOP 1
XOR H AC 1 NOP 1
XOR L AD 1 NOP 1
XOR * EE 2 NOP 1

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"TASM 8085 Assembler. "
/****************************************************************************
/* $Id: tasm85.tab 1.1 1993/07/31 01:12:40 toma Exp $
/****************************************************************************
/* This is the instruction set definition table for the 8085 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/* This table authored and submitted by Gary Kirk Bach.
/*
/*INSTR ARGS OPCODE BYTES MOD CLASS */
/*-----------------*/
ACI * CE 2 NOP 1
ADC B 88 1 NOP 1
ADC C 89 1 NOP 1
ADC D 8A 1 NOP 1
ADC E 8B 1 NOP 1
ADC H 8C 1 NOP 1
ADC L 8D 1 NOP 1
ADC M 8E 1 NOP 1
ADC A 8F 1 NOP 1
ADD B 80 1 NOP 1
ADD C 81 1 NOP 1
ADD D 82 1 NOP 1
ADD E 83 1 NOP 1
ADD H 84 1 NOP 1
ADD L 85 1 NOP 1
ADD M 86 1 NOP 1
ADD A 87 1 NOP 1
ADI * C6 2 NOP 1
ANA B A0 1 NOP 1
ANA C A1 1 NOP 1
ANA D A2 1 NOP 1
ANA E A3 1 NOP 1
ANA H A4 1 NOP 1
ANA L A5 1 NOP 1
ANA M A6 1 NOP 1
ANA A A7 1 NOP 1
ANI * E6 2 NOP 1
CALL * CD 3 NOP 1
CC * DC 3 NOP 1
CM * FC 3 NOP 1
CMA "" 2F 1 NOP 1
CMC "" 3F 1 NOP 1
CMP B B8 1 NOP 1
CMP C B9 1 NOP 1
CMP D BA 1 NOP 1
CMP E BB 1 NOP 1
CMP H BC 1 NOP 1
CMP L BD 1 NOP 1
CMP M BE 1 NOP 1
CMP A BF 1 NOP 1
CNC * D4 3 NOP 1
CNZ * C4 3 NOP 1
CP * F4 3 NOP 1
CPE * EC 3 NOP 1
CPI * FE 2 NOP 1
CPO * E4 3 NOP 1
CZ * CC 3 NOP 1
DAA "" 27 1 NOP 1
DAD B 09 1 NOP 1
DAD D 19 1 NOP 1
DAD H 29 1 NOP 1
DAD SP 39 1 NOP 1
DCR B 05 1 NOP 1
DCR C 0D 1 NOP 1
DCR D 15 1 NOP 1
DCR E 1D 1 NOP 1
DCR H 25 1 NOP 1
DCR L 2D 1 NOP 1
DCR M 35 1 NOP 1
DCR A 3D 1 NOP 1
DCX B 0B 1 NOP 1
DCX D 1B 1 NOP 1
DCX H 2B 1 NOP 1
DCX SP 3B 1 NOP 1
DI "" F3 1 NOP 1
EI "" FB 1 NOP 1
HLT "" 76 1 NOP 1
IN * DB 2 NOP 1
INR B 04 1 NOP 1
INR C 0C 1 NOP 1
INR D 14 1 NOP 1
INR E 1C 1 NOP 1
INR H 24 1 NOP 1
INR L 2C 1 NOP 1
INR M 34 1 NOP 1
INR A 3C 1 NOP 1
INX B 03 1 NOP 1
INX D 13 1 NOP 1
INX H 23 1 NOP 1
INX SP 33 1 NOP 1
JC * DA 3 NOP 1
JM * FA 3 NOP 1
JMP * C3 3 NOP 1
JNC * D2 3 NOP 1
JNZ * C2 3 NOP 1
JP * F2 3 NOP 1
JPE * EA 3 NOP 1
JPO * E2 3 NOP 1
JZ * CA 3 NOP 1
LDA * 3A 3 NOP 1
LDAX B 0A 1 NOP 1
LDAX D 1A 1 NOP 1
LHLD * 2A 3 NOP 1
LXI B,* 01 3 NOP 1
LXI D,* 11 3 NOP 1
LXI H,* 21 3 NOP 1
LXI SP,* 31 3 NOP 1
MOV B,B 40 1 NOP 1
MOV B,C 41 1 NOP 1
MOV B,D 42 1 NOP 1
MOV B,E 43 1 NOP 1
MOV B,H 44 1 NOP 1
MOV B,L 45 1 NOP 1
MOV B,M 46 1 NOP 1
MOV B,A 47 1 NOP 1
MOV C,B 48 1 NOP 1
MOV C,C 49 1 NOP 1
MOV C,D 4A 1 NOP 1
MOV C,E 4B 1 NOP 1
MOV C,H 4C 1 NOP 1
MOV C,L 4D 1 NOP 1
MOV C,M 4E 1 NOP 1
MOV C,A 4F 1 NOP 1
MOV D,B 50 1 NOP 1
MOV D,C 51 1 NOP 1
MOV D,D 52 1 NOP 1
MOV D,E 53 1 NOP 1
MOV D,H 54 1 NOP 1
MOV D,L 55 1 NOP 1
MOV D,M 56 1 NOP 1
MOV D,A 57 1 NOP 1
MOV E,B 58 1 NOP 1
MOV E,C 59 1 NOP 1
MOV E,D 5A 1 NOP 1
MOV E,E 5B 1 NOP 1
MOV E,H 5C 1 NOP 1
MOV E,L 5D 1 NOP 1
MOV E,M 5E 1 NOP 1
MOV E,A 5F 1 NOP 1
MOV H,B 60 1 NOP 1
MOV H,C 61 1 NOP 1
MOV H,D 62 1 NOP 1
MOV H,E 63 1 NOP 1
MOV H,H 64 1 NOP 1
MOV H,L 65 1 NOP 1
MOV H,M 66 1 NOP 1
MOV H,A 67 1 NOP 1
MOV L,B 68 1 NOP 1
MOV L,C 69 1 NOP 1
MOV L,D 6A 1 NOP 1
MOV L,E 6B 1 NOP 1
MOV L,H 6C 1 NOP 1
MOV L,L 6D 1 NOP 1
MOV L,M 6E 1 NOP 1
MOV L,A 6F 1 NOP 1
MOV M,B 70 1 NOP 1
MOV M,C 71 1 NOP 1
MOV M,D 72 1 NOP 1
MOV M,E 73 1 NOP 1
MOV M,H 74 1 NOP 1
MOV M,L 75 1 NOP 1
MOV M,A 77 1 NOP 1
MOV A,B 78 1 NOP 1
MOV A,C 79 1 NOP 1
MOV A,D 7A 1 NOP 1
MOV A,E 7B 1 NOP 1
MOV A,H 7C 1 NOP 1
MOV A,L 7D 1 NOP 1
MOV A,M 7E 1 NOP 1
MOV A,A 7F 1 NOP 1
MVI B,* 06 2 NOP 1
MVI C,* 0E 2 NOP 1
MVI D,* 16 2 NOP 1
MVI E,* 1E 2 NOP 1
MVI H,* 26 2 NOP 1
MVI L,* 2E 2 NOP 1
MVI M,* 36 2 NOP 1
MVI A,* 3E 2 NOP 1
NOP "" 00 1 NOP 1
ORA B B0 1 NOP 1
ORA C B1 1 NOP 1
ORA D B2 1 NOP 1
ORA E B3 1 NOP 1
ORA H B4 1 NOP 1
ORA L B5 1 NOP 1
ORA M B6 1 NOP 1
ORA A B7 1 NOP 1
ORI * F6 2 NOP 1
OUT * D3 2 NOP 1
PCHL "" E9 1 NOP 1
POP B C1 1 NOP 1
POP D D1 1 NOP 1
POP H E1 1 NOP 1
POP PSW F1 1 NOP 1
PUSH B C5 1 NOP 1
PUSH D D5 1 NOP 1
PUSH H E5 1 NOP 1
PUSH PSW F5 1 NOP 1
RAL "" 17 1 NOP 1
RAR "" 1F 1 NOP 1
RC "" D8 1 NOP 1
RET "" C9 1 NOP 1
RIM "" 20 1 NOP 1
RLC "" 07 1 NOP 1
RM "" F8 1 NOP 1
RNC "" D0 1 NOP 1
RNZ "" C0 1 NOP 1
RP "" F0 1 NOP 1
RPE "" E8 1 NOP 1
RPO "" E0 1 NOP 1
RRC "" 0F 1 NOP 1
RST 0 C7 1 NOP 1
RST 1 CF 1 NOP 1
RST 2 D7 1 NOP 1
RST 3 DF 1 NOP 1
RST 4 E7 1 NOP 1
RST 5 EF 1 NOP 1
RST 6 F7 1 NOP 1
RST 7 FF 1 NOP 1
RZ "" C8 1 NOP 1
SBB B 98 1 NOP 1
SBB C 99 1 NOP 1
SBB D 9A 1 NOP 1
SBB E 9B 1 NOP 1
SBB H 9C 1 NOP 1
SBB L 9D 1 NOP 1
SBB M 9E 1 NOP 1
SBB A 9F 1 NOP 1
SBI * DE 2 NOP 1
SHLD * 22 3 NOP 1
SIM "" 30 1 NOP 1
SPHL "" F9 1 NOP 1
STA * 32 3 NOP 1
STAX B 02 1 NOP 1
STAX D 12 1 NOP 1
STC "" 37 1 NOP 1
SUB B 90 1 NOP 1
SUB C 91 1 NOP 1
SUB D 92 1 NOP 1
SUB E 93 1 NOP 1
SUB H 94 1 NOP 1
SUB L 95 1 NOP 1
SUB M 96 1 NOP 1
SUB A 97 1 NOP 1
SUI * D6 2 NOP 1
XCHG "" EB 1 NOP 1
XRA B A8 1 NOP 1
XRA C A9 1 NOP 1
XRA D AA 1 NOP 1
XRA E AB 1 NOP 1
XRA H AC 1 NOP 1
XRA L AD 1 NOP 1
XRA M AE 1 NOP 1
XRA A AF 1 NOP 1
XRI * EE 2 NOP 1
XTHL "" E3 1 NOP 1

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"TASM 8096 Assembler."
/****************************************************************************
/* $Id: tasm96.tab 1.5 1997/09/28 22:14:30 toma Exp $
/****************************************************************************
;* This is the instruction set definition table
;* for the 8096 version of TASM.
;* Thomas N. Anderson, Speech Technology Incorporated
;*
;* See TASM manual for info on table structure.
;*
;*INSTR ARGS OPCODE BYTES MOD CLASS SHIFT MASK
;*-------------------------------------------*
; Revisions:
; Added I7 rule for single arg direct/far (PUSH/POP)
; Changed ADDB *,*,*[*] entry from rule I1 to I6.
;
; Generate opcodes high byte first/
.MSFIRST
.NOARGSHIFT
;
; Note:
; The I1 rule uses ARGVAL for arg validation. If the combined
; args AND ARGVAL is not equal to the combined args then an
; error message is generated.
;
; The I1 rule also uses ARGOR. The value of that mask is OR'd
; with the first byte of the args.
;
; ARGOR
; BYTES CLASS |
; | | |
;INST ARGS OP v RULE v v ARGVAL
;-----------------------------------------;
;OK ADD
ADD *,*,[*]+ 46 4 I1 1 01 00FeFeFe ;
ADD *,*,[*] 46 4 I1 1 00 00FeFeFe ;
ADD *,*,*[*] 47 6 I6 1 00 00FeFeFe ;
ADD *,*,#* 45 5 I1 1 00 FeFeFFFF ;
ADD *,[*]+ 66 3 I1 1 01 0000FFFe ; 1st arg must be even, make odd
ADD *,[*] 66 3 I1 1 00 0000FFFe ; 1st arg must be even
ADD *,*[*] 67 5 I6 1 00 00FFFFFF ;
ADD *,*,* 4701 6 I3 1 00 0000FeFe ; 3rd arg may be far
ADD *,#* 65 4 I1 1 00 00FeFFFF ; 1st arg must be even
ADD *,* 6701 5 I2 1 00 0000FeFe ; 2nd arg may be far
;OK ADDB
ADDB *,*,[*]+ 56 4 I1 1 01 00000000 ; no validation yet
ADDB *,*,[*] 56 4 I1 1 00 00000000 ; no validation yet
ADDB *,*,*[*] 57 6 I6 1 00 00000000 ; no validation yet
ADDB *,*,#* 55 4 I1 1 00 00000000 ; no validation yet
ADDB *,[*]+ 76 3 I1 1 01 0000FFFe ; 1st arg must be even, make odd
ADDB *,[*] 76 3 I1 1 00 0000FFFe ; 1st arg must be even
ADDB *,*[*] 77 5 I6 1 00 00FeFFFe ; 1st,3rd must be even
ADDB *,*,* 5701 6 I3 1 00 00000000 ; 3rd arg may be far
ADDB *,#* 75 3 I1 1 00 00FFFFFF ; odd args ok for byte operations
ADDB *,* 7701 5 I2 1 00 00000000 ; 2nd arg may be far
; No three arg forms for ADDC or ADDCB
ADDC *,[*]+ A6 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ADDC *,[*] A6 3 I1 1 00 0000FFFe ;1st arg must be even
ADDC *,*[*] A7 5 I6 1 00 00FFFFFF ;
ADDC *,#* A5 4 I1 1 00 00FeFFFF ;1st arg must be even
ADDC *,* A701 5 I2 1 00 00000000 ;2nd arg may be far
ADDCB *,[*]+ B6 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ADDCB *,[*] B6 3 I1 1 00 0000FFFe ;1st arg must be even
ADDCB *,*[*] B7 5 I6 1 00 00FFFFFF ;
ADDCB *,#* B5 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
ADDCB *,* B701 5 I2 1 00 00000000 ;2nd arg may be far
; OK AND
AND *,*,[*]+ 42 4 I1 1 01 00000000 ;no validation yet
AND *,*,[*] 42 4 I1 1 00 00000000 ;no validation yet
AND *,*,*[*] 43 6 I6 1 00 00000000 ;no validation yet
AND *,*,#* 41 5 I1 1 00 00000000 ;no validation yet
AND *,[*]+ 62 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
AND *,[*] 62 3 I1 1 00 0000FFFe ;1st arg must be even
AND *,*[*] 63 5 I6 1 00 00FeFFFe ;1st,3rd must be even
AND *,*,* 4301 6 I3 1 00 00000000 ;3rd arg may be far
AND *,#* 61 4 I1 1 00 00FeFFFF ;1st arg must be even
AND *,* 6301 5 I2 1 00 00000000 ;2nd arg may be far
ANDB *,*,[*]+ 52 4 I1 1 01 00000000 ;no validation yet
ANDB *,*,[*] 52 4 I1 1 00 00000000 ;no validation yet
ANDB *,*,*[*] 53 6 I6 1 00 00000000 ;no validation yet
ANDB *,*,#* 51 4 I1 1 00 00000000 ;no validation yet
ANDB *,[*]+ 72 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ANDB *,[*] 72 3 I1 1 00 0000FFFe ;1st arg must be even
ANDB *,*[*] 73 5 I6 1 00 00FFFFFF ;
ANDB *,*,* 5301 6 I3 1 00 00000000 ;3rd arg may be far
ANDB *,#* 71 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
ANDB *,* 7301 5 I2 1 00 00000000 ;2nd arg may be far
BMOV *,* C1 3 I1 2 00 0000FcFF ;long word ptr to two words
BMOVI *,* AD 3 I1 2 00 0000FcFF ;long word ptr to two words
BR [*] E3 2 I1 1 00 00000000 ;
BR * 2000 2 I5 1 00 00000000 ; Same As SJMP
CLR * 01 2 NOP 1 00 00000000 ;
CLRB * 11 2 NOP 1 00 00000000 ;
CLRC "" F8 1 NOP 1 00 00000000 ;
CLRVT "" FC 1 NOP 1 00 00000000 ;
CMP *,[*]+ 8A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
CMP *,[*] 8A 3 I1 1 00 0000FFFe ;1st arg must be even
CMP *,*[*] 8B 5 I6 1 00 00FFFFFF ;
CMP *,#* 89 4 I1 1 00 00FeFFFF ;1st arg must be even
CMP *,* 8B01 5 I2 1 00 00000000 ;2nd arg may be far
CMPB *,[*]+ 9A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
CMPB *,[*] 9A 3 I1 1 00 0000FFFe ;1st arg must be even
CMPB *,*[*] 9B 5 I6 1 00 00FFFFFF ;
CMPB *,#* 99 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
CMPB *,* 9B01 5 I2 1 00 00000000 ;2nd arg may be far
CMPL *,* C5 3 I1 2 00 0000FcFc ;long align multiple of 4
DEC * 05 2 NOP 1 00 00000000 ;
DECB * 15 2 NOP 1 00 00000000 ;
DJNZ *,* E0 3 CREL 1 00 00000000 ;
DJNZW *,* E1 3 CREL 2 00 00000000 ;
DI "" FA 1 NOP 1 00 00000000 ;
DIVU *,[*]+ 8E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIVU *,[*] 8E 3 I1 1 00 0000FFFe ;1st arg must be even
DIVU *,*[*] 8F 5 I6 1 00 0000FFFe ;1st arg must be even
DIVU *,#* 8D 4 I1 1 00 00FeFFFF ;1st arg must be even
DIVU *,* 8F01 5 I2 1 00 00000000 ;2nd arg may be far
DIVUB *,[*]+ 9E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIVUB *,[*] 9E 3 I1 1 00 0000FFFe ;1st arg must be even
DIVUB *,*[*] 9F 5 I6 1 00 0000FFFF ;
DIVUB *,#* 9D 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
DIVUB *,* 9F01 5 I2 1 00 00000000 ;2nd arg may be far
DIV *,[*]+ FE8E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIV *,[*] FE8E 4 I1 1 00 0000FFFe ;1st arg must be even
DIV *,*[*] FE8F 6 I6 1 00 0000FFFe ;1st arg must be even
DIV *,#* FE8D 5 I1 1 00 00FeFFFF ;1st arg must be even
DIV *,* FE8F01 6 I2 1 00 00000000 ;2nd arg may be far
DIVB *,[*]+ FE9E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
DIVB *,[*] FE9E 4 I1 1 00 0000FFFe ;1st arg must be even
DIVB *,*[*] FE9F 6 I6 1 00 0000FFFF ;
DIVB *,#* FE9D 4 I1 1 00 00FFFFFF ;odd args ok for byte operations;
DIVB *,* FE9F01 6 I2 1 00 00000000 ;2nd arg may be far
DPTS "" EC 1 NOP 2 00 00000000 ;
EPTS "" ED 1 NOP 2 00 00000000 ;
EI "" FB 1 NOP 1 00 00000000 ;
EXT * 06 2 NOP 1 00 00000000 ;
EXTB * 16 2 NOP 1 00 00000000 ;
IDLPD #* F6 2 NOP 2 00 00000000 ;
INC * 07 2 NOP 1 00 00000000 ;
INCB * 17 2 NOP 1 00 00000000 ;
JC * DB 2 R1 1 00 00000000
JNC * D3 2 R1 1 00 00000000
JH * D9 2 R1 1 00 00000000
JNH * D1 2 R1 1 00 00000000
JE * DF 2 R1 1 00 00000000
JNE * D7 2 R1 1 00 00000000
JV * DD 2 R1 1 00 00000000
JNV * D5 2 R1 1 00 00000000
JGE * D6 2 R1 1 00 00000000
JLT * DE 2 R1 1 00 00000000
JVT * DC 2 R1 1 00 00000000
JNVT * D4 2 R1 1 00 00000000
JGT * D2 2 R1 1 00 00000000
JLE * DA 2 R1 1 00 00000000
JST * D8 2 R1 1 00 00000000
JNST * D0 2 R1 1 00 00000000
JBC *,*,* 30 3 I4 1 00 00000000
JBS *,*,* 38 3 I4 1 00 00000000
LJMP * E7 3 R2 1 00 00000000
LCALL * EF 3 R2 1 00 00000000
LD *,[*]+ A2 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LD *,[*] A2 3 I1 1 00 0000FFFe ;1st arg must be even
LD *,*[*] A3 5 I6 1 00 00FFFFFF ;
LD *,#* A1 4 I1 1 00 00FFFFFF ;
LD *,* A301 5 I2 1 00 00000000 ;2nd arg may be far
LDB *,[*]+ B2 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LDB *,[*] B2 3 I1 1 00 0000FFFe ;1st arg must be even
LDB *,*[*] B3 5 I6 1 00 00FFFFFF ;
LDB *,#* B1 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
LDB *,* B301 5 I2 1 00 00000000 ;2nd arg may be far
LDBSE *,[*]+ BE 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LDBSE *,[*] BE 3 I1 1 00 0000FFFe ;1st arg must be even
LDBSE *,*[*] BF 5 I6 1 00 00FeFFFe ;1st,3rd must be even
LDBSE *,#* BD 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
LDBSE *,* BF01 5 I2 1 00 00000000 ;2nd arg may be far
LDBZE *,[*]+ AE 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
LDBZE *,[*] AE 3 I1 1 00 0000FFFe ;1st arg must be even
LDBZE *,*[*] AF 5 I6 1 00 00FeFFFe ;1st,3rd must be even
LDBZE *,#* AD 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
LDBZE *,* AF01 5 I2 1 00 00000000 ;2nd arg may be far
MULU *,*,[*]+ 4E 4 I1 1 01 00000000 ;no validation yet
MULU *,*,[*] 4E 4 I1 1 00 00000000 ;no validation yet
MULU *,*,*[*] 4F 6 I6 1 00 00000000 ;no validation yet
MULU *,*,#* 4D 5 I1 1 00 00000000 ;no validation yet
MULU *,[*]+ 6E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
MULU *,[*] 6E 3 I1 1 00 0000FFFe ;1st arg must be even
MULU *,*[*] 6F 5 I6 1 00 00FeFFFe ;1st,3rd must be even
MULU *,*,* 4F01 6 I3 1 00 00000000 ;3rd arg may be far
MULU *,#* 6D 4 I1 1 00 00FeFFFF ;1st arg must be even
MULU *,* 6F01 5 I2 1 00 00000000 ;2nd arg may be far
MULUB *,*,[*]+ 5E 4 I1 1 01 00000000 ;no validation yet
MULUB *,*,[*] 5E 4 I1 1 00 00000000 ;no validation yet
MULUB *,*,*[*] 5F 6 I6 1 00 00000000 ;no validation yet
MULUB *,*,#* 5D 4 I1 1 00 00000000 ;no validation yet
MULUB *,[*]+ 7E 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
MULUB *,[*] 7E 3 I1 1 00 0000FFFe ;1st arg must be even
MULUB *,*[*] 7F 5 I6 1 00 00FFFFFF ;
MULUB *,*,* 5F01 6 I3 1 00 00000000 ;3rd arg may be far
MULUB *,#* 7D 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
MULUB *,* 7F01 5 I2 1 00 00000000 ;2nd arg may be far
MUL *,*,[*]+ FE4E 5 I1 1 01 00000000 ;no validation yet
MUL *,*,[*] FE4E 5 I1 1 00 00000000 ;no validation yet
MUL *,*,*[*] FE4F 7 I6 1 00 00000000 ;no validation yet
MUL *,*,#* FE4D 6 I1 1 00 00000000 ;no validation yet
MUL *,[*]+ FE6E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
MUL *,[*] FE6E 4 I1 1 00 0000FFFe ;1st arg must be even
MUL *,*[*] FE6F 6 I6 1 00 00FeFFFe ;1st,3rd must be even
MUL *,*,* FE4F01 7 I3 1 00 00000000 ;3rd arg may be far
MUL *,#* FE6D 5 I1 1 00 00FFFFFF ;odd args ok for byte operations
MUL *,* FE6F01 6 I2 1 00 00000000 ;2nd arg may be far
MULB *,*,[*]+ FE5E 5 I1 1 01 00000000 ;no validation yet
MULB *,*,[*] FE5E 5 I1 1 00 00000000 ;no validation yet
MULB *,*,*[*] FE5F 7 I6 1 00 00000000 ;no validation yet
MULB *,*,#* FE5D 5 I1 1 00 00000000 ;no validation yet
MULB *,[*]+ FE7E 4 I1 1 01 0000FFFe ;1st arg must be even, make odd
MULB *,[*] FE7E 4 I1 1 00 0000FFFe ;1st arg must be even
MULB *,*[*] FE7F 6 I6 1 00 00FFFFFF ;
MULB *,*,* FE5F01 7 I3 1 00 00000000 ;3rd arg may be far
MULB *,#* FE7D 4 I1 1 00 00FFFFFF ;odd args ok for byte operations
MULB *,* FE7F01 6 I2 1 00 00000000 ;2nd arg may be far
NEG * 03 2 I1 1 00 000000FE ;arg must be even
NEGB * 13 2 I1 1 00 000000FF ;
NOP "" FD 1 NOP 1 00 00000000 ;
NORML *,* 0F 3 I1 1 00 0000FFFF ;long align
NOT * 02 2 NOP 1 00 00000000 ;
NOTB * 12 2 NOP 1 00 00000000 ;
OR *,[*]+ 82 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
OR *,[*] 82 3 I1 1 00 0000FFFe ;1st arg must be even
OR *,*[*] 83 5 I6 1 00 00FeFFFe ;1st,3rd must be even
OR *,#* 81 4 I1 1 00 00FeFFFF ;1st arg must be even
OR *,* 8301 5 I2 1 00 00000000 ;2nd arg may be far
ORB *,[*]+ 92 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ORB *,[*] 92 3 I1 1 00 0000FFFe ;1st arg must be even
ORB *,*[*] 93 5 I6 1 00 00FFFFFF ;
ORB *,#* 91 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
ORB *,* 9301 5 I2 1 00 00000000 ;2nd arg may be far
PUSH #* C9 3 I1 1 00 00000000 ;
PUSH [*]+ CA 2 I1 1 01 000000Fe ;arg must be even
PUSH [*] CA 2 I1 1 00 000000Fe ;arg must be even
PUSH *[*] CB 4 I6 1 00 00FFFFFe ;arg must be even
PUSH * CB01 4 I7 1 00 0000FFFe ;arg must be even
PUSHF "" F2 1 NOP 1 00 00000000 ;
PUSHA "" F4 1 NOP 1 00 00000000 ;
POP [*]+ CE 2 I1 1 01 000000Fe ;arg must be even
POP [*] CE 2 I1 1 00 000000Fe ;arg must be even
POP *[*] CF 4 I6 1 00 00FFFFFE ;
POP * CF01 4 I7 1 00 0000FFFe ;arg must be even
POPF "" F3 1 NOP 1 00 00000000 ;
POPA "" F5 1 NOP 1 00 00000000 ;
RET "" F0 1 NOP 1 00 00000000 ;
RST "" FF 1 NOP 1 00 00000000 ;
SJMP * 2000 2 I5 1 00 00000000
SCALL * 2800 2 I5 1 00 00000000
SUB *,*,[*]+ 4A 4 I1 1 01 00000000 ;no validation yet
SUB *,*,[*] 4A 4 I1 1 00 00000000 ;no validation yet
SUB *,*,*[*] 4B 6 I6 1 00 00000000 ;no validation yet
SUB *,*,#* 49 5 I1 1 00 00000000 ;no validation yet
SUB *,[*]+ 6A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUB *,[*] 6A 3 I1 1 00 0000FFFe ;1st arg must be even
SUB *,*[*] 6B 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUB *,*,* 4B01 6 I3 1 00 00000000 ;3rd arg may be far
SUB *,#* 69 4 I1 1 00 00FeFFFF ;1st arg must be even
SUB *,* 6B01 5 I2 1 00 00000000 ;2nd arg may be far
SUBB *,*,[*]+ 5A 4 I1 1 01 00000000 ;no validation yet
SUBB *,*,[*] 5A 4 I1 1 00 00000000 ;no validation yet
SUBB *,*,*[*] 5B 6 I6 1 00 00000000 ;no validation yet
SUBB *,*,#* 59 4 I1 1 00 00000000 ;no validation yet
SUBB *,[*]+ 7A 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUBB *,[*] 7A 3 I1 1 00 0000FFFe ;1st arg must be even
SUBB *,*[*] 7B 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUBB *,*,* 5B01 6 I3 1 00 00000000 ;3rd arg may be far
SUBB *,#* 79 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
SUBB *,* 7B01 5 I2 1 00 00000000 ;2nd arg may be far
SUBC *,[*]+ AA 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUBC *,[*] AA 3 I1 1 00 0000FFFe ;1st arg must be even
SUBC *,*[*] AB 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUBC *,#* A9 4 I1 1 00 00FeFFFF ;1st arg must be even
SUBC *,* AB01 5 I2 1 00 00000000 ;2nd arg may be far
SUBCB *,[*]+ BA 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
SUBCB *,[*] BA 3 I1 1 00 0000FFFe ;1st arg must be even
SUBCB *,*[*] BB 5 I6 1 00 00FeFFFe ;1st,3rd must be even
SUBCB *,#* B9 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
SUBCB *,* BB01 5 I2 1 00 00000000 ;2nd arg may be far
SHL *,#* 09 3 I1 1 00 0000FE0F ; F
SHL *,* 09 3 I1 1 00 0000FEFF ;
SHLB *,#* 19 3 I1 1 00 0000FF0F ;
SHLB *,* 19 3 I1 1 00 0000FFFF ;
SHLL *,#* 0D 3 I1 1 00 0000FF0F ;
SHLL *,* 0D 3 I1 1 00 0000FFFF ;
SHR *,#* 08 3 I1 1 00 0000FF0F ;word align
SHR *,* 08 3 I1 1 00 0000FFFF ;word align
SHRB *,#* 18 3 I1 1 00 0000FF0F ;byte align
SHRB *,* 18 3 I1 1 00 0000FFFF ;byte align
SHRL *,#* 0C 3 I1 1 00 0000FF0F ;long align
SHRL *,* 0C 3 I1 1 00 0000FFFF ;long align
SHRA *,#* 0A 3 I1 1 00 0000FF0F ;word align
SHRA *,* 0A 3 I1 1 00 0000FFFF ;word align
SHRAB *,#* 1A 3 I1 1 00 0000FF0F ;byte align
SHRAB *,* 1A 3 I1 1 00 0000FFFF ;byte align
SHRAL *,#* 0E 3 I1 1 00 0000FF0F ;long align
SHRAL *,* 0E 3 I1 1 00 0000FFFF ;long align
SETC "" F9 1 NOP 1 00 00000000 ;
SKIP "" 0000 2 NOP 1 00 00000000 ;
SKIP * 00 2 I1 1 00 00000000 ;
ST *,[*]+ C2 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
ST *,[*] C2 3 I1 1 00 0000FFFe ;1st arg must be even
ST *,*[*] C3 5 I6 1 00 FFFFFFFe ;1st,3rd must be even
ST *,* C301 5 I2 1 00 00000000 ;2nd arg may be far
STB *,[*]+ C6 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
STB *,[*] C6 3 I1 1 00 0000FFFe ;1st arg must be even
STB *,*[*] C7 5 I6 1 00 FFFFFFFe ;1st,3rd must be even
STB *,* C701 5 I2 1 00 00000000 ;2nd arg may be far
TRAP "" F7 1 NOP 1 00 00000000 ;
TIJMP *,[*],#* E2 4 I8 2 00 00FEFEFF ;
XCH *,*[*] 0B 5 I6 2 00 00FeFFFe ;1st,3rd must be even
XCH *,* 0B01 5 I2 2 0C 00000000 ;2nd arg may be far
XCHB *,*[*] 1B 5 I6 2 00 00FFFFFF ;
XCHB *,* 1B01 5 I2 2 0C 00000000 ;2nd arg may be far
XOR *,[*]+ 86 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
XOR *,[*] 86 3 I1 1 00 0000FFFe ;1st arg must be even
XOR *,*[*] 87 5 I6 1 00 00FeFFFe ;1st,3rd must be even
XOR *,#* 85 4 I1 1 00 00FeFFFF ;1st arg must be even
XOR *,* 8701 5 I2 1 00 00000000 ;2nd arg may be far
XORB *,[*]+ 96 3 I1 1 01 0000FFFe ;1st arg must be even, make odd
XORB *,[*] 96 3 I1 1 00 0000FFFe ;1st arg must be even
XORB *,*[*] 97 5 I6 1 00 00FFFFFF ;
XORB *,#* 95 3 I1 1 00 00FFFFFF ;odd args ok for byte operations
XORB *,* 9701 5 I2 1 00 00000000 ;2nd arg may be far

594
branches/dgg/LSource/bin/tasm180.tab
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@ -0,0 +1,594 @@
"TASM Z180 Assembler. "
/****************************************************************************
/* $Id: tasm80.tab 1.2 1998/02/28 14:31:22 toma Exp $
/****************************************************************************
/* This is the instruction set definition table
/* for the Z80 version of TASM.
/* Thomas N. Anderson, Speech Technology Incorporated
/* This table authored and submitted by Carl A. Wall, VE3APY.
/*
/* Class bits assigned as follows:
/* Bit-0 = Z80 (base instruction set)
/* Bit-1 = HD64180 (extended instructions)
/* See TASM manual for info on table structure.
/*
/*INSTR ARGS OP BYTES RULE CLASS SHIFT OR */
/*-------------------------------------------*/
ADC A,(HL) 8E 1 NOP 1
ADC A,(IX*) 8EDD 3 ZIX 1
ADC A,(IY*) 8EFD 3 ZIX 1
ADC A,A 8F 1 NOP 1
ADC A,B 88 1 NOP 1
ADC A,C 89 1 NOP 1
ADC A,D 8A 1 NOP 1
ADC A,E 8B 1 NOP 1
ADC A,H 8C 1 NOP 1
ADC A,L 8D 1 NOP 1
ADC A,* CE 2 NOP 1
ADC HL,BC 4AED 2 NOP 1
ADC HL,DE 5AED 2 NOP 1
ADC HL,HL 6AED 2 NOP 1
ADC HL,SP 7AED 2 NOP 1
ADD A,(HL) 86 1 NOP 1
ADD A,(IX*) 86DD 3 ZIX 1
ADD A,(IY*) 86FD 3 ZIX 1
ADD A,A 87 1 NOP 1
ADD A,B 80 1 NOP 1
ADD A,C 81 1 NOP 1
ADD A,D 82 1 NOP 1
ADD A,E 83 1 NOP 1
ADD A,H 84 1 NOP 1
ADD A,L 85 1 NOP 1
ADD A,* C6 2 NOP 1
ADD HL,BC 09 1 NOP 1
ADD HL,DE 19 1 NOP 1
ADD HL,HL 29 1 NOP 1
ADD HL,SP 39 1 NOP 1
ADD IX,BC 09DD 2 NOP 1
ADD IX,DE 19DD 2 NOP 1
ADD IX,IX 29DD 2 NOP 1
ADD IX,SP 39DD 2 NOP 1
ADD IY,BC 09FD 2 NOP 1
ADD IY,DE 19FD 2 NOP 1
ADD IY,IY 29FD 2 NOP 1
ADD IY,SP 39FD 2 NOP 1
AND (HL) A6 1 NOP 1
AND (IX*) A6DD 3 ZIX 1
AND (IY*) A6FD 3 ZIX 1
AND A A7 1 NOP 1
AND B A0 1 NOP 1
AND C A1 1 NOP 1
AND D A2 1 NOP 1
AND E A3 1 NOP 1
AND H A4 1 NOP 1
AND L A5 1 NOP 1
AND * E6 2 NOP 1
BIT *,(HL) 46CB 2 ZBIT 1
BIT *,(IX*) CBDD 4 ZBIT 1 0 4600
BIT *,(IY*) CBFD 4 ZBIT 1 0 4600
BIT *,A 47CB 2 ZBIT 1
BIT *,B 40CB 2 ZBIT 1
BIT *,C 41CB 2 ZBIT 1
BIT *,D 42CB 2 ZBIT 1
BIT *,E 43CB 2 ZBIT 1
BIT *,H 44CB 2 ZBIT 1
BIT *,L 45CB 2 ZBIT 1
CALL C,* DC 3 NOP 1
CALL M,* FC 3 NOP 1
CALL NC,* D4 3 NOP 1
CALL NZ,* C4 3 NOP 1
CALL P,* F4 3 NOP 1
CALL PE,* EC 3 NOP 1
CALL PO,* E4 3 NOP 1
CALL Z,* CC 3 NOP 1
CALL * CD 3 NOP 1
CCF "" 3F 1 NOP 1
CP (HL) BE 1 NOP 1
CP (IX*) BEDD 3 ZIX 1
CP (IY*) BEFD 3 ZIX 1
CP A BF 1 NOP 1
CP B B8 1 NOP 1
CP C B9 1 NOP 1
CP D BA 1 NOP 1
CP E BB 1 NOP 1
CP H BC 1 NOP 1
CP L BD 1 NOP 1
CP * FE 2 NOP 1
CPD "" A9ED 2 NOP 1
CPDR "" B9ED 2 NOP 1
CPIR "" B1ED 2 NOP 1
CPI "" A1ED 2 NOP 1
CPL "" 2F 1 NOP 1
DAA "" 27 1 NOP 1
DEC (HL) 35 1 NOP 1
DEC (IX*) 35DD 3 ZIX 1
DEC (IY*) 35FD 3 ZIX 1
DEC A 3D 1 NOP 1
DEC B 05 1 NOP 1
DEC BC 0B 1 NOP 1
DEC C 0D 1 NOP 1
DEC D 15 1 NOP 1
DEC DE 1B 1 NOP 1
DEC E 1D 1 NOP 1
DEC H 25 1 NOP 1
DEC HL 2B 1 NOP 1
DEC IX 2BDD 2 NOP 1
DEC IY 2BFD 2 NOP 1
DEC L 2D 1 NOP 1
DEC SP 3B 1 NOP 1
DI "" F3 1 NOP 1
DJNZ * 10 2 R1 1
EI "" FB 1 NOP 1
EX (SP),HL E3 1 NOP 1
EX (SP),IX E3DD 2 NOP 1
EX (SP),IY E3FD 2 NOP 1
EX AF,AF' 08 1 NOP 1
EX DE,HL EB 1 NOP 1
EXX "" D9 1 NOP 1
HALT "" 76 1 NOP 1
IM 0 46ED 2 NOP 1
IM 1 56ED 2 NOP 1
IM 2 5EED 2 NOP 1
/* Alternate form of above
IM0 46ED 2 NOP 1
IM1 56ED 2 NOP 1
IM2 5EED 2 NOP 1
IN A,(C) 78ED 2 NOP 1
IN B,(C) 40ED 2 NOP 1
IN C,(C) 48ED 2 NOP 1
IN D,(C) 50ED 2 NOP 1
IN E,(C) 58ED 2 NOP 1
IN H,(C) 60ED 2 NOP 1
IN L,(C) 68ED 2 NOP 1
IN A,(*) DB 2 NOP 1
IN0 A,(*) 38ED 3 NOP 1
IN0 B,(*) 00ED 3 NOP 1
IN0 C,(*) 08ED 3 NOP 1
IN0 D,(*) 10ED 3 NOP 1
IN0 E,(*) 18ED 3 NOP 1
IN0 H,(*) 20ED 3 NOP 1
IN0 L,(*) 28ED 3 NOP 1
INC (HL) 34 1 NOP 1
INC (IX*) 34DD 3 ZIX 1
INC (IY*) 34FD 3 ZIX 1
INC A 3C 1 NOP 1
INC B 04 1 NOP 1
INC BC 03 1 NOP 1
INC C 0C 1 NOP 1
INC D 14 1 NOP 1
INC DE 13 1 NOP 1
INC E 1C 1 NOP 1
INC H 24 1 NOP 1
INC HL 23 1 NOP 1
INC IX 23DD 2 NOP 1
INC IY 23FD 2 NOP 1
INC L 2C 1 NOP 1
INC SP 33 1 NOP 1
IND "" AAED 2 NOP 1
INDR "" BAED 2 NOP 1
INI "" A2ED 2 NOP 1
INIR "" B2ED 2 NOP 1
JP (HL) E9 1 NOP 1
JP (IX) E9DD 2 NOP 1
JP (IY) E9FD 2 NOP 1
JP C,* DA 3 NOP 1
JP M,* FA 3 NOP 1
JP NC,* D2 3 NOP 1
JP NZ,* C2 3 NOP 1
JP P,* F2 3 NOP 1
JP PE,* EA 3 NOP 1
JP PO,* E2 3 NOP 1
JP Z,* CA 3 NOP 1
JP * C3 3 NOP 1
JR C,* 38 2 R1 1
JR NC,* 30 2 R1 1
JR NZ,* 20 2 R1 1
JR Z,* 28 2 R1 1
JR * 18 2 R1 1
LD (BC),A 02 1 NOP 1
LD (DE),A 12 1 NOP 1
LD (HL),A 77 1 NOP 1
LD (HL),B 70 1 NOP 1
LD (HL),C 71 1 NOP 1
LD (HL),D 72 1 NOP 1
LD (HL),E 73 1 NOP 1
LD (HL),H 74 1 NOP 1
LD (HL),L 75 1 NOP 1
LD (HL),* 36 2 NOP 1
LD (IX*),A 77DD 3 ZIX 1
LD (IX*),B 70DD 3 ZIX 1
LD (IX*),C 71DD 3 ZIX 1
LD (IX*),D 72DD 3 ZIX 1
LD (IX*),E 73DD 3 ZIX 1
LD (IX*),H 74DD 3 ZIX 1
LD (IX*),L 75DD 3 ZIX 1
LD (IX*),* 36DD 4 ZIX 1
LD (IY*),A 77FD 3 ZIX 1
LD (IY*),B 70FD 3 ZIX 1
LD (IY*),C 71FD 3 ZIX 1
LD (IY*),D 72FD 3 ZIX 1
LD (IY*),E 73FD 3 ZIX 1
LD (IY*),H 74FD 3 ZIX 1
LD (IY*),L 75FD 3 ZIX 1
LD (IY*),* 36FD 4 ZIX 1
LD (*),A 32 3 NOP 1
LD (*),BC 43ED 4 NOP 1
LD (*),DE 53ED 4 NOP 1
LD (*),HL 22 3 NOP 1
LD (*),IX 22DD 4 NOP 1
LD (*),IY 22FD 4 NOP 1
LD (*),SP 73ED 4 NOP 1
LD A,(BC) 0A 1 NOP 1
LD A,(DE) 1A 1 NOP 1
LD A,(HL) 7E 1 NOP 1
LD A,(IX*) 7EDD 3 ZIX 1
LD A,(IY*) 7EFD 3 ZIX 1
LD A,A 7F 1 NOP 1
LD A,B 78 1 NOP 1
LD A,C 79 1 NOP 1
LD A,D 7A 1 NOP 1
LD A,E 7B 1 NOP 1
LD A,H 7C 1 NOP 1
LD A,I 57ED 2 NOP 1
LD A,L 7D 1 NOP 1
LD A,R 5FED 2 NOP 1
LD A,(*) 3A 3 NOP 1
LD A,* 3E 2 NOP 1
LD B,(HL) 46 1 NOP 1
LD B,(IX*) 46DD 3 ZIX 1
LD B,(IY*) 46FD 3 ZIX 1
LD B,A 47 1 NOP 1
LD B,B 40 1 NOP 1
LD B,C 41 1 NOP 1
LD B,D 42 1 NOP 1
LD B,E 43 1 NOP 1
LD B,H 44 1 NOP 1
LD B,L 45 1 NOP 1
LD B,* 06 2 NOP 1
LD BC,(*) 4BED 4 NOP 1
LD BC,* 01 3 NOP 1
LD C,(HL) 4E 1 NOP 1
LD C,(IX*) 4EDD 3 ZIX 1
LD C,(IY*) 4EFD 3 ZIX 1
LD C,A 4F 1 NOP 1
LD C,B 48 1 NOP 1
LD C,C 49 1 NOP 1
LD C,D 4A 1 NOP 1
LD C,E 4B 1 NOP 1
LD C,H 4C 1 NOP 1
LD C,L 4D 1 NOP 1
LD C,* 0E 2 NOP 1
LD D,(HL) 56 1 NOP 1
LD D,(IX*) 56DD 3 ZIX 1
LD D,(IY*) 56FD 3 ZIX 1
LD D,A 57 1 NOP 1
LD D,B 50 1 NOP 1
LD D,C 51 1 NOP 1
LD D,D 52 1 NOP 1
LD D,E 53 1 NOP 1
LD D,H 54 1 NOP 1
LD D,L 55 1 NOP 1
LD D,* 16 2 NOP 1
LD DE,(*) 5BED 4 NOP 1
LD DE,* 11 3 NOP 1
LD E,(HL) 5E 1 NOP 1
LD E,(IX*) 5EDD 3 ZIX 1
LD E,(IY*) 5EFD 3 ZIX 1
LD E,A 5F 1 NOP 1
LD E,B 58 1 NOP 1
LD E,C 59 1 NOP 1
LD E,D 5A 1 NOP 1
LD E,E 5B 1 NOP 1
LD E,H 5C 1 NOP 1
LD E,L 5D 1 NOP 1
LD E,* 1E 2 NOP 1
LD H,(HL) 66 1 NOP 1
LD H,(IX*) 66DD 3 ZIX 1
LD H,(IY*) 66FD 3 ZIX 1
LD H,A 67 1 NOP 1
LD H,B 60 1 NOP 1
LD H,C 61 1 NOP 1
LD H,D 62 1 NOP 1
LD H,E 63 1 NOP 1
LD H,H 64 1 NOP 1
LD H,L 65 1 NOP 1
LD H,* 26 2 NOP 1
LD HL,(*) 2A 3 NOP 1
LD HL,* 21 3 NOP 1
LD I,A 47ED 2 NOP 1
LD IX,(*) 2ADD 4 NOP 1
LD IX,* 21DD 4 NOP 1
LD IY,(*) 2AFD 4 NOP 1
LD IY,* 21FD 4 NOP 1
LD L,(HL) 6E 1 NOP 1
LD L,(IX*) 6EDD 3 ZIX 1
LD L,(IY*) 6EFD 3 ZIX 1
LD L,A 6F 1 NOP 1
LD L,B 68 1 NOP 1
LD L,C 69 1 NOP 1
LD L,D 6A 1 NOP 1
LD L,E 6B 1 NOP 1
LD L,H 6C 1 NOP 1
LD L,L 6D 1 NOP 1
LD L,* 2E 2 NOP 1
LD R,A 4FED 2 NOP 1
LD SP,(*) 7BED 4 NOP 1
LD SP,HL F9 1 NOP 1
LD SP,IX F9DD 2 NOP 1
LD SP,IY F9FD 2 NOP 1
LD SP,* 31 3 NOP 1
LDD "" A8ED 2 NOP 1
LDDR "" B8ED 2 NOP 1
LDI "" A0ED 2 NOP 1
LDIR "" B0ED 2 NOP 1
NEG "" 44ED 2 NOP 1
NOP "" 00 1 NOP 1
MLT BC 4CED 2 NOP 1
MLT DE 5CED 2 NOP 1
MLT HL 6CED 2 NOP 1
MLT SP 7CED 2 NOP 1
OR (HL) B6 1 NOP 1
OR (IX*) B6DD 3 ZIX 1
OR (IY*) B6FD 3 ZIX 1
OR A B7 1 NOP 1
OR B B0 1 NOP 1
OR C B1 1 NOP 1
OR D B2 1 NOP 1
OR E B3 1 NOP 1
OR H B4 1 NOP 1
OR L B5 1 NOP 1
OR * F6 2 NOP 1
OTDM "" 8BED 2 NOP 1
OTDMR "" 9BED 2 NOP 1
OTDR "" BBED 2 NOP 1
OTIM "" 83ED 2 NOP 1
OTIMR "" 93ED 2 NOP 1
OTIR "" B3ED 2 NOP 1
OUT (C),A 79ED 2 NOP 1
OUT (C),B 41ED 2 NOP 1
OUT (C),C 49ED 2 NOP 1
OUT (C),D 51ED 2 NOP 1
OUT (C),E 59ED 2 NOP 1
OUT (C),H 61ED 2 NOP 1
OUT (C),L 69ED 2 NOP 1
OUT (*),A D3 2 NOP 1
OUT0 (*),A 39ED 3 NOP 1
OUT0 (*),B 01ED 3 NOP 1
OUT0 (*),C 09ED 3 NOP 1
OUT0 (*),D 11ED 3 NOP 1
OUT0 (*),E 19ED 3 NOP 1
OUT0 (*),H 21ED 3 NOP 1
OUT0 (*),L 29ED 3 NOP 1
OUTD "" ABED 2 NOP 1
OUTI "" A3ED 2 NOP 1
POP AF F1 1 NOP 1
POP BC C1 1 NOP 1
POP DE D1 1 NOP 1
POP HL E1 1 NOP 1
POP IX E1DD 2 NOP 1
POP IY E1FD 2 NOP 1
PUSH AF F5 1 NOP 1
PUSH BC C5 1 NOP 1
PUSH DE D5 1 NOP 1
PUSH HL E5 1 NOP 1
PUSH IX E5DD 2 NOP 1
PUSH IY E5FD 2 NOP 1
RES *,(HL) 86CB 2 ZBIT 1
RES *,(IX*) CBDD 4 ZBIT 1 0 8600
RES *,(IY*) CBFD 4 ZBIT 1 0 8600
RES *,A 87CB 2 ZBIT 1
RES *,B 80CB 2 ZBIT 1
RES *,C 81CB 2 ZBIT 1
RES *,D 82CB 2 ZBIT 1
RES *,E 83CB 2 ZBIT 1
RES *,H 84CB 2 ZBIT 1
RES *,L 85CB 2 ZBIT 1
RET "" C9 1 NOP 1
RET C D8 1 NOP 1
RET M F8 1 NOP 1
RET NC D0 1 NOP 1
RET NZ C0 1 NOP 1
RET P F0 1 NOP 1
RET PE E8 1 NOP 1
RET PO E0 1 NOP 1
RET Z C8 1 NOP 1
RETI "" 4DED 2 NOP 1
RETN "" 45ED 2 NOP 1
RL (HL) 16CB 2 NOP 1
RL (IX*) CBDD 4 ZIX 1 0 1600
RL (IY*) CBFD 4 ZIX 1 0 1600
RL A 17CB 2 NOP 1
RL B 10CB 2 NOP 1
RL C 11CB 2 NOP 1
RL D 12CB 2 NOP 1
RL E 13CB 2 NOP 1
RL H 14CB 2 NOP 1
RL L 15CB 2 NOP 1
RLA "" 17 1 NOP 1
RLC (HL) 06CB 2 NOP 1
RLC (IX*) CBDD 4 ZIX 1 0 0600
RLC (IY*) CBFD 4 ZIX 1 0 0600
RLC A 07CB 2 NOP 1
RLC B 00CB 2 NOP 1
RLC C 01CB 2 NOP 1
RLC D 02CB 2 NOP 1
RLC E 03CB 2 NOP 1
RLC H 04CB 2 NOP 1
RLC L 05CB 2 NOP 1
RLCA "" 07 1 NOP 1
RLD "" 6FED 2 NOP 1
RR (HL) 1ECB 2 NOP 1
RR (IX*) CBDD 4 ZIX 1 0 1E00
RR (IY*) CBFD 4 ZIX 1 0 1E00
RR A 1FCB 2 NOP 1
RR B 18CB 2 NOP 1
RR C 19CB 2 NOP 1
RR D 1ACB 2 NOP 1
RR E 1BCB 2 NOP 1
RR H 1CCB 2 NOP 1
RR L 1DCB 2 NOP 1
RRA "" 1F 1 NOP 1
RRC (HL) 0ECB 2 NOP 1
RRC (IX*) CBDD 4 ZIX 1 0 0E00
RRC (IY*) CBFD 4 ZIX 1 0 0E00
RRC A 0FCB 2 NOP 1
RRC B 08CB 2 NOP 1
RRC C 09CB 2 NOP 1
RRC D 0ACB 2 NOP 1
RRC E 0BCB 2 NOP 1
RRC H 0CCB 2 NOP 1
RRC L 0DCB 2 NOP 1
RRCA "" 0F 1 NOP 1
RRD "" 67ED 2 NOP 1
RST 00H C7 1 NOP 1
RST 08H CF 1 NOP 1
RST 10H D7 1 NOP 1
RST 18H DF 1 NOP 1
RST 20H E7 1 NOP 1
RST 28H EF 1 NOP 1
RST 30H F7 1 NOP 1
RST 38H FF 1 NOP 1
/* Alternate form of above
RST 00 C7 1 NOP 1
RST 08 CF 1 NOP 1
RST 10 D7 1 NOP 1
RST 18 DF 1 NOP 1
RST 20 E7 1 NOP 1
RST 28 EF 1 NOP 1
RST 30 F7 1 NOP 1
RST 38 FF 1 NOP 1
SBC A,(HL) 9E 1 NOP 1
SBC A,(IX*) 9EDD 3 ZIX 1
SBC A,(IY*) 9EFD 3 ZIX 1
SBC A,A 9F 1 NOP 1
SBC A,B 98 1 NOP 1
SBC A,C 99 1 NOP 1
SBC A,D 9A 1 NOP 1
SBC A,E 9B 1 NOP 1
SBC A,H 9C 1 NOP 1
SBC A,L 9D 1 NOP 1
SBC HL,BC 42ED 2 NOP 1
SBC HL,DE 52ED 2 NOP 1
SBC HL,HL 62ED 2 NOP 1
SBC HL,SP 72ED 2 NOP 1
SBC A,* DE 2 NOP 1
SCF "" 37 1 NOP 1
SET *,(HL) C6CB 2 ZBIT 1
SET *,(IX*) CBDD 4 ZBIT 1 0 C600
SET *,(IY*) CBFD 4 ZBIT 1 0 C600
SET *,A C7CB 2 ZBIT 1
SET *,B C0CB 2 ZBIT 1
SET *,C C1CB 2 ZBIT 1
SET *,D C2CB 2 ZBIT 1
SET *,E C3CB 2 ZBIT 1
SET *,H C4CB 2 ZBIT 1
SET *,L C5CB 2 ZBIT 1
SLA (HL) 26CB 2 NOP 1
SLA (IX*) CBDD 4 ZIX 1 0 2600
SLA (IY*) CBFD 4 ZIX 1 0 2600
SLA A 27CB 2 NOP 1
SLA B 20CB 2 NOP 1
SLA C 21CB 2 NOP 1
SLA D 22CB 2 NOP 1
SLA E 23CB 2 NOP 1
SLA H 24CB 2 NOP 1
SLA L 25CB 2 NOP 1
SLP "" 76ED 2 NOP 1
SRA (HL) 2ECB 2 NOP 1
SRA (IX*) CBDD 4 ZIX 1 0 2E00
SRA (IY*) CBFD 4 ZIX 1 0 2E00
SRA A 2FCB 2 NOP 1
SRA B 28CB 2 NOP 1
SRA C 29CB 2 NOP 1
SRA D 2ACB 2 NOP 1
SRA E 2BCB 2 NOP 1
SRA H 2CCB 2 NOP 1
SRA L 2DCB 2 NOP 1
SRL (HL) 3ECB 2 NOP 1
SRL (IX*) CBDD 4 ZIX 1 0 3E00
SRL (IY*) CBFD 4 ZIX 1 0 3E00
SRL A 3FCB 2 NOP 1
SRL B 38CB 2 NOP 1
SRL C 39CB 2 NOP 1
SRL D 3ACB 2 NOP 1
SRL E 3BCB 2 NOP 1
SRL H 3CCB 2 NOP 1
SRL L 3DCB 2 NOP 1
SUB (HL) 96 1 NOP 1
SUB (IX*) 96DD 3 ZIX 1
SUB (IY*) 96FD 3 ZIX 1
SUB A 97 1 NOP 1
SUB B 90 1 NOP 1
SUB C 91 1 NOP 1
SUB D 92 1 NOP 1
SUB E 93 1 NOP 1
SUB H 94 1 NOP 1
SUB L 95 1 NOP 1
SUB * D6 2 NOP 1
TST A 3CED 2 NOP 1
TST B 04ED 2 NOP 1
TST C 0CED 2 NOP 1
TST D 14ED 2 NOP 1
TST E 1CED 2 NOP 1
TST H 24ED 2 NOP 1
TST L 2CED 2 NOP 1
TST (HL) 34ED 2 NOP 1
TST * 64ED 3 NOP 1
TSTIO * 74ED 3 NOP 1
XOR (HL) AE 1 NOP 1
XOR (IX*) AEDD 3 ZIX 1
XOR (IY*) AEFD 3 ZIX 1
XOR A AF 1 NOP 1
XOR B A8 1 NOP 1
XOR C A9 1 NOP 1
XOR D AA 1 NOP 1
XOR E AB 1 NOP 1
XOR H AC 1 NOP 1
XOR L AD 1 NOP 1
XOR * EE 2 NOP 1
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