Reintegrate wbw -> trunk

Clean.cmd

@@ -3,6 +3,7 @@
 setlocal
 
 pushd Source && call Clean && popd
+pushd Images && call Clean && popd
 
 if exist *.img del *.img /Q
 if exist *.log del *.log /Q

Doc/Build.txt

@@ -51,21 +51,22 @@ process.  In order to customize your settings, you
 need to modify an existing configuration file or
 create your own.
 
-If you look in the Source directory, you will see
-a series of files named config_xxxx_yyyy.asm.  Each of
+Configuration files are found in the Source\BIOS\Config
+directory.  If you look in the this directory, you will see
+a series of files named XXXX_yyyy.asm.  Each of
 them corresponds to one of the standard configurations
 listed in the ROMList.txt file.
 
 You have two choices.  You can simply modify the existing
 configuration file that is closest to your situation, or
-you can copy it to a new config_xxxx_yyyy.asm file and modify
+you can copy it to a new XXXX_yyyy.asm file and modify
 that.  I recommend that you copy one to your own name so
 that you will always have the unmodified standard configuration
 files left in place.  So, for example, you could just
-copy config_ZETA_std.asm to config_ZETA_wayne.asm.  You MUST
-name your config file as config_xxxx_yyyy.asm.  The xxxx's
-must match your platform (N8VEM, ZETA, N8, S2I, or S100).
-The yyyy's can be whatever you want.
+copy ZETA_std.asm to ZETA_wayne.asm.  You MUST
+name your config file as XXXX_yyyy.asm.  The XXXX portion
+must match your platform (N8VEM, ZETA, ZETA2, N8, UNA).
+The yyyy portion can be whatever you want.
 
 The config files are simply text files with various
 settings.  Open your target config file with your
@@ -93,30 +94,30 @@ ROM disk.  The build process will determine
 which subdirectories to include files from based
 on the following rules:
 
-First, all files from either std_512 or std_1024 will
-be incuded depending on on the size of the ROM you
+First, all files from either ROM_512KB or ROM_1024KB will
+be included depending on on the size of the ROM you
 are building.  If you are building a 512KB ROM, then
-all the files from std_512KB will be included.  If you
-are building a 1MB ROM, then all the files from std_1024KB
-will be included.  Essentialy, the files in std_1204KB are
-a superset of the ones in std_512KB because there is more
+all the files from ROM_512KB will be included.  If you
+are building a 1MB ROM, then all the files from ROM_1024KB
+will be included.  Essentialy, the files in ROM_1204KB are
+a superset of the ones in ROM_512KB because there is more
 space available for the ROM drive.
 
 Second, all files from the directory that corresponds to
 your configuration file will be included.  If you build
-the "ZETA_std" configuration, all files in cfg_ZETA_std will
+the "ZETA_std" configuration, all files in ZETA_std will
 be added.  Note that these files will be in addition
-to the files from the std_XXXKB directory.
+to the files from the ROM_XXXKB directory.
 
-If you created your own config file (like config_ZETA_wayne.asm
+If you created your own config file (like ZETA_wayne.asm
 described above), you MUST create a subdirectory within
 the RomDsk directory and populate it with the files
 you want added.  Normally, you would include the
 files from the original standard config.  So, if
-you created config_ZETA_wayne.asm from config_ZETA_std.asm,
+you created ZETA_wayne.asm from ZETA_std.asm,
 then you would create a subdirectory in RomDsk called
-cfg_ZETA_wayne and copy all the files from cfg_ZETA_std to
-cfg_ZETA_wayne.
+ZETA_wayne and copy all the files from ZETA_std to
+ZETA_wayne.
 
 3. Run the Build Process
 ------------------------
@@ -136,23 +137,22 @@ unless you renamed it.
 First, you will need to build the components that are
 common to all configurations.  These components do not
 require any configuration.  To build these, use the
-following commands and ensure that they complete
+following command and ensure it completes
 without error:
 
-	BuildZCPR-DJ
-	BuildApps2
+	BuildCommon
 
-To run the main build and be prompted for required information,
-just enter "Build".  You will be prompted for the information
-described below and the build should run.  If an error is
-encountered, the build should stop and display an error
-in red text.
+To run the configuration specific build and be prompted
+for required information, just enter "Build".  You will
+be prompted for the information described below and the
+build should run.  If an error is encountered, the build
+should stop and display an error in red text.
 
 If you immediately receive the error "the execution of 
 scripts is disabled on this system", then you will need to 
 change the PowerShell Execution-Polcy to "RemoteSigned".
 To do this, you need to right-click on FixPowerShell.cmd and
-choose "Run as Administrator" to make the change.  If is
+choose "Run as Administrator" to make the change.  It is
 critical that you right-click and use "Run as Administrator"
 or the change will not work (you will get an error
 indicating "Access to the registry denied" if you fail to
@@ -164,7 +164,7 @@ which you will need to provide (don't worry, it is simple):
 Platform:
 
 Respond with the name of the platform that you are targeting.
-It must be one of N8VEM, ZETA, N8, S2I, or S100.
+It must be one of N8VEM, ZETA, ZETA2, N8, or UNA.
 
 Configuration:
 
@@ -180,7 +180,7 @@ ROM Size [512|1024]:
 Respond with either "512" for a 512KB ROM build or "1024" for a
 1MB ROM build.  Only the two choices are possible at this time.
 It is important that you choose a ROM size that is no larger than
-the szie of the ROM you will ultimately be burning.  This is 
+the size of the ROM you will ultimately be burning.  This is 
 dependant on your hardware.
 
 At this point, the build should run and you will see output related
@@ -190,7 +190,7 @@ cause the build to stop immediately and display an error message
 in red.
 
 You will see some lines in the output indicating the amount of
-space variouis components have taken.  You should check these
+space various components have taken.  You should check these
 to make sure you do not see any negative numbers which would
 indicate that you have included too many features/drivers for
 the available memory space.  Here are examples of the lines
@@ -209,11 +209,11 @@ showing the space used:
 If you look in the Output directory.  You should find the following files:
 
      <config>.rom - binary ROM image to burn to EEPROM
-     <config>.sys - system image that can be written to the start of a
-                    disk to enable boot from disk functionality
      <config>.com - executable version of the system image that can be
                     copied via xmodem to a running system to test
                     the build.
+     <config>.img - system image that can be written to an SD/CF Card
+                    and loaded via the UNA FS FAT loader.
 
 The actual ROM image is the file ending in .rom.  It should be exactly
 512KB or 1MB depending on the ROM size you chose.  Simply burn the .rom
@@ -236,7 +236,7 @@ Example Build Run
 -----------------
 
 C:\Users\WWarthen\Projects\N8VEM\Build\RomWBW>Build.cmd
-Platform [N8VEM|ZETA|N8|S2I|S100]: ZETA
+Platform [N8VEM|ZETA|N8|UNA|S100]: ZETA
 Configurations available:
  > ppp
  > std

ReadMe.txt

@@ -8,8 +8,8 @@ Builders: Wayne Warthen (wwarthen@gmail.com)
           Douglas Goodall (douglas_goodall@mac.com)
           David Giles (vk5dg@internode.on.net)
 
-Updated: 2015-03-22
-Version: 2.7.1
+Updated: 2015-04-02
+Version: 2.7.0
 
 This is an adaptation of CP/M-80 2.2 and ZSDOS/ZCPR
 targeting ROMs for all N8VEM Z80 hardware variations
@@ -90,7 +90,7 @@ UNA Variant
 -----------
 
 RomWBW will now run under it's native BIOS (HBIOS) or
-under UNA BIOS (UBIOS).  There are pre-built ROM
+under UNA BIOS (UBIOS).  There is a pre-built ROM
 images for UNA in the Output directory.
 
 CP/M vs. ZSystem
@@ -100,22 +100,20 @@ There are two OS variants included in this distribution
 and you may choose which one you prefer to use.
 
 The traditional Digital Research (DRI) CP/M code is the first
-choice.  The Doc
-directory contains a manual for CP/M usage (cpm22-m.pdf).
-If you are new to the N8VEM systems, I would currently
-recommend using the CP/M variant to start with simply
-because they have gone through more testing and you
-are less likely to encounter problems.
+choice.  The Doc directory contains a manual for CP/M
+usage (cpm22-m.pdf).  If you are new to the N8VEM systems,
+I would currently recommend using the CP/M variant to
+start with simply because they have gone through more
+testing and you are less likely to encounter problems.
 
 The other choice is to use the most popular non-DRI
 CP/M "clone" which is generally referred to as
-ZSystem.  These are intended to be
-functionally equivalent to CP/M and should run all
-CP/M 2.2 code.  They are optimized for the Z80 CPU
-(as opposed to 8080 for CP/M) and have some potentially
-useful improvements.  Please refer to the Doc directory
-and look at the files for zsdos and zcpr (zsdos.pdf &
-zcpr.doc as well as ZSystem.txt).
+ZSystem.  These are intended to be functionally equivalent
+to CP/M and should run all CP/M 2.2 code.  They are
+optimized for the Z80 CPU (as opposed to 8080 for CP/M)
+and have some potentially useful improvements.  Please
+refer to the Doc directory and look at the files for
+zsdos and zcpr (zsdos.pdf & zcpr.doc as well as ZSystem.txt).
 
 Both variants are now included in the pre-built ROM images.
 You will be given the choice to boot either CP/M or

RomList.txt

@@ -67,7 +67,7 @@ custom build.
     - 512KB ROM, 512KB RAM
     - 38.4KB serial console baud rate
     - Basic ROM/RAM disk
-    - IDE support via DISKIO
+    - PPIDE support via built-in PPI
     - Drives A:=ROM, B:=RAM, C:=PPIDE0-00, D:=PPIDE0-01, E:=PPIDE0-02, F:=PPIDE0-03
     
   N8VEM_ppisd.rom for N8VEM Z80 SBC V1/V2 + PPISD:
@@ -148,9 +148,16 @@ custom build.
     - 38.4KB serial console baud rate
     - Basic ROM/RAM disk
     - Floppy support via built-in FDC
-    - PPIDE support via built-in PPI
     - Drives A:=ROM, B:=RAM, C:=FD0, D:=FD1, E:=PPIDE00-0, F:=PPIDE0-01, G:=PPIDE0-02, H:=PPIDE0-03
 
+  ZETA_ppide.rom for Zeta Z80 SBC + PPIDE:
+    - 512KB ROM, 512KB RAM
+    - 38.4KB serial console baud rate
+    - Basic ROM/RAM disk
+    - Floppy support via built-in FDC
+    - PPIDE support via built-in PPI
+    - Drives A:=ROM, B:=RAM, C:=PPIDE0-00, D:=PPIDE0-01, E:=PPIDE0-02, F:=PPIDE0-03
+    
   ZETA_ppisd.rom for Zeta Z80 SBC + PPISD:
     - 512KB ROM, 512KB RAM
     - 38.4KB serial console baud rate
@@ -181,6 +188,14 @@ custom build.
     - PPIDE support via built-in PPI
     - Drives A:=ROM, B:=RAM, C:=FD0, D:=FD1, E:=PPIDE00-0, F:=PPIDE0-01, G:=PPIDE0-02, H:=PPIDE0-03
 
+  ZETA2_ppide.rom for Zeta 2 Z80 SBC + PPIDE:
+    - 512KB ROM, 512KB RAM
+    - 38.4KB serial console baud rate
+    - Basic ROM/RAM disk
+    - Floppy support via built-in FDC
+    - PPIDE support via built-in PPI
+    - Drives A:=ROM, B:=RAM, C:=PPIDE0-00, D:=PPIDE0-01, E:=PPIDE0-02, F:=PPIDE0-03
+    
   ZETA2_ppisd.rom for Zeta 2 Z80 SBC + PPISD:
     - 512KB ROM, 512KB RAM
     - 38.4KB serial console baud rate

Source/BIOS/Config/mk4_diskio3.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	18432		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_ASCI	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_ASCI	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -103,17 +103,17 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 #DEFINE		AUTOCMD	""		; AUTO STARTUP COMMAND FOR CP/M
 ;
-; 18.432MHz XTAL @ FULL SPEED, 38.4Kbps
+; 18.432MHz OSC @ FULL SPEED, 38.4Kbps
 ;
-;Z180_CLKDIV	.EQU	1		; 0=XTAL/2, 1=XTAL, 2=XTAL*2
+;Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC, 2=OSC*2
 ;Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
 ;Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
 ;Z180_CNTLB0	.EQU	20H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT
 ;Z180_CNTLB1	.EQU	20H		; SERIAL PORT 1 DIV, SEE Z180 CLOCKING DOCUMENT
 ;
-; 18.432MHz XTAL @ DOUBLE SPEED, 38.4Kbps
+; 18.432MHz OSC @ DOUBLE SPEED, 38.4Kbps
 ;
-Z180_CLKDIV	.EQU	2		; 0=XTAL/2, 1=XTAL, 2=XTAL*2
+Z180_CLKDIV	.EQU	2		; 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
 Z180_IOWAIT	.EQU	3		; IO WAIT STATES TO INSERT (0-3)
 Z180_CNTLB0	.EQU	21H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT

Source/BIOS/Config/mk4_propio.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	18432		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_ASCI	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_ASCI	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -103,17 +103,17 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 #DEFINE		AUTOCMD	""		; AUTO STARTUP COMMAND FOR CP/M
 ;
-; 18.432MHz XTAL @ FULL SPEED, 38.4Kbps
+; 18.432MHz OSC @ FULL SPEED, 38.4Kbps
 ;
-;Z180_CLKDIV	.EQU	1		; 0=XTAL/2, 1=XTAL, 2=XTAL*2
+;Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC, 2=OSC*2
 ;Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
 ;Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
 ;Z180_CNTLB0	.EQU	20H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT
 ;Z180_CNTLB1	.EQU	20H		; SERIAL PORT 1 DIV, SEE Z180 CLOCKING DOCUMENT
 ;
-; 18.432MHz XTAL @ DOUBLE SPEED, 38.4Kbps
+; 18.432MHz OSC @ DOUBLE SPEED, 38.4Kbps
 ;
-Z180_CLKDIV	.EQU	2		; 0=XTAL/2, 1=XTAL, 2=XTAL*2
+Z180_CLKDIV	.EQU	2		; 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
 Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
 Z180_CNTLB0	.EQU	21H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT

Source/BIOS/Config/mk4_std.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	18432		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_ASCI	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_ASCI	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -103,17 +103,17 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 #DEFINE		AUTOCMD	""		; AUTO STARTUP COMMAND FOR CP/M
 ;
-; 18.432MHz XTAL @ FULL SPEED, 38.4Kbps
+; 18.432MHz OSC @ FULL SPEED, 38.4Kbps
 ;
-;Z180_CLKDIV	.EQU	1		; 0=XTAL/2, 1=XTAL, 2=XTAL*2
+;Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC, 2=OSC*2
 ;Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
 ;Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
 ;Z180_CNTLB0	.EQU	20H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT
 ;Z180_CNTLB1	.EQU	20H		; SERIAL PORT 1 DIV, SEE Z180 CLOCKING DOCUMENT
 ;
-; 18.432MHz XTAL @ DOUBLE SPEED, 38.4Kbps
+; 18.432MHz OSC @ DOUBLE SPEED, 38.4Kbps
 ;
-Z180_CLKDIV	.EQU	2		; 0=XTAL/2, 1=XTAL, 2=XTAL*2
+Z180_CLKDIV	.EQU	2		; 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	1		; MEMORY WAIT STATES TO INSERT (0-3)
 Z180_IOWAIT	.EQU	1		; IO WAIT STATES TO INSERT (0-3)
 Z180_CNTLB0	.EQU	21H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT

Source/BIOS/Config/n8_2312.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	18432		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_ASCI	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_ASCI	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -103,7 +103,7 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 #DEFINE		AUTOCMD	""		; AUTO STARTUP COMMAND FOR CP/M
 ;
-Z180_CLKDIV	.EQU	1		; 0=XTAL/2, 1=XTAL/1
+Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC/1
 Z180_MEMWAIT	.EQU	0		; MEMORY WAIT STATES TO INSERT (0-3)
 Z180_IOWAIT	.EQU	3		; IO WAIT STATES TO INSERT (0-3)
 Z180_CNTLB0	.EQU	20H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT

Source/BIOS/Config/n8_2511.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	18432		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_ASCI	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_ASCI	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -103,7 +103,7 @@ BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 #DEFINE		AUTOCMD	""		; AUTO STARTUP COMMAND FOR CP/M
 ;
-Z180_CLKDIV	.EQU	1		; 0=XTAL/2, 1=XTAL/1
+Z180_CLKDIV	.EQU	1		; 0=OSC/2, 1=OSC/1
 Z180_MEMWAIT	.EQU	0		; MEMORY WAIT STATES TO INSERT (0-3)
 Z180_IOWAIT	.EQU	3		; IO WAIT STATES TO INSERT (0-3)
 Z180_CNTLB0	.EQU	20H		; SERIAL PORT 0 DIV, SEE Z180 CLOCKING DOCUMENT

Source/BIOS/Config/n8vem_ci.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,10 +26,12 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	2		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)
 UART1IOB	.EQU	$80		; UART1 IOBASE IS $80 FOR CASSETTE INTERFACE
+UART1OSC	.EQU	1843200		; UART 1 OSC FREQUENCY
 UART1BAUD	.EQU	300		; UART1 BAUDRATE IS 300 FOR CASSETTE INTERFACE
 UART1FIFO	.EQU	TRUE		; UART1 FIFO ENABLED FOR CASSETTE INTERFACE
 UART1AFC	.EQU	FALSE		; UART1 AUTO FLOW CONTROL DISABLED FOR CASSETTE INTERFACE

Source/BIOS/Config/n8vem_cvdu.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_CRT	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	TRUE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_dide.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_diskio.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_diskio3+cvdu.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_CRT	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_diskio3.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_dsd.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_mfp.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,10 +26,12 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	2		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)
 UART1IOB	.EQU	$88		; UART1 IOBASE AT $88 FOR MFPIC
+UART1OSC	.EQU	1843200		; UART 1 OSC FREQUENCY
 UART1BAUD	.EQU	38400		; UART1 BAUDRATE IS 38400 FOR MFPIC
 UART1FIFO	.EQU	TRUE		; UART1 FIFO ENABLED FOR MFPIC
 UART1AFC	.EQU	FALSE		; UART1 AUTO FLOW CONTROL DISABLED FOR MFPIC (ENABLE IF DESIRED)

Source/BIOS/Config/n8vem_ppide.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_ppisd.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_propio.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_PRPCON	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_rf.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_simh.asm

@@ -5,12 +5,12 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
 ALTCON		.EQU	DEFCON		; ALT CONSOLE DEVICE (USED WHEN CONFIG JUMPER SHORTED)
-CONBAUD		.EQU	38400		; BAUDRATE FOR CONSOLE DURING HARDWARE INIT
+CONBAUD		.EQU	115200		; BAUDRATE FOR CONSOLE DURING HARDWARE INIT
 DEFVDA		.EQU	VDADEV_NONE	; DEFAULT VDA DEVICE (VDADEV_NONE, VDADEV_VDU, VDADEV_CVDU, VDADEV_N8V, VDADEV_UPD7220)
 DEFEMU		.EQU	EMUTYP_TTY	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	FALSE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	FALSE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_std.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/n8vem_vdu.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	8		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	8000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_CRT	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/una_std.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	18432		; CPU OSC FREQ IN KHZ
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
 CLRRAMDISK	.EQU	CLR_AUTO	; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)

Source/BIOS/Config/zeta2_ppide.asm

@@ -0,0 +1,109 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION FOR ZETA
+;==================================================================================================
+;
+; BUILD CONFIGURATION OPTIONS
+;
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
+;
+BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
+DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
+ALTCON		.EQU	DEFCON		; ALT CONSOLE DEVICE (USED WHEN CONFIG JUMPER SHORTED)
+CONBAUD		.EQU	38400		; BAUDRATE FOR CONSOLE DURING HARDWARE INIT
+DEFVDA		.EQU	VDADEV_NONE	; DEFAULT VDA DEVICE (VDADEV_NONE, VDADEV_VDU, VDADEV_CVDU, VDADEV_N8V, VDADEV_UPD7220)
+DEFEMU		.EQU	EMUTYP_TTY	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
+TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
+CLRRAMDISK	.EQU	CLR_AUTO	; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)
+;
+DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
+;
+SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
+DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
+;
+UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
+UARTCNT		.EQU	1		; NUMBER OF UARTS
+UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
+UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
+UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
+UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)
+;
+ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT
+ASCI0BAUD	.EQU	CONBAUD		; ASCI0 BAUDRATE (IMPLEMENTED BY Z180_CNTLB0)
+ASCI1BAUD	.EQU	CONBAUD		; ASCI1 BAUDRATE (IMPLEMENTED BY Z180_CNTLB1)
+;
+VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
+CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
+UPD7220ENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
+N8VENABLE	.EQU	FALSE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
+;
+DEFIOBYTE	.EQU	$00		; DEFAULT INITIAL VALUE FOR CP/M IOBYTE, $00=TTY, $01=CRT (MUST HAVE CRT HARDWARE)
+ALTIOBYTE	.EQU	DEFIOBYTE	; ALT INITIAL VALUE (USED WHEN CONFIG JUMPER SHORTED)
+WRTCACHE	.EQU	TRUE		; ENABLE WRITE CACHING IN CBIOS (DE)BLOCKING ALGORITHM
+DSKTRACE	.EQU	FALSE		; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
+;
+MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
+MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
+;
+FDENABLE	.EQU	TRUE		; TRUE FOR FLOPPY SUPPORT
+FDMODE		.EQU	FDMODE_ZETA2	; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
+FDTRACE		.EQU	1		; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
+FDMEDIA		.EQU	FDM144		; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
+FDMEDIAALT	.EQU	FDM720		; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
+FDMAUTO		.EQU	TRUE		; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
+;
+RFENABLE	.EQU	FALSE		; TRUE FOR RAM FLOPPY SUPPORT
+;
+IDEENABLE	.EQU	FALSE		; TRUE FOR IDE SUPPORT
+IDEMODE		.EQU	IDEMODE_DIO	; IDEMODE_DIO, IDEMODE_DIDE
+IDETRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+IDE8BIT		.EQU	FALSE		; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
+IDECAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+;
+PPIDEENABLE	.EQU	TRUE		; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
+PPIDEIOB	.EQU	$60		; PPIDE IOBASE
+PPIDETRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
+PPIDE8BIT	.EQU	FALSE		; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
+PPIDECAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+PPIDESLOW	.EQU	FALSE		; ADD DELAYS TO HELP PROBLEMATIC HARDWARE (TRY THIS IF PPIDE IS UNRELIABLE)
+;
+SDENABLE	.EQU	FALSE		; TRUE FOR SD SUPPORT
+SDMODE		.EQU	SDMODE_PPI	; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
+SDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+SDCAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+SDCSIOFAST	.EQU	FALSE		; TABLE-DRIVEN BIT INVERTER
+;
+PRPENABLE	.EQU	FALSE		; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
+PRPIOB		.EQU	$A8		; PORT IO ADDRESS BASE
+PRPSDENABLE	.EQU	TRUE		; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
+PRPSDTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
+PRPSDCAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+PRPCONENABLE	.EQU	TRUE		; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
+;
+PPPENABLE	.EQU	FALSE		; TRUE FOR PARPORTPROP SUPPORT
+PPPSDENABLE	.EQU	TRUE		; TRUE FOR PARPORTPROP SD SUPPORT
+PPPSDTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
+PPPSDCAPACITY	.EQU	64		; CAPACITY OF PPP SD DEVICE (IN MB)
+PPPCONENABLE	.EQU	TRUE		; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
+;
+HDSKENABLE	.EQU	FALSE		; TRUE FOR SIMH HDSK SUPPORT
+HDSKTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+HDSKCAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+;
+PPKENABLE	.EQU	FALSE		; TRUE FOR PARALLEL PORT KEYBOARD
+PPKTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
+KBDENABLE	.EQU	FALSE		; TRUE FOR PS/2 KEYBOARD ON I8242
+KBDTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
+;
+TTYENABLE	.EQU	FALSE		; INCLUDE TTY EMULATION SUPPORT
+ANSIENABLE	.EQU	FALSE		; INCLUDE ANSI EMULATION SUPPORT
+ANSITRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
+;
+BOOTTYPE	.EQU	BT_MENU		; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
+BOOT_TIMEOUT	.EQU	20		; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
+BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
+;
+#DEFINE		AUTOCMD	""		; AUTO STARTUP COMMAND FOR CP/M

Source/BIOS/Config/zeta2_ppisd.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/zeta2_ppp.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_PPPCON	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/zeta2_std.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/zeta_ppide.asm

@@ -0,0 +1,109 @@
+;
+;==================================================================================================
+;   ROMWBW 2.X CONFIGURATION FOR ZETA
+;==================================================================================================
+;
+; BUILD CONFIGURATION OPTIONS
+;
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
+;
+BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
+DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
+ALTCON		.EQU	DEFCON		; ALT CONSOLE DEVICE (USED WHEN CONFIG JUMPER SHORTED)
+CONBAUD		.EQU	38400		; BAUDRATE FOR CONSOLE DURING HARDWARE INIT
+DEFVDA		.EQU	VDADEV_NONE	; DEFAULT VDA DEVICE (VDADEV_NONE, VDADEV_VDU, VDADEV_CVDU, VDADEV_N8V, VDADEV_UPD7220)
+DEFEMU		.EQU	EMUTYP_TTY	; DEFAULT VDA EMULATION (EMUTYP_TTY, EMUTYP_ANSI, ...)
+TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+RAMSIZE		.EQU	512		; SIZE OF RAM IN KB, MUST MATCH YOUR HARDWARE!!!
+CLRRAMDISK	.EQU	CLR_AUTO	; CLR_ALWAYS, CLR_NEVER, CLR_AUTO (CLEAR IF INVALID DIR AREA)
+;
+DSKYENABLE	.EQU	FALSE		; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
+;
+SIMRTCENABLE	.EQU	FALSE		; SIMH CLOCK DRIVER
+DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
+;
+UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
+UARTCNT		.EQU	1		; NUMBER OF UARTS
+UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
+UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
+UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
+UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)
+;
+ASCIENABLE	.EQU	FALSE		; TRUE FOR Z180 ASCI SUPPORT
+ASCI0BAUD	.EQU	CONBAUD		; ASCI0 BAUDRATE (IMPLEMENTED BY Z180_CNTLB0)
+ASCI1BAUD	.EQU	CONBAUD		; ASCI1 BAUDRATE (IMPLEMENTED BY Z180_CNTLB1)
+;
+VDUENABLE	.EQU	FALSE		; TRUE FOR VDU BOARD SUPPORT
+CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
+UPD7220ENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
+N8VENABLE	.EQU	FALSE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
+;
+DEFIOBYTE	.EQU	$00		; DEFAULT INITIAL VALUE FOR CP/M IOBYTE, $00=TTY, $01=CRT (MUST HAVE CRT HARDWARE)
+ALTIOBYTE	.EQU	DEFIOBYTE	; ALT INITIAL VALUE (USED WHEN CONFIG JUMPER SHORTED)
+WRTCACHE	.EQU	TRUE		; ENABLE WRITE CACHING IN CBIOS (DE)BLOCKING ALGORITHM
+DSKTRACE	.EQU	FALSE		; ENABLE TRACING OF CBIOS DISK FUNCTION CALLS
+;
+MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
+MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
+;
+FDENABLE	.EQU	TRUE		; TRUE FOR FLOPPY SUPPORT
+FDMODE		.EQU	FDMODE_ZETA	; FDMODE_DIO, FDMODE_ZETA, FDMODE_DIDE, FDMODE_N8, FDMODE_DIO3
+FDTRACE		.EQU	1		; 0=SILENT, 1=FATAL ERRORS, 2=ALL ERRORS, 3=EVERYTHING (ONLY RELEVANT IF FDENABLE = TRUE)
+FDMEDIA		.EQU	FDM144		; FDM720, FDM144, FDM360, FDM120 (ONLY RELEVANT IF FDENABLE = TRUE)
+FDMEDIAALT	.EQU	FDM720		; ALTERNATE MEDIA TO TRY, SAME CHOICES AS ABOVE (ONLY RELEVANT IF FDMAUTO = TRUE)
+FDMAUTO		.EQU	TRUE		; SELECT BETWEEN MEDIA OPTS ABOVE AUTOMATICALLY
+;
+RFENABLE	.EQU	FALSE		; TRUE FOR RAM FLOPPY SUPPORT
+;
+IDEENABLE	.EQU	FALSE		; TRUE FOR IDE SUPPORT
+IDEMODE		.EQU	IDEMODE_DIO	; IDEMODE_DIO, IDEMODE_DIDE
+IDETRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+IDE8BIT		.EQU	FALSE		; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
+IDECAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+;
+PPIDEENABLE	.EQU	TRUE		; TRUE FOR PPIDE SUPPORT (DO NOT COMBINE WITH DSKYENABLE)
+PPIDEIOB	.EQU	$60		; PPIDE IOBASE
+PPIDETRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPIDEENABLE = TRUE)
+PPIDE8BIT	.EQU	FALSE		; USE IDE 8BIT TRANSFERS (PROBABLY ONLY WORKS FOR CF CARDS!)
+PPIDECAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+PPIDESLOW	.EQU	FALSE		; ADD DELAYS TO HELP PROBLEMATIC HARDWARE (TRY THIS IF PPIDE IS UNRELIABLE)
+;
+SDENABLE	.EQU	FALSE		; TRUE FOR SD SUPPORT
+SDMODE		.EQU	SDMODE_PPI	; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
+SDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+SDCAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+SDCSIOFAST	.EQU	FALSE		; TABLE-DRIVEN BIT INVERTER
+;
+PRPENABLE	.EQU	FALSE		; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
+PRPIOB		.EQU	$A8		; PORT IO ADDRESS BASE
+PRPSDENABLE	.EQU	TRUE		; TRUE FOR PROPIO SD SUPPORT (FOR N8VEM PROPIO ONLY!)
+PRPSDTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PRPSDENABLE = TRUE)
+PRPSDCAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+PRPCONENABLE	.EQU	TRUE		; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
+;
+PPPENABLE	.EQU	FALSE		; TRUE FOR PARPORTPROP SUPPORT
+PPPSDENABLE	.EQU	TRUE		; TRUE FOR PARPORTPROP SD SUPPORT
+PPPSDTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPPENABLE = TRUE)
+PPPSDCAPACITY	.EQU	64		; CAPACITY OF PPP SD DEVICE (IN MB)
+PPPCONENABLE	.EQU	TRUE		; TRUE FOR PROPIO CONSOLE SUPPORT (PS/2 KBD & VGA VIDEO)
+;
+HDSKENABLE	.EQU	FALSE		; TRUE FOR SIMH HDSK SUPPORT
+HDSKTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
+HDSKCAPACITY	.EQU	64		; CAPACITY OF DEVICE (IN MB)
+;
+PPKENABLE	.EQU	FALSE		; TRUE FOR PARALLEL PORT KEYBOARD
+PPKTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF PPKENABLE = TRUE)
+KBDENABLE	.EQU	FALSE		; TRUE FOR PS/2 KEYBOARD ON I8242
+KBDTRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF KBDENABLE = TRUE)
+;
+TTYENABLE	.EQU	FALSE		; INCLUDE TTY EMULATION SUPPORT
+ANSIENABLE	.EQU	FALSE		; INCLUDE ANSI EMULATION SUPPORT
+ANSITRACE	.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF ANSIENABLE = TRUE)
+;
+BOOTTYPE	.EQU	BT_MENU		; BT_MENU (WAIT FOR KEYPRESS), BT_AUTO (BOOT_DEFAULT AFTER BOOT_TIMEOUT SECS)
+BOOT_TIMEOUT	.EQU	20		; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
+BOOT_DEFAULT	.EQU	'Z'		; SELECTION TO INVOKE AT TIMEOUT
+;
+#DEFINE		AUTOCMD	""		; AUTO STARTUP COMMAND FOR CP/M

Source/BIOS/Config/zeta_ppisd.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/zeta_ppp.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_PPPCON	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/Config/zeta_std.asm

@@ -5,7 +5,7 @@
 ;
 ; BUILD CONFIGURATION OPTIONS
 ;
-CPUFREQ		.EQU	20		; IN MHZ, USED TO COMPUTE DELAY FACTORS
+CPUOSC		.EQU	20000		; CPU OSC FREQ IN KHZ
 ;
 BOOTCON		.EQU	CIODEV_UART	; CONSOLE DEVICE FOR BOOT MESSAGES (MUST BE PRIMARY SERIAL PORT FOR PLATFORM)
 DEFCON		.EQU	CIODEV_UART	; DEFAULT CONSOLE DEVICE (LOADER AND MONITOR): CIODEV_UART, CIODEV_CRT, CIODEV_PRPCON, CIODEV_PPPCON
@@ -26,6 +26,7 @@ DSRTCENABLE	.EQU	TRUE		; DS-1302 CLOCK DRIVER
 UARTENABLE	.EQU	TRUE		; TRUE FOR UART SUPPORT (ALMOST ALWAYS WANT THIS TO BE TRUE)
 UARTCNT		.EQU	1		; NUMBER OF UARTS
 UART0IOB	.EQU	$68		; UART0 IOBASE
+UART0OSC	.EQU	1843200		; UART 0 OSC FREQUENCY
 UART0BAUD	.EQU	CONBAUD		; UART0 BAUDRATE
 UART0FIFO	.EQU	TRUE		; UART0 TRUE ENABLES UART FIFO (16550 ASSUMED, N8VEM AND ZETA ONLY)
 UART0AFC	.EQU	FALSE		; UART0 TRUE ENABLES AUTO FLOW CONTROL (YOUR TERMINAL/UART MUST SUPPORT RTS/CTS FLOW CONTROL!!!)

Source/BIOS/asci.asm

@@ -3,13 +3,90 @@
 ; ASCI DRIVER (Z180 SERIAL PORTS)
 ;==================================================================================================
 ;
+; BAUD RATE PROGRAMMING:
+; Given a known clock speed (PHI) and target Baud Rate (BAUD):
+;
+; Divisor = PHI / BAUD
+;
+; Program PS, DR, SS bits based on divisor table lookup
+;
+; Divisor = PHI / BAUD
+; Lookup = PHI / BAUD / 160
+;
+; To allow easier computation:
+;
+; Let xPHI = PHI / 1000 (PHI is always divisible by 1000)
+; Let xBAUD = BAUD / 100 (BAUD is always divisible by 100)
+; xPHI will always fit in 2 byte int
+; xBAUD will always fit in 2 byte int
+;
+; Lookup = (xPHI >> 4) / xBAUD
+;
+; If failure to match, fallback to 9600 baud and try again
+;
+; Lookup	PS Bit	PS Div	DR Bit	DR Div	SS Bits	SS Div	Divisor	CNTLB
+; 1		0	10	0	16	0	1	160	XX0X0000
+; 2		0	10	0	16	1	2	320	XX0X0001
+; 3		1	30	0	16	0	1	480	XX1X0000
+; 4		0	10	0	16	2	4	640	XX0X0010
+; 6		1	30	0	16	1	2	960	XX1X0001
+; 8		0	10	0	16	3	8	1280	XX0X0011
+; 12		1	30	0	16	2	4	1920	XX1X0010
+; 16		0	10	0	16	4	16	2560	XX0X0100
+; 24		1	30	0	16	3	8	3840	XX1X0011
+; 32		0	10	0	16	5	32	5120	XX0X0101
+; 48		1	30	0	16	4	16	7680	XX1X0100
+; 64		0	10	0	16	6	64	10240	XX0X0110
+; 96		1	30	0	16	5	32	15360	XX1X0101
+; 128		0	10	1	64	5	32	20480	XX0X1101
+; 192		1	30	0	16	6	64	30720	XX1X0110
+; 256		0	10	1	64	6	64	40960	XX0X1110
+; 384		1	30	1	64	5	32	61440	XX1X1101
+; 768		1	30	1	64	6	64	122880	XX1X1110
+;
+ASCI_LKUP:
+;	LOOKUP		CNTLB VAL
+;	------		----------
+.DW	1 \	.DB	%00000000
+.DW	2 \	.DB	%00000001
+.DW	3 \	.DB	%00100000	
+.DW	4 \	.DB	%00000010
+.DW	6 \	.DB	%00100001
+.DW	8 \	.DB	%00000011
+.DW	12 \	.DB	%00100010
+.DW	16 \	.DB	%00000100
+.DW	24 \	.DB	%00100011
+.DW	32 \	.DB	%00000101
+.DW	48 \	.DB	%00100100
+.DW	64 \	.DB	%00000110
+.DW	96 \	.DB	%00100101
+.DW	128 \	.DB	%00001101
+.DW	192 \	.DB	%00100110
+.DW	256 \	.DB	%00001110
+.DW	384 \	.DB	%00101101
+.DW	768 \	.DB	%00101110
+;
+ASCI_LKUPCNT	.EQU	($ - ASCI_LKUP) / 3
+;
+; CNTLB0/1:
+; 7 6 5 4 3 2 1 0
+; T M P R D S S S
+; | | | | | | | |
+; | | | | | + + +-- SS: SOURCE/SPEED SELECT (R/W)
+; | | | | +-------- DR: DIVIDE RATIO (R/W)
+; | | | +---------- PEO: PARITY EVEN ODD (R/W)
+; | | +------------ PS: ~CTS/PS: CLEAR TO SEND(R) / PRESCALE(W)
+; | +-------------- MP: MULTIPROCESSOR MODE (R/W)
+; +---------------- MPBT: MULTIPROCESSOR BIT TRANSMIT (R/W)
+;
+;
+;
 ; CHARACTER DEVICE DRIVER ENTRY
 ;   A: RESULT (OUT), CF=ERR
 ;   B: FUNCTION (IN)
 ;   C: CHARACTER (IN/OUT)
 ;   E: DEVICE/UNIT (IN)
 ;
-;
 ASCI_DISPATCH:
 	LD	A,C	; GET DEVICE/UNIT
 	AND	$0F	; ISOLATE UNIT

Source/BIOS/bcd.asm

@@ -0,0 +1,65 @@
+;
+; MAKE A BCD NUMBER FROM A BINARY NUMBER
+; 32 BIT BINARY NUMBER IN HL:BC, RESULT STORED AT (DE)
+; DE IS PRESERVED, ALL OTHER REGS DESTROYED
+;
+BIN2BCD:
+	PUSH	IX		; SAVE IX
+	PUSH	BC		; MOVE BC
+	POP	IX		; ... TO IX
+	LD	C,32		; LOOP FOR 32 BITS OF BINARY DWORD
+;
+BIN2BCD0:
+	; OUTER LOOP (ONCE FOR EACH BIT IN BINARY NUMBER)	
+	LD	B,5		; LOOP FOR 5 BYTES OF RESULT
+	PUSH	DE		; SAVE DE
+	ADD	IX,IX		; LEFT SHIFT NEXT BIT FROM HL:IX
+	ADC	HL,HL		; ... INTO CARRY
+;
+BIN2BCD1:
+	; INNER LOOP (ONCE FOR EACH BYTE OF BCD NUMBER)
+	LD	A,(DE)		; GET IT
+	ADC	A,A		; DOUBLE IT W/ CARRY
+	DAA			; DECIMAL ADJUST
+	LD	(DE),A		; SAVE IT
+	INC	DE		; POINT TO NEXT BCD BYTE
+	DJNZ	BIN2BCD1	; LOOP THRU ALL BCD BYTES
+;
+	; REMAINDER OF OUTER LOOP
+	POP	DE		; RECOVER DE
+	DEC	C		; DEC BIT COUNTER
+	JR	NZ,BIN2BCD0	; LOOP TILL DONE WITH ALL BITS
+	POP	IX		; RESTORE IX
+	RET
+;
+; PRINT CONTENTS OF 5 BYTE BCD NUMBER AT (HL)
+; WITH LEADING ZERO SUPPRESSION
+; ALL REGS DESTROYED
+;
+PRTBCD:
+	INC	HL		; BUMP HL TO POINT TO
+	INC	HL		; ...
+	INC	HL		; ...
+	INC	HL		; ... LAST BYTE OF BCD
+	LD	B,5		; LOOP FOR 5 BYTES
+	LD	C,0		; START BY SUPPRESSING LEADING ZEROES
+;
+PRTBCD1:
+	; LOOP TO PRINT ONE BCD BYTE (TWO DIGITS)
+	XOR	A		; CLEAR ACCUM
+	RLD			; ROTATE FIRST NIBBLE INTO A
+	CALL	PRTBCD2		; PRINT IT
+	XOR	A		; CLEAR ACCUM
+	RLD			; ROTATE SECOND NIBBLE INTO A
+	CALL	PRTBCD2		; PRINT IT
+	DEC	HL		; POINT TO PRIOR BYTE
+	DJNZ	PRTBCD1		; LOOP TILL DONE
+	RET			; RETURN
+;
+PRTBCD2:
+	; SUBROUTINE TO PRINT A DIGIT IN A
+	CP	C		; COMPARE INCOMING TO C
+	RET	Z		; IF EQUAL, SUPPRESSING, ABORT
+	DEC	C		; MAKE C NEGATIVE TO STOP SUPPRESSION
+	ADD	A,'0'		; OFFSET TO PRINTABLE VALUE
+	JP	COUT		; EXIT VIA CHARACTER OUT

Source/BIOS/dsrtc.asm

@@ -307,10 +307,10 @@ DSRTC_WRCLK1:
 DSRTC_CMD:
 	XOR	A			; ALL LINES LOW TO RESET
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2MS			; DELAY 2MS
+	CALL	DLY2			; DELAY 2 * 27 T-STATES
 	XOR	DSRTC_CE		; NOW SET CE HIGH
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2MS			; DELAY 2MS
+	CALL	DLY2			; DELAY 2 * 27 T-STATES
 	LD	A,C			; LOAD COMMAND
 	CALL	DSRTC_PUT		; WRITE IT
 	RET
@@ -335,7 +335,7 @@ DSRTC_PUT:
 DSRTC_PUT1:
 	LD	A,DSRTC_CE		; SET CLOCK LOW
 	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY1MS			; DELAY 1MS
+	CALL	DLY1			; DELAY 27 T-STATES
 	LD	A,C			; RECOVER WORKING VALUE
 	RRCA				; ROTATE NEXT BIT TO SEND INTO BIT 7
 	LD	C,A			; SAVE WORKING VALUE
@@ -344,7 +344,7 @@ DSRTC_PUT1:
 	OUT	(DSRTC_BASE),A		; ASSERT DATA BIT ON BUS
 	OR	DSRTC_CLK		; SET CLOCK HI
 	OUT	(DSRTC_BASE),A		; DO IT
-	CALL	DLY1MS			; DELAY 1MS
+	CALL	DLY1			; DELAY 27 T-STATES
 	DJNZ	DSRTC_PUT1		; LOOP IF NOT DONE
 	RET
 ;
@@ -368,7 +368,7 @@ DSRTC_GET:
 DSRTC_GET1:
 	LD	A,DSRTC_CE | DSRTC_RD	; SET CLK LO
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY2MS			; DELAY 2MS
+	CALL	DLY2			; DELAY 2 * 27 T-STATES
 	IN	A,(DSRTC_BASE)		; READ THE RTC PORT
 	AND	%00000001		; ISOLATE THE DATA BIT
 	OR	C			; COMBINE WITH WORKING VALUE
@@ -376,7 +376,7 @@ DSRTC_GET1:
 	LD	C,A			; SAVE WORKING VALUE
 	LD	A,DSRTC_CE | DSRTC_CLK | DSRTC_RD	; CLOCK BACK TO HI
 	OUT	(DSRTC_BASE),A		; WRITE TO RTC PORT
-	CALL	DLY1MS			; DELAY 1MS
+	CALL	DLY1			; DELAY 27 T-STATES
 	DJNZ	DSRTC_GET1		; LOOP IF NOT DONE (13)
 	LD	A,C			; GET RESULT INTO A
 	RET

Source/BIOS/fd.asm

@@ -1375,7 +1375,7 @@ FXR_NULL1:
 FXR_READ:
 	LD	HL,(DIOBUF)		; POINT TO SECTOR BUFFER START
 	LD	DE,(FCD_SECSZ)
-	LD	A,(CPUFREQ + 3) / 4
+	LD	A,(CPUMHZ + 3) / 4
 	LD	(FCD_TO),A
 FXRR1	LD	C,0			; OUTER LOOP TIMEOUT COUNTER
 FXRR2:	LD	B,0			; SETUP FOR 256 ITERATIONS
@@ -1410,7 +1410,7 @@ FXRR5:					; OUTER LOOP, REALLY ONLY HAPPENS WHEN WAITING FOR FIRST BYTE OR ABOR
 FXR_WRITE:
 	LD	HL,(DIOBUF)		; POINT TO SECTOR BUFFER START
 	LD	DE,(FCD_SECSZ)
-	LD	A,(CPUFREQ + 3) / 4
+	LD	A,(CPUMHZ + 3) / 4
 	LD	(FCD_TO),A
 FXRW1	LD	C,0			; OUTER LOOP TIMEOUT COUNTER
 FXRW2:	LD	B,0			; SETUP FOR 256 ITERATIONS

Source/BIOS/hbios.asm

@@ -42,7 +42,8 @@ ROM_SIG:
 	.DW	DESC			; POINTER TO LONGER DESCRIPTION OF ROM
 	.DB	0, 0, 0, 0, 0, 0	; RESERVED FOR FUTURE USE; MUST BE ZERO
 ;
-NAME	.DB	"ROMWBW v", BIOSVER, ", ", BIOSBLD, ", ", TIMESTAMP, 0
+;NAME	.DB	"ROMWBW v", BIOSVER, ", ", BIOSBLD, ", ", TIMESTAMP, 0
+NAME	.DB	"ROMWBW v", BIOSVER, ", ", TIMESTAMP, 0
 AUTH	.DB	"WBW",0
 DESC	.DB	"ROMWBW v", BIOSVER, ", Copyright 2015, Wayne Warthen, GNU GPL v3", 0
 ;
@@ -52,25 +53,26 @@ DESC	.DB	"ROMWBW v", BIOSVER, ", Copyright 2015, Wayne Warthen, GNU GPL v3", 0
 ;   BUILD META DATA
 ;==================================================================================================
 ;
-	.DB	'W',~'W'		; MARKER
-	.DB	RMJ << 4 | RMN		; FIRST BYTE OF VERSION INFO
-	.DB	RUP << 4 | RTP		; SECOND BYTE OF VERSION INFO
+		.DB	'W',~'W'		; MARKER
+		.DB	RMJ << 4 | RMN		; FIRST BYTE OF VERSION INFO
+		.DB	RUP << 4 | RTP		; SECOND BYTE OF VERSION INFO
 ;
-	.DB	PLATFORM	
-	.DB	CPUFREQ		
-	.DW	RAMSIZE		
-	.DW	ROMSIZE		
+		.DB	PLATFORM
+HB_CPUMHZ	.DB	CPUMHZ
+HB_CPUKHZ	.DW	CPUKHZ
+		.DW	RAMSIZE
+		.DW	ROMSIZE
 ;
-	.DB	BID_COM		
-	.DB	BID_USR		
-	.DB	BID_BIOS	
-	.DB	BID_AUX		
-	.DB	BID_RAMD0	
-	.DB	BID_RAMDN	
-	.DB	BID_ROMD0	
-	.DB	BID_ROMDN	
+		.DB	BID_COM
+		.DB	BID_USR
+		.DB	BID_BIOS
+		.DB	BID_AUX
+		.DB	BID_RAMD0
+		.DB	BID_RAMDN
+		.DB	BID_ROMD0
+		.DB	BID_ROMDN
 ;
-	.FILL	($200 - $),$FF		; PAD REMAINDER OF PAGE ONE
+		.FILL	($200 - $),$FF		; PAD REMAINDER OF PAGE ONE
 ;
 ;==================================================================================================
 ;   HBIOS UPPER MEMORY PROXY
@@ -574,14 +576,45 @@ DEVCNT		.EQU	($ - DEVMAP) / 1
 ;
 HB_START:
 ;
+
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+	; SET DEFAULT WAIT STATES TO ACCURATELY MEASURE CPU SPEED
+	LD	A,$F0
+	OUT0	(CPU_DCNTL),A
+
+#IF (Z180_CLKDIV >= 1)
+	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
+	LD	A,$80
+	OUT0	(CPU_CCR),A
+#ENDIF
+
+#IF (Z180_CLKDIV >= 2)
+	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
+	LD	A,$80
+	OUT0	(CPU_CMR),A
+#ENDIF
+
+#ENDIF
+
+	CALL	HB_CPUSPD		; CPU SPEED DETECTION
+;
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+;
+
+	; SET DESIRED WAIT STATES
+	LD	A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
+	OUT0	(CPU_DCNTL),A
+;
+#ENDIF
+;
 ; ANNOUNCE HBIOS
 ;
 	CALL	NEWLINE
 	CALL	NEWLINE
 	PRTX(STR_PLATFORM)
 	PRTS(" @ $")
-	LD	HL,CPUFREQ
-	CALL	PRTDEC
+	LD	HL,(HB_CPUKHZ)
+	CALL	PRTD3M			; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA
 	PRTS("MHz ROM=$")
 	LD	HL,ROMSIZE
 	CALL	PRTDEC
@@ -1496,6 +1529,225 @@ SIZ_ANSI	.EQU	$ - ORG_ANSI
 #DEFINE	DSKY_KBD
 #INCLUDE "util.asm"
 #INCLUDE "time.asm"
+#INCLUDE "bcd.asm"
+;
+#IF ((PLATFORM == PLT_N8VEM) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2))
+;
+; DETECT Z80 CPU SPEED USING DS-1302 RTC
+;
+HB_CPUSPD:
+;
+#IF (DSRTCENABLE)
+;
+	CALL	DSRTC_TSTCLK	; IS CLOCK RUNNING?
+	JR	Z,HB_CPUSPD1		; YES, CONTINUE
+	; MAKE SURE CLOCK IS RUNNING
+	LD	HL,DSRTC_TIMDEF
+	CALL	DSRTC_TIM2CLK
+	LD	HL,DSRTC_BUF
+	CALL	DSRTC_WRCLK
+	CALL	DSRTC_TSTCLK	; NOW IS CLOCK RUNNING?
+	RET	NZ
+;
+HB_CPUSPD1:
+	; WATT FOR AN INITIAL TICK TO ALIGN, THEN WAIT
+	; FOR SECOND TICK AND TO GET A FULL ONE SECOND LOOP COUNT
+	CALL	HB_WAITSECS	; WAIT FOR INITIAL SECS TICK
+	CALL	HB_WAITSECS	; WAIT FOR SECS TICK AGAIN, COUNT INDE
+;
+	LD	A,H
+	OR	L
+	RET	Z		; FAILURE, USE DEFAULT CPU SPEED
+;
+	; TIMES 4 (W/ ROUNDING) FOR CPU SPEED IN KHZ
+	INC	HL
+	SRL	H
+	RR	L
+	SLA	L
+	RL	H
+	SLA	L
+	RL	H
+	SLA	L
+	RL	H
+;	
+	LD	(HB_CPUKHZ),HL
+	LD	DE,1000
+	CALL	DIV16
+	LD	A,C
+	LD	(HB_CPUMHZ),A
+;
+	RET
+;	
+HB_WAITSECS:
+	; WAIT FOR SECONDS TICK
+	; RETURN SECS VALUE IN A, LOOP COUNT IN DE
+	; LOOP TARGET IS 250 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
+	LD	HL,0		; INIT LOOP COUNTER
+	CALL	HB_RDSEC	; GET SECONDS
+	LD	E,A		; SAVE IT
+HB_WAITSECS1:
+	CALL	DLY32
+	CALL	DLY8
+	CALL	DLY4
+	JP	$ + 3		; 10 TSTATES
+;	LD	A,R		; 9 TSTATES
+;	INC	BC		; 6 TSTATES
+	NOP			; 4 TSTATES
+	NOP			; 4 TSTATES
+	NOP			; 4 TSTATES
+	NOP			; 4 TSTATES
+	NOP			; 4 TSTATES
+;
+	CALL	HB_RDSEC	; GET SECONDS
+	INC	HL		; BUMP COUNTER
+	CP	E		; EQUAL?
+	RET	NZ		; DONE IF TICK OCCURRED
+	LD	A,H		; CHECK HL
+	OR	L		; ... FOR OVERFLOW
+	RET	Z		; TIMEOUT, SOMETHING IS WRONG
+	JR	HB_WAITSECS1	; LOOP
+;
+HB_RDSEC:
+	; READ SECONDS BYTE INTO A
+	LD	C,$81			; SECONDS REGISTER HAS CLOCK HALT FLAG
+	CALL	DSRTC_CMD		; SEND THE COMMAND
+	CALL	DSRTC_GET		; READ THE REGISTER
+	CALL	DSRTC_END		; FINISH IT
+	RET
+;
+#ELSE
+;
+	RET				; NO RTC, ABORT
+;
+#ENDIF
+;
+#ENDIF
+;
+;
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4))
+;
+; DETECT Z180 CPU SPEED USING DS-1302 RTC
+;
+HB_CPUSPD:
+;
+#IF (DSRTCENABLE)
+;
+	CALL	DSRTC_TSTCLK		; IS CLOCK RUNNING?
+	JR	Z,HB_CPUSPD1		; YES, CONTINUE
+	; MAKE SURE CLOCK IS RUNNING
+	LD	HL,DSRTC_TIMDEF
+	CALL	DSRTC_TIM2CLK
+	LD	HL,DSRTC_BUF
+	CALL	DSRTC_WRCLK
+	CALL	DSRTC_TSTCLK		; NOW IS CLOCK RUNNING?
+	RET	NZ
+;
+HB_CPUSPD1:
+	; WATT FOR AN INITIAL TICK TO ALIGN, THEN WAIT
+	; FOR SECOND TICK AND TO GET A FULL ONE SECOND LOOP COUNT
+	CALL	HB_WAITSECS	; WAIT FOR INITIAL SECS TICK
+	CALL	HB_WAITSECS	; WAIT FOR SECS TICK AGAIN, COUNT INDE
+;
+	LD	A,H
+	OR	L
+	RET	Z		; FAILURE, USE DEFAULT CPU SPEED
+;
+	; TIMES 8 FOR CPU SPEED IN KHZ
+	SLA	L
+	RL	H
+	SLA	L
+	RL	H
+	SLA	L
+	RL	H
+;
+	LD	(HB_CPUKHZ),HL
+	LD	DE,1000
+	CALL	DIV16
+	LD	A,C
+	LD	(HB_CPUMHZ),A
+;
+	RET
+;	
+HB_WAITSECS:
+	; WAIT FOR SECONDS TICK
+	; RETURN SECS VALUE IN A, LOOP COUNT IN DE
+	; LOOP TARGET IS 250 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 4
+	LD	HL,0		; INIT LOOP COUNTER
+	CALL	HB_RDSEC	; GET SECONDS
+	LD	E,A		; SAVE IT
+HB_WAITSECS1:
+	CALL	DLY64
+	OR	A		; 7 TSTATES
+	;OR	A		; 7 TSTATES
+	;OR	A		; 7 TSTATES
+	;OR	A		; 7 TSTATES
+	NOP			; 6 TSTATES
+	NOP			; 6 TSTATES
+	NOP			; 6 TSTATES
+	NOP			; 6 TSTATES
+	;NOP			; 6 TSTATES
+;
+	CALL	HB_RDSEC	; GET SECONDS
+	INC	HL		; BUMP COUNTER
+	CP	E		; EQUAL?
+	RET	NZ		; DONE IF TICK OCCURRED
+	LD	A,H		; CHECK HL
+	OR	L		; ... FOR OVERFLOW
+	RET	Z		; TIMEOUT, SOMETHING IS WRONG
+	JR	HB_WAITSECS1	; LOOP
+;
+HB_RDSEC:
+	; READ SECONDS BYTE INTO A
+	LD	C,$81			; SECONDS REGISTER HAS CLOCK HALT FLAG
+	CALL	DSRTC_CMD		; SEND THE COMMAND
+	CALL	DSRTC_GET		; READ THE REGISTER
+	CALL	DSRTC_END		; FINISH IT
+	RET
+;
+#ELSE
+;
+	RET				; NO RTC, ABORT
+;
+#ENDIF
+;
+#ENDIF
+;
+; PRINT VALUE OF HL AS THOUSANDTHS, IE. 0.000
+;
+PRTD3M:
+	PUSH	BC
+	PUSH	DE
+	PUSH	HL
+	LD	E,'0'
+	LD	BC,-10000
+	CALL	PRTD3M1
+	LD	E,0
+	LD	BC,-1000
+	CALL	PRTD3M1
+	CALL	PC_PERIOD
+	LD	BC,-100
+	CALL	PRTD3M1
+	LD	C,-10
+	CALL	PRTD3M1
+	LD	C,-1
+	CALL	PRTD3M1
+	POP	HL
+	POP	DE
+	POP	BC
+	RET
+PRTD3M1:
+	LD	A,'0' - 1
+PRTD3M2:
+	INC	A
+	ADD	HL,BC
+	JR	C,PRTD3M2
+	SBC	HL,BC
+	CP	E
+	JR	Z,PRTD3M3
+	LD	E,0
+	CALL	COUT
+PRTD3M3:
+	RET
 ;
 ;==================================================================================================
 ;   HBIOS GLOBAL DATA
@@ -1521,7 +1773,8 @@ HB_INTSTKSAV	.DW	0		; SAVED STACK POINTER DURING INT PROCESSING
 HB_INTSTK	.EQU	$
 
 ;
-STR_BANNER	.DB	"N8VEM HBIOS v", BIOSVER, ", ", BIOSBLD, ", ", TIMESTAMP, "$"
+;STR_BANNER	.DB	"N8VEM HBIOS v", BIOSVER, ", ", BIOSBLD, ", ", TIMESTAMP, "$"
+STR_BANNER	.DB	"N8VEM HBIOS v", BIOSVER, ", ", TIMESTAMP, "$"
 STR_PLATFORM	.DB	PLATFORM_NAME, "$"
 ;
 HB_ATTR:	; ATTRIBUTE TABLE, 128 WORD VALUES

Source/BIOS/loader.asm

@@ -67,7 +67,8 @@ ROM_SIG:
 	.DW	DESC			; POINTER TO LONGER DESCRIPTION OF ROM
 	.DB	0, 0, 0, 0, 0, 0	; RESERVED FOR FUTURE USE; MUST BE ZERO
 ;
-NAME	.DB	"ROMWBW v", BIOSVER, ", ", BIOSBLD, ", ", TIMESTAMP, 0
+;NAME	.DB	"ROMWBW v", BIOSVER, ", ", BIOSBLD, ", ", TIMESTAMP, 0
+NAME	.DB	"ROMWBW v", BIOSVER, ", ", TIMESTAMP, 0
 AUTH	.DB	"WBW",0
 DESC	.DB	"ROMWBW v", BIOSVER, ", Copyright 2014, Wayne Warthen, GNU GPL v3", 0
 ;
@@ -91,16 +92,26 @@ START:
 	; SET BASE FOR CPU IO REGISTERS
    	LD	A,CPU_BASE
 	OUT0	(CPU_ICR),A
-	
+
 	; SET DEFAULT CPU CLOCK MULTIPLIERS (XTAL / 2)
 	XOR	A
 	OUT0	(CPU_CCR),A
 	OUT0	(CPU_CMR),A
-	
+
 	; SET DEFAULT WAIT STATES
 	LD	A,$F0
 	OUT0	(CPU_DCNTL),A
 
+	; MMU SETUP
+	LD	A,$80
+	OUT0	(CPU_CBAR),A		; SETUP FOR 32K/32K BANK CONFIG
+#IF (LDRMODE == LM_ROM)
+	XOR	A
+	OUT0	(CPU_BBR),A		; BANK BASE = 0
+#ENDIF
+	LD	A,(RAMSIZE + RAMBIAS - 64) >> 2
+	OUT0	(CPU_CBR),A		; COMMON BASE = LAST (TOP) BANK
+
 #IF (Z180_CLKDIV >= 1)
 	; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
 	LD	A,$80
@@ -108,7 +119,7 @@ START:
 #ENDIF
 
 #IF (Z180_CLKDIV >= 2)
-	; SET CPU MULTIPLIER TO 1 RESULTINT IN XTAL * 2 SPEED
+	; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED
 	LD	A,$80
 	OUT0	(CPU_CMR),A
 #ENDIF
@@ -117,15 +128,6 @@ START:
 	LD	A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4)
 	OUT0	(CPU_DCNTL),A
 
-	; MMU SETUP
-	LD	A,$80
-	OUT0	(CPU_CBAR),A		; SETUP FOR 32K/32K BANK CONFIG
-#IF (LDRMODE == LM_ROM)
-	XOR	A
-	OUT0	(CPU_BBR),A		; BANK BASE = 0
-#ENDIF
-	LD	A,(RAMSIZE + RAMBIAS - 64) >> 2
-	OUT0	(CPU_CBR),A		; COMMON BASE = LAST (TOP) BANK
 #ENDIF
 ;
 ; HARDWARE BOOTSTRAP FOR ZETA 2
@@ -220,12 +222,20 @@ PHASE2:
 	LD	BC,HB_END	; COPY ALL OF HBIOS IMAGE
 	CALL	HB_BNKCPY	; DO IT
 	CALL	XIO_DOT		; MARK PROGRESS
+	
+	;; HACK TO FLUSH THE OUTPUT FIFO
+	;XOR	A
+	;CALL	XIO_OUTC
+	;CALL	XIO_OUTC
+	;CALL	XIO_OUTC
+	;CALL	XIO_OUTC
 ;
 ; INITIALIZE HBIOS
 ;
 	LD	A,BID_BIOS	; HBIOS BANK
 	LD	HL,0		; ADDRESS 0 IS HBIOS INIT ENTRY ADDRESS
 	CALL	HB_BNKCALL	; DO IT
+	
 ;
 ; CHAIN TO OS LOADER
 ;

Source/BIOS/mk4.inc

@@ -1,6 +1,18 @@
 ;
 ; MARK IV HARDWARE DEFINITIONS
 ;
+#IF (Z180_CLKDIV == 0)
+CPUKHZ		.EQU	CPUOSC / 2	; OSCILLATOR FREQ / 2
+#ENDIF
+#IF (Z180_CLKDIV == 1)
+CPUKHZ		.EQU	CPUOSC		; OSCILLATOR FREQ
+#ENDIF
+#IF (Z180_CLKDIV == 2)
+CPUKHZ		.EQU	CPUOSC * 2	; OSCILLATOR FREQ * 2
+#ENDIF
+;
+CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN KHZ
+;
 CPU_BASE	.EQU	$40		; ONLY RELEVANT FOR Z180
 ;
 RAMBIAS		.EQU	512		; RAM STARTS AT 512K

Source/BIOS/n8.inc

@@ -1,6 +1,18 @@
 ;
 ; N8 HARDWARE DEFINITIONS
 ;
+#IF (Z180_CLKDIV == 0)
+CPUKHZ		.EQU	CPUOSC / 2	; OSCILLATOR FREQ / 2
+#ENDIF
+#IF (Z180_CLKDIV == 1)
+CPUKHZ		.EQU	CPUOSC		; OSCILLATOR FREQ
+#ENDIF
+#IF (Z180_CLKDIV == 2)
+CPUKHZ		.EQU	CPUOSC * 2	; OSCILLATOR FREQ * 2
+#ENDIF
+;
+CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN KHZ
+;
 CPU_BASE	.EQU	$40		; ONLY RELEVANT FOR Z180
 ;
 RAMBIAS		.EQU	0		; RAM STARTS AT 0K

Source/BIOS/n8vem.inc

@@ -1,6 +1,9 @@
 ;
 ; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
 ;
+CPUKHZ		.EQU	CPUOSC	; FOR SBC 1/2, CPUFREQ == OSCILLATOR FREQ
+CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN KHZ
+;
 #IF ((PLATFORM == PLT_N8VEM) | (PLATFORM == PLT_ZETA))
 MPCL_RAM	.EQU 	$78		; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH (WRITE ONLY)
 MPCL_ROM	.EQU 	$7C		; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH (WRITE ONLY)

Source/BIOS/ppk.asm

@@ -28,8 +28,8 @@ PPK_PPIX	.EQU	PPK_PPI + 3	; KEYBOARD PPI CONTROL PORT
 PPK_DAT		.EQU	01111000B	; PPIX MASK TO MANAGE DATA LINE (C:4)
 PPK_CLK		.EQU	01111010B	; PPIX MASK TO MANAGE CLOCK LINE (C:5)
 
-PPK_WAITTO	.EQU	50 * CPUFREQ	; TUNE!!! WANT SMALL AS POSSIBLE W/O ERRORS
-PPK_WAITRDY	.EQU	10 * CPUFREQ	; TUNE!!! 100US LOOP DELAY TO ENSURE DEVICE READY
+PPK_WAITTO	.EQU	50 * CPUMHZ	; TUNE!!! WANT SMALL AS POSSIBLE W/O ERRORS
+PPK_WAITRDY	.EQU	10 * CPUMHZ	; TUNE!!! 100US LOOP DELAY TO ENSURE DEVICE READY
 ;
 ; STATUS BITS (FOR PPK_STATUS)
 ;

Source/BIOS/time.asm

@@ -21,7 +21,7 @@ DOW:
 	; DETERMINE CENTURY AND YEAR OF CENTURY FROM FULL YEAR
 	PUSH	HL		; SAVE FULL YEAR VALUE
 	LD	DE,100		; DIVIDE BY 100 TO GET CC/YY
-	CALL	DIV		; BC NOW HAS CENTURY, HL HAS YEAR OF CENTURY
+	CALL	DIV16		; BC NOW HAS CENTURY, HL HAS YEAR OF CENTURY
 	LD	A,L		; MOVE YEAR TO A, DISCARD H NOT NEEDED
 	LD	(DOW_YR),A	; SAVE YY
 	LD	A,C		; MOVE CENTURY TO A, DISCARD B NOT NEEDED
@@ -87,19 +87,19 @@ DOW_MO	.DB	0
 ;   RETURN DOW IN A (0-6: SUN-SAT)
 ;
 TIMDOW:
+	PUSH	HL
 	INC	HL			; POINT TO MONTH
 	LD	A,(HL)			; LOAD MONTH (BCD)
-	CALL	BCD2BIN			; CVT TO BINARY
+	CALL	BCD2BYTE		; CVT TO BINARY
 	LD	D,A			; D := MONTH (BINARY)
 	INC	HL			; POINT TO DATE
 	LD	A,(HL)			; LOAD DATE (BCD)
-	CALL	BCD2BIN			; CVT TO BINARY
+	CALL	BCD2BYTE		; CVT TO BINARY
 	LD	E,A			; E := DATE (BINARY)
 	POP	HL			; RECOVER PTR TO START OF BUF
-	PUSH	HL
 	PUSH	DE			; SAVE DE FOR NOW
 	LD	A,(HL)			; LOAD YEAR OF CENTURY (BCD)
-	CALL	BCD2BIN			; CVT TO BINARY
+	CALL	BCD2BYTE		; CVT TO BINARY
 	LD	L,A			; YEAR VALUE
 	LD	H,0			; .. IN HL
 	LD	DE,2000			; ASSUME CENTURY IS 20XX
@@ -167,27 +167,31 @@ DOWTBL		.DB	"Sun$", "Mon$", "Tue$", "Wed$"
 ; HL IS PRESERVED
 ;
 LEAP:
-	PUSH	HL
 	LD	DE,4
-	CALL	DIV
-	POP	HL
+	CALL	LEAPDIV
 	JR	NZ,NOLEAP	; IF YEAR NOT DIVISIBLE BY 4: NOT LEAP
-	PUSH	HL
 	LD	DE,100
-	CALL	DIV
-	POP	HL
+	CALL	LEAPDIV
 	JR	NZ,ISLEAP	; ELSE IF YEAR NOT DIVISIBLE BY 100: LEAP
-	PUSH	HL
 	LD	DE,400
-	CALL	DIV
-	POP	HL
+	CALL	LEAPDIV
 	JR	Z,ISLEAP	; ELSE IF YEAR DIVISIBLE BY 400: LEAP
 	JR	NOLEAP		; OTHERWISE NOT LEAP
 ;
 NOLEAP:
-	OR	$FF		; ZF=NZ SIGNALS FALSE (NOT LEAP YEAR)
+	OR	$FF		; NZ SIGNALS FALSE (NOT LEAP YEAR)
 	RET
 ;
 ISLEAP:
-	XOR	A		; ZF=Z SIGNALS TRUE (IS LEAP YEAR)
+	XOR	A		; ZF SIGNALS TRUE (IS LEAP YEAR)
+	RET
+;
+LEAPDIV:
+	; SET Z FLAG BASED ON REMAINDER OF HL / DE
+	; PRESERVE HL
+	PUSH	HL
+	CALL	DIV16
+	LD	A,H
+	OR	L
+	POP	HL
 	RET

Source/BIOS/uart.asm

@@ -47,8 +47,6 @@ UART0_DLL		.EQU	UART0IOB + 0	; DLAB=1: DIVISOR LATCH (LS)
 UART0_DLM		.EQU	UART0IOB + 1	; DLAB=1: DIVISOR LATCH (MS)
 UART0_EFR		.EQU	UART0IOB + 2	; ENHANCED FEATURE (WHEN LCR = $BF)
 ;
-UART0_DIV	.EQU	(1843200 / (16 * UART0BAUD))
-;
 #ENDIF
 ;
 #IF (UARTCNT >= 2)
@@ -66,7 +64,6 @@ UART1_DLL		.EQU	UART1IOB + 0	; DLAB=1: DIVISOR LATCH (LS)
 UART1_DLM		.EQU	UART1IOB + 1	; DLAB=1: DIVISOR LATCH (MS)
 UART1_EFR		.EQU	UART1IOB + 2	; ENHANCED FEATURE (WHEN LCR = $BF)
 ;
-UART1_DIV	.EQU	(1843200 / (16 * UART1BAUD))
 #ENDIF
 ;
 #IF (UARTCNT >= 3)
@@ -84,7 +81,6 @@ UART2_DLL		.EQU	UART2IOB + 0	; DLAB=1: DIVISOR LATCH (LS)
 UART2_DLM		.EQU	UART2IOB + 1	; DLAB=1: DIVISOR LATCH (MS)
 UART2_EFR		.EQU	UART2IOB + 2	; ENHANCED FEATURE (WHEN LCR = $BF)
 ;
-UART2_DIV	.EQU	(1843200 / (16 * UART2BAUD))
 #ENDIF
 ;
 #IF (UARTCNT >= 4)
@@ -102,7 +98,6 @@ UART3_DLL		.EQU	UART3IOB + 0	; DLAB=1: DIVISOR LATCH (LS)
 UART3_DLM		.EQU	UART3IOB + 1	; DLAB=1: DIVISOR LATCH (MS)
 UART3_EFR		.EQU	UART3IOB + 2	; ENHANCED FEATURE (WHEN LCR = $BF)
 ;
-UART3_DIV	.EQU	(1843200 / (16 * UART3BAUD))
 #ENDIF
 ;
 ; CHARACTER DEVICE DRIVER ENTRY
@@ -161,10 +156,14 @@ UART0_INIT:
 ;
 	; SETUP FOR GENERIC INIT ROUTINE
 	LD	(UART_BASE),A		; IO BASE ADDRESS
-	LD	DE,UART0BAUD / 10	; BAUD RATE / 10
-	LD	(UART_BAUD),DE		; SAVE IT
-	LD	DE,UART0_DIV		; DIVISOR
-	LD	(UART_DIV),DE		; SAVE IT
+	LD	DE,UART0OSC >> 16
+	LD	(UART_OSCHI),DE
+	LD	DE,UART0OSC & $FFFF
+	LD	(UART_OSCLO),DE
+	LD	DE,UART0BAUD >> 16
+	LD	(UART_BAUDHI),DE
+	LD	DE,UART0BAUD & $FFFF
+	LD	(UART_BAUDLO),DE
 ;
 	; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
 	XOR	A			; START WITH NO FEATURES
@@ -244,10 +243,14 @@ UART1_INIT:
 ;
 	; SETUP FOR GENERIC INIT ROUTINE
 	LD	(UART_BASE),A		; IO BASE ADDRESS
-	LD	DE,UART1BAUD / 10	; BAUD RATE / 10
-	LD	(UART_BAUD),DE		; SAVE IT
-	LD	DE,UART1_DIV		; DIVISOR
-	LD	(UART_DIV),DE		; SAVE IT
+	LD	DE,UART1OSC >> 16
+	LD	(UART_OSCHI),DE
+	LD	DE,UART1OSC & $FFFF
+	LD	(UART_OSCLO),DE
+	LD	DE,UART1BAUD >> 16
+	LD	(UART_BAUDHI),DE
+	LD	DE,UART1BAUD & $FFFF
+	LD	(UART_BAUDLO),DE
 ;
 	; MAP REQUESTED FEATURES TO FLAGS IN UART_FUNC
 	XOR	A			; START WITH NO FEATURES
@@ -327,17 +330,17 @@ UART_INITP:
 
 	; HL IS USED BELOW TO REFER TO FEATURE BITS ENABLED
 	LD	HL,UART_FEAT		; HL POINTS TO FEATURE FLAGS BYTE
-	XOR	A			; RESET ALL FEATRUES
+	XOR	A			; RESET ALL FEATURES
 	LD	(HL),A			; SAVE IT
 
 	; START OF UART INITIALIZATION, SET BAUD RATE
 	LD	A,80H
 	UART_OUT(UART_LCR)		; DLAB ON
-	LD	DE,(UART_DIV)
-	LD	A,E
-	UART_OUT(UART_DLL)		; SET DIVISOR (LS)
-	LD	A,D
+	CALL	UART_COMPDIV		; COMPUTE DIVISOR TO BC
+	LD	A,B
 	UART_OUT(UART_DLM)		; SET DIVISOR (MS)
+	LD	A,C
+	UART_OUT(UART_DLL)		; SET DIVISOR (LS)
 	
 	; SET LCR TO DEFAULT
 	LD	A,$03			; DLAB OFF, 8 DATA, 1 STOP, NO PARITY
@@ -454,13 +457,17 @@ UART_INITP1:
 	; ALL DONE IF NO UART WAS DETECTED
 	LD	A,(UART_TYPE)
 	OR	A
-	JR	Z,UART_INITP3
+;	JR	Z,UART_INITP3
 ;
 	; PRINT BAUD RATE
 	PRTS(" BAUD=$")
-	LD	HL,(UART_BAUD)
-	CALL	PRTDEC
-	PRTC('0')
+	LD	HL,(UART_BAUDHI)
+	LD	BC,(UART_BAUDLO)
+	LD	DE,UART_INITBUF
+	CALL	BIN2BCD
+	EX	DE,HL
+	CALL	PRTBCD
+;	CALL	PRTDEC
 ;
 	; PRINT FEATURES ENABLED
 	LD	A,(UART_FEAT)
@@ -475,6 +482,8 @@ UART_INITP3:
 ;
 	RET
 ;
+UART_INITBUF	.FILL	5,0		; WORKING BUFFER FOR BCD NUMBER
+;
 ; UART DETECTION ROUTINE
 ;
 UART_DETECT:
@@ -577,6 +586,40 @@ UART_DETECT_16850:
 	LD	A,UART_16850
 	RET
 ;
+; COMPUTE DIVISOR TO BC
+; USES UART_BAUD AND UART_OSC VARIABLES BELOW
+;
+UART_COMPDIV:
+	; SETUP DE:HL WITH OSC FREQUENCY
+	LD	DE,(UART_OSCHI)
+	LD	HL,(UART_OSCLO)
+	; DIVIDE OSC FREQ BY PRESCALE FACTOR OF 16
+	LD	B,4	; 4 ITERATIONS
+UART_COMPDIV1:
+	SRL	D
+	RR	E
+	RR	H
+	RR	L
+	DJNZ	UART_COMPDIV1
+	; CONVERT FROM DE:HL -> A:HL (THROW AWAY HIGH BYTE)
+	LD	A,E
+	; SETUP C:DE WITH TARGET BAUD RATE
+	LD	BC,(UART_BAUDHI)
+	LD	DE,(UART_BAUDLO)
+	; DIVIDE OSC FREQ AND BAUD BY 2 UNTIL FREQ FITS IN 16 BITS
+UART_COMPDIV2:
+	SRL	A
+	RR	H
+	RR	L
+	SRL	C
+	RR	D
+	RR	E
+	OR	A
+	JR	NZ,UART_COMPDIV2
+	; DIVIDE ADJUSTED VALUES (OSC FREQ / BAUD RATE)
+	CALL	DIV16
+	RET
+;
 ; ROUTINES TO READ/WRITE PORTS INDIRECTLY
 ;
 ; READ VALUE OF UART PORT ON TOS INTO REGISTER A
@@ -637,8 +680,11 @@ UART_STR_16850		.DB	"16850$"
 UART_BASE		.DB	0		; BASE IO ADDRESS FOR ACTIVE UART
 UART_TYPE		.DB	0		; UART TYPE DISCOVERED
 UART_FEAT		.DB	0		; UART FEATURES DISCOVERED
-UART_BAUD		.DW	0		; BAUD RATE
-UART_DIV		.DW	0		; BAUD DIVISOR
+UART_BAUDLO		.DW	0		; BAUD RATE LO WORD
+UART_BAUDHI		.DW	0		; BAUD RATE HI WORD
+UART_OSCLO		.DW	0		; UART OSC FREQUENCY LO
+UART_OSCHI		.DW	0		; UART OSC FREQUENCY HI
+;UART_DIV		.DW	0		; BAUD DIVISOR
 UART_FUNC		.DB	0		; UART FUNCTIONS REQUESTED
 ;
 ;

Source/BIOS/una.inc

@@ -1,6 +1,9 @@
 ;
 ; UNA HARDWARE DEFINITIONS
 ;
+CPUKHZ		.EQU	CPUOSC		; OSCILLATOR FREQ
+CPUMHZ		.EQU	CPUKHZ / 1000	; CPU FREQ IN KHZ
+;
 ; DUMMY VALUES BELOW TO ALLOW DBGMON TO BUILD...
 ; NEED TO REMOVE AND CLEAN THIS UP LATER.
 ;

Source/BIOS/util.asm

@@ -472,7 +472,7 @@ ADDHLA:
 ;	[00H..99H] -> [0..99]
 ;****************************
 ;
-BCD2BIN:
+BCD2BYTE:
 	PUSH	BC
 	LD	C,A
 	AND	0F0H
@@ -493,13 +493,14 @@ BCD2BIN:
 ;	[0..99] => [00H..99H]
 ;*****************************
 ;
-BIN2BCD:
+BYTE2BCD:
 	PUSH	BC
 	LD	B,10
 	LD	C,-1
-DIV10:	INC	C
+BYTE2BCD1:
+	INC	C
 	SUB	B
-	JR	NC,DIV10
+	JR	NC,BYTE2BCD1
 	ADD	A,B
 	LD	B,A
 	LD	A,C
@@ -525,7 +526,7 @@ DIV10:	INC	C
 ;
 DELAY:					; 17 T STATES (FOR CALL)
 	PUSH	BC			; 11 T STATES
-	LD	B,((CPUFREQ * 2)  - 4)	; 8 T STATES
+	LD	B,((CPUMHZ * 2)  - 4)	; 8 T STATES
 	DJNZ	$			; (B*13) - 5 T STATES
 	POP	BC			; 10 T STATES
 	RET				; 10 T STATES
@@ -549,23 +550,24 @@ LDELAY:
 	POP	DE
 	RET
 ;
-; SHORT DELAY FUNCTIONS.  THESE ASSUME A CLOCK SPEED OF 33MHZ,
-; SO THEY WILL RUN LONGER FOR SLOWER CLOCK SPEEDS.  SO, THESE
-; ARE ONLY APPROPRIATE FOR VERY SHORT DELAYS.
-;
-DLY64MS:
-	CALL	DLY32MS
-DLY32MS:
-	CALL	DLY16MS
-DLY16MS:
-	CALL	DLY8MS
-DLY8MS:
-	CALL	DLY4MS
-DLY4MS:
-	CALL	DLY2MS
-DLY2MS:
-	CALL	DLY1MS
-DLY1MS:
+; SHORT DELAY FUNCTIONS.  NO CLOCK SPEED COMPENSATION, SO THEY
+; WILL RUN LONGER ON SLOWER SYSTEMS.  THE NUMBER INDICATES THE
+; NUMBER OF CALL/RET INVOCATIONS.  A SINGLE CALL/RET IS
+; 27 T-STATES ON A Z80, 25 T-STATES ON A Z180
+;
+DLY64:
+	CALL	DLY32
+DLY32:
+	CALL	DLY16
+DLY16:
+	CALL	DLY8
+DLY8:
+	CALL	DLY4
+DLY4:
+	CALL	DLY2
+DLY2:
+	CALL	DLY1
+DLY1:
 	RET
 
 ;
@@ -584,26 +586,57 @@ MULT8_LOOP:
 MULT8_NOADD:
 	DJNZ MULT8_LOOP
 	RET
-;
-; COMPUTE HL / DE
-; RESULT IN BC, REMAINDER IN HL, AND SET ZF DEPENDING ON REMAINDER
-; A, DE DESTROYED
-;
-DIV:
-	XOR	A
-	LD	BC,0
-DIV1:
+;;
+;; COMPUTE HL / DE
+;; RESULT IN BC, REMAINDER IN HL, AND SET ZF DEPENDING ON REMAINDER
+;; A, DE DESTROYED
+;;
+;DIV:
+;	XOR	A
+;	LD	BC,0
+;DIV1:
+;	SBC	HL,DE
+;	JR	C,DIV2
+;	INC	BC
+;	JR	DIV1
+;DIV2:
+;	XOR	A
+;	ADC	HL,DE		; USE ADC SO ZF IS SET
+;	RET
+;===============================================================
+;
+; COMPUTE HL / DE = BC W/ REMAINDER IN HL
+;
+DIV16:
+	; HL -> AC
+	LD	A,H
+	LD	C,L
+
+	; SETUP
+	LD	HL,0
+	LD	B,16
+;
+DIV16A:
+	; LOOP
+;	.DB	$CB,$31		; SLL	C
+	SLA	C
+	SET	0,C
+	RLA
+	ADC	HL,HL
 	SBC	HL,DE
-	JR	C,DIV2
-	INC	BC
-	JR	DIV1
-DIV2:
-	XOR	A
-	ADC	HL,DE		; USE ADC SO ZF IS SET
+	JR	NC,DIV16B
+	ADD	HL,DE
+	DEC	C
+DIV16B:
+	DJNZ	DIV16A
+
+	; AC -> BC
+	LD	B,A
+
 	RET
 ;
 ; FILL MEMORY AT HL WITH VALUE A, LENGTH IN BC, ALL REGS USED
-; LENGTH *MSUT* BE GREATER THAN 1 FOR PROPER OPERATION!!!
+; LENGTH *MUST* BE GREATER THAN 1 FOR PROPER OPERATION!!!
 ;
 FILL:
 	LD	D,H		; SET DE TO HL

Source/BIOS/ver.inc

@@ -1,7 +1,5 @@
 #DEFINE	RMJ	2
 #DEFINE	RMN	7
-#DEFINE	RUP	1
+#DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"2.7.1"
-#DEFINE BIOSBLD "Build 1 Developmental"
-#DEFINE REVISION 500
+#DEFINE BIOSVER	"2.7.0"

Source/BIOS/xio.asm

@@ -26,7 +26,7 @@ XIO_INIT:	; MINIMAL UART INIT
 
 #IF ((PLATFORM == PLT_N8VEM) | (PLATFORM == PLT_ZETA) | (PLATFORM == PLT_ZETA2) | (PLATFORM == PLT_S2I))
 
-XIO_DIV		.EQU	(1843200 / (16 * CONBAUD))
+XIO_DIV	.EQU	(UART0OSC / (16 * CONBAUD))
 
 	LD	A,$80			; LCR := DLAB ON
 	OUT	(SIO_LCR),A		; SET LCR