diff --git a/branches/dgg/Doc/Interrupts.txt b/branches/dgg/Doc/Interrupts.txt
new file mode 100644
index 00000000..1fd7ba95
--- /dev/null
+++ b/branches/dgg/Doc/Interrupts.txt
@@ -0,0 +1,64 @@
+Interrupts for RomWBW Firmware
+
+INTRODUCTION
+  The Z80 has four modes of interrupts.  Mode 0 is not suitable as the N8VEM range does not have the hardware to support it.  Mode 1 interrupts can be used if we're very careful when using banked memory.  This means either disabling interrupts whenever a new bank of memory is switched into the lower 32k or providing a means of dealing with the interrupt in each bank of memory switched into the lower 32k.  The /NMI interrupt has similar problems except that it must have a way dealing with it in all banks as it can't be disabled with the hardware provided.
+  So that leaves the Z80's most powerful interrupt mode - Mode 2.  Which is now catered for in the RomWBW firmware.  As of v2.2 the firmware will allow Mode 2 interrupts on the N8 or an N8VEM Z80-SBC with either a Zilog Peripherals or a 4PIO board.  Mode 2 allows interrupt service routines to be placed anywhere within the 64k addressable by the Z80.  The firmware is configured to keep these routines in the top 32k, out of harm's way.
+
+WHAT WON'T WORK
+  First the warnings.  The N8VEM Z80-SBC by itself can't use Mode 2 interrupts as it does not have the necessary hardware.  Similarly for the Zeta.  The /NMI input for any of the boards should not be used as mentioned in the introduction.
+
+N8 HARDWARE
+  The Z180 has 10 sources of maskable interrupts, three external and seven internal.  
+/INT0 works in much the same way as the /INT pin on a Z80.  It does not generate its own vector; that must be supplied externally by the interrupting device.  It should only be used with hardware that supports Mode 2 e.g. a Zilog Peripherals Board on the ECB BUS.  None of the on-board sources are suitable (PPI U7, TMS9918A).
+/INT1 generates its own vector and is suitable to be used with the on-board peripherals. 
+/INT2 generates its own vector and is connected to the on-board floppy drive controller.
+All internal interrupts only use Mode 2.
+
+N8VEM Z80-SBC HARDWARE
+  The only interrupt source on the Z80-SBC is the UART.  The UART's INT pin needs to be inverted and connected to a Z80 peripheral chip that can generate the interrupt vector.  For a MK-I board a modification is needed.  The collector of Q1 should be disconnected from the /INT pin and routed to pin A23 of the ECB connector with a 4k7 pull-up resistor (The /INT pin should still have its pull-up resistor R4 connected).  For the MK-II board install a jumper on pins 2-3 of K12.
+
+ZILOG PERIPHERALS
+  This board contains a Z80-DART, Z80-CTC and two Z80-PIOs, all of which can be used with Mode 2 interrupts.  To use an external non-vectored interrupt source (such as the CPU board's UART), pin A23 of the ECB BUS can be connected to an unused input of any of these chips.  The recommended modification is connecting ECB BUS pin A23 to pin 10 of header X4.  Then install a jumper on pins 9-10 of header X4 to use the channel 3 input of the CTC as a interrupt controller.
+
+4PIO
+  This board contains four Z80-PIOs, all of which can be used with Mode 2 interrupts.  To use an external non-vectored interrupt source one of the ports should be configured in PIO Mode 3.  This bit I/O mode can set up any to all of its eight port pins as an interrupt input.
+
+FIRMWARE
+  The RomWBW firmware itself does not use any interrupts (though this may change).  All it does is check which platform it is configured for and set the CPU to the appropriate mode.  Thirty-two bytes at FF00-FF1F are reserved for sixteen Mode 2 interrupt vectors.  All are set to point to a dummy Interrupt Service Routine (ISR) which merely:
+DUMISR:
+	EI		; RE-ENABLE INTERRUPTS
+	RETI		; RETURN FROM INTERRUPT
+It is left to the application to alter the vector address to point to the new ISR.  The firmware will configure the N8's CPU or chips on a Zilog Peripherals or 4PIO board to point to the vector table.  The default table (from bnk1.asm) is
+; DEFAULT VECTORS ALL POINT TO DUMMY INTERRUPT SERVICE ROUTINE
+HB_IVT:				; *** = NOT USED
+				; VECTOR ADDR	N8	4PIO	ZILOG PERIPHERAL
+	.DW	DUMISR		; FF00		/INT1	PIO0 A	CTC CHANNEL 0
+	.DW	DUMISR		; FF02		/INT2	PIO0 B	CTC CHANNEL 1
+	.DW	DUMISR		; FF04		PRT0	PIO1 A	CTC CHANNEL 2
+	.DW	DUMISR		; FF06		PRT1	PIO1 B	CTC CHANNEL 3
+	.DW	DUMISR		; FF08		DMA0	PIO2 A	PIO1 PORT A
+	.DW	DUMISR		; FF0A		DMA1	PIO2 B	PIO1 PORT B
+	.DW	DUMISR		; FF0C		CSI/O	PIO3 A	PIO2 PORT A
+	.DW	DUMISR		; FF0E		ASCI0	PIO3 B	PIO2 PORT B
+	.DW	DUMISR		; FF10		ASCI1	***	DART - ANY OR CH.B TX EMPTY
+	.DW	DUMISR		; FF12		***	***	DART CH.B EXTERNAL STATUS CHANGE
+	.DW	DUMISR		; FF14		***	***	DART CH.B RX CHAR AVAILABLE
+	.DW	DUMISR		; FF16		***	***	DART CH.B SPECIAL RECEIVE CONDITION
+	.DW	DUMISR		; FF18		***	***	DART CH.A TX EMPTY
+	.DW	DUMISR		; FF1A		***	***	DART CH.A EXTERNAL STATUS CHANGE
+	.DW	DUMISR		; FF1C		***	***	DART CH.A RX CHAR AVAILABLE
+	.DW	DUMISR		; FF1E		***	***	DART CH.A SPECIAL RECEIVE CONDITION
+
+FIRMWARE CONFIGURATION
+  For the N8 or Zeta boards no changes need to be made.  For the Z80-SBC boards there are configuration options for a Zilog Peripherals or one 4PIO board.  Only the board's base address needs to be set to match the jumpers on the board.  Suitable values that are unlikely to clash with other hardware are 10H, 0A0H, 0B0H, 0C0H, 0D0H and 0E0H.  A value of 0 is for no board attached.
+Alter these to suit your hardware (only one board of either type is supported by default).
+PIO4BASE	.EQU	0	;
+ZPBASE		.EQU	0	;
+
+OTHER NOTES
+  While there is no reason why a Zilog Peripherals or 4PIO board cannot be connected to a N8, this combination isn't configured in the firmware.
+
+  In the source is a file called "isr.asm".  Any interrupt service routines needed to be placed in the CBIOS area can be added to this file.  
+
+DGG
+
diff --git a/branches/dgg/Source/bnk1.asm b/branches/dgg/Source/bnk1.asm
index 9d561894..cb3e651d 100644
--- a/branches/dgg/Source/bnk1.asm
+++ b/branches/dgg/Source/bnk1.asm
@@ -46,6 +46,61 @@ INITSYS2:
 	LD	(CONDEV),A	; SET THE ACTIVE CONSOLE DEVICE
 #ENDIF
 ;
+; PERFORM INTERRUPT INITIALISATION
+;
+#IF (INTMODE = 2)
+	LD	A,0FFH		; INTERRUPT VECTOR TABLE PAGE
+	LD	I,A		; INTERRUPT VECTOR REGISTER
+	IM	2		; MODE 2 INTERRUPTS
+#IF (PLATFORM = PLT_N8)
+	XOR	A		; PUT Z180 VECTORS ON PAGE BOUNDARY
+	OUT	(CPU_IL),A
+#ENDIF
+#IF ((PLATFORM = PLT_N8VEM) & (ZPBASE !=0))
+				; INIT VECTORS ON ZILOG PERIPHERALS BOARD
+				; INIT Z80-CTC
+	XOR	A		; VECTOR AT FF00H
+	OUT	(ZPBASE+0),A	; ALL CHANNELS
+
+				; INIT Z80-PIO1
+	LD	A,08H		; VECTOR AT FF08H
+	OUT	(ZPBASE+0AH),A	; PORT A
+	LD	A,0AH		; VECTOR AT FF0AH
+	OUT	(ZPBASE+0BH),A	; PORT B
+
+				; INIT Z80-PIO2
+	LD	A,0CH		; VECTOR AT FF0CH
+	OUT	(ZPBASE+0EH),A	; PORT A
+	LD	A,0EH		; VECTOR AT FF0EH
+	OUT	(ZPBASE+0FH),A	; PORT B
+
+				; INIT Z80-DART/SIO
+	LD	A,02		; POINT TO REGISTER 2
+	OUT	(ZPBASE+7),A	; CHANNEL B COMMAND
+	LD	A,10H		; VECTOR AT FF10H
+	OUT	(ZPBASE+7),A	; ONE VECTOR FOR WHOLE CHIP
+#ENDIF
+#IF ((PLATFORM = PLT_N8VEM) & (PIO4BASE !=0))
+				; INIT VECTORS ON A 4PIO BOARD
+	XOR	A		; VECTOR AT FF00H
+	OUT	(PIO4BASE+1)	; PIO0 PORT A
+	LD	A,02		; VECTOR AT FF02H
+	OUT	(PIO4BASE+3)	; PIO0 PORT B
+	LD	A,04		; VECTOR AT FF04H
+	OUT	(PIO4BASE+5)	; PIO1 PORT A
+	LD	A,06		; VECTOR AT FF02H
+	OUT	(PIO4BASE+7)	; PIO1 PORT B
+	LD	A,08		; VECTOR AT FF02H
+	OUT	(PIO4BASE+9)	; PIO2 PORT A
+	LD	A,0AH		; VECTOR AT FF02H
+	OUT	(PIO4BASE+B)	; PIO2 PORT B
+	LD	A,0CH		; VECTOR AT FF02H
+	OUT	(PIO4BASE+D)	; PIO3 PORT A
+	LD	A,0EH		; VECTOR AT FF02H
+	OUT	(PIO4BASE+F)	; PIO3 PORT B
+#ENDIF
+#ENDIF
+;
 ; PERFORM DEVICE INITIALIZATION
 ;
 #IF (UARTENABLE)
@@ -411,8 +466,26 @@ HB_IMG	.EQU	$
 ;
 ; AREA RESERVED FOR UP TO 16 INTERRUPT VECTOR ENTRIES (MODE 2)
 ;
-HB_IVT:
-	.FILL	20H,0FFH
+; DEFAULT VECTORS ALL POINT TO DUMMY INTERRUPT SERVICE ROUTINE
+HB_IVT:				; *** = NOT USED
+				; VECTOR ADDR	N8	4PIO	ZILOG PERIPHERAL
+	.DW	DUMISR		; FF00		/INT1	PIO0 A	CTC CHANNEL 0
+	.DW	DUMISR		; FF02		/INT2	PIO0 B	CTC CHANNEL 1
+	.DW	DUMISR		; FF04		PRT0	PIO1 A	CTC CHANNEL 2
+	.DW	DUMISR		; FF06		PRT1	PIO1 B	CTC CHANNEL 3
+	.DW	DUMISR		; FF08		DMA0	PIO2 A	PIO1 A
+	.DW	DUMISR		; FF0A		DMA1	PIO2 B	PIO1 B
+	.DW	DUMISR		; FF0C		CSI/O	PIO3 A	PIO2 A
+	.DW	DUMISR		; FF0E		ASCI0	PIO3 B	PIO2 B
+	.DW	DUMISR		; FF10		ASCI1	***	DART - ANY OR CH.B TX EMPTY
+	.DW	DUMISR		; FF12		***	***	DART CH.B EXTERNAL STATUS CHANGE
+	.DW	DUMISR		; FF14		***	***	DART CH.B RX CHAR AVAILABLE
+	.DW	DUMISR		; FF16		***	***	DART CH.B SPECIAL RECEIVE CONDITION
+	.DW	DUMISR		; FF18		***	***	DART CH.A TX EMPTY
+	.DW	DUMISR		; FF1A		***	***	DART CH.A EXTERNAL STATUS CHANGE
+	.DW	DUMISR		; FF1C		***	***	DART CH.A RX CHAR AVAILABLE
+	.DW	DUMISR		; FF1E		***	***	DART CH.A SPECIAL RECEIVE CONDITION
+;	.FILL	20H,0FFH
 ;
 ;==================================================================================================
 ;   HBIOS INITIALIZATION
@@ -482,6 +555,15 @@ HB_ENTRY:
 ;
 HB_STKSAV	.DW	0	; PREVIOUS STACK POINTER (SEE PROXY)
 ;
+;==================================================================================================
+;   DUMMY INTERRUPT SERVICE ROUTINE
+;==================================================================================================
+;
+HB_DUMISR:
+DUMISR	.EQU	$
+	EI			; RE-ENABLE INTERRUPTS
+	RETI			; RETURN FROM INTERRUPT
+;
 HB_SLACK	.EQU	(HB_END - $)
 		.ECHO	"HBIOS space remaining: "
 		.ECHO	HB_SLACK
diff --git a/branches/dgg/Source/cbios.asm b/branches/dgg/Source/cbios.asm
index 3edaed53..e5cee404 100644
--- a/branches/dgg/Source/cbios.asm
+++ b/branches/dgg/Source/cbios.asm
@@ -98,8 +98,11 @@ BOOT:
 ;__________________________________________________________________________________________________			
 WBOOT:
 	DI
-	IM	1
-
+#IF (INTMODE = 2)
+	IM 	2		; HARDWARE SUPPORTS MODE 2 INTERRUPTS
+#ELSE
+	IM	1		; HARDWARE DOES NOT SUPPORT MODE 2 INTERRUPTS
+#ENDIF
 	LD	SP,ISTACK	; STACK FOR INITIALIZATION
 	
 	; RELOAD COMMAND PROCESSOR FROM CACHE
@@ -162,6 +165,9 @@ CURDSK:
 	LD	A,(CDISK)		; GET CURRENT USER/DISK
 GOCCP:
 	LD	C,A			; SETUP C WITH CURRENT USER/DISK, ASSUME IT IS OK
+#IF (INTMODE = 2)
+	EI				; BE BRAVE
+#ENDIF
 	JP	CCP
 ;
 ;__________________________________________________________________________________________________			
@@ -876,9 +882,9 @@ BLK_CMPLOOP:
 ; BLOCK DATA - INSERT CPM DMA BUF INTO PROPER PART OF PHYSICAL SECTOR BUFFER
 ;
 BLK_BLOCK:
-	CALL		BLK_SETUP	; SETUP SOURCE AND DESTINATION
-	EX		DE,HL		; SWAP HL/DE FOR BLOCK OPERATION
-	LD		BC,128		; DMA BUFFER SIZE
+	CALL	BLK_SETUP	; SETUP SOURCE AND DESTINATION
+	EX	DE,HL		; SWAP HL/DE FOR BLOCK OPERATION
+	LD	BC,128		; DMA BUFFER SIZE
 	LDIR				; COPY THE DATA
 	RET
 ;
@@ -887,9 +893,9 @@ BLK_BLOCK:
 ; DEBLOCK DATA - EXTRACT DESIRED CPM DMA BUF FROM PHYSICAL SECTOR BUFFER
 ;
 BLK_DEBLOCK:
-	CALL		BLK_SETUP	; SETUP SOURCE AND DESTINATION
-	LD		BC,128		; DMA BUFFER SIZE
-	LDIR				; COPY THE DATA
+	CALL	BLK_SETUP	; SETUP SOURCE AND DESTINATION
+	LD	BC,128		; DMA BUFFER SIZE
+	LDIR			; COPY THE DATA
 	RET
 ;
 ;__________________________________________________________________________________________________
@@ -898,17 +904,17 @@ BLK_DEBLOCK:
 ; AT EXIT, HL = ADDRESS OF DESIRED BLOCK IN SECTOR BUFFER, DE = DMA
 ;
 BLK_SETUP:	
-	LD		BC,(SEKSEC)
-	LD		A,C
-	AND		3		; A = INDEX OF CPM BUF IN SEC BUF
-	RRCA				; MULTIPLY BY 64
+	LD	BC,(SEKSEC)
+	LD	A,C
+	AND	3		; A = INDEX OF CPM BUF IN SEC BUF
+	RRCA			; MULTIPLY BY 64
 	RRCA
-	LD		E,A		; INTO LOW ORDER BYTE OF DESTINATION
-	LD		D,0		; HIGH ORDER BYTE IS ZERO
-	LD		HL,(BUFADR)	; HL = START OF SEC BUF
-	ADD		HL,DE		; ADD IN COMPUTED OFFSET
-	ADD		HL,DE		; HL NOW = INDEX * 128 (SOURCE)
-	LD		DE,(DMAADR)	; DE = DESTINATION = DMA BUF
+	LD	E,A		; INTO LOW ORDER BYTE OF DESTINATION
+	LD	D,0		; HIGH ORDER BYTE IS ZERO
+	LD	HL,(BUFADR)	; HL = START OF SEC BUF
+	ADD	HL,DE		; ADD IN COMPUTED OFFSET
+	ADD	HL,DE		; HL NOW = INDEX * 128 (SOURCE)
+	LD	DE,(DMAADR)	; DE = DESTINATION = DMA BUF
 	RET
 ;
 ;==================================================================================================
@@ -1344,6 +1350,13 @@ MD_DMACPY:
 ;
 #INCLUDE "memmgr.asm"
 ;
+ORG_ISR		.EQU	$
+#INCLUDE "isr.asm"
+SIZ_ISR		.EQU	$ - ORG_ISR
+		.ECHO	"ISR occupies "
+		.ECHO	SIZ_ISR
+		.ECHO	" bytes.\n"
+;
 ;==================================================================================================
 ; UTILITY FUNCTIONS
 ;==================================================================================================
@@ -1793,15 +1806,15 @@ SLACK		.EQU	(CBIOS_END - $ - 32 - 32 - 16 - 512)
 ; OF THE MEDIA ID'S (SAME SEQUENCE, NO GAPS)
 ;
 DPB_MAP:
-	.DW	0		; MID_NONE (NO MEDIA)
-	.DW	DPB_ROM		; MID_MDROM
-	.DW	DPB_RAM		; MID_MDRAM
-	.DW	DPB_HD		; MID_HD
-	.DW	DPB_FD720	; MID_FD720
-	.DW	DPB_FD144	; MID_FD144
-	.DW	DPB_FD360	; MID_FD360
-	.DW	DPB_FD120	; MID_FD120
-	.DW	DPB_FD111	; MID_FD111
+	.DW	0			; MID_NONE (NO MEDIA)
+	.DW	DPB_ROM			; MID_MDROM
+	.DW	DPB_RAM			; MID_MDRAM
+	.DW	DPB_HD			; MID_HD
+	.DW	DPB_FD720		; MID_FD720
+	.DW	DPB_FD144		; MID_FD144
+	.DW	DPB_FD360		; MID_FD360
+	.DW	DPB_FD120		; MID_FD120
+	.DW	DPB_FD111		; MID_FD111
 ;
 DPB_CNT	.EQU	($ - DPB_MAP) / 2
 ;
@@ -2003,7 +2016,12 @@ CFGBUF:				; START OF 256 BYTE CONFIG BUFFER
 ;
 INIT:
 	DI
-	IM	1
+#IF (INTMODE = 2)
+	IM 	2		; HARDWARE SUPPORTS MODE 2 INTERRUPTS
+	CALL	INITISR		; INITIALISE VECTOR TABLE AND ANY INTERRUPT HARDWARE
+#ELSE
+	IM	1		; HARDWARE DOES NOT SUPPORT MODE 2 INTERRUPTS
+#ENDIF
 	
 	; SETUP A TEMP STACK IN UPPER 32K
 	LD	SP,ISTACK		; STACK FOR INITIALIZATION
@@ -2025,17 +2043,17 @@ INIT:
 	LD	(IOBYTE),A		; STORE IT
 	
 #IF (PLATFORM != PLT_N8)
-	IN	A,(RTC)		; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER
-;	LD	A,40H		; *DEBUG* SIMULATE JUMPER OPEN
-;	LD	A,00H		; *DEBUG* SIMULATE JUMPER SHORTED
-	AND	40H		; ISOLATE BIT 6
-	JR	Z,INIT1		; IF BIT6=0, SHORTED, USE ALT IOBYTE
-	LD	A,DEFIOBYTE	; LOAD DEF IOBYTE VALUE
-	JR	INIT2		; CONTINUE
+	IN	A,(RTC)			; RTC PORT, BIT 6 HAS STATE OF CONFIG JUMPER
+;	LD	A,40H			; *DEBUG* SIMULATE JUMPER OPEN
+;	LD	A,00H			; *DEBUG* SIMULATE JUMPER SHORTED
+	AND	40H			; ISOLATE BIT 6
+	JR	Z,INIT1			; IF BIT6=0, SHORTED, USE ALT IOBYTE
+	LD	A,DEFIOBYTE		; LOAD DEF IOBYTE VALUE
+	JR	INIT2			; CONTINUE
 INIT1:
-	LD	A,ALTIOBYTE	; LOAD ALT IOBYTE VALUE
+	LD	A,ALTIOBYTE		; LOAD ALT IOBYTE VALUE
 INIT2:	
-	LD	(IOBYTE),A	; SET THE ACTIVE IOBYTE
+	LD	(IOBYTE),A		; SET THE ACTIVE IOBYTE
 #ENDIF
 	
 	; DEFAULT DRIVE
diff --git a/branches/dgg/Source/config_n8vem.asm b/branches/dgg/Source/config_n8vem.asm
index e97bafc7..f4b719cb 100644
--- a/branches/dgg/Source/config_n8vem.asm
+++ b/branches/dgg/Source/config_n8vem.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/config_n8vem_dide.asm b/branches/dgg/Source/config_n8vem_dide.asm
index 1e7d50d4..7639932d 100644
--- a/branches/dgg/Source/config_n8vem_dide.asm
+++ b/branches/dgg/Source/config_n8vem_dide.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/config_n8vem_diskio.asm b/branches/dgg/Source/config_n8vem_diskio.asm
index ef7ecf3b..cae51b49 100644
--- a/branches/dgg/Source/config_n8vem_diskio.asm
+++ b/branches/dgg/Source/config_n8vem_diskio.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/config_n8vem_diskio3.asm b/branches/dgg/Source/config_n8vem_diskio3.asm
index f56e1e98..f0314e3a 100644
--- a/branches/dgg/Source/config_n8vem_diskio3.asm
+++ b/branches/dgg/Source/config_n8vem_diskio3.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/config_n8vem_ppide.asm b/branches/dgg/Source/config_n8vem_ppide.asm
index 0b446223..07bec712 100644
--- a/branches/dgg/Source/config_n8vem_ppide.asm
+++ b/branches/dgg/Source/config_n8vem_ppide.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/config_n8vem_ppisd.asm b/branches/dgg/Source/config_n8vem_ppisd.asm
index 4dff875f..f1ebe93f 100644
--- a/branches/dgg/Source/config_n8vem_ppisd.asm
+++ b/branches/dgg/Source/config_n8vem_ppisd.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/config_n8vem_propio.asm b/branches/dgg/Source/config_n8vem_propio.asm
index be2262e0..8ac84388 100644
--- a/branches/dgg/Source/config_n8vem_propio.asm
+++ b/branches/dgg/Source/config_n8vem_propio.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/config_n8vem_vdu.asm b/branches/dgg/Source/config_n8vem_vdu.asm
index 5f1bb97a..515256ed 100644
--- a/branches/dgg/Source/config_n8vem_vdu.asm
+++ b/branches/dgg/Source/config_n8vem_vdu.asm
@@ -84,3 +84,6 @@ BOOT_DEFAULT	.EQU	'R'		; SELECTION TO INVOKE AT TIMEOUT
 ;
 BAUDRATE	.EQU	38400		; IN BPS: 1200, 9600, 38400, ..., 115200
 TERMTYPE	.EQU	TERM_ANSI	; TERM_TTY=0, TERM_ANSI=1, TERM_WYSE=2
+;
+PIO4BASE	.EQU	0		; BASE ADDRESS OF 4PIO BOARD (0=NO BOARD, USE 10H, 0A0H, 0B0H, 0C0H, 0D0H, 0E0H
+ZPBASE		.EQU	0		; BASE ADDRESS OF ZILOG PERIPHERALS BOARD (SAME AS PIO4BASE)
diff --git a/branches/dgg/Source/sd.asm b/branches/dgg/Source/sd.asm
index 931e9d63..513e9272 100644
--- a/branches/dgg/Source/sd.asm
+++ b/branches/dgg/Source/sd.asm
@@ -88,14 +88,22 @@ SD_DISPATCH:
 ;
 SD_MEDIA:
 	; INITIALIZE THE SD CARD TO ACCOMMODATE HOT SWAPPING
+#IF (INTMODE = 2)
+	DI
+#ENDIF
 	CALL	SD_INITCARD
 	LD	A,MID_NONE	; ASSUME FAILURE
-	RET	NZ		; INIT FAILED, RETURN WITH HL=0
+;	RET	NZ		; INIT FAILED, RETURN WITH HL=0
+	JR	NZ,SD_MEDIAEND	; INIT FAILED, RETURN WITH HL=0
 
 	; SET READY AND RETURN
 	XOR	A
 	LD	(SD_STAT),A	; SD_STAT = 0 = OK
 	LD	A,MID_HD
+SD_MEDIAEND:
+#IF (INTMODE = 2)
+	EI
+#ENDIF
 	RET
 ;
 SD_INIT:
@@ -715,8 +723,12 @@ SD_CHKCARD:
 	RET				; RETURN WITH STATUS IN A
 
 SD_RDSEC:
+#IF (INTMODE = 2)
+	DI
+#ENDIF
 	CALL	SD_CHKCARD	; CHECK / REINIT CARD AS NEEDED
-	RET	NZ
+;	RET	NZ
+	JR	NZ,SD_RDSECEND
 
 	CALL	SD_WAITRDY	; WAIT FOR CARD TO BE READY FOR A COMMAND
 	JP	NZ,SD_ERRRDYTO	; HANDLE NOT READY TIMEOUT ERROR
@@ -732,13 +744,21 @@ SD_RDSEC:
 	CALL	SD_GETDATA	; GET THE BLOCK
 	CALL	SD_DONE
 	JP	NZ,SD_ERRDATA	; DATA XFER ERROR
+SD_RDSECEND:
+#IF (INTMODE = 2)
+	EI
+#ENDIF
 	RET
 ;
 ; WRITE ONE SECTOR
 ;
 SD_WRSEC:
+#IF (INTMODE = 2)
+	DI
+#ENDIF
 	CALL	SD_CHKCARD	; CHECK / REINIT CARD AS NEEDED
-	RET	NZ
+;	RET	NZ
+	JR	NZ,SD_WRSECEND
 
 	CALL	SD_WAITRDY	; WAIT FOR CARD TO BE READY FOR A COMMAND
 	JP	NZ,SD_ERRRDYTO	; HANDLE NOT READY TIMEOUT ERROR
@@ -754,6 +774,10 @@ SD_WRSEC:
 	CALL	SD_PUTDATA	; PUT THE BLOCK
 	CALL	SD_DONE
 	JP	NZ,SD_ERRDATA	; DATA XFER ERROR
+SD_WRSECEND:
+#IF (INTMODE = 2)
+	EI
+#ENDIF
 	RET
 ;
 ;	
@@ -844,6 +868,9 @@ SD_CARDERR:
 #ENDIF
 	POP	AF
 	LD	(SD_STAT),A
+#IF (INTMODE = 2)
+	EI
+#ENDIF
 	RET
 ;
 ; PRINT DIAGNONSTIC PREFIX
diff --git a/branches/dgg/Source/std.asm b/branches/dgg/Source/std.asm
index 01cd7693..01223386 100644
--- a/branches/dgg/Source/std.asm
+++ b/branches/dgg/Source/std.asm
@@ -438,6 +438,20 @@ BDOS:	 	.EQU 	CCP+806H	; BASE OF BDOS
 BIOS:	 	.EQU 	CCP+1600H	; BASE OF BIOS
 CCPSIZ:		.EQU	00800H
 ;
+#IF (PLATFORM = PLT_N8) 
+INTMODE		.EQU	2	; N8 USES MODE 2 INTERRUPTS
+#ENDIF
+#IF (PLATFORM = PLT_ZETA)
+INTMODE		.EQU	1	; ZETA CAN ONLY USE MODE 1 
+#ENDIF
+#IF (PLATFORM = PLT_N8VEM)
+  #IF ((ZPBASE != 0) | (PIO4BASE != 0))
+INTMODE		.EQU	2	; MODE 2 WITH ZILOG PERIPHERALS OR 4PIO
+  #ELSE
+INTMODE		.EQU	1	; N8VEM BY ITSELF CAN ONLY USE MODE 1
+  #ENDIF
+#ENDIF
+
 #IF (PLATFORM == PLT_N8VEM)
   #DEFINE 	PLATFORM_NAME	"N8VEM Z80 SBC"
 #ENDIF
diff --git a/branches/dgg/Source/util.asm b/branches/dgg/Source/util.asm
index 48b6d32c..a5dee9cc 100644
--- a/branches/dgg/Source/util.asm
+++ b/branches/dgg/Source/util.asm
@@ -191,6 +191,7 @@ WRITESTR2:
 ; PANIC: TRY TO DUMP MACHINE STATE AND HALT
 ;
 PANIC:
+	DI				; STOP ANY INTERRUPTS
 	PUSH	HL
 	PUSH	DE
 	PUSH	BC
diff --git a/branches/dgg/Source/vdu.asm b/branches/dgg/Source/vdu.asm
index d9762a12..bac9376a 100644
--- a/branches/dgg/Source/vdu.asm
+++ b/branches/dgg/Source/vdu.asm
@@ -804,6 +804,11 @@ VDU_INIT6845:
 ; HORIZONTAL LINE WIDTH IS 64uS.  FOR A 2 MHz CHARACTER CLOCK (R0+1)/2000000 = 64uS
 ; NEAREST NUMBER OF LINES IS 312 = (R4+1) * (R9+1) + R5.
 ; 15625 / 312 = 50.08 FIELDS PER SECOND (NEAR ENOUGH-DGG)
+;
+; IF TRYING THE SLOWER CHAR CLOCK TO GIVE 9 PIXELS HORIZONTAL PER CHAR, CHANGE THE FOLLOWING
+; JUMPER K1 1-2 TO GIVE 1.777MHz CHAR CLOCK
+; CHANGE R0 TO 112 FOR A HSYNC OF 15732
+; CHANGE R2 TO 91 TO CENTRE DISPLAY     
      
      
 ;__VDU_CRTINIT_____________________________________________________________________________________