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Support Z180 IM1

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Added proper support for interrupt mode 1 on Z180.
This commit is contained in:
Wayne Warthen
2023-07-01 15:33:18 -07:00
parent 5c0894b8c1
commit 229bdaa308
7 changed files with 76 additions and 103 deletions
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31
Source/HBIOS/std.asm
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@@ -728,12 +728,13 @@ MON_SERIAL .EQU MON_LOC + (1 * 3) ; MONITOR ENTRY (SERIAL PORT)
;
; INTERRUPT MODE 2 SLOT ASSIGNMENTS
;
#IF ((INTMODE == 2) | (INTMODE == 3))
#IF (((CPUFAM == CPU_Z180) | (CPUFAM == CPU_Z280)) & (INTMODE > 0))
#IF ((CPUFAM == CPU_Z180) | (CPUFAM == CPU_Z280))
; NOTE THAT Z180 PROCESSES ALL INTERNAL INTERRUPTS JUST LIKE
; IM2 EVEN WHEN CHIP IS IN IM1 MODE. SO WE INCLUDE THE IM2
; INTERRUPT ASSIGNMENTS FOR IM1 BELOW.
; Z180-BASED SYSTEMS
INT_INT1 .EQU 0 ; Z180 INT 1
INT_INT2 .EQU 1 ; Z180 INT 2
INT_TIM0 .EQU 2 ; Z180 TIMER 0
@@ -750,19 +751,18 @@ INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
INT_SIO0 .EQU 13 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B
#ELSE
#ENDIF
; Z80-BASED SYSTEMS
#IF (PLATFORM == PLT_MBC)
#IF ((CPUFAM == CPU_Z80) & (INTMODE == 2))
#IF (PLATFORM == PLT_MBC)
; MBC Z80
;INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
;INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
;INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
;INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; MBC UART 0
INT_UART1 .EQU 5 ; MBC UART 1
INT_UART0 .EQU 4 ; UART 0
INT_UART1 .EQU 5 ; UART 1
INT_SIO0 .EQU 8 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 9 ; ZILOG SIO 1, CHANNEL A & B
INT_CTC0A .EQU 12 ; ZILOG CTC 0, CHANNEL A
@@ -774,14 +774,15 @@ INT_CTC0D .EQU 15 ; ZILOG CTC 0, CHANNEL D
;INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
;INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ELSE
#ELSE
; GENERIC Z80
INT_CTC0A .EQU 0 ; ZILOG CTC 0, CHANNEL A
INT_CTC0B .EQU 1 ; ZILOG CTC 0, CHANNEL B
INT_CTC0C .EQU 2 ; ZILOG CTC 0, CHANNEL C
INT_CTC0D .EQU 3 ; ZILOG CTC 0, CHANNEL D
INT_UART0 .EQU 4 ; MBC UART 0
INT_UART1 .EQU 5 ; MBC UART 1
INT_UART0 .EQU 4 ; UART 0
INT_UART1 .EQU 5 ; UART 1
INT_SIO0 .EQU 7 ; ZILOG SIO 0, CHANNEL A & B
INT_SIO1 .EQU 8 ; ZILOG SIO 1, CHANNEL A & B
INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A
@@ -790,13 +791,11 @@ INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A
INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B
#ENDIF
#ENDIF
#ENDIF
#DEFINE IVT(INTX) HB_IVT+(INTX * 4)+1
#DEFINE VEC(INTX) INTX*2
#ENDIF
;
; SET DEFAULT CSIO SPEED (INTERNAL CLOCK, SLOW AS POSSIBLE)
; DIV 1280, 14KHZ @ 18MHZ CLK