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Rename ZZRC -> ZZRCC, Update to CLRDIR

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- The naming of ZZRCC was incorrectly ZZRC.  Corrected.
- Max Scane has provided a small bug fix for CLRDIR.
- Minor build updates for new HTalk utility.
This commit is contained in:
Wayne Warthen
2023-10-08 17:57:58 -07:00
parent 76867b8351
commit 25fb2bd59e
58 changed files with 285 additions and 197 deletions
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41
Source/ZRC/Bank Layout.txt Normal file
View File

@@ -0,0 +1,41 @@
ZRC has no real ROM. It has a single 2048K RAM chip. There
are two startup modes supported by RomWBW.
The normal startup mode treats the first 512KB like ROM and the
remaining 1536KB as RAM. The first 512KB (pseudo-ROM) must be preloaded
by the ZRC CF Loader. This mode simulates a normal ROM-based RomWBW
startup.
Bank Contents Description
---- -------- -----------
0x0 BOOT Boot Bank (HBIOS image) +
0x1 IMG0 ROM Loader, Monitor, ROM OSes |
0x2 IMG1 ROM Applications | Pseudo-ROM
0x3 IMG2 Reserved |
0x4-0xF ROMD ROM Disk Banks +
0x10 BIOS HBIOS Bank (operating)
0x11-0x3B RAMD RAM Disk Banks
0x3C BUF OS Buffers (CP/M3)
0x3D AUX Aux Bank (CP/M 3, BPBIOS, etc.)
0x3E USR User Bank (CP/M TPA, etc.)
0x3F COM Common Bank, Upper 32KB
The ROMless startup mode treats the entire 2048KB as RAM. However, in
this mode, only the first 512KB of RAM is utilized. This is because
the RAM Disk is seeded by the CF Loader which is currently constrained
to loading 512KB. The entire 512KB of RAM (less the top 32KB) must be
preloaded by the ZRC CF Loader. There will be no ROM disk available
under RomWBW. There will be a RAM Disk and it's initial contents will
be seeded by the image loaded by the CF Loader.
Bank Contents Description
-------- -------- -----------
0x0 BIOS HBIOS Bank (operating)
0x1 IMG0 ROM Loader, Monitor, ROM OSes
0x2 IMG1 ROM Applications
0x3 IMG2 Reserved
0x4-0xB RAMD RAM Disk Banks
0xC BUF OS Buffers (CP/M3)
0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.)
0xE USR User Bank (CP/M TPA, etc.)
0xF COM Common Bank, Upper 32KB

33
Source/ZRC/ZRC Disk Layout.txt
View File

@@ -1,19 +1,17 @@
CF Boot Loader: Sector 0 (bytes 0-255)
RomWBW Partition Table: Sector 0 (bytes 256-511)
ZRC Monitor: Sectors 0xF8-0xFF (bytes 0x1F000-0x1FFFF)
RomWBW: Sectors 0x120-0x51F (bytes 0x24000-0xA3FFF)
Start of Slices (0x1E partition): Sector 0x800 (byte 0x100000)
ZRC Disk Prefix Layout
======================
Start Length Description
------- ------- ---------------------------
0x00000 0x00100 CF Boot Loader
0x00100 0x00100 RomWBW Partition Table
0x00200 0x1EE00 Filler
0x1F000 0x01000 ZRC Monitor
0x20000 0x04000 Filler
0x24000 0x80000 RomWBW
0xA4000 0x5C000 Filler
0x100000: Start of slices (partition 0x1E)
---- Bytes ---- --- Sectors ---
Start Length Start Length Description
------- ------- ------- ------- ---------------------------
0x00000 0x00100 0 0.5 CF Boot Loader
0x00100 0x00100 0.5 0.5 RomWBW Partition Table
0x00200 0x1EE00 1 247 Unused
0x1F000 0x01000 248 8 ZRC Monitor v0.7
0x20000 0x04000 256 32 Unused
0x24000 0x80000 288 1024 RomWBW
0xA4000 0x5C000 1312 736 Unused
0x100000 2048 Start of slices (partition 0x1E)
Notes
-----
@@ -21,4 +19,7 @@ Notes
- At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
- CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
- ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of RAM
- ZRC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
- ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
-- WBW 2:30 PM 10/8/2023