Rename ZZRC -> ZZRCC, Update to CLRDIR

- The naming of ZZRCC was incorrectly ZZRC.  Corrected.
- Max Scane has provided a small bug fix for CLRDIR.
- Minor build updates for new HTalk utility.

Source/ZZRCC/Bank Layout.txt

@@ -0,0 +1,39 @@
+ZZRCC has no real ROM.  It has a single 512K RAM chip.  There
+are two startup modes supported by RomWBW.
+
+The normal startup mode treats the first 256KB like ROM and the second 
+256KB as RAM.  The first 256KB (pseudo-ROM) must be preloaded by the 
+ZZRCC CF Loader.  This mode simulates a normal ROM-based RomWBW
+startup.
+
+Bank		Contents	Description
+----		--------	-----------
+0x0		BOOT		Boot Bank (HBIOS image)		+
+0x1		IMG0		ROM Loader, Monitor, ROM OSes	|
+0x2		IMG1		ROM Applications		| Pseudo-ROM
+0x3		IMG2		Reserved			|
+0x4-0x7		ROMD		ROM Disk Banks			+
+0x8		BIOS		HBIOS Bank (operating)
+0x9-0xB		RAMD		RAM Disk Banks
+0xC		BUF		OS Buffers (CP/M3)
+0xD		AUX		Aux Bank (CP/M 3, BPBIOS, etc.)
+0xE		USR		User Bank (CP/M TPA, etc.)
+0xF		COM		Common Bank, Upper 32KB
+
+The ROMless startup mode treats the entire 512KB as RAM.  The entire
+512KB of RAM (less the top 32KB) must be preloaded by the ZZRCC CF
+Loader.  There will be no ROM disk available under RomWBW.  There
+will be a RAM Disk and it's initial contents will be seeded by the
+image loaded by the CF Loader.
+
+Bank		Contents	Description
+--------	--------	-----------
+0x0		BIOS		HBIOS Bank (operating)
+0x1		IMG0		ROM Loader, Monitor, ROM OSes
+0x2		IMG1		ROM Applications
+0x3		IMG2		Reserved
+0x4-0xB		RAMD		RAM Disk Banks
+0xC		BUF		OS Buffers (CP/M3)
+0xD		AUX		Aux Bank (CP/M 3, BPBIOS, etc.)
+0xE		USR		User Bank (CP/M TPA, etc.)
+0xF		COM		Common Bank, Upper 32KB

Source/ZZRCC/Build.cmd

@@ -0,0 +1,41 @@
+:: @echo off
+setlocal
+
+set ROMFILE=..\..\Binary\RCZ280_zzrcc.rom
+set ROMSIZE=262144
+
+set TOOLS=../../Tools
+
+set PATH=%TOOLS%\srecord;%PATH%
+
+if exist ..\..\Binary\RCZ280_zzrcc.rom call :build_zzrcc
+
+if exist ..\..\Binary\RCZ280_zzrcc_ram.rom call :build_zzrcc_ram
+
+goto :eof
+
+:build_zzrcc
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat
+
+copy /b ..\..\Binary\hd1k_zzrcc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrcc_combo.img || exit /b
+
+goto :eof
+
+:build_zzrcc_ram
+
+srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary
+move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat
+
+copy /b ..\..\Binary\hd1k_zzrcc_ram_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrcc_ram_combo.img || exit /b
+
+goto :eof

Source/ZZRCC/Clean.cmd

@@ -0,0 +1,3 @@
+@echo off
+setlocal
+

Source/ZZRCC/Makefile

@@ -0,0 +1,48 @@
+HD1KZZRCCPREFIX = hd1k_zzrcc_prefix.dat
+HD1KZZRCCCOMBOIMG = hd1k_zzrcc_combo.img
+HD1KZZRCCRAMPREFIX = hd1k_zzrcc_ram_prefix.dat
+HD1KZZRCCRAMCOMBOIMG = hd1k_zzrcc_ram_combo.img
+ZZRCCROM = ../../Binary/RCZ280_zzrcc.rom
+ZZRCCRAMROM = ../../Binary/RCZ280_zzrcc_ram.rom
+HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \
+	../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img
+
+OBJECTS :=
+
+ifneq ($(wildcard $(ZZRCCROM)),)
+	OBJECTS += $(HD1KZZRCCPREFIX) $(HD1KZZRCCCOMBOIMG)
+endif
+
+ifneq ($(wildcard $(ZZRCCRAMROM)),)
+	OBJECTS += $(HD1KZZRCCRAMPREFIX) $(HD1KZZRCCRAMCOMBOIMG)
+endif
+
+DEST=../../Binary
+
+TOOLS = ../../Tools
+
+include $(TOOLS)/Makefile.inc
+
+DIFFPATH = $(DIFFTO)/Binary
+
+$(HD1KZZRCCPREFIX):
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
+
+$(HD1KZZRCCRAMPREFIX):
+	srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x0 0x100 zzrcc_cfldr.bin -binary -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x100 0x200 zzrcc_ptbl.bin -binary -offset 0x100 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary
+	srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCRAMROM) -binary -offset 0x24000 -o temp.dat -binary
+	mv temp.dat $@
+
+$(HD1KZZRCCCOMBOIMG): $(HD1KZZRCCPREFIX) $(HD1KIMGS)
+	cat $^ > $@
+
+$(HD1KZZRCCRAMCOMBOIMG): $(HD1KZZRCCRAMPREFIX) $(HD1KIMGS)
+	cat $^ > $@

Source/ZZRCC/ZZRCC Disk Layout.txt

@@ -0,0 +1,25 @@
+ZZRCC Disk Prefix Layout
+========================
+
+---- Bytes ----   --- Sectors ---
+Start   Length    Start   Length    Description
+------- -------   ------- -------   ---------------------------
+0x00000 0x00100   0       0.5       CF Boot Loader
+0x00100 0x00100   0.5     0.5       RomWBW Partition Table
+0x00200 0x1EE00   1       247       Unused
+0x1F000 0x01000   248     8         ZZRCC Monitor v0.5
+0x20000 0x04000   256     32        Unused
+0x24000 0x80000   288     1024      RomWBW
+0xA4000 0x5C000   1312    736       Unused  
+0x100000          2048              Start of slices (partition 0x1E)
+
+Notes
+-----
+
+- At startup CPLD ROM is mapped to Z280 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
+- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
+- CF Boot Loader reads ZZRCC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
+- ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of physical RAM
+- ZZRCC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000
+
+-WBW 2:36 PM 10/8/2023