mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 22:43:15 -06:00
Support for DS1305 RTC on S100 FPGA Z80
This commit is contained in:
Wayne Warthen
@@ -5912,6 +5912,16 @@ MD: TYPE=RAM
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PPIDE: IO=48, MASTER
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PPIDE: IO=48, SLAVE
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FP: LEDIO=255
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DS5RTC: RTCIO=104, IO=104
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SSER: IO=52
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SCON: IO=0
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MD: TYPE=RAM
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PPIDE: IO=48, MASTER
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PPIDE: IO=48, SLAVE
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SD: MODE=FZ80, IO=108, UNITS=2
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##### Notes:
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- Requires matching FPGA code
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@@ -5933,7 +5943,8 @@ may be discovered by RomWBW in your system.
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| CTC | System | Zilog Clock/Timer |
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| CVDU | Video | MC8563-based Video Display Controller |
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| DMA | System | Zilog DMA Controller |
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| DS1307 | RTC | Maxim DS1307 PCF I2C Real-Time Clock w/ NVRAM |
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| DS5RTC | RTC | Maxim DS1305 SPI Real-Time Clock w/ NVRAM |
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| DS7RTC | RTC | Maxim DS1307 PCF I2C Real-Time Clock w/ NVRAM |
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| DS1501RTC | RTC | Maxim DS1501/DS1511 Watchdog Real-Time Clock |
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| DSRTC | RTC | Maxim DS1302 Real-Time Clock w/ NVRAM |
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| DUART | Char | SCC2681 or compatible Dual UART |
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@@ -5973,6 +5984,7 @@ may be discovered by RomWBW in your system.
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| SN76489 | Sound | SN76489 Programmable Sound Generator |
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| SPK | Sound | Bit-bang Speaker |
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| SYQ | Disk | Iomega SparQ Drive on PPI |
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| SSER | Char | Simple Serial Interface |
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| TMS | Video | TMS9918/38/58 Video Display Controller |
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| UART | Char | 16C550 Family Serial Interface |
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| USB-FIFO | Char | FT232H-based ECB USB FIFO |
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@@ -28,7 +28,3 @@
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;
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CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ
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CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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;
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; SD CARD SUPPORT CURRENTLY BROKEN
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SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
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SDTRACE .SET 3 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
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@@ -124,6 +124,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -128,6 +128,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU TRUE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $34 ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -155,6 +155,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -121,6 +121,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -121,6 +121,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -128,6 +128,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -132,6 +132,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
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;
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
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@@ -121,6 +121,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
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DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
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DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
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;
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
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;
|
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
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|
||||
@@ -126,6 +126,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
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DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
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;
|
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SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
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SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
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|
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@@ -119,6 +119,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
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;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
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SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
|
||||
@@ -108,6 +108,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
|
||||
@@ -119,6 +119,8 @@ SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
|
||||
DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM)
|
||||
DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF]
|
||||
;
|
||||
DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
|
||||
;
|
||||
SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
|
||||
SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG
|
||||
SSERSTATUS .EQU $FF ; SSER: STATUS PORT
|
||||
|
||||
566
Source/HBIOS/ds5rtc.asm
Normal file
566
Source/HBIOS/ds5rtc.asm
Normal file
@@ -0,0 +1,566 @@
|
||||
;
|
||||
;==================================================================================================
|
||||
; MAXIM DS1305 RTC DRIVER
|
||||
;==================================================================================================
|
||||
;
|
||||
; THE DS1305 USES AN SPI INTERFACE. THIS DRIVER CURRENTLY ASSUMES THE
|
||||
; FPGA-BASED SPI INTERFACE IMPLEMENTED IN THE S100 FPGA Z80.
|
||||
;
|
||||
; TRICKLE CHARGING IS NOT CURRENTLY IMPLEMENTED SINCE THE S100 FPGA Z80
|
||||
; DOES NOT SUPPORT THE USER OF A SUPER CAPACITOR.
|
||||
;
|
||||
; REGISTER ADDRESSES (HEX / BCD):
|
||||
;
|
||||
; +---+-----+---------------+-------------------+------------------+----------------+
|
||||
; |ADR| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | RANGE | REGISTER |
|
||||
; +---+-----+---------------+-------------------+------------------+----------------+
|
||||
; | 0 | 0 | 10-SECOND | 1-SECOND | 00-59 | SECONDS |
|
||||
; +---+-----+-----+---------+-------------------+------------------+----------------+
|
||||
; | 1 | 0 | 10-MINUTE | 1-MINUTE | 00-59 | MINUTES |
|
||||
; +---+-----+-----+---------+-------------------+------------------+----------------+
|
||||
; | 2 | 0 | 0 | 10-HOUR | 1-HOUR | 00-23 | HOURS |
|
||||
; +---+-----+-----+----+----+-------------------+------------------+----------------+
|
||||
; | 3 | 0 | 0 | 0 | 0 | DAY OF WEEK | 01-07 | DAY OF WEEK |
|
||||
; +---+-----+-----+----+----+----+--------------+------------------+----------------+
|
||||
; | 4 | 0 | 0 | 10-DATE | 1-DATE | 01-31 | DATE |
|
||||
; +---+-----+-----+----+----+-------------------+------------------+----------------+
|
||||
; | 5 | 0 | 0 |10-MONTH | 1-MONTH | 01-12 | MONTH |
|
||||
; +---+-----+-----+----+----+-------------------+------------------+----------------+
|
||||
; | 6 | 10-YEAR | 1-YEAR | 00-99 | YEAR |
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
; --- ALARM 0 ---
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
; | 7 | M | 10-SECOND | 1-SECOND | 00-59 | SECONDS ALARM |
|
||||
; +---+-----+---------------+-------------------+------------------+----------------+
|
||||
; | 8 | M | 10-MINUTE | 1-MINUTE | 00-59 | MINUTES ALARM |
|
||||
; +---+-----+-----+---------+-------------------+------------------+----------------+
|
||||
; | 9 | M | 0 | 10-HOUR | 1-HOUR | 00-23 | HOURS ALARM |
|
||||
; +---+-----+-----+----+----+-------------------+------------------+----------------+
|
||||
; | A | M | 0 | 0 | 0 | DAY | 1-7 | DAY ALARM |
|
||||
; +---+-----+-----+----+----+----+--------------+------------------+----------------+
|
||||
; --- ALARM 1 ---
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
; | B | M | 10-SECOND | 1-SECOND | 00-59 | SECONDS ALARM |
|
||||
; +---+-----+---------------+-------------------+------------------+----------------+
|
||||
; | C | M | 10-MINUTE | 1-MINUTE | 00-59 | MINUTES ALARM |
|
||||
; +---+-----+-----+---------+-------------------+------------------+----------------+
|
||||
; | D | M | 0 | 10-HOUR | 1-HOUR | 00-23 | HOURS ALARM |
|
||||
; +---+-----+-----+----+----+-------------------+------------------+----------------+
|
||||
; | E | M | 0 | 0 | 0 | DAY | 1-7 | DAY ALARM |
|
||||
; +---+-----+-----+----+----+----+--------------+------------------+----------------+
|
||||
;
|
||||
; +---+-----+-----+---------+-------------------+------------------+----------------+
|
||||
; | F |/EOSC| WP | 0 | 0 | 0 |INTC|AIE1|AIE0| | CONTROL REG |
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
; |10 | 0 | 0 | 0 | 0 | 0 | 0 |IRQ1|IRQ0| | STATUS REG |
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
; |11 | TRICKLE CHG ENABLE | DIODE |RESISTOR | | TRICKLE CHG REG|
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
; |12-1F | RESERVED | | |
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
; |20-7F | USER NVRAM | 00-FF | |
|
||||
; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+
|
||||
;
|
||||
; 0 = SHOULD BE SET TO 0 FOR VALID TIME/CALENDAR RANGE.
|
||||
; CLOCK CALENDAR DATA IS BCD. AUTOMATIC LEAP YEAR ADJUSTMENT.
|
||||
; DAY-OF-WEEK CODED AS SUNDAY = 1 THROUGH SATURDAY = 7.
|
||||
;
|
||||
; CONSTANTS
|
||||
;
|
||||
DS5RTC_BASE .EQU $68
|
||||
DS5RTC_DATA .EQU DS5RTC_BASE + 0
|
||||
DS5RTC_SELECT .EQU DS5RTC_BASE + 2 ; WRITE
|
||||
DS5RTC_STATUS .EQU DS5RTC_BASE + 2 ; READ
|
||||
DS5RTC_RUN .EQU DS5RTC_BASE + 3 ; START READ/WRITE USING IN/OUT OPCODE
|
||||
;
|
||||
; IO PORTS
|
||||
;
|
||||
DS5NVM_BASE .EQU DS5RTC_BASE + $20
|
||||
|
||||
DS5RTC_REG_SEC .EQU $00
|
||||
DS5RTC_REG_MIN .EQU $01
|
||||
DS5RTC_REG_HOUR .EQU $02
|
||||
DS5RTC_REG_WEEKDAY .EQU $03
|
||||
DS5RTC_REG_DATE .EQU $04
|
||||
DS5RTC_REG_MONTH .EQU $05
|
||||
DS5RTC_REG_YEAR .EQU $06
|
||||
DS5RTC_REG_ALM0_SEC .EQU $07
|
||||
DS5RTC_REG_ALM0_MIN .EQU $08
|
||||
DS5RTC_REG_ALM0_HOUR .EQU $09
|
||||
DS5RTC_REG_ALM0_DAY .EQU $0A
|
||||
DS5RTC_REG_ALM1_SEC .EQU $0B
|
||||
DS5RTC_REG_ALM1_MIN .EQU $0C
|
||||
DS5RTC_REG_ALM1_HOUR .EQU $0D
|
||||
DS5RTC_REG_ALM1_DAY .EQU $0E
|
||||
DS5RTC_REG_CONTROL .EQU $0F
|
||||
DS5RTC_REG_STATUS .EQU $10
|
||||
DS5RTC_REG_TCHG .EQU $11
|
||||
DS5RTC_REG_NVM_BASE .EQU $20
|
||||
;
|
||||
; VALUES FOR DIFFERENT BATTERY OR SUPERCAPACITOR CHARGE RATES
|
||||
;
|
||||
DS5RTC_TC1D2K .EQU %10100101 ; 1 DIODE 2K RESISTOR (DEFAULT)
|
||||
DS5RTC_TC1D4K .EQU %10100110 ; 1 DIODE 4K RESISTOR
|
||||
DS5RTC_TC1D8K .EQU %10100111 ; 1 DOIDE 8K RESISTOR
|
||||
DS5RTC_TC2D2K .EQU %10101001 ; 2 DIODES 2K RESISTOR
|
||||
DS5RTC_TC2D4K .EQU %10101010 ; 2 DIODES 4K RESISTOR
|
||||
DS5RTC_TC2D8K .EQU %10101011 ; 2 DIODES 8K RESISTOR
|
||||
;
|
||||
;
|
||||
;
|
||||
DS5RTC_BUFSIZE .EQU 6 ; 6 BYTE BUFFER (YYMMDDHHMMSS)
|
||||
;
|
||||
DEVECHO "DS5RTC: RTCIO="
|
||||
DEVECHO DS5RTC_BASE
|
||||
DEVECHO ", IO="
|
||||
DEVECHO DS5RTC_BASE
|
||||
DEVECHO "\n"
|
||||
;
|
||||
; RTC DEVICE INITIALIZATION ENTRY
|
||||
;
|
||||
DS5RTC_INIT:
|
||||
LD A,(RTC_DISPACT) ; RTC DISPATCHER ALREADY SET?
|
||||
OR A ; SET FLAGS
|
||||
RET NZ ; IF ALREADY ACTIVE, ABORT
|
||||
;
|
||||
CALL NEWLINE ; FORMATTING
|
||||
PRTS("DS5RTC: IO=0x$")
|
||||
LD A, DS5RTC_BASE
|
||||
CALL PRTHEXBYTE
|
||||
;
|
||||
CALL DS5RTC_DETECT ; HARDWARE DETECTION
|
||||
JR Z,DS5RTC_INIT1 ; IF ZERO, ALL GOOD
|
||||
PRTS(" NOT PRESENT$") ; NOT ZERO, H/W NOT PRESENT
|
||||
OR $FF ; SIGNAL FAILURE
|
||||
RET ; BAIL OUT
|
||||
;
|
||||
DS5RTC_INIT1:
|
||||
; DISPLAY CURRENT TIME
|
||||
CALL PC_SPACE ; FORMATTING
|
||||
LD HL,DS5RTC_BUF ; USE INTERNAL BUFFER
|
||||
CALL DS5RTC_RDCLK ; GET RAW RTC DATE/TIME
|
||||
LD HL,DS5RTC_TIMBUF ; POINT TO HBIOS TIME BUF
|
||||
CALL DS5RTC_CLK2TIM ; CONVERT TO HBIOS FMT
|
||||
LD HL,DS5RTC_TIMBUF ; POINT TO HBIOS TIME BUF
|
||||
CALL PRTDT ; PRINT FORMATTED DATE/TIME
|
||||
;
|
||||
; ADD OURSELVES TO RTC DISPATCHER
|
||||
LD BC,DS5RTC_DISPATCH
|
||||
CALL RTC_SETDISP
|
||||
;
|
||||
XOR A
|
||||
RET
|
||||
;
|
||||
; RTC DEVICE FUNCTION DISPATCH ENTRY
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
|
||||
; B: FUNCTION (IN)
|
||||
;
|
||||
DS5RTC_DISPATCH:
|
||||
LD A, B ; Get requested function
|
||||
AND $0F ; Isolate Sub-Function
|
||||
JP Z, DS5RTC_GETTIM ; Get Time
|
||||
DEC A
|
||||
JP Z, DS5RTC_SETTIM ; Set Time
|
||||
DEC A
|
||||
JP Z, DS5RTC_GETBYT ; Get NVRAM Byte Value
|
||||
DEC A
|
||||
JP Z, DS5RTC_SETBYT ; Set NVRAM Byte Value
|
||||
DEC A
|
||||
JP Z, DS5RTC_GETBLK ; Get NVRAM Data Block Value
|
||||
DEC A
|
||||
JP Z, DS5RTC_SETBLK ; Set NVRAM Data Block Value
|
||||
DEC A
|
||||
JP Z, DS5RTC_GETALM ; Get Alarm
|
||||
DEC A
|
||||
JP Z, DS5RTC_SETALM ; Set Alarm
|
||||
;
|
||||
; RTC GET TIME
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
|
||||
; HL: DATE/TIME BUFFER (OUT)
|
||||
; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
|
||||
; 24 HOUR TIME FORMAT IS ASSUMED
|
||||
;
|
||||
DS5RTC_GETTIM:
|
||||
PUSH HL ; SAVE ADR OF OUTPUT BUF
|
||||
;
|
||||
; READ THE CLOCK
|
||||
LD HL,DS5RTC_BUF ; POINT TO CLOCK BUFFER
|
||||
CALL DS5RTC_RDCLK ; READ THE CLOCK
|
||||
LD HL,DS5RTC_TIMBUF ; POINT TO TIME BUFFER
|
||||
CALL DS5RTC_CLK2TIM ; CONVERT CLOCK TO TIME
|
||||
;
|
||||
; NOW COPY TO REAL DESTINATION (INTERBANK SAFE)
|
||||
LD A,BID_BIOS ; COPY FROM BIOS BANK
|
||||
LD (HB_SRCBNK),A ; SET IT
|
||||
LD A,(HB_INVBNK) ; COPY TO CURRENT USER BANK
|
||||
LD (HB_DSTBNK),A ; SET IT
|
||||
LD HL,DS5RTC_TIMBUF ; SOURCE ADR
|
||||
POP DE ; DEST ADR
|
||||
LD BC,6 ; LENGTH IS 6 BYTES
|
||||
#IF (INTMODE == 1)
|
||||
DI
|
||||
#ENDIF
|
||||
CALL HB_BNKCPY ; COPY THE CLOCK DATA
|
||||
#IF (INTMODE == 1)
|
||||
EI
|
||||
#ENDIF
|
||||
;
|
||||
; CLEAN UP AND RETURN
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; AND RETURN
|
||||
;
|
||||
; RTC SET TIME
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
|
||||
; HL: DATE/TIME BUFFER (IN)
|
||||
; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
|
||||
; 24 HOUR TIME FORMAT IS ASSUMED
|
||||
;
|
||||
DS5RTC_SETTIM:
|
||||
; COPY INCOMING TIME DATA TO OUR TIME BUFFER
|
||||
LD A,(HB_INVBNK) ; COPY FROM CURRENT USER BANK
|
||||
LD (HB_SRCBNK),A ; SET IT
|
||||
LD A,BID_BIOS ; COPY TO BIOS BANK
|
||||
LD (HB_DSTBNK),A ; SET IT
|
||||
LD DE,DS5RTC_TIMBUF ; DEST ADR
|
||||
LD BC,6 ; LENGTH IS 6 BYTES
|
||||
#IF (INTMODE == 1)
|
||||
DI
|
||||
#ENDIF
|
||||
CALL HB_BNKCPY ; COPY THE CLOCK DATA
|
||||
#IF (INTMODE == 1)
|
||||
EI
|
||||
#ENDIF
|
||||
;
|
||||
; WRITE TO CLOCK
|
||||
LD HL,DS5RTC_TIMBUF ; POINT TO TIME BUFFER
|
||||
CALL DS5RTC_TIM2CLK ; CONVERT TO CLOCK FORMAT
|
||||
LD HL,DS5RTC_BUF ; POINT TO CLOCK BUFFER
|
||||
CALL DS5RTC_WRCLK ; WRITE TO THE CLOCK
|
||||
;
|
||||
; CLEAN UP AND RETURN
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; AND RETURN
|
||||
;
|
||||
; RTC GET NVRAM BYTE
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
|
||||
; C: INDEX (IN)
|
||||
; E: VALUE (OUT)
|
||||
;
|
||||
DS5RTC_GETBYT:
|
||||
LD A,C ; INDEX TO A
|
||||
ADD A,$20 ; NVRAM STARTS AT REG $20
|
||||
LD C,A ; BACK TO REG C
|
||||
CALL DS5RTC_GET ; DO IT
|
||||
LD E,A ; MOVE RESULT TO E
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; DONE
|
||||
;
|
||||
; RTC SET NVRAM BYTE
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
|
||||
; C: INDEX (IN)
|
||||
; E: VALUE (IN)
|
||||
;
|
||||
DS5RTC_SETBYT:
|
||||
LD A,C ; INDEX TO A
|
||||
ADD A,$20 ; NVRAM STARTS AT REG $20
|
||||
LD C,A ; BACK TO REG C
|
||||
CALL DS5RTC_WPOFF ; DISABLE WRITE PROTECT
|
||||
CALL DS5RTC_PUT ; DO IT
|
||||
CALL DS5RTC_WPOFF ; ENABLE WRITE PROTECT
|
||||
LD E,A ; MOVE RESULT TO E
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; DONE
|
||||
;
|
||||
; RTC GET BLOCK
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
|
||||
; HL: BUFFER ADDRESS (IN)
|
||||
;
|
||||
DS5RTC_GETBLK:
|
||||
SYSCHKERR(ERR_NOTIMPL)
|
||||
RET
|
||||
;
|
||||
; RTC GET BLOCK
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
|
||||
; HL: BUFFER ADDRESS (IN)
|
||||
;
|
||||
DS5RTC_SETBLK:
|
||||
SYSCHKERR(ERR_NOTIMPL)
|
||||
RET
|
||||
;
|
||||
; RTC GET ALARM
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERROR
|
||||
; HL: DATE/TIME BUFFER ADDRESS (IN)
|
||||
; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
|
||||
; 24 HOUR TIME FORMAT IS ASSUMED
|
||||
;
|
||||
DS5RTC_GETALM:
|
||||
SYSCHKERR(ERR_NOTIMPL)
|
||||
RET
|
||||
;
|
||||
; RTC SET ALARM
|
||||
; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERROR
|
||||
; HL: DATE/TIME BUFFER ADDRESS (IN)
|
||||
; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
|
||||
; 24 HOUR TIME FORMAT IS ASSUMED
|
||||
;
|
||||
DS5RTC_SETALM:
|
||||
SYSCHKERR(ERR_NOTIMPL)
|
||||
RET
|
||||
;
|
||||
;==================================================================================================
|
||||
; INTERNAL PROCEDURES
|
||||
;==================================================================================================
|
||||
;
|
||||
; TURN ON WRITE PROTECT
|
||||
;
|
||||
DS5RTC_WPON:
|
||||
PUSH AF
|
||||
PUSH BC
|
||||
LD A,%01000000 ; CONTROL REGISTER W/P ON VALUE
|
||||
LD C,DS5RTC_REG_CONTROL ; CONTROL REGISTER ADR
|
||||
CALL DS5RTC_PUT ; SET CONTROL REGISTER
|
||||
POP BC
|
||||
POP AF
|
||||
RET
|
||||
;
|
||||
; TURN OFF WRITE PROTECT
|
||||
;
|
||||
DS5RTC_WPOFF:
|
||||
PUSH AF
|
||||
PUSH BC
|
||||
XOR A ; CONTROL REGISTER W/P OFF VALUE
|
||||
LD C,DS5RTC_REG_CONTROL ; CONTROL REGISTER ADR
|
||||
CALL DS5RTC_PUT ; SET CONTROL REGISTER
|
||||
POP BC
|
||||
POP AF
|
||||
RET
|
||||
;
|
||||
; DETECT RTC HARDWARE PRESENCE
|
||||
;
|
||||
DS5RTC_DETECT:
|
||||
CALL DS5RTC_WPOFF ; DISABLE WRITE PROTECT
|
||||
;
|
||||
; TEST AN NVRAM BYTE (NON-DESTRUCTIVE)
|
||||
LD C,$7F ; LAST NVRAM BYTE
|
||||
CALL DS5RTC_GET ; GET CURRENT VALUE
|
||||
LD B,A ; SAVE IN B
|
||||
XOR $FF ; FLIP ALL BITS
|
||||
CALL DS5RTC_PUT ; SAVE TO RTC NVRAM
|
||||
CALL DS5RTC_GET ; GET UPDATED VALUE
|
||||
XOR $FF ; FLIP ALL BITS
|
||||
CP B ; COMPARE W/ ORIGINAL READ
|
||||
PUSH AF ; SAVE FLAGS
|
||||
CALL DS5RTC_PUT ; RESAVE ORIGINAL VALUE
|
||||
;
|
||||
CALL DS5RTC_WPON ; RESTORE WRITE PROTECT
|
||||
POP AF ; RESTORE FLAGS
|
||||
RET ; ZF INDICATES PRESENCE
|
||||
;
|
||||
; READ RTC DATE/TIME INTO INTERNAL BUFFER
|
||||
;
|
||||
DS5RTC_RDCLK:
|
||||
LD B,7 ; 7 BYTE DATE/TIME BUFFER
|
||||
LD C,DS5RTC_REG_SEC ; START W/ SECONDS REGISTER
|
||||
LD HL,DS5RTC_BUF ; USE INTERNAL BUFFER
|
||||
CALL DS5RTC_GETBUF ; FILL THE BUFFER
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; RETURN
|
||||
;
|
||||
; WRITE RTC DATE/TIME FROM INTERNAL BUFFER
|
||||
;
|
||||
DS5RTC_WRCLK:
|
||||
CALL DS5RTC_WPOFF ; DISABLE WRITE PROTECT
|
||||
LD B,7 ; 7 BYTE DATE/TIME BUFFER
|
||||
LD C,DS5RTC_REG_SEC ; START W/ SECONDS REGISTER
|
||||
LD HL,DS5RTC_BUF ; USE INTERNAL BUFFER
|
||||
CALL DS5RTC_PUTBUF ; FILL THE BUFFER
|
||||
CALL DS5RTC_WPON ; RESTORE WRITE PROTECT
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; RETURN
|
||||
;
|
||||
; CONVERT DATA IN CLOCK BUFFER TO TIME BUFFER AT HL
|
||||
;
|
||||
DS5RTC_CLK2TIM:
|
||||
LD A,(DS5RTC_YR)
|
||||
LD (HL),A
|
||||
INC HL
|
||||
LD A,(DS5RTC_MON)
|
||||
LD (HL),A
|
||||
INC HL
|
||||
LD A,(DS5RTC_DT)
|
||||
LD (HL),A
|
||||
INC HL
|
||||
LD A,(DS5RTC_HR)
|
||||
LD (HL),A
|
||||
INC HL
|
||||
LD A,(DS5RTC_MIN)
|
||||
LD (HL),A
|
||||
INC HL
|
||||
LD A,(DS5RTC_SEC)
|
||||
LD (HL),A
|
||||
RET
|
||||
;
|
||||
; CONVERT DATA IN TIME BUFFER AT HL TO CLOCK BUFFER
|
||||
;
|
||||
DS5RTC_TIM2CLK:
|
||||
PUSH HL
|
||||
LD A,(HL)
|
||||
LD (DS5RTC_YR),A
|
||||
INC HL
|
||||
LD A,(HL)
|
||||
LD (DS5RTC_MON),A
|
||||
INC HL
|
||||
LD A,(HL)
|
||||
LD (DS5RTC_DT),A
|
||||
INC HL
|
||||
LD A,(HL)
|
||||
LD (DS5RTC_HR),A
|
||||
INC HL
|
||||
LD A,(HL)
|
||||
LD (DS5RTC_MIN),A
|
||||
INC HL
|
||||
LD A,(HL)
|
||||
LD (DS5RTC_SEC),A
|
||||
POP HL
|
||||
CALL TIMDOW
|
||||
INC A ; CONVERT FROM 0-6 TO 1-7
|
||||
LD (DS5RTC_DAY),A
|
||||
RET
|
||||
;
|
||||
; READ A BUFFER OF BYTES FROM THE RTC
|
||||
; START RTC ADR IN C, COUNT IN B, BUF PTR IN HL
|
||||
;
|
||||
DS5RTC_GETBUF:
|
||||
LD A,1
|
||||
OUT (DS5RTC_SELECT),A ; SELECT RTC
|
||||
LD A,C ; ADDRESS TO A
|
||||
OUT (DS5RTC_DATA),A ; SEND TO INTERFACE
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION
|
||||
DS5RTC_GETBUF1:
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO READ DATA
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR DATA
|
||||
IN A,(DS5RTC_DATA) ; GET VALUE
|
||||
LD (HL),A ; SAVE BYTE IN BUFFER
|
||||
INC HL ; BUMP BUF PTR
|
||||
DJNZ DS5RTC_GETBUF1 ; LOOP FOR REQUESTED BYTES
|
||||
LD A,0
|
||||
OUT (DS5RTC_SELECT),A ; DESELECT DEVICE
|
||||
RET
|
||||
;
|
||||
; WRITE A BUFFER OF BYTES TO THE RTC
|
||||
; START RTC ADR IN C, COUNT IN B, BUF PTR IN HL
|
||||
;
|
||||
DS5RTC_PUTBUF:
|
||||
LD A,1
|
||||
OUT (DS5RTC_SELECT),A ; SELECT RTC
|
||||
LD A,C ; ADDRESS TO A
|
||||
SET 7,A ; SET WRITE BIT
|
||||
OUT (DS5RTC_DATA),A ; SEND TO INTERFACE
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION
|
||||
DS5RTC_PUTBUF1:
|
||||
LD A,(HL) ; NEXT BYTE TO WRITE
|
||||
INC HL ; BUMP BUF PTR
|
||||
OUT (DS5RTC_DATA),A ; SEND TO INTERFACE
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE BYTE
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION
|
||||
DJNZ DS5RTC_PUTBUF1 ; LOOP FOR REQUESTED BYTES
|
||||
LD A,0
|
||||
OUT (DS5RTC_SELECT),A ; DESELECT DEVICE
|
||||
RET
|
||||
;
|
||||
; GET A BYTE FROM THE RTC
|
||||
; ADDRESS IN C, RETURN VALLUE IN A
|
||||
;
|
||||
DS5RTC_GET:
|
||||
LD A,1
|
||||
OUT (DS5RTC_SELECT),A ; SELECT RTC
|
||||
LD A,C ; ADDRESS TO A
|
||||
OUT (DS5RTC_DATA),A ; SEND TO INTERFACE
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO READ DATA
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR DATA
|
||||
IN A,(DS5RTC_DATA) ; GET VALUE
|
||||
PUSH AF ; SAVE VALUE
|
||||
LD A,0
|
||||
OUT (DS5RTC_SELECT),A ; DESELECT DEVICE
|
||||
POP AF ; RESTORE VALUE
|
||||
RET
|
||||
;
|
||||
; PUT A BYTE TO THE RTC
|
||||
; ADDRESS IN C, VALUE IN A
|
||||
;
|
||||
DS5RTC_PUT:
|
||||
PUSH AF ; SAVE VALUE TO PUT
|
||||
LD A,1
|
||||
OUT (DS5RTC_SELECT),A ; SELECT RTC
|
||||
LD A,C ; ADDRESS TO A
|
||||
SET 7,A ; SET WRITE BIT
|
||||
OUT (DS5RTC_DATA),A ; SEND TO INTERFACE
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION
|
||||
POP AF ; RECOVER VALUE TO PUT
|
||||
OUT (DS5RTC_DATA),A ; VALUE TO OUTPUT
|
||||
OUT (DS5RTC_RUN),A ; SPI TRANSACTOIN TO WRITE VALUE
|
||||
CALL DS5RTC_WAITBSY ; WAIT FOR WRITE TO COMPLETE
|
||||
LD A,0
|
||||
OUT (DS5RTC_SELECT),A ; DESELECT DEVICE
|
||||
RET
|
||||
;
|
||||
; WAIT UNTIL SPI INTERFACE IS NO LONGER BUSY
|
||||
;
|
||||
DS5RTC_WAITBSY:
|
||||
PUSH AF ; PRESERVE AF
|
||||
PUSH BC ; PRESERVE BC
|
||||
;
|
||||
; AFTER INITIATING A SPI TRANSACTION, IT MAY TAKE A WHILE
|
||||
; FOR THE BUSY STATUS TO BE REFLECTED. THE DELAYS BELOW
|
||||
; ENSURE ENOUGH TIME HAS ELAPSED.
|
||||
CALL DELAY
|
||||
CALL DELAY
|
||||
CALL DELAY
|
||||
CALL DELAY
|
||||
CALL DELAY
|
||||
CALL DELAY
|
||||
CALL DELAY
|
||||
CALL DELAY
|
||||
;
|
||||
; SINCE THIS ROUTINE MAY BE USED TO DETECT AN RTC THAT DOES
|
||||
; NOT EXIST, WE PROTECT THE WAIT WITH A TIMEOUT LOOP TO
|
||||
; PREVENT A SYSTEM STALL.
|
||||
LD B,0
|
||||
DS5RTC_WAITBSY1:
|
||||
IN A,(DS5RTC_STATUS) ; GET STATUS BYTE
|
||||
OR A ; SET FLAGS
|
||||
JR Z,DS5RTC_WAITBSY2 ; IF ZERO, WE ARE DONE
|
||||
DJNZ DS5RTC_WAITBSY1 ; TRY TILL COUNTER EXHAUSTED
|
||||
DS5RTC_WAITBSY2:
|
||||
POP BC ; RECOVER BC
|
||||
POP AF ; RECOVER AF
|
||||
RET
|
||||
;
|
||||
; DS5RTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS1305
|
||||
; FIELDS BELOW MATCH ORDER OF DS1305 FIELDS (BCD)
|
||||
;
|
||||
DS5RTC_BUF:
|
||||
DS5RTC_SEC .DB 0 ; SECOND
|
||||
DS5RTC_MIN .DB 0 ; MINUTE
|
||||
DS5RTC_HR .DB 0 ; HOUR
|
||||
DS5RTC_DAY .DB 0 ; DAY OF WEEK
|
||||
DS5RTC_DT .DB 0 ; DATE
|
||||
DS5RTC_MON .DB 0 ; MONTH
|
||||
DS5RTC_YR .DB 0 ; YEAR
|
||||
;
|
||||
; DS5RTC_TIMBUF IS TEMP BUF USED TO STORE TIME TEMPORARILY TO DISPLAY
|
||||
; IT.
|
||||
;
|
||||
DS5RTC_TIMBUF .FILL 6,0 ; 6 BYTES FOR GETTIM
|
||||
;
|
||||
; DS5RTC_TIMDEF IS DEFAULT TIME VALUE TO INITIALIZE CLOCK IF IT IS
|
||||
; NOT RUNNING.
|
||||
;
|
||||
DS5RTC_TIMDEF: ; DEFAULT TIME VALUE TO INIT CLOCK
|
||||
.DB $00,$01,$01 ; 2000-01-01
|
||||
.DB $00,$00,$00 ; 00:00:00
|
||||
@@ -165,14 +165,6 @@ DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW)
|
||||
; RTC DEVICE PRE-INITIALIZATION ENTRY
|
||||
;
|
||||
DSRTC_PREINIT:
|
||||
;
|
||||
;; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER
|
||||
;; TO THEIR QUIESENT STATE
|
||||
;LD A,(DSRTC_OPRVAL) ; GET CURRENT SHADOW REG VAL
|
||||
;AND ~DSRTC_MASK ; CLEAR OUR BITS
|
||||
;OR DSRTC_IDLE ; SET OUR IDLE BITS
|
||||
;LD (DSRTC_OPRVAL),A ; SAVE IT
|
||||
;
|
||||
XOR A ; ZERO
|
||||
LD (DSRTC_STAT),A ; CLEAR STATUS
|
||||
CALL DSRTC_DETECT ; HARDWARE DETECTION
|
||||
|
||||
@@ -173,7 +173,7 @@ SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT
|
||||
; SET DIAGNOSTIC LEDS
|
||||
;
|
||||
; SCxxx: LED Port=0x0E, bit 2, inverted, dedicated port (LEDMODE_SC)
|
||||
; SC7xx: LED Port=0x0E, bit 0, inverted, dedicated port (LEDMODE_STD)
|
||||
; SC7xx/SC5xx: LED Port=0x0E, bit 0, inverted, dedicated port (LEDMODE_STD)
|
||||
; TinyZ80: LED Port=0x6E, bit 0, inverted, dedicated port (LEDMODE_STD)
|
||||
; Z80-512K: LED Port=0x6E, bit 0, inverted, dedicated port (LEDMODE_STD)
|
||||
; MBC: LED Port=0x70, bits 1-0, normal, shared w/ RTC port (LEDMODE_RTC)
|
||||
@@ -3705,6 +3705,9 @@ HB_INITTBL:
|
||||
#IF (DS7RTCENABLE)
|
||||
.DW DS7RTC_INIT
|
||||
#ENDIF
|
||||
#IF (DS5RTCENABLE)
|
||||
.DW DS5RTC_INIT
|
||||
#ENDIF
|
||||
#IF (RP5RTCENABLE)
|
||||
.DW RP5RTC_INIT
|
||||
#ENDIF
|
||||
@@ -7953,12 +7956,12 @@ SIZ_PCF .EQU $ - ORG_PCF
|
||||
MEMECHO " bytes.\n"
|
||||
#ENDIF
|
||||
;
|
||||
#IF (DS7RTCENABLE)
|
||||
ORG_DS7RTC .EQU $
|
||||
#INCLUDE "ds7rtc.asm"
|
||||
SIZ_DS7RTC .EQU $ - ORG_DS7RTC
|
||||
MEMECHO "DS7RTC occupies "
|
||||
MEMECHO SIZ_DS7RTC
|
||||
#IF (DS5RTCENABLE)
|
||||
ORG_DS5RTC .EQU $
|
||||
#INCLUDE "ds5rtc.asm"
|
||||
SIZ_DS5RTC .EQU $ - ORG_DS5RTC
|
||||
MEMECHO "DS5RTC occupies "
|
||||
MEMECHO SIZ_DS5RTC
|
||||
MEMECHO " bytes.\n"
|
||||
#ENDIF
|
||||
;
|
||||
|
||||
@@ -359,6 +359,7 @@ RTCDEV_SIMH .EQU $02 ; SIMH
|
||||
RTCDEV_INT .EQU $03 ; PERIODIC INT TIMER
|
||||
RTCDEV_DS7 .EQU $04 ; DS1307 (I2C)
|
||||
RTCDEV_RP5 .EQU $05 ; RP5C01
|
||||
RTCDEV_DS5 .EQU $06 ; DS1305 (SPI)
|
||||
;
|
||||
; DSKY DEVICE IDS
|
||||
;
|
||||
|
||||
@@ -2066,7 +2066,6 @@ SD_DESELECT:
|
||||
#ENDIF
|
||||
#ENDIF
|
||||
; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS
|
||||
;;;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R))
|
||||
#IF (SD_INVCS)
|
||||
#IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80)) & (SD_DEVCNT > 1))
|
||||
XOR SD_CS0 | SD_CS1
|
||||
@@ -2104,12 +2103,10 @@ SD_WAITRX:
|
||||
;
|
||||
SD_WAITBSY:
|
||||
PUSH AF
|
||||
CALL PC_PERIOD ; *DEBUG*
|
||||
;;;CALL DLY32
|
||||
SD_WAITBSY1:
|
||||
IN A,(SD_SELSTAT)
|
||||
BIT 7,A
|
||||
JR NZ,SD_WAITBSY
|
||||
;;;CALL DLY32
|
||||
JR NZ,SD_WAITBSY1
|
||||
POP AF
|
||||
RET
|
||||
#ENDIF
|
||||
@@ -2194,11 +2191,9 @@ SD_PUT1:
|
||||
CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY
|
||||
OUT (SD_DATA),A ; POST THE VALUE
|
||||
OUT (SD_ACTION),A ; INITIATE THE WRITE
|
||||
;;;CALL SD_WAITBSY
|
||||
|
||||
CALL PC_SPACE ; *DEBUG*
|
||||
CALL PC_GT ; *DEBUG*
|
||||
CALL PRTHEXBYTE ; *DEBUG*
|
||||
;;;CALL PC_SPACE ; *DEBUG*
|
||||
;;;CALL PC_GT ; *DEBUG*
|
||||
;;;CALL PRTHEXBYTE ; *DEBUG*
|
||||
#ENDIF
|
||||
RET ; DONE
|
||||
;
|
||||
@@ -2308,10 +2303,9 @@ SD_GET1:
|
||||
IN A,(SD_ACTION) ; INITIATE READ
|
||||
CALL SD_WAITBSY ; WAIT FOR DONE
|
||||
IN A,(SD_DATA) ; GET THE VALUE
|
||||
;;;CALL SD_WAITBSY
|
||||
CALL PC_SPACE ; *DEBUG*
|
||||
CALL PC_LT ; *DEBUG*
|
||||
CALL PRTHEXBYTE ; *DEBUG*
|
||||
;;;CALL PC_SPACE ; *DEBUG*
|
||||
;;;CALL PC_LT ; *DEBUG*
|
||||
;;;CALL PRTHEXBYTE ; *DEBUG*
|
||||
#ENDIF
|
||||
RET
|
||||
;
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
#DEFINE RMN 5
|
||||
#DEFINE RUP 0
|
||||
#DEFINE RTP 0
|
||||
#DEFINE BIOSVER "3.5.0-dev.52"
|
||||
#DEFINE BIOSVER "3.5.0-dev.54"
|
||||
#define rmj RMJ
|
||||
#define rmn RMN
|
||||
#define rup RUP
|
||||
|
||||
@@ -3,5 +3,5 @@ rmn equ 5
|
||||
rup equ 0
|
||||
rtp equ 0
|
||||
biosver macro
|
||||
db "3.5.0-dev.52"
|
||||
db "3.5.0-dev.54"
|
||||
endm
|
||||
|
||||
Reference in New Issue
Block a user