MirrorRepos/RomWBW
1
0
Fork 1
mirror of https://github.com/wwarthen/RomWBW.git synced 2026-02-06 22:43:15 -06:00
Code Issues Projects Releases Wiki Activity

SC126 Support and SIO Update

Browse Source
This commit is contained in:
Wayne Warthen
2019-06-21 14:17:46 -07:00
parent b0aab772ef
commit 293ca770de
9 changed files with 111 additions and 36 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
Source/Apps/RTC.asm
View File

@@ -19,6 +19,8 @@
;
;[2018/11/8] v1.2 PMS Add boot option. Code optimization.
;
;[2019/06/21] v1.3 Finalized RC2014 Z180 support.
;
;
; Constants
;
@@ -30,7 +32,9 @@ mask_rst .EQU %00010000 ; De-activate RTC reset line
PORT_SBC .EQU $70 ; RTC port for SBC/ZETA
PORT_N8 .EQU $88 ; RTC port for N8
PORT_MK4 .EQU $8A ; RTC port for MK4
PORT_RC .EQU $C0 ; RTC port for RC2014
PORT_RCZ80 .EQU $C0 ; RTC port for RC2014
PORT_RCZ180 .EQU $0C ; RTC port for RC2014
PORT_EZZ80 .EQU $C0 ; RTC port for EZZ80 (actually does not have one!!!)
BDOS .EQU 5 ; BDOS invocation vector
@@ -1066,14 +1070,18 @@ HINIT:
LD DE,PLT_MK4
CP $05 ; Mark IV
JR Z,RTC_INIT2
LD C,PORT_RC
LD DE,PLT_RC
CP $07 ; RC2014
LD C,PORT_RCZ80
LD DE,PLT_RCZ80
CP $07 ; RC2014 w/ Z80
JR Z,RTC_INIT2
LD C,PORT_RCZ180
LD DE,PLT_RCZ180
CP $08 ; RC2014 w/ Z180
JR Z,RTC_INIT2
CP $09 ; Easy Z80
JR Z,RTC_INIT2
;LD C,PORT_EZZ80
;LD DE,PLT_EZZ80
;CP $09 ; Easy Z80
;JR Z,RTC_INIT2
;
; Unknown platform
LD DE,PLTERR ; BIOS error message
@@ -1288,8 +1296,8 @@ RTC_TOP_LOOP_DELAY:
JP RTC_TOP_LOOP_1
RTC_TOP_LOOP_BOOT:
LD A,BID_BOOT ; BOOT BANK
LD HL,0 ; ADDRESS ZERO
LD A,BID_BOOT ; BOOT BANK
LD HL,0 ; ADDRESS ZERO
CALL HB_BNKCALL ; DOES NOT RETURN
RTC_TOP_LOOP_CHARGE:
@@ -1537,7 +1545,7 @@ TESTING_BIT_DELAY_OVER:
RTC_HELP_MSG:
.DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "RTC: Version 1.2"
.TEXT "RTC: Version 1.3"
.DB 0Ah, 0Dh ; line feed and carriage return
.TEXT "Commands: E)xit T)ime st(A)rt S)et R)aw L)oop C)harge N)ocharge D)elay I)nit G)et P)ut B)oot H)elp"
.DB 0Ah, 0Dh ; line feed and carriage return
@@ -1650,15 +1658,17 @@ RTC_GET_BUFFER:
.DB 0Ah, 0Dh ; line feed and carriage return
.DB "$" ; line terminator
BIOERR .TEXT "\r\nUnknown BIOS, aborting...\r\n$"
PLTERR .TEXT "\r\n\r\nUnknown hardware platform, aborting...\r\n$"
UBERR .TEXT "\r\nUNA UBIOS is not currently supported, aborting...\r\n$"
HBTAG .TEXT "RomWBW HBIOS$"
UBTAG .TEXT "UNA UBIOS"
PLT_SBC .TEXT ", SBC/Zeta RTC Latch Port 0x70\r\n$"
PLT_N8 .TEXT ", N8 RTC Latch Port 0x88\r\n$"
PLT_MK4 .TEXT ", Mark 4 RTC Latch Port 0x8A\r\n$"
PLT_RC .TEXT ", RC2014 RTC Module Latch Port 0xC0\r\n$"
BIOERR .TEXT "\r\nUnknown BIOS, aborting...\r\n$"
PLTERR .TEXT "\r\n\r\nUnknown/unsupported hardware platform, aborting...\r\n$"
UBERR .TEXT "\r\nUNA UBIOS is not currently supported, aborting...\r\n$"
HBTAG .TEXT "RomWBW HBIOS$"
UBTAG .TEXT "UNA UBIOS"
PLT_SBC .TEXT ", SBC/Zeta RTC Latch Port 0x70\r\n$"
PLT_N8 .TEXT ", N8 RTC Latch Port 0x88\r\n$"
PLT_MK4 .TEXT ", Mark 4 RTC Latch Port 0x8A\r\n$"
PLT_RCZ80 .TEXT ", RC2014 Z80 RTC Module Latch Port 0xC0\r\n$"
PLT_RCZ180 .TEXT ", RC2014 Z180 RTC Module Latch Port 0x0C\r\n$"
PLT_EZZ80 .TEXT ", Easy Z80 RTC Module Latch Port 0xC0\r\n$"
;
; Generic FOR-NEXT loop algorithm

4
Source/CBIOS/ver.inc
View File

@@ -1,5 +1,5 @@
#DEFINE RMJ 2
#DEFINE RMN 9
#DEFINE RUP 1
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.1"
#DEFINE BIOSVER "2.9.2-pre.0"

32
Source/HBIOS/Config/RCZ180_sc126.asm Normal file
View File

@@ -0,0 +1,32 @@
;
;==================================================================================================
; RC2014 W/ Z180 CPU USING NATIVE Z180 MEMORY MANAGER
;==================================================================================================
;
#include "cfg_rcz180.asm"
;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .SET 1 ; IO WAIT STATES TO INSERT (0-3)
;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG
;
ASCIENABLE .SET TRUE ; TRUE FOR Z180 ASCI SUPPORT
SIOENABLE .SET FALSE ; TRUE TO AUTO-DETECT ZILOG SIO/2
SIOMODE .SET SIOMODE_RC ; TYPE OF SIO/2 TO DETECT: SIOMODE_RC, SIOMODE_SMB
ACIAENABLE .SET FALSE ; TRUE TO AUTO-DETECT MOTOROLA 6850 ACIA
;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY SUPPORT
FDMODE .SET FDMODE_RCWDC ; FDMODE_RCSMC, FDMODE_RCWDC
;
IDEENABLE .SET TRUE ; TRUE FOR IDE DEVICE SUPPORT (CF MODULE)
IDEMODE .SET IDEMODE_RC ; TYPE OF CF MODULE: IDEMODE_RC, IDEMODE_SMB
PPIDEENABLE .SET FALSE ; TRUE FOR PPIDE DEVICE SUPPORT (PPIDE MODULE)
;
DSRTCENABLE .SET TRUE ; DS-1302 CLOCK DRIVER
;
SDENABLE .SET TRUE ; TRUE FOR SD SUPPORT
SDMODE .SET SDMODE_SC126 ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .SET 2 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .SET TRUE ; TABLE-DRIVEN BIT INVERTER

43
Source/HBIOS/sd.asm
View File

@@ -158,6 +158,15 @@ SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
#ENDIF
;
#IF (SDMODE == SDMODE_SC126) ; N8-2312
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTC ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00001101 ; QUIESCENT STATE
SD_CS .EQU %00000100 ; RTC:2 IS SELECT
SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
#ENDIF
;
; SD CARD COMMANDS
;
SD_CMD_GO_IDLE_STATE .EQU $40 + 0 ; $40, CMD0 -> R1
@@ -315,6 +324,22 @@ SD_INIT:
LD A,SD_TRDR
CALL PRTHEXBYTE
#ENDIF
;
#IF (SDMODE == SDMODE_SC126)
PRTS(" MODE=SC126$")
#IF (SDCSIOFAST)
PRTS(" FAST$")
#ENDIF
PRTS(" OPR=0x$")
LD A,SD_OPRREG
CALL PRTHEXBYTE
PRTS(" CNTR=0x$")
LD A,SD_CNTR
CALL PRTHEXBYTE
PRTS(" TRDR=0x$")
LD A,SD_TRDR
CALL PRTHEXBYTE
#ENDIF
;
CALL SD_PROBE ; CHECK FOR HARDWARE
JR Z,SD_INIT00 ; CONTINUE IF PRESENT
@@ -847,7 +872,7 @@ SD_INITCARD5:
CALL SD_EXECCMDND ; EXEC COMMAND W/ NO DATA
RET NZ ; ABORT ON ERROR
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION
; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
@@ -1301,7 +1326,7 @@ SD_SETUP:
OUT (SD_OPRREG),A
#ENDIF
;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
; CSIO SETUP
; LD A,2 ; 18MHz/20 <= 400kHz
LD A,6 ; ???
@@ -1372,7 +1397,7 @@ SD_CHKWP:
;
SD_SELECT:
LD A,(SD_OPRVAL)
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART))
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC126))
AND ~SD_CS ; SET SD_CS (CHIP SELECT)
#ELSE
OR SD_CS ; SET SD_CS (CHIP SELECT)
@@ -1385,7 +1410,7 @@ SD_SELECT:
;
SD_DESELECT:
LD A,(SD_OPRVAL)
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART))
#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC126))
OR SD_CS ; RESET SD_CS (CHIP SELECT)
#ELSE
AND ~SD_CS ; RESET SD_CS (CHIP SELECT)
@@ -1394,7 +1419,7 @@ SD_DESELECT:
OUT (SD_OPRREG),A
RET
;
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
;
; CSIO WAIT FOR TRANSMIT READY (TX REGSITER EMPTY)
;
@@ -1417,7 +1442,7 @@ SD_WAITRX:
; SEND ONE BYTE
;
SD_PUT:
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
CALL MIRROR ; MSB<-->LSB MIRROR BITS, RESULT IN C
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
OUT0 (SD_TRDR),C ; PUT BYTE IN BUFFER
@@ -1449,7 +1474,7 @@ SD_PUT1:
; RECEIVE ONE BYTE
;
SD_GET:
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4))
#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126))
CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING
IN0 A,(Z180_CNTR) ; GET CSIO STATUS
SET 5,A ; START RECEIVER
@@ -1748,7 +1773,7 @@ SD_DSKBUF .DW 0 ; ADR OF ACTIVE DISK BUFFER
; MSB<-->LSB MIRROR BITS IN A, RESULT IN C
;
MIRROR:
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4)) & SDCSIOFAST)
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126)) & SDCSIOFAST)
LD BC,MIRTAB ; 256 BYTE MIRROR TABLE
ADD A,C ; ADD OFFSET
LD C,A
@@ -1769,7 +1794,7 @@ MIRROR1:
;
; LOOKUP TABLE TO MIRROR BITS IN A BYTE
;
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4)) & SDCSIOFAST)
#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC126)) & SDCSIOFAST)
MIRTAB .DB 00H, 80H, 40H, 0C0H, 20H, 0A0H, 60H, 0E0H, 10H, 90H, 50H, 0D0H, 30H, 0B0H, 70H, 0F0H
.DB 08H, 88H, 48H, 0C8H, 28H, 0A8H, 68H, 0E8H, 18H, 98H, 58H, 0D8H, 38H, 0B8H, 78H, 0F8H

8
Source/HBIOS/sio.asm
View File

@@ -562,9 +562,9 @@ BROK:
;
; SET RECEIVE DATA BITS WR3
;
LD A,D
AND $C0
OR $01
LD A,D ; DATA BITS
AND $C0 ; CLEAR OTHER BITS
OR $21 ; CTS/DCD AUTO, RX ENABLE
LD BC,SIO_INITVALS+9
LD (BC),A
@@ -625,7 +625,7 @@ SIO_INITVALS:
.DB $01, $18 ; WR1: INTERRUPT ON ALL RECEIVE CHARACTERS
#ENDIF
.DB $02, IVT_SER0 ; WR2: INTERRUPT VECTOR OFFSET
.DB $03, $C1 ; WR3: 8 BIT RCV, RX ENABLE
.DB $03, $E1 ; WR3: 8 BIT RCV, CTS/DCD AUTO, RX ENABLE
.DB $05, $EA ; WR5: DTR, 8 BITS SEND, TX ENABLE, RTS 1 11 0 1 0 1 0 (1=DTR,11=8bits,0=sendbreak,1=TxEnable,0=sdlc,1=RTS,0=txcrc)
SIO_INITLEN .EQU $ - SIO_INITVALS
;

2
Source/HBIOS/std.asm
View File

@@ -1,4 +1,5 @@
; The purpose of this file is to define generic symbols and to include
; The purpose of this file is to define generic symbols and to include
; the appropriate std-*.inc file to bring in platform specifics.
; There are several classes of systems supported by SBC.
@@ -145,6 +146,7 @@ SDMODE_PPI .EQU 4 ; PPISD MINI BOARD
SDMODE_UART .EQU 5 ; SD INTERFACE VIA UART
SDMODE_DSD .EQU 6 ; DUAL SD
SDMODE_MK4 .EQU 7 ; MARK IV
SDMODE_SC126 .EQU 8 ; SC126
;
; SERIAL DEVICE CONFIGURATION CONSTANTS
;

4
Source/HBIOS/ver.inc
View File

@@ -1,5 +1,5 @@
#DEFINE RMJ 2
#DEFINE RMN 9
#DEFINE RUP 1
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.1"
#DEFINE BIOSVER "2.9.2-pre.0"