From 2d0ebf49f79b6e7f7049cec7b1a2ce0124baf37b Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Wed, 15 Oct 2025 17:38:59 -0700
Subject: [PATCH] S100 Config Tweaking

---
 ReadMe.md                         |   2 +-
 ReadMe.txt                        |   2 +-
 Source/HBIOS/Config/S100_std.asm  |   1 -
 Source/HBIOS/Config/SZ80_fpga.asm |   2 +-
 Source/HBIOS/Config/SZ80_std.asm  |   8 --
 Source/HBIOS/cfg_DUO.asm          |   6 ++
 Source/HBIOS/cfg_DYNO.asm         |   6 ++
 Source/HBIOS/cfg_EPITX.asm        |   6 ++
 Source/HBIOS/cfg_EZZ80.asm        |   6 ++
 Source/HBIOS/cfg_GMZ180.asm       |   6 ++
 Source/HBIOS/cfg_HEATH.asm        |   6 ++
 Source/HBIOS/cfg_MASTER.asm       |   6 ++
 Source/HBIOS/cfg_MBC.asm          |   6 ++
 Source/HBIOS/cfg_MK4.asm          |   6 ++
 Source/HBIOS/cfg_MON.asm          |   6 ++
 Source/HBIOS/cfg_MSX.asm          |   6 ++
 Source/HBIOS/cfg_N8.asm           |   6 ++
 Source/HBIOS/cfg_NABU.asm         |   6 ++
 Source/HBIOS/cfg_RCEZ80.asm       |   6 ++
 Source/HBIOS/cfg_RCZ180.asm       |   6 ++
 Source/HBIOS/cfg_RCZ280.asm       |   6 ++
 Source/HBIOS/cfg_RCZ80.asm        |   6 ++
 Source/HBIOS/cfg_RPH.asm          |   6 ++
 Source/HBIOS/cfg_S100.asm         |   6 ++
 Source/HBIOS/cfg_SBC.asm          |   6 ++
 Source/HBIOS/cfg_SCZ180.asm       |   6 ++
 Source/HBIOS/cfg_SZ80.asm         |   6 ++
 Source/HBIOS/fv.asm               |  18 +++-
 Source/HBIOS/hbios.asm            | 120 ++++++++++++++++-------
 Source/HBIOS/hbios.inc            |   2 +
 Source/HBIOS/invntdev.asm         |   2 +
 Source/HBIOS/pldser.asm           | 154 ++++++++++++++++++++++++++++++
 Source/HBIOS/scon.asm             |  41 ++++++++
 Source/HBIOS/term.asm             |   8 +-
 Source/HBIOS/tser.asm             | 116 ++++++++++++++++++++++
 Source/ver.inc                    |   2 +-
 Source/ver.lib                    |   2 +-
 37 files changed, 559 insertions(+), 53 deletions(-)
 create mode 100644 Source/HBIOS/pldser.asm
 create mode 100644 Source/HBIOS/tser.asm

diff --git a/ReadMe.md b/ReadMe.md
index e3fd9dfb..9abfab7f 100644
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -7,7 +7,7 @@
 **RomWBW Introduction** \
 Version 3.6 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-13 Oct 2025
+15 Oct 2025
 
 # Overview
 
diff --git a/ReadMe.txt b/ReadMe.txt
index 45ee5018..83ede818 100644
--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW Introduction
 Wayne Warthen (wwarthen@gmail.com)
-13 Oct 2025
+15 Oct 2025
 
 
 
diff --git a/Source/HBIOS/Config/S100_std.asm b/Source/HBIOS/Config/S100_std.asm
index 9148156b..33a0a98f 100644
--- a/Source/HBIOS/Config/S100_std.asm
+++ b/Source/HBIOS/Config/S100_std.asm
@@ -57,7 +57,6 @@ Z180_CLKDIV	.SET	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.SET	1		; Z180: MEMORY WAIT STATES (0-3)
 Z180_IOWAIT	.SET	3		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
-CRTACT		.SET	TRUE		; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
 DSRTCENABLE	.SET	FALSE		; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 ;
diff --git a/Source/HBIOS/Config/SZ80_fpga.asm b/Source/HBIOS/Config/SZ80_fpga.asm
index 055d4164..f89c02d8 100644
--- a/Source/HBIOS/Config/SZ80_fpga.asm
+++ b/Source/HBIOS/Config/SZ80_fpga.asm
@@ -58,7 +58,7 @@ FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 ;
 DS5RTCENABLE	.SET	TRUE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
-SSERENABLE	.SET	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
+TSERENABLE	.SET	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 ;
 LPTENABLE	.SET	TRUE		; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM)
 ;
diff --git a/Source/HBIOS/Config/SZ80_std.asm b/Source/HBIOS/Config/SZ80_std.asm
index b58472ce..9f4f40c3 100644
--- a/Source/HBIOS/Config/SZ80_std.asm
+++ b/Source/HBIOS/Config/SZ80_std.asm
@@ -55,14 +55,6 @@ MEMMGR		.SET	MM_SZ80		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ51
 FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.SET	$05		; FP: PORT ADDRESS FOR FP LEDS
 ;
-SSERENABLE	.SET	TRUE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
-SSERSTATUS	.SET	$AA		; SSER: STATUS PORT
-SSERDATA	.SET	$AC		; SSER: DATA PORT
-SSERIRDY	.SET	%10000000	; SSER: INPUT READY BIT MASK
-SSERIINV	.SET	TRUE		; SSER: INPUT READY BIT INVERTED
-SSERORDY	.SET	%01000000	; SSER: OUTPUT READY BIT MASK
-SSEROINV	.SET	TRUE		; SSER: OUTPUT READY BIT INVERTED
-;
 PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
 ;
 ESPSDENABLE	.SET	TRUE		; ESPSD: ENABLE S100 ESP32 SD DISK DRIVER (ESPSD.ASM)
diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm
index 1313acf5..4913352f 100644
--- a/Source/HBIOS/cfg_DUO.asm
+++ b/Source/HBIOS/cfg_DUO.asm
@@ -178,6 +178,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm
index 389e278a..53d39dc3 100644
--- a/Source/HBIOS/cfg_DYNO.asm
+++ b/Source/HBIOS/cfg_DYNO.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm
index a14c6aaa..cfe38175 100644
--- a/Source/HBIOS/cfg_EPITX.asm
+++ b/Source/HBIOS/cfg_EPITX.asm
@@ -173,6 +173,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	2		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm
index 8494a170..a95ea208 100644
--- a/Source/HBIOS/cfg_EZZ80.asm
+++ b/Source/HBIOS/cfg_EZZ80.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm
index 03f29fda..7b336e5f 100644
--- a/Source/HBIOS/cfg_GMZ180.asm
+++ b/Source/HBIOS/cfg_GMZ180.asm
@@ -172,6 +172,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm
index 180ad14e..8dd3817f 100644
--- a/Source/HBIOS/cfg_HEATH.asm
+++ b/Source/HBIOS/cfg_HEATH.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm
index 07f13fb6..b7746c9c 100644
--- a/Source/HBIOS/cfg_MASTER.asm
+++ b/Source/HBIOS/cfg_MASTER.asm
@@ -216,6 +216,12 @@ SSERIINV	.EQU	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.EQU	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.EQU	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.EQU	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.EQU	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.EQU	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.EQU	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.EQU	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.EQU	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.EQU	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm
index a074e93c..c259f791 100644
--- a/Source/HBIOS/cfg_MBC.asm
+++ b/Source/HBIOS/cfg_MBC.asm
@@ -171,6 +171,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm
index 7a3ffbd5..e008dd1e 100644
--- a/Source/HBIOS/cfg_MK4.asm
+++ b/Source/HBIOS/cfg_MK4.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm
index 8f782f48..6056acc7 100644
--- a/Source/HBIOS/cfg_MON.asm
+++ b/Source/HBIOS/cfg_MON.asm
@@ -174,6 +174,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_MSX.asm b/Source/HBIOS/cfg_MSX.asm
index 72c56afc..2daf181c 100644
--- a/Source/HBIOS/cfg_MSX.asm
+++ b/Source/HBIOS/cfg_MSX.asm
@@ -180,6 +180,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm
index 8ee843e7..8398e44e 100644
--- a/Source/HBIOS/cfg_N8.asm
+++ b/Source/HBIOS/cfg_N8.asm
@@ -179,6 +179,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm
index c3725c82..23de765e 100644
--- a/Source/HBIOS/cfg_NABU.asm
+++ b/Source/HBIOS/cfg_NABU.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm
index af598485..5211516d 100644
--- a/Source/HBIOS/cfg_RCEZ80.asm
+++ b/Source/HBIOS/cfg_RCEZ80.asm
@@ -175,6 +175,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm
index 258215ea..ca339bcb 100644
--- a/Source/HBIOS/cfg_RCZ180.asm
+++ b/Source/HBIOS/cfg_RCZ180.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm
index cf527532..b94b9a09 100644
--- a/Source/HBIOS/cfg_RCZ280.asm
+++ b/Source/HBIOS/cfg_RCZ280.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm
index 9c211699..a379d3ca 100644
--- a/Source/HBIOS/cfg_RCZ80.asm
+++ b/Source/HBIOS/cfg_RCZ80.asm
@@ -180,6 +180,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm
index 83145218..bc024045 100644
--- a/Source/HBIOS/cfg_RPH.asm
+++ b/Source/HBIOS/cfg_RPH.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	FALSE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
diff --git a/Source/HBIOS/cfg_S100.asm b/Source/HBIOS/cfg_S100.asm
index 17d6c7b3..58279f07 100644
--- a/Source/HBIOS/cfg_S100.asm
+++ b/Source/HBIOS/cfg_S100.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm
index acf60bf9..1ad50a8e 100644
--- a/Source/HBIOS/cfg_SBC.asm
+++ b/Source/HBIOS/cfg_SBC.asm
@@ -172,6 +172,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 ;
 UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm
index 82a80bab..96b55a13 100644
--- a/Source/HBIOS/cfg_SCZ180.asm
+++ b/Source/HBIOS/cfg_SCZ180.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	FALSE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/cfg_SZ80.asm b/Source/HBIOS/cfg_SZ80.asm
index d5d631f7..2bdc2d78 100644
--- a/Source/HBIOS/cfg_SZ80.asm
+++ b/Source/HBIOS/cfg_SZ80.asm
@@ -177,6 +177,12 @@ SSERIINV	.SET	FALSE		; SSER: INPUT READY BIT INVERTED
 SSERORDY	.SET	%00000010	; SSER: OUTPUT READY BIT MASK
 SSEROINV	.SET	TRUE		; SSER: OUTPUT READY BIT INVERTED
 ;
+PLDSERENABLE	.SET	TRUE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
+PLDSERCFG	.SET	SER_9600_8N1	; PLDSER: SERIAL LINE CONFIG
+;
+TSERENABLE	.SET	FALSE		; TSER: ENABLE T35 SERIAL DRIVER (TSER.ASM)
+TSERCFG		.SET	SER_9600_8N1	; TSER: SERIAL LINE CONFIG
+;
 DUARTENABLE	.SET	FALSE		; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM)
 DUARTCNT	.SET	1		; DUART: NUMBER OF CHIPS TO DETECT (1-2)
 DUART0BASE	.SET	$A0		; DUART 0: BASE ADDRESS OF CHIP
diff --git a/Source/HBIOS/fv.asm b/Source/HBIOS/fv.asm
index 64259530..d045350d 100644
--- a/Source/HBIOS/fv.asm
+++ b/Source/HBIOS/fv.asm
@@ -58,6 +58,9 @@ KBDENABLE	.SET	TRUE		; INCLUDE KBD KEYBOARD SUPPORT
 ;
 FV_INIT:
 	LD	IY,FV_IDAT		; POINTER TO INSTANCE DATA
+;
+	OR	$FF			; CLEAR THE
+	LD	(FV_UNIT),A		; ... UNIT NUMBER
 ;
 	CALL	NEWLINE			; FORMATTING
 	PRTS("FV: IO=0x$")
@@ -72,9 +75,9 @@ FV_INIT:
 	RET
 ;
 FV_INIT1:
-	; RECORD DRIVER ACTIVE
-	OR	$FF
-	LD	(FV_ACTIVE),A
+;;;	; RECORD DRIVER ACTIVE
+;;;	OR	$FF
+;;;	LD	(FV_ACTIVE),A
 	; DISPLAY CONSOLE DIMENSIONS
 	LD	A,FV_COLS
 	CALL	PC_SPACE
@@ -100,7 +103,13 @@ FV_INIT1:
 	LD	DE,FV_FNTBL		; DE := FUNCTION TABLE ADDRESS
 	LD	HL,FV_IDAT		; HL := FPGA VGA INSTANCE DATA PTR
 	CALL	TERM_ATTACH		; DO IT
+	CP	$FF			; ERROR?
+	JR	NZ,FV_INIT2		; CONTINUE IF ALL GOOD
+	OR	A			; IF ERROR, SET FLAGS
+	RET				; AND RETURN
 
+FV_INIT2:
+	LD	(FV_UNIT),A		; RECORD OUR UNIT NUMBER
 	XOR	A			; SIGNAL SUCCESS
 	RET
 ;
@@ -485,7 +494,8 @@ FV_BLKCPY:
 ;==================================================================================================
 ;
 FV_POS		.DW 	0	; CURRENT DISPLAY POSITION
-FV_ACTIVE	.DB	FALSE	; FLAG FOR DRIVER ACTIVE
+;;;FV_ACTIVE	.DB	FALSE	; FLAG FOR DRIVER ACTIVE
+FV_UNIT		.DB	$FF	; ASSIGNED UNIT NUMBER
 ;
 ;==================================================================================================
 ;   VGA DRIVER - INSTANCE DATA
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index b8130ce3..602ba097 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -3013,19 +3013,39 @@ HB_CONRDY:
 ; IS NO CRT DEVICE.
 ;
 ;
-#IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_SZ80))
+#IF ((PLATFORM == PLT_S100) & SCONENABLE)
+	IN	A,($75)			; GET IO BYTE
+	AND	%00000001		; ISOLATE CONSOLE BIT
+	JR	NZ,HB_CONRDY_Z		; NOT SET, BYPASS CONSOLE SWITCH
+	LD	A,(SCON_UNIT)		; GET THE CONSOLE UNIT NUMBER
+	CP	$FF			; VALID?
+	JR	Z,HB_CONRDY_Z		; IF NOT, BYPASS CONSOLE SWITCH
+	LD	(CB_CONDEV),A		; SET CONSOLE DEVICE
+#ENDIF
+;
+#IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_SZ80) & SCONENABLE)
 	IN	A,($EF)			; GET IO BYTE
 	AND	%00100000		; ISOLATE CONSOLE BIT
-	JR	Z,HB_SZ80CON_Z		; IF ZERO, BYPASS CONSOLE SWITCH
-	LD	A,(CB_CRTDEV)		; GET CRT DEVICE
-	CP	$FF			; CHECK FOR NO H/W
-	JR	Z,HB_SZ80CON_Z		; IF ZERO, BYPASS CONSOLE SWITCH
+	JR	Z,HB_CONRDY_Z		; IF ZERO, BYPASS CONSOLE SWITCH
+	LD	A,(SCON_UNIT)		; GET THE CONSOLE UNIT NUMBER
+	CP	$FF			; VALID?
+	JR	Z,HB_CONRDY_Z		; IF NOT, BYPASS CONSOLE SWITCH
 	LD	(CB_CONDEV),A		; SET CONSOLE DEVICE
+#ENDIF
 ;
-HB_SZ80CON_Z:
-;
+#IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_Z2) & SCONENABLE)
+	IN	A,($36)			; GET IO BYTE
+	AND	%00000111		; ISOLATE CONSOLE BITS
+	CP	%00000111		; PROPELLER CONSOLE REQUEST?
+	JR	NZ,HB_CONRDY_Z		; IF NOT, BYPASS CONSOLE SWITCH
+	LD	A,(SCON_UNIT)		; GET THE CONSOLE UNIT NUMBER
+	CP	$FF			; VALID?
+	JR	Z,HB_CONRDY_Z		; IF NOT, BYPASS CONSOLE SWITCH
+	LD	(CB_CONDEV),A		; SET CONSOLE DEVICE
 #ENDIF
 ;
+HB_CONRDY_Z:
+;
 ; SUPPRESS HARDWARE FLOW CONTROL TEMPORARILY, IF NEEDED.  THIS IS
 ; GENERALLY NOT USED ANYMORE BECAUSE THE UART DRIVER NOW CHECKS FOR
 ; A VALID CTS SIGNAL AND ADJUSTS AS NEEDED.
@@ -3719,37 +3739,41 @@ HB_WDZ:
 	JR	Z,INITSYS3		; Z=SHORTED, BYPASS CONSOLE SWITCH
   #ENDIF
 ;
-  #IF (PLATFORM == PLT_S100)
-	IN	A,($75)			; GET IO BYTE
-	AND	%00000001		; ISOLATE CONSOLE BIT
-	JR	NZ,INITSYS3		; NOT SET, BYPASS CONSOLE SWITCH
-  #ENDIF
+HB_CRTACT:
+	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
+	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
 ;
-  #IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_Z2))
+#ENDIF
+;
+#IF ((PLATFORM == PLT_SZ80) & (MEMMGR == MM_Z2) & FVENABLE)
 	; IOBYTE: XXXXXVVC
 	;              00-	FORCE ONBOARD VGA/PS2 KBD (FV)
 	;              --1	FORCE PROPELLER CONSOLE (SCON)
 	;              110	NORMAL USB SERIAL BOOT
 	;
-	; WE ASSUME THAT THE ONBOARD VGA (FV) IS ALWAYS DETECTED AND
-	; WILL BE THE CURRENT CRTDEV.  SCON IS ASSUMED TO BE THE
-	; DEVICE AT CRTDEV + 1.  THESE ARE REASONABLE ASSUMPTIONS
-	; UNLESS THE DRIVER DETECTION OR DRIVER ORDER IS CHANGED.
+	;;;; WE ASSUME THAT THE ONBOARD VGA (FV) IS ALWAYS DETECTED AND
+	;;;; WILL BE THE CURRENT CRTDEV.  SCON IS ASSUMED TO BE THE
+	;;;; DEVICE AT CRTDEV + 1.  THESE ARE REASONABLE ASSUMPTIONS
+	;;;; UNLESS THE DRIVER DETECTION OR DRIVER ORDER IS CHANGED.
+	;;;IN	A,($36)			; GET IO BYTE
+	;;;AND	%00000110		; ISOLATE BITS
+	;;;JR	Z,HB_CRTACT		; FORCE ONBOARD CRT
+	;;;IN	A,($36)			; GET IO BYTE
+	;;;AND	%00000001		; ISOLATE BIT
+	;;;JR	Z,INITSYS3		; NORMAL USB SERIAL BOOT
+	;;;LD	A,(CB_CRTDEV)		; GET CRT DEV
+	;;;INC	A			; SWITCH FROM FV -> SCON
+	;;;LD	(CB_CRTDEV),A		; SAVE IT AND DO CONSOLE SWITCH
+	
+	; IF ONBOARD VGA/PS2 KBD IS REQUESTED, SETUP FOR CONSOLE SWITCH
 	IN	A,($36)			; GET IO BYTE
 	AND	%00000110		; ISOLATE BITS
-	JR	Z,HB_CRTACT		; FORCE ONBOARD CRT
-	IN	A,($36)			; GET IO BYTE
-	AND	%00000001		; ISOLATE BIT
-	JR	Z,INITSYS3		; NORMAL USB SERIAL BOOT
-	LD	A,(CB_CRTDEV)		; GET CRT DEV
-	INC	A			; SWITCH FROM FV -> SCON
-	LD	(CB_CRTDEV),A		; SAVE IT AND DO CONSOLE SWITCH
-  #ENDIF
-;
-HB_CRTACT:
-	LD	A,(CB_CRTDEV)		; GET CRT DISPLAY DEVICE
-	LD	(HB_NEWCON),A		; AND QUEUE TO SWITCH
-;
+	JR	NZ,INITSYS3		; BIT(S) NOT ZERO, BYPASS SWITCH
+	LD	A,(FV_UNIT)		; GET FV UNIT NUMBER
+	CP	$FF			; IS HARDWARE THERE?
+	JR	Z,INITSYS3		; IF NOT, BYPASS SWITCH
+	LD	(HB_NEWCON),A		; ELSE QUEUE TO SWITCH
+	LD	(CB_CRTDEV),A		; AND ENSURE IT IS THE CRT DEVICE
 #ENDIF
 ;
 #IF (FPSW_ENABLE)
@@ -4062,9 +4086,6 @@ HB_INITRLEN	.EQU	(($ - HB_INIT_REC) / 2)
 ;
 HB_PCINITTBL:
 ;
-#IF (SSERENABLE)
-	.DW	SSER_PREINIT
-#ENDIF
 #IF (ASCIENABLE)
 	.DW	ASCI_PREINIT
 #ENDIF
@@ -4086,6 +4107,15 @@ HB_PCINITTBL:
 #IF (ACIAENABLE)
 	.DW	ACIA_PREINIT
 #ENDIF
+#IF (SSERENABLE)
+	.DW	SSER_PREINIT
+#ENDIF
+#IF (TSERENABLE)
+	.DW	TSER_PREINIT
+#ENDIF
+#IF (PLDSERENABLE)
+	.DW	PLDSER_PREINIT
+#ENDIF
 #IF (UFENABLE)
 	.DW	UF_PREINIT
 #ENDIF
@@ -4176,6 +4206,12 @@ HB_INITTBL:
 #IF (SSERENABLE)
 	.DW	SSER_INIT
 #ENDIF
+#IF (TSERENABLE)
+	.DW	TSER_INIT
+#ENDIF
+#IF (PLDSERENABLE)
+	.DW	PLDSER_INIT
+#ENDIF
 #IF (ASCIENABLE)
 	.DW	ASCI_INIT
 #ENDIF
@@ -8853,6 +8889,24 @@ SIZ_SSER	.EQU	$ - ORG_SSER
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (TSERENABLE)
+ORG_TSER	.EQU	$
+  #INCLUDE "tser.asm"
+SIZ_TSER	.EQU	$ - ORG_TSER
+		MEMECHO	"TSER occupies "
+		MEMECHO	SIZ_TSER
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
+#IF (PLDSERENABLE)
+ORG_PLDSER	.EQU	$
+  #INCLUDE "pldser.asm"
+SIZ_PLDSER	.EQU	$ - ORG_PLDSER
+		MEMECHO	"PLDSER occupies "
+		MEMECHO	SIZ_PLDSER
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (ASCIENABLE)
 ORG_ASCI	.EQU	$
   #INCLUDE "asci.asm"
diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index 774ef29e..4170e291 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -396,6 +396,8 @@ CIODEV_ESPSER	.EQU	$0D
 CIODEV_SCON	.EQU	$0E
 CIODEV_SSER	.EQU	$0F
 CIODEV_EZ80UART	.EQU	$10
+CIODEV_PLDSER	.EQU	$11
+CIODEV_TSER	.EQU	$12
 ;
 ; SUB TYPES OF CHAR DEVICES
 ;
diff --git a/Source/HBIOS/invntdev.asm b/Source/HBIOS/invntdev.asm
index 045416bb..b45f1f72 100644
--- a/Source/HBIOS/invntdev.asm
+++ b/Source/HBIOS/invntdev.asm
@@ -637,6 +637,8 @@ PS_SDESPSER	.TEXT	"ESPSER$"
 PS_SDSCON	.TEXT	"SCON$"
 PS_SDSSER	.TEXT	"SSER$"
 PS_SDEZ80	.TEXT	"EZ80$"
+PS_SDPLDSER	.TEXT	"PLDSER$"
+PS_SDTSER	.TEXT	"TSER$"
 ;
 ; CHARACTER SUB TYPE STRINGS
 ;
diff --git a/Source/HBIOS/pldser.asm b/Source/HBIOS/pldser.asm
new file mode 100644
index 00000000..f468c3d9
--- /dev/null
+++ b/Source/HBIOS/pldser.asm
@@ -0,0 +1,154 @@
+;
+;==================================================================================================
+; PLD-USB SERIAL DRIVER
+;==================================================================================================
+;
+; THIS SERIAL DRIVER SUPPORTS THE DLP-USB DEVICE ON THE S100 SERIAL-IO
+; BOARD.  THE STATUS PORT IS ACTUALLY BITS 6-7 OF PORT C OF THE 8255.  IT IS ASSUMED
+; THAT THE 8255 IS ALREADY PROGRAMMED AS NEEDED.
+;
+; TODO:
+;
+PLDSER_STAT	.EQU	$AA
+PLDSER_DATA	.EQU	$AC
+;
+		DEVECHO	"PLDSER: IO="
+		DEVECHO	PLDSER_DATA
+		DEVECHO	"\n"
+;
+;
+;
+PLDSER_PREINIT:
+;
+; TEST FOR PRESENCE
+;
+	XOR	A			; CLEAR ACCUM
+	LD	(PLDSER_PRESENT),A	; PRESET TO NOT PRESENT
+	CALL	PLDSER_DETECT		; CHECK FOR HARDWARE, Z=PRESENT
+	RET	NZ			; ABORT IF NOT PRESENT
+	OR	$FF			; PRESENT FLAG
+	LD	(PLDSER_PRESENT),A	; STORE IT
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	D,0			; PHYSICAL UNIT IS ZERO
+	LD	E,CIODEV_PLDSER		; DEVICE TYPE
+	LD	BC,PLDSER_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+;
+	XOR	A
+	RET
+;
+;
+;
+PLDSER_INIT:
+	LD	A,(PLDSER_PRESENT)	; PRESENT FLAG
+	OR	A			; SET FLAGS
+	RET	Z			; ABORT IF NOT PRESENT
+	CALL	NEWLINE
+	PRTS("PLDSER:$")
+	PRTS(" IO=0x$")			; FORMATTING
+	LD	A,PLDSER_DATA
+	CALL	PRTHEXBYTE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+PLDSER_FNTBL:
+	.DW	PLDSER_IN
+	.DW	PLDSER_OUT
+	.DW	PLDSER_IST
+	.DW	PLDSER_OST
+	.DW	PLDSER_INITDEV
+	.DW	PLDSER_QUERY
+	.DW	PLDSER_DEVICE
+#IF (($ - PLDSER_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID PLDSER FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+PLDSER_IN:
+	CALL	PLDSER_IST		; CHECK FOR CHAR PENDING
+	JR	Z,PLDSER_IN		; WAIT FOR IT IF NECESSARY
+	IN	A,(PLDSER_DATA)		; READ THE CHAR
+	LD	E,A
+	RET
+;
+;
+;
+PLDSER_IST:
+	IN	A,(PLDSER_STAT)		; READ LINE STATUS REGISTER
+	CPL
+	AND	%10000000		; ISOLATE DATA READY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+PLDSER_OUT:
+	CALL	PLDSER_OST		; CHECK FOR OUTPUT READY
+	JR	Z,PLDSER_OUT		; WAIT IF NECESSARY
+	LD	A,E			; RECOVER THE CHAR TO WRITE
+	OUT	(PLDSER_DATA),A		; WRITE THE CHAR
+	RET
+;
+;
+;
+PLDSER_OST:
+	IN	A,(PLDSER_STAT)		; READ LINE STATUS REGISTER
+	CPL
+	AND	%01000000 		; ISOLATE OUTPUT RDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+PLDSER_INITDEV:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;
+;
+PLDSER_QUERY:
+	LD	DE,PLDSERCFG
+	XOR	A
+	RET
+;
+;
+;
+PLDSER_DEVICE:
+	LD	D,CIODEV_PLDSER		; D := DEVICE TYPE
+	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$00			; C := DEVICE TYPE, 0x00 IS RS-232
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,PLDSER_DATA		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; TEST FOR HARDWARE PRESENCE BY CHECKING THE STATUS PORT.  IF IT IS
+; $FF, WE ASSUME NOT PRESENT.  THEN READ PORT A DIFFERENT WAY.  IF
+; PRESENT PORT SHOULD HAVE SAME VALUE.
+;
+; THIS COULD BE SIGNIFICANTLY IMPROVED.
+; 
+;
+PLDSER_DETECT:
+	IN	A,(PLDSER_STAT)		; GET DATA PORT VALUE DIRECTLY
+	CP	$FF			; CHECK FOR $FF
+	JR	NZ,PLDSER_DETECT1	; IF NOT $FF, MAY BE ACTIVE, CONTINUE
+	OR	A			; SWITCH ZF BACK TO NZ
+	RET				; DONE
+PLDSER_DETECT1:
+	LD	C,PLDSER_STAT		; PORT ADR TO C
+	IN	B,(C)			; GET DATA PORT VALUE VIA (C)
+	CP	B			; COMPARE, EQUAL IMPLIES ACTIVE PORT
+	RET
+;
+;
+;
+PLDSER_PRESENT	.DB	0		; FLAG FOR HARDWARE PRESENT
\ No newline at end of file
diff --git a/Source/HBIOS/scon.asm b/Source/HBIOS/scon.asm
index f6457bc3..3821f29b 100644
--- a/Source/HBIOS/scon.asm
+++ b/Source/HBIOS/scon.asm
@@ -25,11 +25,17 @@ SCON_ROWS	.EQU	40
 SCON_PREINIT:
 ;
 ; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	OR	$FF			; CLEAR OUT
+	LD	(SCON_UNIT),A		; ... SCON UNIT NUMBER
+	CALL	SCON_DETECT		; SEE IF WE ARE THERE
+	RET	NZ			; ABORT IF NOT
 ;
 	LD	D,0			; PHYSICAL UNIT IS ZERO
 	LD	E,CIODEV_SCON		; DEVICE TYPE
 	LD	BC,SCON_FNTBL		; BC := FUNCTION TABLE ADDRESS
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+	LD	(SCON_UNIT),A		; RECORD OUR UNIT NUMBER
 	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 	XOR	A			; SIGNAL SUCCESS
@@ -44,6 +50,16 @@ SCON_INIT:
 	LD	A,SCON_IOBASE
 	CALL	PRTHEXBYTE
 ;
+	LD	A,(SCON_UNIT)
+	CP	$FF
+	JR	NZ,SCON_INIT1
+;
+	; HARDWARE NOT PRESENT
+	PRTS(" NOT PRESENT$")
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;
+SCON_INIT1:
 	; DISPLAY CONSOLE DIMENSIONS
 	CALL	PC_SPACE
 	LD	A,SCON_COLS
@@ -140,3 +156,28 @@ SCON_DEVICE:
 	LD	L,SCON_IOBASE		; L := BASE I/O ADDRESS
 	XOR	A			; SIGNAL SUCCESS
 	RET
+
+;
+; TEST FOR HARDWARE PRESENCE.
+; THIS IS REALLY A POOR SOLUTION.  WE ASSUME THAT THE STATUS AND
+; DATA PORT SHOULD NOT BE THE SAME VALUE.  IF SO, IT PROBABLY MEANS
+; THERE IS NOTHING THERE.
+;
+SCON_DETECT:
+	IN	A,(SCON_STATUS)		; GET STATUS PORT VALUE DIRECTLY
+	CP	$FF			; CHECK FOR $FF
+	JR	Z,SCON_DETECT1		; IF $FF, NOT ACTIVE
+	LD	B,A			; STASH IN B
+	IN	A,(SCON_DATA)		; READ DATA PORT
+	CP	B			; SAME?
+	JR	Z,SCON_DETECT1		; IF SO, NOT ACTIVE
+	XOR	A			; SIGNAL ACTIVE
+	RET
+	
+SCON_DETECT1:
+	OR	$FF			; SET NZ TO SIGNAL NOT PRESENT
+	RET				; DONE
+;
+;
+;
+SCON_UNIT	.DB	$FF		; OUR ASSIGNED UNIT NUMBER
\ No newline at end of file
diff --git a/Source/HBIOS/term.asm b/Source/HBIOS/term.asm
index 6f193013..5ad5513e 100644
--- a/Source/HBIOS/term.asm
+++ b/Source/HBIOS/term.asm
@@ -68,8 +68,11 @@ TERM_ATTACH:
 	CALL	ANSI_INIT		; INIT ANSI, DE := ANSI_FNTBL
   #ENDIF
 	POP	HL			; RECOVER VDA INSTANCE DATA  PTR
-	RET	NZ			; BAIL OUT ON ERROR
+	JR	Z,TERM_ATTACH1		; CONTINUE IF GOOD RETURN
+	OR	$FF			; SET ERROR RETURN
+	RET				; BAIL OUT ON ERROR
 ;
+TERM_ATTACH1:
 	; ADD OURSELVES TO CIO DISPATCH TABLE
 	PUSH	DE			; COPY EMULATOR FUNC TBL ADDRESS
 	POP	BC			; ... TO BC
@@ -77,13 +80,14 @@ TERM_ATTACH:
 	POP	DE			; ... TO DE
 	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
 	;;;LD	(HCB + HCB_CRTDEV),A	; SET OURSELVES AS THE CRT DEVICE
+	PUSH	AF			; SAVE UNIT ASSIGNED
 	CALL	CIO_SETCRT		; SET OURSELVES AS THE CRT DEVICE
 ;
 	; INCREMENT DEVICE COUNT
 	LD	HL,TERM_DEVCNT		; POINT TO DEVICE COUNT
 	INC	(HL)			; INCREMENT IT
 ;
-	XOR	A			; SIGNAL SUCCESS
+	POP	AF			; RETURN UNIT ASSIGNED
 	RET				; RETURN
 ;
 ;======================================================================
diff --git a/Source/HBIOS/tser.asm b/Source/HBIOS/tser.asm
new file mode 100644
index 00000000..1313580c
--- /dev/null
+++ b/Source/HBIOS/tser.asm
@@ -0,0 +1,116 @@
+;
+;==================================================================================================
+; S100 Z80 FPGA T35 SERIAL DRIVER
+;==================================================================================================
+;
+; THIS SERIAL DRIVER SUPPORTS THE SERIAL INTERFACE OF THE T35 FPGA.
+;
+; TODO:
+;
+TSER_STAT	.EQU	$34
+TSER_DATA	.EQU	$35
+;
+		DEVECHO	"TSER: IO="
+		DEVECHO	TSER_DATA
+		DEVECHO	"\n"
+;
+;
+;
+TSER_PREINIT:
+;
+; ADD OURSELVES TO CIO DISPATCH TABLE
+;
+	LD	D,0			; PHYSICAL UNIT IS ZERO
+	LD	E,CIODEV_TSER		; DEVICE TYPE
+	LD	BC,TSER_FNTBL		; BC := FUNCTION TABLE ADDRESS
+	CALL	CIO_ADDENT		; ADD ENTRY, A := UNIT ASSIGNED
+;
+	XOR	A
+	RET
+;
+;
+;
+TSER_INIT:
+	CALL	NEWLINE
+	PRTS("TSER:$")
+	PRTS(" IO=0x$")			; FORMATTING
+	LD	A,TSER_DATA
+	CALL	PRTHEXBYTE
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DRIVER FUNCTION TABLE
+;
+TSER_FNTBL:
+	.DW	TSER_IN
+	.DW	TSER_OUT
+	.DW	TSER_IST
+	.DW	TSER_OST
+	.DW	TSER_INITDEV
+	.DW	TSER_QUERY
+	.DW	TSER_DEVICE
+#IF (($ - TSER_FNTBL) != (CIO_FNCNT * 2))
+	.ECHO	"*** INVALID TSER FUNCTION TABLE ***\n"
+#ENDIF
+;
+;
+;
+TSER_IN:
+	CALL	TSER_IST		; CHECK FOR CHAR PENDING
+	JR	Z,TSER_IN		; WAIT FOR IT IF NECESSARY
+	IN	A,(TSER_DATA)		; READ THE CHAR
+	LD	E,A
+	RET
+;
+;
+;
+TSER_IST:
+	IN	A,(TSER_STAT)		; READ LINE STATUS REGISTER
+	AND	%00000001		; ISOLATE DATA READY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+TSER_OUT:
+	CALL	TSER_OST		; CHECK FOR OUTPUT READY
+	JR	Z,TSER_OUT		; WAIT IF NECESSARY
+	LD	A,E			; RECOVER THE CHAR TO WRITE
+	OUT	(TSER_DATA),A		; WRITE THE CHAR
+	RET
+;
+;
+;
+TSER_OST:
+	IN	A,(TSER_STAT)		; READ LINE STATUS REGISTER
+	CPL
+	AND	%00000010 		; ISOLATE OUTPUT RDY
+	JP	Z,CIO_IDLE		; RETURN VIA IDLE PROCESSING
+	OR	$FF			; SET A=$FF TO SIGNAL READY
+	RET				; RETURN
+;
+;
+;
+TSER_INITDEV:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+;
+;
+TSER_QUERY:
+	LD	DE,TSERCFG
+	XOR	A
+	RET
+;
+;
+;
+TSER_DEVICE:
+	LD	D,CIODEV_TSER		; D := DEVICE TYPE
+	LD	E,0			; E := DEVICE NUM, ALWAYS 0
+	LD	C,$00			; C := DEVICE TYPE, 0x00 IS RS-232
+	LD	H,0			; H := 0, DRIVER HAS NO MODES
+	LD	L,TSER_DATA		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
diff --git a/Source/ver.inc b/Source/ver.inc
index 4eb1e6cb..3fed1e83 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	6
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.6.0-dev.35"
+#DEFINE BIOSVER	"3.6.0-dev.36"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
diff --git a/Source/ver.lib b/Source/ver.lib
index caa06444..918ebbac 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	6
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.6.0-dev.35"
+	db	"3.6.0-dev.36"
 	endm