diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf
index 679a558e..f5c256cc 100644
Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ
diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf
index ba2bb9ec..0acd571b 100644
Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ
diff --git a/Doc/RomWBW Hardware.pdf b/Doc/RomWBW Hardware.pdf
index 9581b189..9957bb19 100644
Binary files a/Doc/RomWBW Hardware.pdf and b/Doc/RomWBW Hardware.pdf differ
diff --git a/Doc/RomWBW Introduction.pdf b/Doc/RomWBW Introduction.pdf
index 602e39f6..fccd89c0 100644
Binary files a/Doc/RomWBW Introduction.pdf and b/Doc/RomWBW Introduction.pdf differ
diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf
index 2100b0ef..142f1441 100644
Binary files a/Doc/RomWBW System Guide.pdf and b/Doc/RomWBW System Guide.pdf differ
diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf
index 3b51a5f3..2fcab94d 100644
Binary files a/Doc/RomWBW User Guide.pdf and b/Doc/RomWBW User Guide.pdf differ
diff --git a/ReadMe.md b/ReadMe.md
index 7676a7e8..fdaab2f1 100644
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -7,7 +7,7 @@
 **RomWBW Introduction** \
 Version 3.6 \
 Wayne Warthen  ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \
-21 Nov 2025
+25 Nov 2025
 
 # Overview
 
diff --git a/ReadMe.txt b/ReadMe.txt
index 94ffb2cb..1378794f 100644
--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -1,6 +1,6 @@
 RomWBW Introduction
 Wayne Warthen (wwarthen@gmail.com)
-21 Nov 2025
+25 Nov 2025
 
 
 
diff --git a/Source/Doc/Hardware.md b/Source/Doc/Hardware.md
index 4a5e0c25..7a01a0e6 100644
--- a/Source/Doc/Hardware.md
+++ b/Source/Doc/Hardware.md
@@ -2493,6 +2493,7 @@ Note:
 | RP5C01    | Ricoh RPC01A Real-Time Clock w/ NVRAM                  |
 | SIMRTC    | SIMH Simulator Real-Time Clock                         |
 | MMRTC     | NS MM58167B Real-Time Clock (no NVRAM)                 |
+| DS12RTC   | Dallas Semiconductor DS1288x Real-Time Clock w/ NVRAM  |
 
 ## DsKy (DiSplay KeYpad)
 
diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md
index 09322708..3452b338 100644
--- a/Source/Doc/SystemGuide.md
+++ b/Source/Doc/SystemGuide.md
@@ -1444,6 +1444,7 @@ unit.  The table below enumerates these values.
 | RTCDEV_EZ80     | 0x07   | eZ80 on-chip RTC                         | ez80rtc.asm |
 | RTCDEV_PC       | 0x08   | MC146818/DS1285/DS12885 RTC w/ NVRAM     | pcrtc.asm   |
 | RTCDEV_MM       | 0x09   | NS MM58167B RTC (no NVRAM)               | mmrtc.asm   |
+| RTCDEV_DS12     | 0x0A   | DS1288x RTC w/NVRAM                      | ds12rtc.asm   |
 
 The time functions to get and set the time (RTCGTM and RTCSTM) require a
 6 byte date/time buffer in the following format. Each byte is BCD 
diff --git a/Source/HBIOS/Config/SZ180_std.asm b/Source/HBIOS/Config/SZ180_std.asm
index 5e4a42ed..5fcaae20 100644
--- a/Source/HBIOS/Config/SZ180_std.asm
+++ b/Source/HBIOS/Config/SZ180_std.asm
@@ -59,6 +59,7 @@ Z180_IOWAIT	.SET	3		; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 ;
 INTRTCENABLE	.SET	TRUE		; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM)
 MMRTCENABLE	.SET	TRUE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+DS12RTCENABLE	.SET	TRUE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
 ;
 ASCIENABLE	.SET	TRUE		; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
 PLDSERENABLE	.SET	TRUE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
diff --git a/Source/HBIOS/Config/SZ80_std.asm b/Source/HBIOS/Config/SZ80_std.asm
index 0dc552ce..2fe89c63 100644
--- a/Source/HBIOS/Config/SZ80_std.asm
+++ b/Source/HBIOS/Config/SZ80_std.asm
@@ -48,7 +48,7 @@
 #INCLUDE "cfg_SZ80.asm"
 ;
 CPUOSC		.SET	8000000		; CPU OSC FREQ IN MHZ
-RAMSIZE		.SET	1024		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
+RAMSIZE		.SET	896		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 ROMSIZE		.SET	0		; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.SET	MM_SZ80		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512|SZ80]
 ;
@@ -56,6 +56,7 @@ FPLED_ENABLE	.SET	TRUE		; FP: ENABLES FRONT PANEL LEDS
 FPLED_IO	.SET	$05		; FP: PORT ADDRESS FOR FP LEDS
 ;
 MMRTCENABLE	.SET	TRUE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
+DS12RTCENABLE	.SET	TRUE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
 ;
 PLDSERENABLE	.SET	TRUE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
 SCCENABLE	.SET	TRUE		; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM)
diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm
index 080b6659..7b73bd0d 100644
--- a/Source/HBIOS/cfg_DUO.asm
+++ b/Source/HBIOS/cfg_DUO.asm
@@ -171,6 +171,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm
index 5958754f..6d2c1d00 100644
--- a/Source/HBIOS/cfg_DYNO.asm
+++ b/Source/HBIOS/cfg_DYNO.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm
index d52146de..40ad1661 100644
--- a/Source/HBIOS/cfg_EPITX.asm
+++ b/Source/HBIOS/cfg_EPITX.asm
@@ -166,6 +166,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm
index 812c7c27..e2463064 100644
--- a/Source/HBIOS/cfg_EZZ80.asm
+++ b/Source/HBIOS/cfg_EZZ80.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm
index 1b4c61b8..e2aadd64 100644
--- a/Source/HBIOS/cfg_GMZ180.asm
+++ b/Source/HBIOS/cfg_GMZ180.asm
@@ -165,6 +165,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm
index 91800be5..6146432c 100644
--- a/Source/HBIOS/cfg_HEATH.asm
+++ b/Source/HBIOS/cfg_HEATH.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_MASTER.asm b/Source/HBIOS/cfg_MASTER.asm
index 1235ad56..a882246b 100644
--- a/Source/HBIOS/cfg_MASTER.asm
+++ b/Source/HBIOS/cfg_MASTER.asm
@@ -206,6 +206,8 @@ DS5RTCENABLE	.EQU	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.EQU	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.EQU	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 PCRTCENABLE	.EQU	FALSE		; PCRTC: DISABLE DS12885 etc. RTC
 PCRTC_BASE	.EQU	$C0		; Default port for PCRTC, like DSRTC.
 ;
diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm
index 0341cc12..3ae28e03 100644
--- a/Source/HBIOS/cfg_MBC.asm
+++ b/Source/HBIOS/cfg_MBC.asm
@@ -164,6 +164,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm
index e0575cbc..25c72ed7 100644
--- a/Source/HBIOS/cfg_MK4.asm
+++ b/Source/HBIOS/cfg_MK4.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm
index 6a04af30..db29c120 100644
--- a/Source/HBIOS/cfg_MON.asm
+++ b/Source/HBIOS/cfg_MON.asm
@@ -167,6 +167,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_MSX.asm b/Source/HBIOS/cfg_MSX.asm
index d06b8dda..72cd4974 100644
--- a/Source/HBIOS/cfg_MSX.asm
+++ b/Source/HBIOS/cfg_MSX.asm
@@ -173,6 +173,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm
index b30ac4fa..eced079a 100644
--- a/Source/HBIOS/cfg_N8.asm
+++ b/Source/HBIOS/cfg_N8.asm
@@ -172,6 +172,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm
index 28f79467..5e982f5b 100644
--- a/Source/HBIOS/cfg_NABU.asm
+++ b/Source/HBIOS/cfg_NABU.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_RCEZ80.asm b/Source/HBIOS/cfg_RCEZ80.asm
index 2d2c57c5..0f1b3d5e 100644
--- a/Source/HBIOS/cfg_RCEZ80.asm
+++ b/Source/HBIOS/cfg_RCEZ80.asm
@@ -168,6 +168,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm
index ec016b6e..49d9c257 100644
--- a/Source/HBIOS/cfg_RCZ180.asm
+++ b/Source/HBIOS/cfg_RCZ180.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm
index 8e5bc2df..2e57b6de 100644
--- a/Source/HBIOS/cfg_RCZ280.asm
+++ b/Source/HBIOS/cfg_RCZ280.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm
index 66f04201..d69941c4 100644
--- a/Source/HBIOS/cfg_RCZ80.asm
+++ b/Source/HBIOS/cfg_RCZ80.asm
@@ -173,6 +173,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm
index d260bd44..eb0a352d 100644
--- a/Source/HBIOS/cfg_RPH.asm
+++ b/Source/HBIOS/cfg_RPH.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm
index 3b4d9d65..d0715d67 100644
--- a/Source/HBIOS/cfg_SBC.asm
+++ b/Source/HBIOS/cfg_SBC.asm
@@ -165,6 +165,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm
index 01b0973d..ec80f52f 100644
--- a/Source/HBIOS/cfg_SCZ180.asm
+++ b/Source/HBIOS/cfg_SCZ180.asm
@@ -170,6 +170,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_SZ180.asm b/Source/HBIOS/cfg_SZ180.asm
index a355116c..9cbf1549 100644
--- a/Source/HBIOS/cfg_SZ180.asm
+++ b/Source/HBIOS/cfg_SZ180.asm
@@ -167,6 +167,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 ;
 PLDSERENABLE	.SET	FALSE		; PLDSER: ENABLE PLD-USB SERIAL DRIVER (PLDSER.ASM)
diff --git a/Source/HBIOS/cfg_SZ80.asm b/Source/HBIOS/cfg_SZ80.asm
index 753122da..a752f904 100644
--- a/Source/HBIOS/cfg_SZ80.asm
+++ b/Source/HBIOS/cfg_SZ80.asm
@@ -160,6 +160,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm
index 0de6f6de..d1d80274 100644
--- a/Source/HBIOS/cfg_Z80RETRO.asm
+++ b/Source/HBIOS/cfg_Z80RETRO.asm
@@ -168,6 +168,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm
index cb253639..85f98aae 100644
--- a/Source/HBIOS/cfg_ZETA.asm
+++ b/Source/HBIOS/cfg_ZETA.asm
@@ -157,6 +157,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm
index 11501264..bad7c3cc 100644
--- a/Source/HBIOS/cfg_ZETA2.asm
+++ b/Source/HBIOS/cfg_ZETA2.asm
@@ -168,6 +168,8 @@ DS5RTCENABLE	.SET	FALSE		; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM)
 ;
 MMRTCENABLE	.SET	FALSE		; MMRTC: ENABLE NS MM58167B RTC DRIVER (MMRTC.ASM)
 ;
+DS12RTCENABLE	.SET	FALSE		; DS12RTC: ENABLE DS1288X RTC DRIVER (DS12RTC.ASM)
+;
 SSERENABLE	.SET	FALSE		; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM)
 SSERCFG		.SET	SER_9600_8N1	; SSER: SERIAL LINE CONFIG
 SSERSTATUS	.SET	$FF		; SSER: STATUS PORT
diff --git a/Source/HBIOS/ds12rtc.asm b/Source/HBIOS/ds12rtc.asm
new file mode 100644
index 00000000..7a3bb864
--- /dev/null
+++ b/Source/HBIOS/ds12rtc.asm
@@ -0,0 +1,380 @@
+;
+;==================================================================================================
+; DALLAS SEMICONDUCTOR DS1288X REAL TIME CLOCK
+;==================================================================================================
+;
+; THIS DRIVER IS FOR THE DS1288X REAL-TIME CLOCK AND NVRAM.
+; THE INTERFACE IS ASSUMED TO BE LIKE AN IBM PC AT PORT 0X70.
+;
+; TODO:
+;   CHECK CONTROL REG A, BIT 7 (VALID RAM/TIME) AND NOTIFY
+;   USER IF BATTERY IS DISCHARGED.
+;
+;  REGISTER ADDRESSES (HEX / BCD):
+;
+;  +---------+----------------------------------------------+--------+
+;  | REG     | FUNCTION                                     | RANGE  |
+;  +---------+----------------------------------------------+--------+
+;  | $00     | SECONDS                                      | 0-59   |
+;  | $01     | SECONDS ALARM                                | 0-59   |
+;  | $02     | MINUTES                                      | 0-59   |
+;  | $03     | MINUTES ALARM                                | 0-59   |
+;  | $04     | HOURS                                        | 00-23  |
+;  | $05     | HOURS ALARM                                  | 00-23  |
+;  | $06     | DAY                                          | 01-07  |
+;  | $07     | DATE                                         | 01-31  |
+;  | $08     | MONTH                                        | 01-12  |
+;  | $09     | YEAR                                         | 00-99  |
+;  | $0A     | CONTROL (SEE BELOW)                          | --     |
+;  | $0B     | CONTROL (SEE BELOW)                          | --     |
+;  | $0C     | CONTROL (SEE BELOW)                          | --     |
+;  | $0D     | CONTROL (SEE BELOW)                          | --     |
+;  | $0E-$31 | RAM                                          | --     |
+;  | $32     | CENTURY                                      | 00-99  |
+;  | $33-$7F | RAM                                          | --     |
+;  +---------+----------------------------------------------+--------+
+;
+;  +-----+-------+-------+-------+-------+-------+-------+-------+-------+
+;  | REG | BIT 7 | BIT 6 | BIT 5 | BIT 4 | BIT 3 | BIT 2 | BIT 1 | BIT 0 |
+;  +-----+-------+-------+-------+-------+-------+-------+-------+-------+
+;  | $0A | UIP   | DV2   | DV1   | DV0   | RS3   | RS2   | RS1   | RS0   |
+;  | $0B | SET   | PIE   | AIE   | UIE   | SQWE  | DM    | 24/12 | DSE   |
+;  | $0C | IRQF  | PF    | AF    | UF    | 0     | 0     | 0     | 0     |
+;  | $0D | VRT   | 0     | 0     | 0     | 0     | 0     | 0     | 0     |
+;  +-----+-------+-------+-------+-------+-------+-------+-------+-------+
+;
+DS12RTC_IO	.EQU	$70
+DS12RTC_SEL	.EQU	DS12RTC_IO + 0
+DS12RTC_DATA	.EQU	DS12RTC_IO + 1
+;
+	DEVECHO	"DS12RTC:"
+;
+	DEVECHO	" IO="
+	DEVECHO	DS12RTC_IO
+	DEVECHO	"\n"
+;
+; RTC DEVICE PRE-INITIALIZATION ENTRY
+;
+DS12RTC_PREINIT:
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; RTC DEVICE INITIALIZATION ENTRY
+;
+DS12RTC_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("DS12RTC:$")
+;
+	; PRINT RTC PORT ADDRESS
+	PRTS(" IO=0x$")			; LABEL FOR IO ADDRESS
+	LD	A,DS12RTC_IO		; GET IO ADDRESS
+	CALL	PRTHEXBYTE		; PRINT IT
+;
+	CALL	DS12RTC_DETECT		; HARDWARE DETECTION
+	JR	Z,DS12RTC_INIT1		; CONTINUE IF FOUND
+;
+	; HANDLE HARDWARE MISSING
+	PRTS(" NOT PRESENT$")		; NOT ZERO, H/W NOT PRESENT
+	OR	$FF			; SIGNAL FAILURE
+	RET				; BAIL OUT
+;
+DS12RTC_INIT1:
+	; INITIALIZE RTC
+	CALL	DS12RTC_INITDEV
+;
+	; DISPLAY CURRENT TIME
+	CALL	PC_SPACE
+	LD	HL,DS12RTC_TIMBUF
+	CALL	DS12RTC_RDCLK
+	LD	HL,DS12RTC_TIMBUF
+	CALL	PRTDT
+;
+	; REGISTER THE RTC
+	LD	BC,DS12RTC_DISPATCH
+	CALL	RTC_SETDISP
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; RTC DEVICE FUNCTION DISPATCH ENTRY
+;   A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR
+;   B: FUNCTION (IN)
+;
+DS12RTC_DISPATCH:
+	LD	A,B		; GET REQUESTED FUNCTION
+	AND	$0F		; ISOLATE SUB-FUNCTION
+	JP	Z,DS12RTC_GETTIM	; GET TIME
+	DEC	A
+	JP	Z,DS12RTC_SETTIM	; SET TIME
+	DEC	A
+	JP	Z,DS12RTC_GETBYT	; GET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,DS12RTC_SETBYT	; SET NVRAM BYTE VALUE
+	DEC	A
+	JP	Z,DS12RTC_GETBLK	; GET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,DS12RTC_SETBLK	; SET NVRAM DATA BLOCK VALUES
+	DEC	A
+	JP	Z,DS12RTC_GETALM	; GET ALARM
+	DEC	A
+	JP	Z,DS12RTC_SETALM	; SET ALARM
+	DEC	A
+	JP	Z,DS12RTC_DEVICE	; REPORT RTC DEVICE INFO
+;
+	SYSCHKERR(ERR_NOFUNC)
+	RET
+;
+; ALARM FUNCTIONALITY NOT IMPLEMENTED
+;
+DS12RTC_GETBLK:
+DS12RTC_SETBLK:
+DS12RTC_GETALM:
+DS12RTC_SETALM:
+	SYSCHKERR(ERR_NOTIMPL)
+	RET
+;
+; RTC GET TIME
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS12RTC_GETTIM:
+	PUSH	HL			; SAVE ADR OF OUTPUT BUF
+;
+	LD	HL,DS12RTC_TIMBUF	; POINTER TO CLK DATA
+	CALL	DS12RTC_RDCLK		; READ IT
+;
+	; NOW COPY TO REAL DESTINATION (INTERBANK SAFE)
+	LD	A,BID_BIOS		; COPY FROM BIOS BANK
+	LD	(HB_SRCBNK),A           ; SET IT
+	LD	A,(HB_INVBNK)		; COPY TO CURRENT USER BANK
+	LD	(HB_DSTBNK),A           ; SET IT
+	LD	HL,DS12RTC_TIMBUF		; SOURCE ADR
+	POP	DE			; DEST ADR
+	LD	BC,6			; LENGTH IS 6 BYTES
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; CLEAN UP AND RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; RTC SET TIME
+; BUFFER FORMAT IS BCD: YYMMDDHHMMSS
+; 24 HOUR TIME FORMAT IS ASSUMED
+;
+DS12RTC_SETTIM:
+	; COPY INCOMING TIME DATA TO OUR TIME BUFFER
+	LD	A,(HB_INVBNK)		; COPY FROM CURRENT USER BANK
+	LD	(HB_SRCBNK),A		; SET IT
+	LD	A,BID_BIOS		; COPY TO BIOS BANK
+	LD	(HB_DSTBNK),A		; SET IT
+	LD	DE,DS12RTC_TIMBUF		; DEST ADR
+	LD	BC,6			; LENGTH IS 6 BYTES
+#IF (INTMODE == 1)
+	DI
+#ENDIF
+	CALL	HB_BNKCPY		; COPY THE CLOCK DATA
+#IF (INTMODE == 1)
+	EI
+#ENDIF
+;
+	; WRITE TO CLOCK
+	LD	HL,DS12RTC_TIMBUF	; POINTER TO CLK DATA
+	CALL	DS12RTC_WRCLK		; WRITE TO THE CLOCK
+;
+	; CLEAN UP AND RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; AND RETURN
+;
+; RTC GET NVRAM BYTE
+;   C: INDEX
+;   E: VALUE (OUTPUT)
+;
+DS12RTC_GETBYT:
+	LD	A,C			; INDEX TO ACCUM
+	ADD	A,$0E			; RAM STARTS AT INDEX $0E
+	LD	C,A			; INDEX BACK TO C
+	CALL	DS12RTC_RDREG		; GET THE VALUE
+	LD	E,A			; PUT IN E TO RETURN
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; RTC SET NVRAM BYTE
+;   C: INDEX
+;   E: VALUE
+;
+DS12RTC_SETBYT:
+	LD	A,C			; INDEX TO ACCUM
+	ADD	A,$0E			; RAM STARTS AT INDEX $0E
+	LD	C,A			; INDEX BACK TO C
+	LD	A,E			; PUT VALUE IN A
+	CALL	DS12RTC_WRREG		; WRITE IT
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;
+; REPORT RTC DEVICE INFO
+;
+DS12RTC_DEVICE:
+	LD	D,RTCDEV_DS12		; D := DEVICE TYPE
+	LD	E,0			; E := PHYSICAL DEVICE NUMBER
+	LD	H,0			; H := MODE
+	LD	L,DS12RTC_IO		; L := BASE I/O ADDRESS
+	XOR	A			; SIGNAL SUCCESS
+	RET
+;
+; DETECT RTC HARDWARE PRESENCE
+; RETURN Z IF PRESENT
+;
+DS12RTC_DETECT:
+	LD	C,$7F			; USE LAST RAM BYTE FOR TESTING
+	CALL	DS12RTC_RDREG		; GET CURRENT VALUE
+	LD	B,A			; SAVE IT
+	LD	A,$A5			; TEST VALUE
+	CALL	DS12RTC_WRREG		; WRITE IT
+	CALL	DS12RTC_RDREG		; READ IT BACK
+	CP	$A5			; COMPARE TO TEST VALUE
+	PUSH	AF			; SAVE RESULTS
+	LD	A,B			; RECOVER ORIGINAL VALUE
+	CALL	DS12RTC_WRREG		; RESTORE IT
+	POP	AF			; RECOVER RESULT
+	RET				; AND RETURN
+;
+; READ CLOCK DATA INTO BUFFER AT HL (YYMMDDHHMMSS)
+;
+DS12RTC_RDCLK:
+	LD	D,H			; RESET DE
+	LD	E,L			; ... IN CASE OF RESTART
+	LD	C,$09			; START WITH YEAR REG
+	CALL	DS12RTC_RDCLK1		; DO YEAR (REG $09)
+	JR	NZ,DS12RTC_RDCLK	; RESTART IF UIP DETECTED
+	CALL	DS12RTC_RDCLK1		; DO MONTH (REG $08)
+	JR	NZ,DS12RTC_RDCLK	; RESTART IF UIP DETECTED
+	CALL	DS12RTC_RDCLK1		; DO DAY OF MONTH (REG $07)
+	JR	NZ,DS12RTC_RDCLK	; RESTART IF UIP DETECTED
+	DEC	C			; SKIP DAY OF WEEK (REG $06)
+	DEC	C			; SKIP HOURS ALARM (REG $05)
+	CALL	DS12RTC_RDCLK1		; DO HOUR (REG $04)
+	JR	NZ,DS12RTC_RDCLK	; RESTART IF UIP DETECTED
+	DEC	C			; SKIP MINUTES ALARM (REG $03)
+	CALL	DS12RTC_RDCLK1		; DO MINUTES (REG $02)
+	JR	NZ,DS12RTC_RDCLK	; RESTART IF UIP DETECTED
+	DEC	C			; SKIP SECONDS ALARM (REG $01)
+	CALL	DS12RTC_RDCLK1		; DO SECONDS (REG $00)
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;	
+DS12RTC_RDCLK1:
+	CALL	DS12RTC_RDREG		; GET IT
+	LD	(DE),A			; STORE IN BUF
+	INC	DE			; BUMP BUF PTR
+	DEC	C			; DEC REGISTER
+	JR	DS12RTC_UIP		; RETURN VIA CHECK FOR UPDATE IN PROGRESS
+;
+; WRITE CLOCK DATA FROM BUFFER AT HL
+;
+DS12RTC_WRCLK:
+	LD	D,H			; RESET DE
+	LD	E,L			; ... IN CASE OF RESTART
+	LD	C,$09			; START WITH YEAR REG
+	CALL	DS12RTC_WRCLK1		; DO YEAR (REG $09)
+	JR	NZ,DS12RTC_WRCLK	; RESTART IF SO
+	CALL	DS12RTC_WRCLK1		; DO MONTH (REG $08)
+	JR	NZ,DS12RTC_WRCLK	; RESTART IF SO
+	CALL	DS12RTC_WRCLK1		; DO DAY OF MONTH (REG $07)
+	JR	NZ,DS12RTC_WRCLK	; RESTART IF SO
+	DEC	C			; SKIP DAY OF WEEK (REG $06)
+	DEC	C			; SKIP HOURS ALARM (REG $05)
+	CALL	DS12RTC_WRCLK1		; DO HOUR (REG $04)
+	JR	NZ,DS12RTC_WRCLK	; RESTART IF SO
+	DEC	C			; SKIP MINUTES ALARM (REG $03)
+	CALL	DS12RTC_WRCLK1		; DO MINUTES (REG $02)
+	JR	NZ,DS12RTC_WRCLK	; RESTART IF SO
+	DEC	C			; SKIP SECONDS ALARM (REG $01)
+	CALL	DS12RTC_WRCLK1		; DO SECONDS (REG $00)
+;
+	XOR	A			; SIGNAL SUCCESS
+	RET				; DONE
+;	
+DS12RTC_WRCLK1:				; 108TS
+	LD	A,(DE)			; GET VALUE
+	CALL	DS12RTC_WRREG		; WRITE IT
+	INC	DE			; BUMP BUF PTR
+	DEC	C			; DEC REGISTER
+	JR	DS12RTC_UIP		; RETURN VIA CHECK FOR UPDATE IN PROGRESS
+;
+; INITIALIZE RTC
+;
+DS12RTC_INITDEV:
+;
+	; GET CLOCK STATUS
+	LD	C,$0A			; CONTROL REGISTER A
+	CALL	DS12RTC_RDREG		; READ IT
+	PUSH	AF			; SAVE IT
+;
+	; SET THE CONTROL REGISTERS
+	LD	C,$0A			; CONTROL REGISTER A
+	LD	A,%00100110		; START CLOCK, 1.024KHZ SQUARE WAVE OUTPOUT
+	CALL	DS12RTC_WRREG		; SEND IT
+	INC	C			; CONTROL REGISTER B
+	LD	A,%00000010		; NO INTS, NO ALM, NO SQW, BCD, 24HR, NO DS
+	CALL	DS12RTC_WRREG		; SEND IT
+;
+	POP	AF			; RECOVER ORIGINAL STATUS
+	AND	%01110000		; ISOLATE DV BITS
+	CP	%00100000		; NORMAL RUNNING VALUE?
+	RET	Z			; IF SO, DONE
+;
+	; PROGRAM DEFAULT DATE/TIME
+	LD	HL,DS12RTC_TIMDEF	; POINT TO DEFAULT DATE/TIME BUF
+	CALL	DS12RTC_WRCLK		; WRITE TO THE CLOCK
+	RET				; DONE
+;
+; READ REGSITER
+;   C=REGISTER
+;   A=VALUE
+;
+DS12RTC_RDREG:				; 43TS
+	LD	A,C			; REGSITER TO A
+	OUT	(DS12RTC_SEL),A		; SELECT IT
+	IN	A,(DS12RTC_DATA)	; GET REG VALUE
+	RET				; DONE
+;
+; WRITE REGSITER
+;   C=REGSITER
+;   A=VALUE
+;
+DS12RTC_WRREG:				; 64TS
+	PUSH	AF			; SAVE VALUE TO WRITE
+	LD	A,C			; REGSITER TO A
+	OUT	(DS12RTC_SEL),A		; SELECT IT
+	POP	AF			; RECOVER VALUE TO WRITE
+	OUT	(DS12RTC_DATA),A	; GET REG VALUE
+	RET				; DONE
+;
+; CHECK FOR UPDATE IN PROGRESS
+; RETURN NZ IF SO, RETURN Z IF CLEAR TO PROCEED
+; ASSUMES THAT RTC EXISTS AND IS FUNCTIONING
+;
+; UIP BIT WILL BE SET 244US BEFORE AN UPDATE BEGINS.
+; THE UIP BIT MAY NEED TO BE CHECKED REPEATEDLY DURING
+; MULTIPLE BYTE READS/WRITES IF THE PROCESSING MAY
+; TAKE MORE THAN 240US.
+;
+DS12RTC_UIP:
+	PUSH	BC
+	LD	C,$0A
+	CALL	DS12RTC_RDREG		; GET CONTROL REG $0A
+	AND	$80			; ISOLATE UIP BIT
+	POP	BC
+	RET
+;
+; DS12RTC_TIMBUF IS DRIVER'S INTERNAL CLOCK DATA BUFFER
+;
+DS12RTC_TIMBUF	.FILL	6,0		; 6 BYTES FOR GETTIM, YYMMDDHHMMSS
+DS12RTC_TIMDEF	.DB	$00,$01,$01,$00,$00,$00
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index b9c22ee9..2dc64919 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -993,9 +993,17 @@ Z280_SYSCALL_GO:
 ; rotates the requested bank numbers by 4.  With wrapping, this
 ; causes a RomWBW request for the top two banks to be mapped to
 ; physical banks $02 & $03.
-; 
-; Z80 CPU Physical:  $00 $01 $02 $03 ... $38 $39 $3A $3B $3C $3D $3E $3F
-; RomWBW Logical:    $04 $05 $06 $07 ... $3C $3D $3E $3F $00 $01 $02 $03
+;
+; RomWBW Logical:    $00 $01 $02 $03 ... $38 $39 $3A $3B $3C $3D $3E $3F
+; Z80 CPU Physical:  $04 $05 $06 $07 ... $3C $3D $3E $3F $00 $01 $02 $03
+;
+; RomWBW Bank Id:    $80    $81    $82    $83    ... $98    $99    $9A    $9B    $9C    $9D    $9E    $9F
+; Physical Address:  $10000 $18000 $20000 $28000 ... $D0000 $D8000 $E0000 $E8000 $F0000 $F8000 $00000 $08000
+;
+; WARNING: If the MS-DOS Support Board is used with ROM enabled it will
+; map ROM to $F0000-$FFFFF!  This means that we can only use bank ids
+; up to $9B which is 28 banks or 896K.  The RAMSIZE config must be limited
+; to 896 in this case.
 ;
 	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
 	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
@@ -1003,7 +1011,7 @@ Z280_SYSCALL_GO:
 	ADD	A,ROMSIZE / 32		; STARTING RAM BANK NUMBER OFFSET
 ;
 HBX_ROM:
-	ADD	A,2			; OFFSET TO SKIP OVER FIXED PAGES
+	ADD	A,2			; OFFSET TO ALIGN WITH FIXED COMMON BANK
 	RLA				; LOW 2 BITS
 	RLA				; ... ARE NOT USED
 	RLA				; TIMES 2 - GET 16K PAGE INSTEAD OF 32K
@@ -4275,6 +4283,9 @@ HB_INITTBL:
 #IF (MMRTCENABLE)
 	.DW	MMRTC_INIT
 #ENDIF
+#IF (DS12RTCENABLE)
+	.DW	DS12RTC_INIT
+#ENDIF
 #IF (INTRTCENABLE)
 	.DW	INTRTC_INIT
 #ENDIF
@@ -8919,6 +8930,15 @@ SIZ_MMRTC	.EQU	$ - ORG_MMRTC
 		MEMECHO	" bytes.\n"
 #ENDIF
 ;
+#IF (DS12RTCENABLE)
+ORG_DS12RTC	.EQU	$
+  #INCLUDE "ds12rtc.asm"
+SIZ_DS12RTC	.EQU	$ - ORG_DS12RTC
+		MEMECHO	"DS12RTC occupies "
+		MEMECHO	SIZ_DS12RTC
+		MEMECHO	" bytes.\n"
+#ENDIF
+;
 #IF (INTRTCENABLE)
 ORG_INTRTC	.EQU	$
   #INCLUDE "intrtc.asm"
diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc
index e20bf0c1..dbb8c059 100644
--- a/Source/HBIOS/hbios.inc
+++ b/Source/HBIOS/hbios.inc
@@ -439,6 +439,7 @@ RTCDEV_DS5	.EQU	$06		; DS1305 (SPI)
 RTCDEV_EZ80	.EQU	$07		; EZ80 ON-CHIP RTC
 RTCDEV_PC	.EQU	$08		; PC style parallel RTC
 RTCDEV_MM	.EQU	$09		; NS MM58167B RTC (NO NVRAM)
+RTCDEV_DS12	.EQU	$0A		; DS1288X
 ;
 ; DSKY DEVICE IDS
 ;
diff --git a/Source/ver.inc b/Source/ver.inc
index 040be9de..480aee5b 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,7 +2,7 @@
 #DEFINE	RMN	6
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.6.0-dev.40"
+#DEFINE BIOSVER	"3.6.0-dev.41"
 #define rmj	RMJ
 #define rmn	RMN
 #define rup	RUP
diff --git a/Source/ver.lib b/Source/ver.lib
index 444e787a..7834387c 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	6
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.6.0-dev.40"
+	db	"3.6.0-dev.41"
 	endm