ZRC support courtesy Bill Shen

Doc/ChangeLog.txt

@@ -6,6 +6,7 @@ Version 3.1.1
 - WBW: Enhanced SYSTEM RESET function to allow a warm start back to boot loader
 - C?O: Add DUART driver
 - WBW: Early Z280 support (requires 512K RAM/ROM board)
+- HCS: ZRC memory manager support
 
 Version 3.1
 -----------

Source/HBIOS/Config/RCZ80_zrc.asm

@@ -0,0 +1,45 @@
+;
+;==================================================================================================
+;   RC2014 Z80 ZRC CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#define	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "cfg_rcz80.asm"
+;
+CPUOSC		.SET	7372800		; CPU OSC FREQ IN MHZ
+;
+MEMMGR		.SET	MM_ZRC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+;
+UARTENABLE	.SET	TRUE		; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
+ACIAENABLE	.SET	TRUE		; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
+SIOENABLE	.SET	TRUE		; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
+;
+TMSENABLE	.SET	FALSE		; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
+TMSTIMENABLE	.SET	FALSE		; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1)
+;
+FDENABLE	.SET	FALSE		; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
+FDMODE		.SET	FDMODE_RCWDC	; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC]
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

Source/HBIOS/Makefile

@@ -16,6 +16,7 @@ else
 	OBJECTS += RCZ80_mt.rom RCZ80_mt.com
 	OBJECTS += RCZ80_duart.rom RCZ80_duart.com
 	OBJECTS += RCZ80_std.rom RCZ80_std.com
+	OBJECTS += RCZ80_zrc.rom RCZ80_zrc.com
 	OBJECTS += SBC_simh.rom SBC_simh.com
 	OBJECTS += SBC_std.rom SBC_std.com
 	OBJECTS += SCZ180_126.rom SCZ180_126.com

Source/HBIOS/cfg_ezz80.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_master.asm

@@ -25,7 +25,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_NONE		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_NONE		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_mk4.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS

Source/HBIOS/cfg_n8.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_N8		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_N8		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS

Source/HBIOS/cfg_rcz180.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_rcz280.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_rcz80.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	1		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z2		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z2		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 MPGSEL_0	.EQU	$78		; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_1	.EQU	$79		; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)

Source/HBIOS/cfg_sbc.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;

Source/HBIOS/cfg_scz180.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	2		; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_115200_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_Z180		; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
+MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS

Source/HBIOS/cfg_zeta.asm

@@ -28,7 +28,7 @@ INTMODE		.EQU	0		; INTERRUPT MODE: 0=NONE, 1=MODE 1, 2=MODE 2
 DEFSERCFG	.EQU	SER_38400_8N1	; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
 ;
 RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
-MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180]: MEMORY MANAGER
+MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;

Source/HBIOS/hbios.asm

@@ -411,6 +411,20 @@ HBX_BNKSEL1:
 	OUT0	(Z180_BBR),A		; WRITE TO BANK BASE
 	RET				; DONE
 #ENDIF
+#IF (MEMMGR == MM_Z280)
+	; TBD
+	RET				; DONE
+#ENDIF
+#IF (MEMMGR == MM_ZRC)
+	BIT	7,A			; BIT 7 SET REQUESTS RAM PAGE
+	JR	Z,HBX_ROM		; NOT SET, SELECT ROM PAGE
+	RES	7,A			; RAM PAGE REQUESTED: CLEAR ROM BIT
+	ADD	A,$10			; ADD 16 x 32K - RAM STARTS FROM 512K
+;
+HBX_ROM:
+	OUT	($1F),A			; HCS WRITE TO THE BANK CONTROL REGISTER
+	RET				; DONE
+#ENDIF
 ;
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ; Copy Data - Possibly between banks.  This resembles CP/M 3, but

Source/HBIOS/std.asm

@@ -80,6 +80,8 @@ MM_SBC		.EQU	1		; ORIGINAL N8VEM/RBC Z80 SBC BANKED MEMORY
 MM_Z2		.EQU	2		; 16K X 4 BANKED MEMORY INTRODUCED ON ZETA2
 MM_N8		.EQU	3		; Z180 CUSTOMIZED FOR N8 MEMORY EXTENSIONS
 MM_Z180		.EQU	4		; Z180 NATIVE MEMORY MANAGER
+MM_Z280		.EQU	5		; Z280 NATIVE MEMORY MANAGER
+MM_ZRC		.EQU	6		; ZRC BANK SWITCHING
 ;
 ; BOOT STYLE
 ;

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.20"
+#DEFINE BIOSVER	"3.1.1-pre.21"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.20"
+	db	"3.1.1-pre.21"
 	endm