diff --git a/.gitignore b/.gitignore index 7ad6b419..2f933740 100644 --- a/.gitignore +++ b/.gitignore @@ -99,6 +99,7 @@ Tools/unix/zx/zx !Source/ZRC512/*.bin !Source/Z1RCC/*.bin !Source/ZZRCC/*.bin +!Source/FZ80/*.bin !Tools/cpm/** !Tools/unix/zx/* !Tools/zx/* diff --git a/Binary/Apps/Test/inttest.doc b/Binary/Apps/Test/inttest.doc new file mode 100644 index 00000000..686c140a --- /dev/null +++ b/Binary/Apps/Test/inttest.doc @@ -0,0 +1,44 @@ +INTTEST +======= + +RomWBW includes an API allowing applications to "hook" interrupts. +The `INTTEST` utility allows you to test this functionality. + + +** Syntax ** + +`INTTEST` + + +** Usage ** + +`INTTEST` is an interactive application. At startup, it will display +a list of the interrupt vector slots in your system along with the +current vector address for each of them. + +It then prompts you to enter the slot number (in hex) of a vector to +hook. After entering this, the application will watch the hooked +vector and countdown from 0xFF to 0x00 as interrupts are noted. + +When the counter reaches 0x00, the interrupt is unhooked and the +application terminates. The application can also be terminated by +pressing . + + +** Notes ** + +If your system is running without interrupts active, the application +will terminate immediately. + +All slots have vectors even if the corresponding interrupt is not +doing anything. In this case, the vector is pointing to the "bad +interrupt" handler. + +If you hook a vector that is not receiving any interrupts, the +down-counter will not do anything. + + +** Etymology* * + +The `INTTEST` command is an original product and the source code is +provided in the RomWBW distribution. diff --git a/Binary/ReadMe.txt b/Binary/ReadMe.txt index d25fa002..be0294ce 100644 --- a/Binary/ReadMe.txt +++ b/Binary/ReadMe.txt @@ -6,37 +6,37 @@ *** *** *********************************************************************** -This directory ("Binary") is part of the RomWBW System Software -distribution archive. It contains the completed binary outputs of -the build process. As described below, these files are used to +This directory ("Binary") is part of the RomWBW System Software +distribution archive. It contains the completed binary outputs of +the build process. As described below, these files are used to assemble a working RetroBrew Computers system. -The files in this directory are created by the build process that is -documented in the ReadMe.txt file in the Source directory. When -released the directory is populated with the default output files. -However, the output of custom builds will be placed in this directory +The files in this directory are created by the build process that is +documented in the ReadMe.txt file in the Source directory. When +released the directory is populated with the default output files. +However, the output of custom builds will be placed in this directory as well. -If you only see a few files in this directory, then you downloaded -just the source from GitHub. To retrieve the full release download -package, go to https://github.com/wwarthen/RomWBW. On this page, -look for the text "XX releases" where XX is a number. Click on this -text to go to the releases page. On this page, you will see the -latest releases listed. For each release, you will see a package -file called something like "RomWBW-2.9.0-Package.zip". Click on the +If you only see a few files in this directory, then you downloaded +just the source from GitHub. To retrieve the full release download +package, go to https://github.com/wwarthen/RomWBW. On this page, +look for the text "XX releases" where XX is a number. Click on this +text to go to the releases page. On this page, you will see the +latest releases listed. For each release, you will see a package +file called something like "RomWBW-2.9.0-Package.zip". Click on the package file for the release you want to download. ROM Firmware Images (_.rom) ------------------------------------- -The files with a ".rom" extension are binary images ready to program -into an appropriate PROM. These files are named with the format -_.rom. refers to the primary platform such as Zeta, -N8, Mark IV, etc. refers to the specific configuration. In -general, there will be a standard configuration ("std") for each -platform. So, for example, the file called MK4_std.rom is a ROM -image for the Mark IV with the standard configuration. If a custom -configuration called "custom" is created and built, a new file called +The files with a ".rom" extension are binary images ready to program +into an appropriate PROM. These files are named with the format +_.rom. refers to the primary platform such as Zeta, +N8, Mark IV, etc. refers to the specific configuration. In +general, there will be a standard configuration ("std") for each +platform. So, for example, the file called MK4_std.rom is a ROM +image for the Mark IV with the standard configuration. If a custom +configuration called "custom" is created and built, a new file called MK4_custom.rom will be added to this directory. Documentation of the pre-built ROM Images is contained in @@ -54,52 +54,52 @@ contents. Refer to the RomWBW User Guide for more information. ROM Executable Images (_.com) --------------------------------------- -When a ROM image (".rom") is created, an executable version of the -ROM is also created. These files have the same naming convention as -the ROM Image files, but have the extension ".com". These files can +When a ROM image (".rom") is created, an executable version of the +ROM is also created. These files have the same naming convention as +the ROM Image files, but have the extension ".com". These files can be copied to a working system and run like a normal CP/M application. -When run on the target system, they install in RAM just like they had +When run on the target system, they install in RAM just like they had been loaded from ROM. This allows a new ROM build to be tested without reprogramming the actual ROM. -WARNING: In a few cases the .com file is too big to load. If you get -a message like "Full" or "BAD LOAD" when trying to load one of the -.com files, it is too big. In these cases, you will not be able to +WARNING: In a few cases the .com file is too big to load. If you get +a message like "Full" or "BAD LOAD" when trying to load one of the +.com files, it is too big. In these cases, you will not be able to test the ROM prior to programming it. VDU ROM Image (vdu.rom) ----------------------- -The VDU video board requires a dedicated onboard ROM containing the -font data. The "vdu.rom" file contains the binary data to program +The VDU video board requires a dedicated onboard ROM containing the +font data. The "vdu.rom" file contains the binary data to program onto that chip. -Disk Images (fd_*.img, hd_*.img, psys.img) ------------------------------------------- +Disk Images (fd_*.img, hd_*.img) +-------------------------------- -RomWBW includes a mechanism for generating floppy disk and hard disk -binary images that are ready to copy directly to a floppy, hard disk, -CF Card, or SD Card which will then be ready for use in any +RomWBW includes a mechanism for generating floppy disk and hard disk +binary images that are ready to copy directly to a floppy, hard disk, +CF Card, or SD Card which will then be ready for use in any RomWBW-based system. -Essentially, these files contain prepared floppy and hard disk images -with a large set of programs and related files. By copying the -contents of these files to appropriate media as described below, you +Essentially, these files contain prepared floppy and hard disk images +with a large set of programs and related files. By copying the +contents of these files to appropriate media as described below, you can quickly create ready-to-use media. Win32DiskImager or RawWriteWin can be used to copy images directly to media. These programs are included in the RomWBW Tools directory. -The fd_*.img files are floppy disk images. They are sized for 1.44MB -floppy media and can be copied to actual floppy disks using -RawWriteWin (as long as you have access to a floppy drive on your -Windows computer). The resulting floppy disks will be usable on any +The fd_*.img files are floppy disk images. They are sized for 1.44MB +floppy media and can be copied to actual floppy disks using +RawWriteWin (as long as you have access to a floppy drive on your +Windows computer). The resulting floppy disks will be usable on any RomWBW-based system with floppy drive(s). -Likewise, the hd512_*.img and hd1k_*.img files are hard disk images. -Each file is intended to be copied to the start of any type of hard -disk media (typically a CF Card or SD Card). The resulting media will -be usable on any RomWBW-based system that accepts the corresponding +Likewise, the hd512_*.img and hd1k_*.img files are hard disk images. +Each file is intended to be copied to the start of any type of hard +disk media (typically a CF Card or SD Card). The resulting media will +be usable on any RomWBW-based system that accepts the corresponding media type. NOTE: The hd512_*.img files are equivalent to the hd_*.img @@ -109,34 +109,58 @@ maximum number of CP/M directory entries from 512 to 1024. Refer to the ReadMe.txt in the Source/Images directory for details. -Documentation of the pre-built disk images is contained in the +Documentation of the pre-built disk images is contained in the "RomWBW User Guide" found in the Doc directory. The contents of the disk images is contained in the "RomWBW Disk Catalog", but it is significantly out-of-date. -The contents of the floppy/hard disk images are created by -the BuildImages.cmd script in the Source directory. Additional -information on how to generate custom disk images is found in the +The contents of the floppy/hard disk images are created by +the BuildImages.cmd script in the Source directory. Additional +information on how to generate custom disk images is found in the Source\Images ReadMe.txt file. -The psys.img file contains a full implementation of the UCSD p-System -for the Z80 running under RomWBW. This image file must be placed on -disk media by itself (not appended or concatenated with hd*.img files. -Refer to the Source/pSys/ReadMe.txt file for more information on the +Disk Images (hd512_combo.img, hd1k_combo.img, *_std_hd1k_combo.img) +------------------------------------------------------------------- + +The hd512_combo.img and hd1k_combo.img file are the primary combo +disk image files suitable for most platforms. + +The *_std_hd1k_combo.img files are platform specific combo files +typically used in romless platforms, they also contain RomWBW binary code +that is loaded at boot time into RAM + +Disk Images (hd1k_prefix.dat, *_std_hd1k_prefix.dat) +---------------------------------------------------- + +The hd1k_prefix.dat file is part of the combo disk images and is +applied to hd1k image files as a prefix, it contains the standard +partion table. + +The *_std_hd1k_prefix.dat files are platform specific prefixes +typically used in romless platforms, they also contain RomWBW binary code +that is loaded at boot time into RAM + +Disk Images (psys.img) +---------------------- + +The psys.img file contains a full implementation of the UCSD p-System +for the Z80 running under RomWBW. This image file must be placed on +disk media by itself (not appended or concatenated with hd*.img files. +Refer to the Source/pSys/ReadMe.txt file for more information on the p-System implementation. Propeller ROM Images (*.eeprom) ------------------------------- -The files with and extension of ".eeprom" contain the binary images -to be programmed into the Propeller-based boards. The list below +The files with and extension of ".eeprom" contain the binary images +to be programmed into the Propeller-based boards. The list below indicates which file targets each of the Propeller board variants: ParPortProp ParPortProp.eeprom PropIO V1 PropIO.eeprom PropIO V2 PropIO2.eeprom -Refer to the board documentation of the boards for more information +Refer to the board documentation of the boards for more information on how to program the EEPROMs on these boards. Apps Directory @@ -144,4 +168,4 @@ Apps Directory The Apps subdirectory contains the executable application files that are specific to RomWBW. The source for these applications is found -in the Source\Apps directory of the distribution. \ No newline at end of file +in the Source\Apps directory of the distribution. diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index bc0a0084..d90d4e34 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -14,9 +14,29 @@ Version 3.5 - DDW: Added support for Duodyne Media board - WBW: Auto restore TMS video on user reset (CP/M warm boot) - L?B: Added support for NABU w/ RomWBW Option Board -- M?P: Reorganization of Doc directory introducing subfolders +- MAP: Reorganization of Doc directory introducing subfolders - WBW: Upgraded BBCBASIC to v5.00 - W?S: Updated FLASH utility to v1.3.9 +- WBW: Support RCBus PS/2 Keyboard (EP/Sally) +- M?R: Update Timer app to display output in decimal +- WBW: Preliminary support for S100 FPGA Z80 platform +- WBW: Added simple serial (SSER) driver +- WBW: Added preliminary support for S100 FPGA Z80 SD Cards +- M?R: Consolidated ROM Applications document into the Applications document +- M?R: Reviewed and substantially improved the Applications document +- WBW: Added support for DS1305 RTC on S100 FPGA Z80 +- WBW: Added support for Les Bird's RCBus Graphics/Sound/Joystick module +- WBW: Added support for Les Bird's Dual 16C550 UART module +- WBW: Refactor UART driver for more flexible configuration +- M?R: Added hour/minute/second display to timer app +- WBW: Substantial customization of NZ-COM disk image +- WBW: Refactor build post-processing (ZRC, ZZRCC, etc.) +- MAP: Improved section Real Time Clock in User Guide document +- WBW: Support for Hitachi HD44780-based LCD display +- DRJ: Added support for Genesis STD Bus Z180 platform +- MAP: Improved section Disk Management in User Guide document +- WBW: Add CPU speed selection for HEATH platform to HBIOS +- WBW: Add Warm/Cold reboot options to CPUSPD utility Version 3.4 ----------- @@ -685,4 +705,4 @@ interrupts disabled the BIOS will now start OK even if some vagrant hardware is asserting an interrupt (DISKIO). Seems like this is better anyway -- general idea is that we only enable interupts precisely when desired for very specific controled purposes since there is no -concept of interrupt dispatching available. \ No newline at end of file +concept of interrupt dispatching available. diff --git a/Doc/Contrib/AY-3-8910 Registers.xlsx b/Doc/Contrib/AY-3-8910 Registers.xlsx new file mode 100644 index 00000000..6fdc0b5e Binary files /dev/null and b/Doc/Contrib/AY-3-8910 Registers.xlsx differ diff --git a/Doc/Contrib/ZSystem.txt b/Doc/Contrib/ZSystem.txt index c4b99b0a..f5166ef9 100644 --- a/Doc/Contrib/ZSystem.txt +++ b/Doc/Contrib/ZSystem.txt @@ -20,7 +20,7 @@ Beyond the construction and integration of the actual DOS itself, the majority o The remainder of this document details the changes I made as I went along. In all cases, my goal was to keep the result as close to the original distribution as possible. I started by copying all of the files from the distribution (contained in zsdos2.zip) into Support\ZSDOS. From there I tested, modified, updated, and customized as documented below. Finally, I cherry picked files that made sense to include on the ZSystem ROM disks. -1. CLOCKS.DAT has been updated to include the RomWBW clock driver, HBCLK. I have also added the SIMHCLOK clock driver. +1. CLOCKS.DAT has been updated to include the RomWBW clock driver, WBWCLK. I have also added the SIMHCLOK clock driver. 2. STAMPS.DAT has been replaced with an updated version. The update was called STAMPS11.DAT and was found on the Walnut Creek CP/M CDROM. The original version has a bug that prevents RSX (resident system extension) mode to load properly. diff --git a/Doc/Hard Disk Anatomy.pdf b/Doc/Hard Disk Anatomy.pdf index a65a9912..d525eb68 100644 Binary files a/Doc/Hard Disk Anatomy.pdf and b/Doc/Hard Disk Anatomy.pdf differ diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index 5a314bdc..770540d5 100644 Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf index 9a3dd69b..c2107200 100644 Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ diff --git a/Doc/RomWBW Errata.pdf b/Doc/RomWBW Errata.pdf index f0d71fd3..04afa161 100644 Binary files a/Doc/RomWBW Errata.pdf and b/Doc/RomWBW Errata.pdf differ diff --git a/Doc/RomWBW ROM Applications.pdf b/Doc/RomWBW ROM Applications.pdf deleted file mode 100644 index 94e8b6fe..00000000 Binary files a/Doc/RomWBW ROM Applications.pdf and /dev/null differ diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf index 7ca987cd..f3282575 100644 Binary files a/Doc/RomWBW System Guide.pdf and b/Doc/RomWBW System Guide.pdf differ diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf index 3f5224c5..8235586b 100644 Binary files a/Doc/RomWBW User Guide.pdf and b/Doc/RomWBW User Guide.pdf differ diff --git a/Doc/Testing Notes.txt b/Doc/Testing Notes.txt deleted file mode 100644 index 9175409f..00000000 --- a/Doc/Testing Notes.txt +++ /dev/null @@ -1,144 +0,0 @@ -SIMH (X) ----- -- Test UART driver -- Test HDSK driver - -Zeta 1 (X) ------- -- Test UART driver -- Test PPP detection (startup w/ and w/o PPP) -- Test boot to CRT -- Test PPPSD driver -- Test PPPCON driver (video & kbd) -- Test FD driver -- Test FDU app - -Zeta 2 (X) ------- -- Test UART driver -- Test PPP detection (startup w/ and w/o PPP) -- Test boot to CRT -- Test PPPSD driver -- Test PPPCON driver (video & kbd) -- Test FD driver -- Test FDU app - -RCBus (X) ------- -- Test SIO driver (Serial Module) -- Test ACIA driver (Dual Serial Module) -- Test IDE driver (Compact Flash Module) -- Test PPIDE driver (IDE Module) -- Test FD driver (SMC and WDC) -- Test FDU app (SMC and WDC) - -N8-2312 (X) -------- -- Test ASCI driver -- Test SD driver (CSIO mode) -- Test FD driver -- Test FDU app -- Test TMS driver (video & kbd) - -N8-2511 (X) -------- -- Test ASCI driver -- Test SD driver (Juha mode) -- Test FD driver -- Test FDU app -- Test TMS driver (video & kbd) - -SBC (X) ---- -- Test UART driver -- Test PPIDE driver -- Test PPISD driver -- Test PRP detection -- Test boot to CRT console - -MK4 (X) ---- -- Test ASCI driver -- Test IDE driver -- Test SD driver -- Test PRP detection - -RAMF (X) ----- -- Test RAMF driver - -PRP (X) ---- -- Test PRPSD driver -- Test PRPCON driver (video & kbd) - -SCG (X) ---- -- Test TMS driver (video) - -VDU (X) ---- -- Test CVDU driver (video & kbd) - -CVDU (X) ----- -- Test CVDU driver (video & kbd) - -VGA (X) ---- -- Test VGA driver (video & kbd) - -DIO (X) ---- -- Test FD driver -- Test FDU app -- Test IDE driver - -DIO3 (X) ----- -- Test FD driver -- Test FDU app -- Test PPIDE driver - -DIDE (X) ----- -- Test FD driver -- Test FDU app -- Test IDE driver - -DSD (X) ---- -- Test SD driver - -4UART (X) ------ -- Test UART driver - - -UNA (X) ---- -- General Startup -- Boot from disk functionality -- Image loading -- Monitor -- XM app -- ASSIGN app -- MODE app -- SYSCOPY app -- OSLDR app -- FDU app -- FDISK80 app - -GENERAL (X) -------- -- Boot to ROM -- Boot to Disk -- Boot to Monitor -- XM app -- XM port auto-detect -- ASSIGN app -- MODE app -- SYSCOPY app -- FDU app -- FDISK80 app -- TUNE app diff --git a/ReadMe.md b/ReadMe.md index 7595af2c..e7b6a0b3 100644 --- a/ReadMe.md +++ b/ReadMe.md @@ -3,7 +3,7 @@ **RomWBW ReadMe** \ Version 3.5 \ Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \ -17 May 2024 +11 Sep 2024 # Overview @@ -124,8 +124,6 @@ Documentation for RomWBW includes: Guide](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20System%20Guide.pdf) - [RomWBW Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Applications.pdf) -- [RomWBW ROM - Applications](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20ROM%20Applications.pdf) - [RomWBW Errata](https://github.com/wwarthen/RomWBW/raw/master/Doc/RomWBW%20Errata.pdf) @@ -198,7 +196,10 @@ let me know if I missed you! Microsoft Fortran Compiler, and a Games compendium. - Martin R has provided substantial help reviewing and improving the - User Guide. + User Guide and Applications documents. + +- Mark Pruden has also contributed a great deal of content to the User + Guide. - Jacques Pelletier has contributed the DS1501 RTC driver code. diff --git a/ReadMe.txt b/ReadMe.txt index b784b4c0..1ec80567 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -1,6 +1,6 @@ RomWBW ReadMe Wayne Warthen (wwarthen@gmail.com) -17 May 2024 +11 Sep 2024 @@ -122,7 +122,6 @@ Documentation for RomWBW includes: - RomWBW User Guide - RomWBW System Guide - RomWBW Applications -- RomWBW ROM Applications - RomWBW Errata @@ -198,7 +197,10 @@ let me know if I missed you! BASIC Compiler, Microsoft Fortran Compiler, and a Games compendium. - Martin R has provided substantial help reviewing and improving the - User Guide. + User Guide and Applications documents. + +- Mark Pruden has also contributed a great deal of content to the User + Guide. - Jacques Pelletier has contributed the DS1501 RTC driver code. diff --git a/Source/Apps/Test/Build.cmd b/Source/Apps/Test/Build.cmd index e56d13b3..def4c1fc 100644 --- a/Source/Apps/Test/Build.cmd +++ b/Source/Apps/Test/Build.cmd @@ -25,6 +25,7 @@ pushd piomon && call Build || exit /b & popd pushd banktest && call Build || exit /b & popd pushd portscan && call Build || exit /b & popd pushd sound && call Build || exit /b & popd +pushd testh8p && call Build || exit /b & popd goto :eof diff --git a/Source/Apps/Test/Clean.cmd b/Source/Apps/Test/Clean.cmd index 4e81e284..733b934e 100644 --- a/Source/Apps/Test/Clean.cmd +++ b/Source/Apps/Test/Clean.cmd @@ -22,3 +22,4 @@ pushd piomon && call Clean || exit /b 1 & popd pushd banktest && call Clean || exit /b 1 & popd pushd portscan && call Clean || exit /b 1 & popd pushd sound && call Clean || exit /b 1 & popd +pushd testh8p && call Clean || exit /b 1 & popd diff --git a/Source/Apps/Test/Makefile b/Source/Apps/Test/Makefile index 7d70c01b..2eb38d98 100644 --- a/Source/Apps/Test/Makefile +++ b/Source/Apps/Test/Makefile @@ -1,5 +1,5 @@ OBJECTS = -SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info 2piotst piomon banktest portscan sound +SUBDIRS = DMAmon I2C inttest ppidetst ramtest tstdskng rzsz vdctest kbdtest ps2info 2piotst piomon banktest portscan sound testh8p DEST = ../../../Binary/Apps/Test TOOLS =../../../Tools diff --git a/Source/Apps/Test/inttest/Build.cmd b/Source/Apps/Test/inttest/Build.cmd index e26d9b73..0d05f824 100644 --- a/Source/Apps/Test/inttest/Build.cmd +++ b/Source/Apps/Test/inttest/Build.cmd @@ -8,4 +8,5 @@ set TASMTABS=%TOOLS%\tasm32 tasm -t180 -g3 -fFF inttest.asm inttest.com inttest.lst || exit /b copy /Y inttest.com ..\..\..\..\Binary\Apps\Test\ || exit /b +copy /Y inttest.doc ..\..\..\..\Binary\Apps\Test\ || exit /b diff --git a/Source/Apps/Test/inttest/Makefile b/Source/Apps/Test/inttest/Makefile index 04222fbd..25570390 100644 --- a/Source/Apps/Test/inttest/Makefile +++ b/Source/Apps/Test/inttest/Makefile @@ -1,5 +1,7 @@ OBJECTS = inttest.com +DOCS = inttest.doc DEST = ../../../../Binary/Apps/Test +DOCDEST = ../../../../Binary/Apps/Test TOOLS =../../../../Tools USETASM=1 diff --git a/Source/Apps/Test/inttest/inttest.doc b/Source/Apps/Test/inttest/inttest.doc new file mode 100644 index 00000000..686c140a --- /dev/null +++ b/Source/Apps/Test/inttest/inttest.doc @@ -0,0 +1,44 @@ +INTTEST +======= + +RomWBW includes an API allowing applications to "hook" interrupts. +The `INTTEST` utility allows you to test this functionality. + + +** Syntax ** + +`INTTEST` + + +** Usage ** + +`INTTEST` is an interactive application. At startup, it will display +a list of the interrupt vector slots in your system along with the +current vector address for each of them. + +It then prompts you to enter the slot number (in hex) of a vector to +hook. After entering this, the application will watch the hooked +vector and countdown from 0xFF to 0x00 as interrupts are noted. + +When the counter reaches 0x00, the interrupt is unhooked and the +application terminates. The application can also be terminated by +pressing . + + +** Notes ** + +If your system is running without interrupts active, the application +will terminate immediately. + +All slots have vectors even if the corresponding interrupt is not +doing anything. In this case, the vector is pointing to the "bad +interrupt" handler. + +If you hook a vector that is not receiving any interrupts, the +down-counter will not do anything. + + +** Etymology* * + +The `INTTEST` command is an original product and the source code is +provided in the RomWBW distribution. diff --git a/Source/Apps/Test/ps2info/ps2info.asm b/Source/Apps/Test/ps2info/ps2info.asm index 2acbf282..22a6ea7d 100644 --- a/Source/Apps/Test/ps2info/ps2info.asm +++ b/Source/Apps/Test/ps2info/ps2info.asm @@ -11,6 +11,7 @@ ; WBW 2022-04-01: Add menu for test functions ; WBW 2022-04-02: Fix prtchr register saving/recovery ; WBW 2023-10-19: Add support for Duodyne +; WBW 2024-06-10: Add support for RC2014 ; ;======================================================================= ; @@ -25,6 +26,10 @@ iodat_rph .equ $8C ; PS/2 controller data port address ; Duodyne: iocmd_duo .equ $4D ; PS/2 controller command port address iodat_duo .equ $4C ; PS/2 controller data port address +; RC2014 (EP/Sally) +iocmd_rc .equ $64 ; PS/2 controller command port address +iodat_rc .equ $60 ; PS/2 controller data port address + ; cpumhz .equ 8 ; for time delay calculations (not critical) ; @@ -87,6 +92,8 @@ setup1: jr z,setup_rph cp '3' ; Duodyne jr z,setup_duo + cp '4' ; RC2014 EP/Sally + jr z,setup_rc cp 'X' jr z,exit jr setup @@ -115,6 +122,14 @@ setup_duo: ld de,str_duo jr setup2 ; +setup_rc: + ld a,iocmd_rc + ld (iocmd),a + ld a,iodat_rc + ld (iodat),a + ld de,str_rc + jr setup2 +; setup2: call prtstr call crlf2 @@ -1437,16 +1452,18 @@ delay1: ; Constants ;======================================================================= ; -str_banner .db "PS/2 Keyboard/Mouse Information v0.8, 6-Nov-2023",0 +str_banner .db "PS/2 Keyboard/Mouse Information v0.9, 10-Jun-2024",0 str_hwmenu .db "PS/2 Controller Port Options:\r\n\r\n" .db " 1 - Nhyodyne\r\n" .db " 2 - Rhyophyre\r\n" .db " 3 - Duodyne\r\n" + .db " 4 - RC2014\r\n" .db " X - Exit Application\r\n" .db "\r\nSelection? ",0 str_mbc .db "Nhyodyne",0 str_rph .db "Rhyophyre",0 str_duo .db "Duodyne",0 +str_rc .db "RC2014 (Saly)",0 str_menu .db "PS/2 Testing Options:\r\n\r\n" .db " C - Test PS/2 Controller\r\n" .db " K - Test PS/2 Keyboard\r\n" diff --git a/Source/Apps/Test/testh8p/Build.cmd b/Source/Apps/Test/testh8p/Build.cmd new file mode 100644 index 00000000..d22386d9 --- /dev/null +++ b/Source/Apps/Test/testh8p/Build.cmd @@ -0,0 +1,10 @@ +@echo off +setlocal + +set TOOLS=../../../../Tools +set PATH=%TOOLS%\tasm32;%PATH% +set TASMTABS=%TOOLS%\tasm32 + +tasm -t80 -g3 -fFF testh8p.asm testh8p.com testh8p.lst || exit /b + +copy /Y testh8p.com ..\..\..\..\Binary\Apps\Test\ || exit /b diff --git a/Source/Apps/Test/testh8p/Clean.cmd b/Source/Apps/Test/testh8p/Clean.cmd new file mode 100644 index 00000000..9ecb428f --- /dev/null +++ b/Source/Apps/Test/testh8p/Clean.cmd @@ -0,0 +1,6 @@ +@echo off +setlocal + +if exist *.com del *.com +if exist *.lst del *.lst +if exist *.bin del *.bin diff --git a/Source/Apps/Test/testh8p/Makefile b/Source/Apps/Test/testh8p/Makefile new file mode 100644 index 00000000..d8e7dd1d --- /dev/null +++ b/Source/Apps/Test/testh8p/Makefile @@ -0,0 +1,9 @@ +OBJECTS = testh8p.com +# DOCS = testh8p.doc +DEST = ../../../../Binary/Apps/Test +DOCDEST = ../../../../Binary/Apps/Test +TOOLS =../../../../Tools + +USETASM=1 + +include $(TOOLS)/Makefile.inc \ No newline at end of file diff --git a/Source/Apps/Test/testh8p/testh8p.asm b/Source/Apps/Test/testh8p/testh8p.asm new file mode 100644 index 00000000..ada91ca3 --- /dev/null +++ b/Source/Apps/Test/testh8p/testh8p.asm @@ -0,0 +1,238 @@ +;=============================================================================== +; H8 Panel Test +;=============================================================================== +; +; AUTHOR: WAYNE WARTHEN (wwarthen@gmail.com) +;_______________________________________________________________________________ +; +; +; Trivial utility to test the register pair display functionality of the +; Heath H8 Front Panel. +; +; Program will display a set of known register values on the console, +; then go into an infinite loop. The H8 panel can then be checked to +; see if the correct values are displayed. +; +; There is no way to exit this program. You must reset your system. +; +;=============================================================================== +; Definitions +;=============================================================================== +; +stksiz .equ $40 ; Working stack size +; +restart .equ $0000 ; CP/M restart vector +bdos .equ $0005 ; BDOS invocation vector +; +regA .equ $11 +regBC .equ $2233 +regDE .equ $4455 +regHL .equ $6677 +; +;=============================================================================== +; Code Section +;=============================================================================== +; +; + .org $100 +; + ; setup stack (save old value) + ld (stksav),sp ; save stack + ld sp,stack ; set new stack +; + ld de,str_prefix + call prtstr +; + ld de,str_A + ld hl,regA + call prtreg + ld de,str_BC + ld hl,regBC + call prtreg + ld de,str_DE + ld hl,regDE + call prtreg + ld de,str_HL + ld hl,regHL + call prtreg + ld de,str_SP + ld hl,regSP + call prtreg + ld de,str_PC + ld hl,regPC + call prtreg +; + ld a,regA + ld bc,regBC + ld de,regDE + ld hl,regHL +regPC: jr $ +; +; +; +prtreg: + call prtstr ; print label + ld a,h ; first byte + call prtoctbyte ; print it + ld a,'.' ; separator + call prtchr ; print it + ld a,l ; second byte + call prtoctbyte ; print it + ret +; +; +; +prtoctbyte: + rlca ; 2 ms bits + rlca + push af + and %00000011 ; isolate + add a,'0' ; make char + call prtchr ; show it + pop af + rlca ; next 3 bits + rlca + rlca + push af + and %00000111 ; isolate + add a,'0' ; make char + call prtchr ; show it + pop af + rlca ; next 3 bits + rlca + rlca + push af + and %00000111 ; isolate + add a,'0' ; make char + call prtchr ; show it + pop af + ret +; +; Print character in A without destroying any registers +; +prtchr: + push bc ; save registers + push de + push hl + ld e,a ; character to print in E + ld c,$02 ; BDOS function to output a character + call bdos ; do it + pop hl ; restore registers + pop de + pop bc + ret +; +; Print a zero terminated string at (DE) without destroying any registers +; +prtstr: + push de +; +prtstr1: + ld a,(de) ; get next char + or a + jr z,prtstr2 + call prtchr + inc de + jr prtstr1 +; +prtstr2: + pop de ; restore registers + ret +; +; Start a new line +; +crlf2: + call crlf ; two of them +crlf: + push af ; preserve AF + ld a,13 ; + call prtchr ; print it + ld a,10 ; + call prtchr ; print it + pop af ; restore AF + ret +; +; Print the value in A in hex without destroying any registers +; +prthex: + push af ; save AF + push de ; save DE + call hexascii ; convert value in A to hex chars in DE + ld a,d ; get the high order hex char + call prtchr ; print it + ld a,e ; get the low order hex char + call prtchr ; print it + pop de ; restore DE + pop af ; restore AF + ret ; done +; +; print the hex word value in hl +; +prthexword: + push af + ld a,h + call prthex + ld a,l + call prthex + pop af + ret +; +; print the hex dword value in de:hl +; +prthex32: + push bc + push de + pop bc + call prthexword + push hl + pop bc + call prthexword + pop bc + ret +; +; Convert binary value in A to ascii hex characters in DE +; +hexascii: + ld d,a ; save A in D + call hexconv ; convert low nibble of A to hex + ld e,a ; save it in E + ld a,d ; get original value back + rlca ; rotate high order nibble to low bits + rlca + rlca + rlca + call hexconv ; convert nibble + ld d,a ; save it in D + ret ; done +; +; Convert low nibble of A to ascii hex +; +hexconv: + and $0F ; low nibble only + add a,$90 + daa + adc a,$40 + daa + ret +; +;=============================================================================== +; Storage Section +;=============================================================================== +; +rtcbuf .fill 6,$FF ; RTC data buffer +; +str_prefix .db "\r\n\r\nRegisters: ",0 +; +str_A .db "A=",0 +str_BC .db ", BC=",0 +str_DE .db ", DE=",0 +str_HL .db ", HL=",0 +str_SP .db ", SP=",0 +str_PC .db ", PC=",0 +; +stksav .dw 0 ; stack pointer saved at start + .fill stksiz,0 ; stack +stack .equ $ ; stack top +regSP: +; + .end diff --git a/Source/Apps/Tune/tune.asm b/Source/Apps/Tune/tune.asm index 8a9d1800..21acd6cb 100644 --- a/Source/Apps/Tune/tune.asm +++ b/Source/Apps/Tune/tune.asm @@ -49,6 +49,8 @@ ; 2024-02-23 [WBW] Include ACR value in config table ; 2024-04-16 [WBW] Add support for NABU AY-3-8910 ; 2024-05-10 [WBW] Hack to avoid corrupting bits 6&7 of PSG R7 for NABU! +; 2024-07-08 [WBW] Add support for Les Bird's Graphics, Sound, Joystick +; 2024-07-11 [WBW] Updated, Les Bird's module now uses same settings as EB6 ;_______________________________________________________________________________ ; ; ToDo: @@ -572,8 +574,8 @@ CFGSIZ .EQU $ - CFGTBL .DB $07, $D8, $D0, $D8, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (EB) .DW HWSTR_RCEB ; - .DB $07, $A0, $A1, $A2, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (EB Rev 6) - .DW HWSTR_RCEB6 + .DB $07, $A0, $A1, $A2, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (MSX) + .DW HWSTR_RCMSX ; .DB $07, $D1, $D0, $D0, $FF, $FF, $FF ; RCZ80 W/ RC SOUND MODULE (MF) .DW HWSTR_RCMF @@ -584,8 +586,8 @@ CFGSIZ .EQU $ - CFGTBL .DB $08, $68, $60, $68, $C0, $FF, $FF ; RCZ180 W/ RC SOUND MODULE (EB) .DW HWSTR_RCEB ; - .DB $08, $A0, $A1, $A2, $C0, $FF, $FF ; RCZ180 W/ RC SOUND MODULE (EB Rev 6) - .DW HWSTR_RCEB6 + .DB $08, $A0, $A1, $A2, $C0, $FF, $FF ; RCZ180 W/ RC SOUND MODULE (MSX) + .DW HWSTR_RCMSX ; .DB $08, $61, $60, $60, $C0, $FF, $FF ; RCZ180 W/ RC SOUND MODULE (MF) .DW HWSTR_RCMF @@ -596,8 +598,8 @@ CFGSIZ .EQU $ - CFGTBL .DB $09, $D8, $D0, $D8, $FF, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (EB) .DW HWSTR_RCEB ; - .DB $09, $A0, $A1, $A2, $FF, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (EB Rev 6) - .DW HWSTR_RCEB6 + .DB $09, $A0, $A1, $A2, $FF, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (MSX) + .DW HWSTR_RCMSX ; .DB $09, $D1, $D0, $D0, $FF, $FF, $FF ; EZZ80 W/ RC SOUND MODULE (MF) .DW HWSTR_RCMF @@ -608,8 +610,8 @@ CFGSIZ .EQU $ - CFGTBL .DB $0A, $68, $60, $68, $C0, $FF, $FF ; SCZ180 W/ RC SOUND MODULE (EB) .DW HWSTR_RCEB ; - .DB $0A, $A0, $A1, $A2, $C0, $FF, $FF ; SCZ180 W/ RC SOUND MODULE (EB Rev 6) - .DW HWSTR_RCEB6 + .DB $0A, $A0, $A1, $A2, $C0, $FF, $FF ; SCZ180 W/ RC SOUND MODULE (MS6) + .DW HWSTR_RCMSX ; .DB $0A, $61, $60, $60, $C0, $FF, $FF ; SCZ180 W/ RC SOUND MODULE (MF) .DW HWSTR_RCMF @@ -620,8 +622,8 @@ CFGSIZ .EQU $ - CFGTBL .DB $0B, $D8, $D0, $D8, $FF, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB) .DW HWSTR_RCEB ; - .DB $0B, $A0, $A1, $A2, $FF, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (EB Rev 6) - .DW HWSTR_RCEB6 + .DB $0B, $A0, $A1, $A2, $FF, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (MSX) + .DW HWSTR_RCMSX ; .DB $0B, $D1, $D0, $D0, $FF, $FF, $FF ; RCZ280 W/ RC SOUND MODULE (MF) .DW HWSTR_RCMF @@ -666,7 +668,7 @@ TMP .DB 0 ; work around use of undocumented Z80 HBIOSMD .DB 0 ; NON-ZERO IF USING HBIOS SOUND DRIVER, ZERO OTHERWISE OCTAVEADJ .DB 0 ; AMOUNT TO ADJUST OCTAVE UP OR DOWN -MSGBAN .DB "Tune Player for RomWBW v3.8, 10-May-2024",0 +MSGBAN .DB "Tune Player for RomWBW v3.10, 11-Jul-2024",0 MSGUSE .DB "Copyright (C) 2024, Wayne Warthen, GNU GPL v3",13,10 .DB "PTxPlayer Copyright (C) 2004-2007 S.V.Bulba",13,10 .DB "MYMPlay by Marq/Lieves!Tuore",13,10,13,10 @@ -687,7 +689,7 @@ MSGERR .DB "App Error", 0 HWSTR_SCG .DB "SCG ECB Board",0 HWSTR_N8 .DB "N8 Onboard Sound",0 HWSTR_RCEB .DB "RCBus Sound Module (EB)",0 -HWSTR_RCEB6 .DB "RCBus Sound Module (EBv6)",0 +HWSTR_RCMSX .DB "RCBus Sound Module (MSX)",0 HWSTR_RCMF .DB "RCBus Sound Module (MF)",0 HWSTR_LINC .DB "Z50 LiNC Sound Module",0 HWSTR_MBC .DB "NHYODYNE Sound Module",0 diff --git a/Source/Apps/cpuspd/cpuspd.asm b/Source/Apps/cpuspd/cpuspd.asm index 86f63e0a..4fef256c 100644 --- a/Source/Apps/cpuspd/cpuspd.asm +++ b/Source/Apps/cpuspd/cpuspd.asm @@ -23,6 +23,12 @@ rtc_port .equ $70 ; RTC latch port adr restart .equ $0000 ; CP/M restart vector bdos .equ $0005 ; BDOS invocation vector ; +bf_sysreset .equ $F0 ; restart system +; +bf_sysres_int .equ $00 ; reset hbios internal +bf_sysres_warm .equ $01 ; warm start (restart boot loader) +bf_sysres_cold .equ $02 ; cold start +; ident .equ $FFFE ; loc of RomWBW HBIOS ident ptr ; ;======================================================================= @@ -113,6 +119,10 @@ main1: ; main2: ret z ; if end, nothing to do + cp 'W' ; warm boot? + jp z,wboot ; if so, do it + cp 'C' ; cold boot? + jp z,cboot ; if so, do it cp ',' ; no new speed? jr z,main2a ; go to wait states ; parse speed string (half, full, double) @@ -161,6 +171,9 @@ parse_spd: ld c,2 ; assume double speed cp 'D' ; check it jr z,parse_spd1 ; if equal, done + ld c,3 ; assume quad speed + cp 'Q' ; check it + jr z,parse_spd1 ; if equal, done or a ; clear CF ccf ; set CF to indicate error ret @@ -222,6 +235,9 @@ show_spd: ld de,str_dbl cp 2 jr z,show_spd1 + ld de,str_quad + cp 3 + jr z,show_spd1 jp err_invalid show_spd1: call prtstr @@ -267,6 +283,24 @@ usage: or $FF ret ; +; Handle Warm Boot +; +wboot: + ld de,str_warmboot ; message + call prtstr ; display it + ld b,bf_sysreset ; system restart + ld c,bf_sysres_warm ; warm start + call $fff0 ; call hbios +; +; Handle Cold Boot +; +cboot: + ld de,str_coldboot ; message + call prtstr ; display it + ld b,bf_sysreset ; system restart + ld c,bf_sysres_cold ; cold start + call $fff0 ; call hbios +; ; Error Handlers ; err_una: @@ -510,9 +544,6 @@ prtd3m2: call prtchr prtd3m3: ret - - - ; ; Get the next non-blank character from (HL). ; @@ -665,7 +696,7 @@ delay1: ; Constants ;======================================================================= ; -str_banner .db "RomWBW CPU Speed Selector v0.6, 29-Dec-2023",0 +str_banner .db "RomWBW CPU Speed Selector v1.0, 11-Sep-2024",0 str_spacer .db " ",0 str_oscspd .db " MHz Oscillator",0 str_cpuspd .db " CPU speed is ",0 @@ -674,8 +705,11 @@ str_mhz .db " MHz",0 str_slow .db " (Half)",0 str_full .db " (Full)",0 str_dbl .db " (Double)",0 +str_quad .db " (Quad)",0 str_memws .db " Memory Wait State(s)",0 str_iows .db " I/O Wait State(s)",0 +str_warmboot .db "\r\n\r\nWarm booting...",0 +str_coldboot .db "\r\n\r\nCold booting...",0 str_err_una .db " ERROR: UNA not supported by application",0 str_err_inv .db " ERROR: Invalid BIOS (signature missing)",0 str_err_ver .db " ERROR: Unexpected HBIOS version",0 @@ -684,8 +718,10 @@ str_err_not_sup .db " ERROR: Platform or configuration does not support CPU sp str_err_invalid .db " ERROR: Invalid configuration!",0 str_err_api .db " ERROR: HBIOS API error!",0 str_usage .db " Usage: CPUSPD ,,\r\n" + .db " CPUSPD (W)armBoot\r\n" + .db " CPUSPD (C)oldBoot\r\n" .db "\r\n" - .db " : \"Half\", \"Full\", or \"Double\"\r\n" + .db " : (H)alf | (F)ull | (D)ouble | (Q)uad\r\n" .db " : Memory wait states\r\n" .db " : I/O wait states\r\n" .db "\r\n" diff --git a/Source/Apps/rtc.asm b/Source/Apps/rtc.asm index c49157f5..7d456da7 100644 --- a/Source/Apps/rtc.asm +++ b/Source/Apps/rtc.asm @@ -33,6 +33,8 @@ ; ;[2023/07/07] v1.9 Support DUODYNE ; +;[2024/09/02] v1.10 Support Genesis STD Z180 +; ; Constants ; mask_data .EQU %10000000 ; RTC data line @@ -52,6 +54,7 @@ PORT_RCZ280 .EQU $C0 ; RTC port for RCZ280 PORT_MBC .EQU $70 ; RTC port for MBC PORT_RPH .EQU $84 ; RTC port for RHYOPHYRE PORT_DUO .EQU $94 ; RTC port for DUODYNE +PORT_STDZ180 .EQU $84 ; RTC Port for STD Bus Z180 board BDOS .EQU 5 ; BDOS invocation vector @@ -1143,7 +1146,13 @@ HINIT: CP 17 ; DUODYNE JP Z,RTC_INIT2 ; - ; Unknown platform + LD C,PORT_STDZ180 + LD DE,PLT_STDZ180 + CP 21 ; STD Z180 + JP Z,RTC_INIT2 +; + +; Unknown platform LD DE,PLTERR ; BIOS error message LD C,9 ; BDOS string display function CALL BDOS ; Do it @@ -1769,6 +1778,7 @@ PLT_RCZ280 .TEXT ", RCBus Z280 RTC Module Latch Port 0xC0\r\n$" PLT_MBC .TEXT ", MBC RTC Latch Port 0x70\r\n$" PLT_RPH .TEXT ", RHYOPHYRE RTC Latch Port 0x84\r\n$" PLT_DUO .TEXT ", DUODYNE RTC Latch Port 0x70\r\n$" +PLT_STDZ180 .TEXT ", STD Z180 RTC Module latch port 0x84\r\n$" ; ; Generic FOR-NEXT loop algorithm diff --git a/Source/Apps/timer.asm b/Source/Apps/timer.asm index 7c68a075..d9c2f895 100644 --- a/Source/Apps/timer.asm +++ b/Source/Apps/timer.asm @@ -1,9 +1,10 @@ ;=============================================================================== ; TIMER - Display system timer value -; +; Version 1.31 24-July-2024 ;=============================================================================== ; ; Author: Wayne Warthen (wwarthen@gmail.com) +; Updated: MartinR (July 2024) - A user of uppercase mnemonics ;_______________________________________________________________________________ ; ; Usage: @@ -14,520 +15,791 @@ ; ; Operation: ; Reads and displays system timer value. +; +; This code will only execute on a Z80 CPU (or derivitive) +; +; This source code assembles with TASM V3.2 under Windows-11 using the +; following command line: +; tasm -80 -g3 -l TIMER.ASM TIMER.COM +; ie: Z80 CPU; output format 'binary' named .COM (rather than .OBJ) +; and includes a symbol table as part of the listing file. ;_______________________________________________________________________________ ; ; Change Log: ; 2018-01-14 [WBW] Initial release ; 2018-01-17 [WBW] Add HBIOS check ; 2019-11-08 [WBW] Add seconds support +; 2024-06-30 [MR ] Display values in decimal rather than hexadecimal +; 2024-07-24 [MR ] Also display value in Hours-Mins-Secs format ;_______________________________________________________________________________ ; -; ToDo: +; Includes binary-to-decimal subroutine by Alwin Henseler +; Located at: https://www.msx.org/forum/development/msx-development/32-bit-long-ascii ;_______________________________________________________________________________ ; -#include "../ver.inc" +; Includes division subroutines from: https://wikiti.brandonw.net/ +;;_______________________________________________________________________________ +; +#include "../ver.inc" ; Used for building RomWBW +;#include "ver.inc" ; Used for testing purposes during code development ; ;=============================================================================== ; Definitions ;=============================================================================== ; -stksiz .equ $40 ; Working stack size +STKSIZ .EQU $40 ; Working stack size +; +RESTART .EQU $0000 ; CP/M restart vector +BDOS .EQU $0005 ; BDOS invocation vector ; -restart .equ $0000 ; CP/M restart vector -bdos .equ $0005 ; BDOS invocation vector +IDENT .EQU $FFFE ; loc of RomWBW HBIOS ident ptr ; -ident .equ $FFFE ; loc of RomWBW HBIOS ident ptr +BF_SYSVER .EQU $F1 ; BIOS: VER function +BF_SYSGET .EQU $F8 ; HBIOS: SYSGET function +BF_SYSSET .EQU $F9 ; HBIOS: SYSSET function +BF_SYSGETTIMER .EQU $D0 ; TIMER subfunction +BF_SYSSETTIMER .EQU $D0 ; TIMER subfunction +BF_SYSGETSECS .EQU $D1 ; SECONDS subfunction +BF_SYSSETSECS .EQU $D1 ; SECONDS subfunction ; -bf_sysver .equ $F1 ; BIOS: VER function -bf_sysget .equ $F8 ; HBIOS: SYSGET function -bf_sysset .equ $F9 ; HBIOS: SYSGET function -bf_sysgettimer .equ $D0 ; TIMER subfunction -bf_syssettimer .equ $D0 ; TIMER subfunction -bf_sysgetsecs .equ $D1 ; SECONDS subfunction -bf_syssetsecs .equ $D1 ; SECONDS subfunction +;ASCII Control Characters +LF .EQU 00AH ; Line Feed +CR .EQU 00DH ; Carriage Return ; ;=============================================================================== ; Code Section ;=============================================================================== ; - .org $100 + .ORG $100 ; ; setup stack (save old value) - ld (stksav),sp ; save stack - ld sp,stack ; set new stack + LD (STKSAV),SP ; save stack + LD SP,STACK ; set new stack ; ; initialization - call init ; initialize - jr nz,exit ; abort if init fails + CALL INIT ; initialize + JR NZ,EXIT ; abort if init fails ; ; process - call process ; do main processing - jr nz,exit ; abort on error + CALL PROCESS ; do main processing + JR NZ,EXIT ; abort on error ; -exit: ; clean up and return to command processor - call crlf ; formatting - ld sp,(stksav) ; restore stack - ;jp restart ; return to CP/M via restart - ret ; return to CP/M w/o restart +EXIT: ; clean up and return to command processor + CALL CRLF ; formatting + LD SP,(STKSAV) ; restore stack + ;JP RESTART ; return to CP/M via restart + RET ; return to CP/M w/o restart ; ; Initialization ; -init: - call crlf ; formatting - ld de,msgban ; point to version message part 1 - call prtstr ; print it +INIT: + CALL CRLF ; formatting + LD DE,MSGBAN ; point to version message part 1 + CALL PRTSTR ; print it ; - call idbio ; identify active BIOS - cp 1 ; check for HBIOS - jp nz,errbio ; handle BIOS error + CALL IDBIO ; identify active BIOS + CP 1 ; check for HBIOS + JP NZ,ERRBIO ; handle BIOS error ; - ld a,rmj << 4 | rmn ; expected HBIOS ver - cp d ; compare with result above - jp nz,errbio ; handle BIOS error + LD A,RMJ << 4 | RMN ; expected HBIOS ver + CP D ; compare with result above + JP NZ,ERRBIO ; handle BIOS error ; -initx +INITX: ; initialization complete - xor a ; signal success - ret ; return + XOR A ; signal success + RET ; return ; ; Process ; -process: +PROCESS: ; look for start of parms - ld hl,$81 ; point to start of parm area (past len byte) + LD HL,$81 ; point to start of parm area (past len byte) ; -process00: - call nonblank ; skip to next non-blank char - jp z,process0 ; no more parms, go to display +PROCESS00: + CALL NONBLANK ; skip to next non-blank char + JP Z,PROCESS0 ; no more parms, go to display ; ; check for option, introduced by a "/" - cp '/' ; start of options? - jp nz,usage ; yes, handle option - call option ; do option processing - ret nz ; done if non-zero return - jr process00 ; continue looking for options + CP '/' ; start of options? + JP NZ,USAGE ; yes, handle option + CALL OPTION ; do option processing + RET NZ ; done if non-zero return + JR PROCESS00 ; continue looking for options ; -process0: +PROCESS0: ; ; Test of API function to set seconds value - ;ld b,bf_sysset ; HBIOS SYSGET function - ;ld c,bf_syssetsecs ; SECONDS subfunction - ;ld de,0 ; set seconds value - ;ld hl,1000 ; ... to 1000 - ;rst 08 ; call HBIOS, DE:HL := seconds value + ;LD B,BF_SYSSET ; HBIOS SYSGET function + ;LD C,BF_SYSSETSECS ; SECONDS subfunction + ;LD DE,0 ; set seconds value + ;LD HL,1000 ; ... to 1000 + ;RST 08 ; call HBIOS, DE:HL := seconds value ; ; get and print seconds value - call crlf2 ; formatting -; -process1: - ld b,bf_sysget ; HBIOS SYSGET function - ld c,bf_sysgettimer ; TIMER subfunction - rst 08 ; call HBIOS, DE:HL := timer value - - ld a,(first) - or a - ld a,0 - ld (first),a - jr nz,process1a - - ; test for new value - ld a,(last) ; last LSB value to A - cp l ; compare to current LSB - jr z,process2 ; if equal, bypass display - -process1a: - ; save and print new value - ld a,l ; new LSB value to A - ld (last),a ; save as last value - call prtcr ; back to start of line - ;call nz,prthex32 ; display it - call prthex32 ; display it - ld de,strtick ; tag - call prtstr ; display it + CALL CRLF2 ; formatting +; +PROCESS1: + LD B,BF_SYSGET ; HBIOS SYSGET function + LD C,BF_SYSGETTIMER ; TIMER subfunction + RST 08 ; call HBIOS, DE:HL := timer value - ; get and print seconds value - ld b,bf_sysget ; HBIOS SYSGET function - ld c,bf_sysgetsecs ; SECONDS subfunction - rst 08 ; call HBIOS, DE:HL := seconds value - call prthex32 ; display it - ld a,'.' ; fraction separator - call prtchr ; print it - ld a,c ; get fractional component - call prthex ; print it - ld de,strsec ; tag - call prtstr ; display it -; -process2: - ld a,(cont) ; continuous display? - or a ; test for true/false - jr z,process3 ; if false, get out -; - ld c,6 ; BDOS: direct console I/O - ld e,$FF ; input char - call bdos ; call BDOS, A := char - or a ; test for zero - jr z,process1 ; loop until char pressed -; -process3: - xor a ; signal success - ret + LD A,(FIRST) + OR A + LD A,0 + LD (FIRST),A + JR NZ,PROCESS1A + + ; TEST FOR NEW VALUE + LD A,(LAST) ; last LSB value to A + CP L ; compare to current LSB + JP Z,PROCESS2 ; if equal, bypass display + +;******************************************************************************* +;******************************************************************************* + +; Formatting code added/amended to print values in decimal and Hours-Mins-Secs +; MartinR June & July-2024 + +PROCESS1A: +; Save and print new value + LD A,L ; new LSB value to A + LD (LAST),A ; save as last value + CALL PRTCR ; back to start of line + + CALL B2D32 ; Convert DE:HL into ASCII; Start of ASCII buffer returned in HL + EX DE,HL + CALL PRTSTR ; Display the value + + LD DE,STRTICK ; "Ticks" message + CALL PRTSTR ; Display it + +; Get and print seconds value in decimal + + LD B,BF_SYSGET ; HBIOS SYSGET function + LD C,BF_SYSGETSECS ; SECONDS subfunction + RST 08 ; Call HBIOS; DE:HL := seconds value; C := fractional part + + LD (SEC_MS),DE ; Store the most significant part of the 'seconds' value + LD (SEC_LS),HL ; And the less significant...... + LD A,C ; And also the fractional part + SLA A ; But double the 50Hz 'ticks' value to give 1/100ths of a second + LD (SEC_FR),A + + CALL B2D32 ; Convert DE:HL into ASCII; Start of ASCII buffer returned in HL + EX DE,HL + CALL PRTSTR ; Display the value + + CALL PRTDOT ; Print a '.' seperator + + LD A,(SEC_FR) ; Retrieve fractional part (1/100ths second) + CALL B2D8 ; Convert into ASCII - up to 3 digits. Umber of digits returned C + CALL PRT_LEAD0 ; Print a leading zero if there is exactly 1 character in the string + EX DE,HL ; Start of ASCII buffer returned in HL + CALL PRTSTR ; Display fractional part of the value + + LD DE,STRSEC ; "Seconds" message + CALL PRTSTR ; Display it + +; Now print the seconds value as HMS + + LD BC,(SEC_MS) ; Retrive the 'seconds' value into AC:IX + LD A,B + LD IX,(SEC_LS) + LD DE,3600 ; 3600 seconds in an hour + CALL DIV32BY16 ; AC:IX divided by DE; Answer in AC:IX; Remainder in HL + + PUSH HL ; Preserve the remainder on the stack + + LD D,A ; Shuffle registers around ready for conversion to ASCII + LD A,C ; AC:IX into DE:HL + LD E,A + PUSH IX + POP HL + + CALL B2D32 ; Convert DE:HL into ASCII; Start of ASCII buffer returned in HL + EX DE,HL + CALL PRTSTR ; Display the hours value + + CALL PRTCOLON ; Print a ':' seperator + + POP HL ; Retrive the remainder (seconds) + + LD C,60 ; 60 seconds in a minute + CALL DIV_HL_C ; HL divided by C; Answer in HL; Remainder in A + + PUSH AF ; Preserve the remainder (seconds) on the stack + + CALL B2D16 ; Convert HL into ASCII; Start of ASCII buffer returned in HL; Count in C + CALL PRT_LEAD0 ; Print a leading zero if there is exactly 1 character in the string + EX DE,HL + CALL PRTSTR ; Display the minutes value + + CALL PRTCOLON ; Print a ':' seperator + + POP AF ; Retrive the remainder (seconds) + + CALL B2D8 ; Convert A into ASCII; Start of ASCII buffer returned in HL; Count in C + CALL PRT_LEAD0 ; Print a leading zero if there is exactly 1 character in the string + EX DE,HL + CALL PRTSTR ; Display the seconds value + + CALL PRTDOT ; Print a '.' seperator + + LD A,(SEC_FR) ; Retrieve the fractional part (1/100ths) of the seconds + CALL B2D8 ; Convert A into ASCII; Start of ASCII buffer returned in HL + CALL PRT_LEAD0 ; Print a leading zero if there is exactly 1 character in the string + EX DE,HL + CALL PRTSTR ; Display the value + + LD DE,STRHMS ; Print "HH:MM:SS" message + CALL PRTSTR + +;******************************************************************************* +;******************************************************************************* + +PROCESS2: + LD A,(CONT) ; continuous display? + OR A ; test for true/false + JR Z,PROCESS3 ; if false, get out ; -; Handle special options + LD C,6 ; BDOS: direct console I/O + LD E,$FF ; input char + CALL BDOS ; call BDOS, A := char + OR A ; test for zero + JP Z,PROCESS1 ; loop until char pressed ; -option: +PROCESS3: + XOR A ; signal success + RET ; - inc hl ; next char - ld a,(hl) ; get it - or a ; zero terminator? - ret z ; done if so - cp ' ' ; blank? - ret z ; done if so - cp '?' ; is it a '?'? - jp z,usage ; yes, display usage - cp 'C' ; is it a 'C', continuous? - jp z,setcont ; yes, set continuous display - cp 'R' - jp z,reset ; reset timer - jp errprm ; anything else is an error +; Handle special options ; -usage: +OPTION: + INC HL ; next char + LD A,(HL) ; get it + OR A ; zero terminator? + RET Z ; done if so + CP ' ' ; blank? + RET Z ; done if so + CP '?' ; is it a '?'? + JP Z,USAGE ; yes, display usage + CP 'C' ; is it a 'C', continuous? + JP Z,SETCONT ; yes, set continuous display + JP ERRPRM ; anything else is an error ; - jp erruse ; display usage and get out +USAGE: + JP ERRUSE ; display usage and get out ; -setcont: +SETCONT: ; - or $FF ; set A to true - ld (cont),a ; and set continuous flag - jr option ; check for more option letters - -reset: - ; Test of API function to set seconds value - push bc - push hl - push de - push af - ld b,bf_sysset ; HBIOS SYSGET function - ld c,bf_syssettimer; SECONDS subfunction - ld de,0 ; set seconds value - ld hl,0 ; ... to 1000 - rst 08 ; call HBIOS, DE:HL := seconds value - - ld b,bf_sysset ; HBIOS SYSGET function - ld c,bf_syssetsecs ; SECONDS subfunction - ld de,0 ; set seconds value - ld hl,0 ; ... to 1000 - rst 08 ; call HBIOS, DE:HL := seconds value - - pop af - pop de - pop hl - pop bc - jr option + OR $FF ; SET A TO TRUE + LD (CONT),A ; AND SET CONTINUOUS FLAG + JR OPTION ; CHECK FOR MORE OPTION LETTERS ; ; Identify active BIOS. RomWBW HBIOS=1, UNA UBIOS=2, else 0 ; -idbio: +IDBIO: ; - ; Check for UNA (UBIOS) - ld a,($FFFD) ; fixed location of UNA API vector - cp $C3 ; jp instruction? - jr nz,idbio1 ; if not, not UNA - ld hl,($FFFE) ; get jp address - ld a,(hl) ; get byte at target address - cp $FD ; first byte of UNA push ix instruction - jr nz,idbio1 ; if not, not UNA - inc hl ; point to next byte - ld a,(hl) ; get next byte - cp $E5 ; second byte of UNA push ix instruction - jr nz,idbio1 ; if not, not UNA, check others + ; CHECK FOR UNA (UBIOS) + LD A,($FFFD) ; fixed location of UNA API vector + CP $C3 ; jp instruction? + JR NZ,IDBIO1 ; if not, not UNA + LD HL,($FFFE) ; get jp address + LD A,(HL) ; get byte at target address + CP $FD ; first byte of UNA push ix instruction + JR NZ,IDBIO1 ; if not, not UNA + INC HL ; point to next byte + LD A,(HL) ; get next byte + CP $E5 ; second byte of UNA push ix instruction + JR NZ,IDBIO1 ; if not, not UNA, check others ; - ld bc,$04FA ; UNA: get BIOS date and version - rst 08 ; DE := ver, HL := date + LD BC,$04FA ; UNA: get BIOS date and version + RST 08 ; DE := ver, HL := date ; - ld a,2 ; UNA BIOS id = 2 - ret ; and done + LD A,2 ; UNA BIOS id = 2 + RET ; and done ; -idbio1: +IDBIO1: ; Check for RomWBW (HBIOS) - ld hl,($FFFE) ; HL := HBIOS ident location - ld a,'W' ; First byte of ident - cp (hl) ; Compare - jr nz,idbio2 ; Not HBIOS - inc hl ; Next byte of ident - ld a,~'W' ; Second byte of ident - cp (hl) ; Compare - jr nz,idbio2 ; Not HBIOS -; - ld b,bf_sysver ; HBIOS: VER function - ld c,0 ; required reserved value - rst 08 ; DE := version, L := platform id + LD HL,($FFFE) ; HL := HBIOS ident location + LD A,'W' ; First byte of ident + CP (HL) ; Compare + JR NZ,IDBIO2 ; Not HBIOS + INC HL ; Next byte of ident + LD A,~'W' ; Second byte of ident + CP (HL) ; Compare + JR NZ,IDBIO2 ; Not HBIOS ; - ld a,1 ; HBIOS BIOS id = 1 - ret ; and done + LD B,BF_SYSVER ; HBIOS: VER function + LD C,0 ; required reserved value + RST 08 ; DE := version, L := platform id +; + LD A,1 ; HBIOS BIOS id = 1 + RET ; and done ; -idbio2: +IDBIO2: ; No idea what this is - xor a ; Setup return value of 0 - ret ; and done + XOR A ; Setup return value of 0 + RET ; and done ; ; Print character in A without destroying any registers ; -prtchr: - push bc ; save registers - push de - push hl - ld e,a ; character to print in E - ld c,$02 ; BDOS function to output a character - call bdos ; do it - pop hl ; restore registers - pop de - pop bc - ret +PRTCHR: + PUSH BC ; save registers + PUSH DE + PUSH HL + LD E,A ; character to print in E + LD C,$02 ; BDOS function to output a character + CALL BDOS ; do it + POP HL ; restore registers + POP DE + POP BC + RET ; -prtdot: +; Print a 0 if C=1 ; - ; shortcut to print a dot preserving all regs - push af ; save af - ld a,'.' ; load dot char - call prtchr ; print it - pop af ; restore af - ret ; done +PRT_LEAD0: + DEC C ; Decrement C, and a value of 1 becomee zero + RET NZ ; If C wasn't 1, then no leading space required + LD A,'0' ; Print the leading zero + JR Z,PRTCHR ; -prtcr: +PRTDOT: ; ; shortcut to print a dot preserving all regs - push af ; save af - ld a,13 ; load CR value - call prtchr ; print it - pop af ; restore af - ret ; done + PUSH AF ; save af + LD A,'.' ; load dot char + CALL PRTCHR ; print it + POP AF ; restore af + RET ; done +; +PRTCOLON: +; + ; shortcut to print a colon preserving all regs + PUSH AF ; save af + LD A,':' ; load colon char + CALL PRTCHR ; print it + POP AF ; restore af + RET ; done +; +PRTCR: +; + ; shortcut to print a CR preserving all regs + PUSH AF ; save af + LD A,13 ; load CR value + CALL PRTCHR ; print it + POP AF ; restore af + RET ; done ; ; Print a zero terminated string at (DE) without destroying any registers ; -prtstr: - push de +PRTSTR: + PUSH DE ; -prtstr1: - ld a,(de) ; get next char - or a - jr z,prtstr2 - call prtchr - inc de - jr prtstr1 +PRTSTR1: + LD A,(DE) ; get next char + OR A + JR Z,PRTSTR2 + CALL PRTCHR + INC DE + JR PRTSTR1 ; -prtstr2: - pop de ; restore registers - ret +PRTSTR2: + POP DE ; restore registers + RET ; ; Print the value in A in hex without destroying any registers ; -prthex: - push af ; save AF - push de ; save DE - call hexascii ; convert value in A to hex chars in DE - ld a,d ; get the high order hex char - call prtchr ; print it - ld a,e ; get the low order hex char - call prtchr ; print it - pop de ; restore DE - pop af ; restore AF - ret ; done +PRTHEX: + PUSH AF ; save AF + PUSH DE ; save DE + CALL HEXASCII ; convert value in A to hex chars in DE + LD A,D ; get the high order hex char + CALL PRTCHR ; print it + LD A,E ; get the low order hex char + CALL PRTCHR ; print it + POP DE ; restore DE + POP AF ; restore AF + RET ; done ; ; print the hex word value in bc ; -prthexword: - push af - ld a,b - call prthex - ld a,c - call prthex - pop af - ret +PRTHEXWORD: + PUSH AF + LD A,B + CALL PRTHEX + LD A,C + CALL PRTHEX + POP AF + RET ; ; print the hex dword value in de:hl ; -prthex32: - push bc - push de - pop bc - call prthexword - push hl - pop bc - call prthexword - pop bc - ret +PRTHEX32: + PUSH BC + PUSH DE + POP BC + CALL PRTHEXWORD + PUSH HL + POP BC + CALL PRTHEXWORD + POP BC + RET ; ; Convert binary value in A to ascii hex characters in DE ; -hexascii: - ld d,a ; save A in D - call hexconv ; convert low nibble of A to hex - ld e,a ; save it in E - ld a,d ; get original value back - rlca ; rotate high order nibble to low bits - rlca - rlca - rlca - call hexconv ; convert nibble - ld d,a ; save it in D - ret ; done +HEXASCII: + LD D,A ; save A in D + CALL HEXCONV ; convert low nibble of A to hex + LD E,A ; save it in E + LD A,D ; get original value back + RLCA ; rotate high order nibble to low bits + RLCA + RLCA + RLCA + CALL HEXCONV ; convert nibble + LD D,A ; save it in D + RET ; done ; ; Convert low nibble of A to ascii hex ; -hexconv: - and $0F ; low nibble only - add a,$90 - daa - adc a,$40 - daa - ret +HEXCONV: + AND $0F ; low nibble only + ADD A,$90 + DAA + ADC A,$40 + DAA + RET ; ; Print value of A or HL in decimal with leading zero suppression ; Use prtdecb for A or prtdecw for HL ; -prtdecb: - push hl - ld h,0 - ld l,a - call prtdecw ; print it - pop hl - ret -; -prtdecw: - push af - push bc - push de - push hl - call prtdec0 - pop hl - pop de - pop bc - pop af - ret -; -prtdec0: - ld e,'0' - ld bc,-10000 - call prtdec1 - ld bc,-1000 - call prtdec1 - ld bc,-100 - call prtdec1 - ld c,-10 - call prtdec1 - ld e,0 - ld c,-1 -prtdec1: - ld a,'0' - 1 -prtdec2: - inc a - add hl,bc - jr c,prtdec2 - sbc hl,bc - cp e - ret z - ld e,0 - call prtchr - ret +PRTDECB: + PUSH HL + LD H,0 + LD L,A + CALL PRTDECW ; print it + POP HL + RET +; +PRTDECW: + PUSH AF + PUSH BC + PUSH DE + PUSH HL + CALL PRTDEC0 + POP HL + POP DE + POP BC + POP AF + RET +; +PRTDEC0: + LD E,'0' + LD BC,-10000 + CALL PRTDEC1 + LD BC,-1000 + CALL PRTDEC1 + LD BC,-100 + CALL PRTDEC1 + LD C,-10 + CALL PRTDEC1 + LD E,0 + LD C,-1 +PRTDEC1: + LD A,'0' - 1 +PRTDEC2: + INC A + ADD HL,BC + JR C,PRTDEC2 + SBC HL,BC + CP E + RET Z + LD E,0 + CALL PRTCHR + RET ; ; Start a new line ; -crlf2: - call crlf ; two of them -crlf: - push af ; preserve AF - ld a,13 ; - call prtchr ; print it - ld a,10 ; - call prtchr ; print it - pop af ; restore AF - ret +CRLF2: + CALL CRLF ; two of them +CRLF: + PUSH AF ; preserve AF + LD A,CR + CALL PRTCHR ; print CR + LD A,LF + CALL PRTCHR ; print LF + POP AF ; restore AF + RET ; ; Get the next non-blank character from (HL). ; -nonblank: - ld a,(hl) ; load next character - or a ; string ends with a null - ret z ; if null, return pointing to null - cp ' ' ; check for blank - ret nz ; return if not blank - inc hl ; if blank, increment character pointer - jr nonblank ; and loop +NONBLANK: + LD A,(HL) ; load next character + OR A ; string ends with a null + RET Z ; if null, return pointing to null + CP ' ' ; check for blank + RET NZ ; return if not blank + INC HL ; if blank, increment character pointer + JR NONBLANK ; and loop ; ; Convert character in A to uppercase ; -ucase: - cp 'a' ; if below 'a' - ret c ; ... do nothing and return - cp 'z' + 1 ; if above 'z' - ret nc ; ... do nothing and return - res 5,a ; clear bit 5 to make lower case -> upper case - ret ; and return +UCASE: + CP 'a' ; if below 'a' + RET C ; ... do nothing and return + CP 'z' + 1 ; if above 'z' + RET NC ; ... do nothing and return + RES 5,A ; clear bit 5 to make lower case -> upper case + RET ; and return ; ; Add the value in A to HL (HL := HL + A) ; -addhl: - add a,l ; A := A + L - ld l,a ; Put result back in L - ret nc ; if no carry, we are done - inc h ; if carry, increment H - ret ; and return +ADDHL: + ADD A,L ; A := A + L + LD L,A ; Put result back in L + RET NC ; if no carry, we are done + INC H ; if carry, increment H + RET ; and return ; ; Jump indirect to address in HL ; -jphl: - jp (hl) +JPHL: + JP (HL) ; ; Errors ; -erruse: ; command usage error (syntax) - ld de,msguse - jr err +ERRUSE: ; command usage error (syntax) + LD DE,MSGUSE + JR ERR +; +ERRPRM: ; command parameter error (syntax) + LD DE,MSGPRM + JR ERR ; -errprm: ; command parameter error (syntax) - ld de,msgprm - jr err +ERRBIO: ; invalid BIOS or version + LD DE,MSGBIO + JR ERR ; -errbio: ; invalid BIOS or version - ld de,msgbio - jr err +ERR: ; print error string and return error signal + CALL CRLF2 ; print newline ; -err: ; print error string and return error signal - call crlf2 ; print newline +ERR1: ; without the leading crlf + CALL PRTSTR ; print error string ; -err1: ; without the leading crlf - call prtstr ; print error string +ERR2: ; without the string +; CALL CRLF ; print newline + OR $FF ; signal error + RET ; done ; -err2: ; without the string -; call crlf ; print newline - or $FF ; signal error - ret ; done ; ;=============================================================================== -; Storage Section +; Subroutine to print decimal numbers ;=============================================================================== ; -last .db 0 ; last LSB of timer value -cont .db 0 ; non-zero indicates continuous display -first .db $FF ; first pass flag (true at start) -; -stksav .dw 0 ; stack pointer saved at start - .fill stksiz,0 ; stack -stack .equ $ ; stack top -; -; Messages -; -msgban .db "TIMER v1.2, 10-Nov-2019",13,10 - .db "Copyright (C) 2019, Wayne Warthen, GNU GPL v3",0 -msguse .db "Usage: TIMER [/C] [/?]",13,10 - .db " ex. TIMER (display current timer value)",13,10 - .db " TIMER /? (display version and usage)",13,10 - .db " TIMER /C (display timer value continuously)",13,10 - .db " TIMER /R (reset timer values to 0)",0 -msgprm .db "Parameter error (TIMER /? for usage)",0 -msgbio .db "Incompatible BIOS or version, " - .db "HBIOS v", '0' + rmj, ".", '0' + rmn, " required",0 -strtick .db " Ticks, ",0 -strsec .db " Seconds",0 -; - .end +; Combined routine for conversion of different sized binary numbers into +; directly printable ASCII(Z)-string +; Input value in registers, number size and -related to that- registers to fill +; is selected by calling the correct entry: +; +; entry inputregister(s) decimal value 0 to: +; B2D8 A 255 (3 digits) +; B2D16 HL 65535 5 " +; B2D24 E:HL 16777215 8 " +; B2D32 DE:HL 4294967295 10 " +; B2D48 BC:DE:HL 281474976710655 15 " +; B2D64 IX:BC:DE:HL 18446744073709551615 20 " +; +; The resulting string is placed into a small buffer attached to this routine, +; this buffer needs no initialization and can be modified as desired. +; The number is aligned to the right, and leading 0's are replaced with spaces. +; On exit HL points to the first digit, (B)C = number of decimals +; This way any re-alignment / postprocessing is made easy. +; Changes: AF,BC,DE,HL,IX +; +; by Alwin Henseler +; https://msx.org/forum/topic/who-who/dutch-hardware-guy-pops-back-sort +; +; Found at: +; https://www.msx.org/forum/development/msx-development/32-bit-long-ascii +; +; Tweaked to assemble using TASM 3.2 by MartinR 23June2024 +; +B2D8: LD H,0 + LD L,A +B2D16: LD E,0 +B2D24: LD D,0 +B2D32: LD BC,0 +B2D48: LD IX,0 ; zero all non-used bits +B2D64: LD (B2DINV),HL + LD (B2DINV+2),DE + LD (B2DINV+4),BC + LD (B2DINV+6),IX ; place full 64-bit input value in buffer + LD HL,B2DBUF + LD DE,B2DBUF+1 + LD (HL),' ' +B2DFILC .EQU $-1 ; address of fill-character + LD BC,18 + LDIR ; fill 1st 19 bytes of buffer with spaces + LD (B2DEND-1),BC ; set BCD value to "0" & place terminating 0 + LD E,1 ; no. of bytes in BCD value + LD HL,B2DINV+8 ; (address MSB input)+1 + LD BC,00909H + XOR A +B2DSKP0:DEC B + JR Z,B2DSIZ ; all 0: continue with postprocessing + DEC HL + OR (HL) ; find first byte <>0 + JR Z,B2DSKP0 +B2DFND1:DEC C + RLA + JR NC,B2DFND1 ; determine no. of most significant 1-bit + RRA + LD D,A ; byte from binary input value +B2DLUS2:PUSH HL + PUSH BC +B2DLUS1:LD HL,B2DEND-1 ; address LSB of BCD value + LD B,E ; current length of BCD value in bytes + RL D ; highest bit from input value -> carry +B2DLUS0:LD A,(HL) + ADC A,A + DAA + LD (HL),A ; double 1 BCD byte from intermediate result + DEC HL + DJNZ B2DLUS0 ; and go on to double entire BCD value (+carry!) + JR NC,B2DNXT + INC E ; carry at MSB -> BCD value grew 1 byte larger + LD (HL),1 ; initialize new MSB of BCD value +B2DNXT: DEC C + JR NZ,B2DLUS1 ; repeat for remaining bits from 1 input byte + POP BC ; no. of remaining bytes in input value + LD C,8 ; reset bit-counter + POP HL ; pointer to byte from input value + DEC HL + LD D,(HL) ; get next group of 8 bits + DJNZ B2DLUS2 ; and repeat until last byte from input value +B2DSIZ: LD HL,B2DEND ; address of terminating 0 + LD C,E ; size of BCD value in bytes + OR A + SBC HL,BC ; calculate address of MSB BCD + LD D,H + LD E,L + SBC HL,BC + EX DE,HL ; HL=address BCD value, DE=start of decimal value + LD B,C ; no. of bytes BCD + SLA C ; no. of bytes decimal (possibly 1 too high) + LD A,'0' + RLD ; shift bits 4-7 of (HL) into bit 0-3 of A + CP '0' ; (HL) was > 9h? + JR NZ,B2DEXPH ; if yes, start with recording high digit + DEC C ; correct number of decimals + INC DE ; correct start address + JR B2DEXPL ; continue with converting low digit +B2DEXP: RLD ; shift high digit (HL) into low digit of A +B2DEXPH:LD (DE),A ; record resulting ASCII-code + INC DE +B2DEXPL:RLD + LD (DE),A + INC DE + INC HL ; next BCD-byte + DJNZ B2DEXP ; and go on to convert each BCD-byte into 2 ASCII + SBC HL,BC ; return with HL pointing to 1st decimal + RET + +B2DINV: .FILL 8 ; space for 64-bit input value (LSB first) +B2DBUF: .FILL 20 ; space for 20 decimal digits +B2DEND: .DB 000H ; space for terminating character + +;******************************************************************************* + +; The following routine divides AC:IX by DE and places the quotient +; in AC:IX and the remainder in HL + +; https://wikiti.brandonw.net/ + +; IN: ACIX=dividend, DE=divisor +; OUT: ACIX=quotient, DE=divisor, HL=remainder, B=0 + +DIV32BY16: + LD HL,0 + LD B,32 +DIV32BY16_LOOP: + ADD IX,IX + RL C + RLA + ADC HL,HL + JR C,DIV32BY16_OVERFLOW + SBC HL,DE + JR NC,DIV32BY16_SETBIT + ADD HL,DE + DJNZ DIV32BY16_LOOP + RET +DIV32BY16_OVERFLOW: + OR A + SBC HL,DE +DIV32BY16_SETBIT: + INC IX + DJNZ DIV32BY16_LOOP + RET + +;******************************************************************************* + +; The following routine divides HL by C and places the quotient in HL +; and the remainder in A + +; https://wikiti.brandonw.net/ + +DIV_HL_C: + XOR A + LD B, 16 + +LOOPDIV1: + ADD HL, HL + RLA + JR C, $+5 + CP C + JR C, $+4 + + SUB C + INC L + + DJNZ LOOPDIV1 + + RET + +;=============================================================================== +; Messages Section +;=============================================================================== + +MSGBAN .DB "TIMER v1.31, 24-Jul-2024",CR,LF + .DB "Copyright (C) 2019, Wayne Warthen, GNU GPL v3",CR,LF + .DB "Updated by MartinR 2024",0 +MSGUSE .DB "Usage: TIMER [/C] [/?]",CR,LF + .DB " ex. TIMER (display current timer value)",CR,LF + .DB " TIMER /? (display version and usage)",CR,LF + .DB " TIMER /C (display timer value continuously)",0 +MSGPRM .DB "Parameter error (TIMER /? for usage)",0 +MSGBIO .DB "Incompatible BIOS or version, " + .DB "HBIOS v", '0' + rmj, ".", '0' + rmn, " required",0 +STRTICK .DB " Ticks ",0 +STRSEC .DB " Seconds ",0 +STRHMS .DB " HH:MM:SS",0 + +;=============================================================================== +; Storage Section +;=============================================================================== + +SEC_MS .DW 0 ; Storage space to preserve the seconds value as +SEC_LS .DW 0 ; most and less significant parts +SEC_FR .DB 0 ; And the fractional part (1/100s of a second) + +LAST .DB 0 ; last LSB of timer value +CONT .DB 0 ; non-zero indicates continuous display +FIRST .DB $FF ; first pass flag (true at start) + +STKSAV .DW 0 ; stack pointer saved at start + .FILL STKSIZ,0 ; stack +STACK .EQU $ ; new stack top + + .END diff --git a/Source/Build.cmd b/Source/Build.cmd index dd462f12..ea5ca9f7 100644 --- a/Source/Build.cmd +++ b/Source/Build.cmd @@ -11,6 +11,7 @@ call BuildZRC || exit /b call BuildZ1RCC || exit /b call BuildZZRCC || exit /b call BuildZRC512 || exit /b +call BuildFZ80 || exit /b if "%1" == "dist" ( call Clean || exit /b diff --git a/Source/BuildFZ80.cmd b/Source/BuildFZ80.cmd new file mode 100644 index 00000000..1844e7cc --- /dev/null +++ b/Source/BuildFZ80.cmd @@ -0,0 +1,4 @@ +@echo off +setlocal + +pushd FZ80 && call Build || exit /b & popd diff --git a/Source/Doc/Applications.md b/Source/Doc/Applications.md index a972b53e..309e2a05 100644 --- a/Source/Doc/Applications.md +++ b/Source/Doc/Applications.md @@ -1,17 +1,873 @@ -$define{doc_title}{Applications}$ +$define{doc_title}{Applications Guide}$ +$define{doc_author}{MartinR \& Phillip Summers}$ +$define{doc_authmail}{}$ $include{"Book.h"}$ # Summary -RomWBW includes a small suite of custom applications to maximize the -features available. In general, these applications are operating -system agnostic -- they run under any of the included operating +RomWBW is supplied with a suite of software applications that enhance +the use of the system. Some of these applications have been written +entirely from scratch for RomWBW. Others are pre-existing software +that has been customized for the RomWBW environment. This document +serves as a reference for these RomWBW-specific applications. + +The primary usage documentation for RomWBW is the $doc_user$. It is assumed +that the reader is generally familiar with this document. + +RomWBW also includes many generic software applications that have not +been modified for RomWBW (e.g., MSBASIC). These generic applications +are not documented here. Please refer to the application specific +documentation for these generic applications. The documentation for +some of these generic applications is included in the Doc folder of +the RomWBW distribution. + +The applications described in this document fall into two general +categories. + +1. **ROM Applications** are software applications that are loaded + from the the ROM memory of your RomWBW system. + +2. **CP/M Applications** are software applications that are loaded + from disk using a previously loaded CP/M (or CP/M like) operating + system using its command line. + +Note that some applications are available in both forms. For example, +Microsoft BASIC is available as a ROM application and as an application +that runs under CP/M. Only the ROM variant is documented here because +the CP/M variant is not RomWBW-specific. + +You will see that two of the RomWBW operating systems are included +here as ROM Applications. Although operating systems are normally +loaded from disk, RomWBW does include a way to launch CP/M 2.2 and +Z-System directly from ROM. + +Most RomWBW systems include a ROM disk. A running operating system +can load applications from the ROM disk just like a floppy or hard +disk. Applications loaded from the ROM disk by CP/M are considered +to be CP/M applications, **not** ROM applications. + +`\clearpage`{=latex} + +# Boot Menu + +The system start-up process is described in some detail in the RomWBW +User Guide, and for the sake of completeness there is some overlap here. + +When a RomWBW system is started the user is presented with a sign-on +message at the default console detailing the RomWBW version and build +date. The system follows this with the list of hardware that it has +discovered, a list of devices and the system units assigned to them, +before finally inviting the to select a boot device with the prompt: + +``` +Boot [H=Help]: +``` + +At this point, the user may specify a unit, optionally with a slice, +to boot from. Note that it is not possible to boot from from the serial (ASCI) +or memory disk (MD) devices. + +Alternatively the user may select one of the built-in Boot Loader commands. +A menu of which may be displayed by pressing the H or ? keys (for Help). +Furthermore, a ROM application may also be started from this prompt. + +This start-up process is described in some detailed in the RomWBW User Guide, +and there is some overlap here. + +## Help + +After pressing H or ? at the boot prompt the user will be presented with +the following list of available commands: + +``` +L - List ROM Applications +D - Device Inventory +R - Reboot System +I [] - Set Console Interface/Baud code +V [] - View/Set HBIOS Diagnostic Verbosity +[.] - Boot Disk Unit/Slice +``` + +The function performed by each command is described below: + +L: + +: Lists the applications and operating systems that are built into the + RomWBW ROM - e.g., low-level monitor utility, CP/M, or BASIC. + + +D: + +: Displays the list of system devices that was first displayed when the + system was started. + + +R: + +: Will restart the system. Note that this does not reset hardware devices + in the same way that power-on or pressing the reset button would. + + +I: + +: Allows the user to select the interface connected to the console, and + optionally the Baud rate. This could be used to allow the system to be + operated from a second console. + +V: + +: Enables the display of invalid RomWBW HBIOS API calls. This option + is very unlikely to be used by a user and is used for development + purposes. + +And, finally, the system may be booted by specifying the unit number, +and optional slice, separated by a period('.'), of where the disk operating +system software is located - eg 2, 4.1, 5.3 + +Alternatively, a RomWBW ROM application may be started by pressing the appropriate +key from the applications menu, shown in the following section. + +## List ROM Applications + +If the user presses the L key at the Boot Loader prompt then the system will +display the list of ROM applications that are built into RomWBW. If a command +letter is known, then it may be entered directly at the prompt rather than +first displaying the menu. + +The ROM applications available from the boot prompt are: + +``` +M: Monitor +C: CP/M 2.2 +Z: Z-System +B: BASIC +T: Tasty BASIC +F: Forth +P: Play a Game +N: Network Boot +X: XModem Flash Updater +U: User App +``` + +Each of these will now be described in greater detail. + +# ROM Applications + +## Monitor + +The Monitor program is a low-level utility that can be used +for testing and programming. It allows programs to be entered, +memory to be examined and modified, and input/output devices to +be read or written to. + +It's key advantage is that is available at boot up. + +Its key disadvantages are that code cannot be entered in assembly +language and there is no ability to save to persistent storage (disks). + +The available memory area for programming is `0100h-EDFFh`. +The following areas are reserved: + +Memory Area | Function +------------|----------------------------------- +`0000-00FFh`| Jump and restart (RST) vectors +`EE00-FDFFh`| Monitor +`FE00-FFFFh`| HBIOS proxy + +The monitor uses a prompt in the format of `xx>` where xx is the +RomWBW bank id number. For example, the prompt may look like this +and means that Bank Id 0x8E is currently mapped into the low 32K +of processor memory. + +`8E>` + +Please refer to Section 4 of the $doc_sys# for a description of the +RomWBW Bank Id and how it relates to the physical bank of memory being +mapped to the lower 32K of the processor. The method of assigning +banks for specific RomWBW functions is also described. + +Commands can be entered at the command prompt. +Automatic case conversion takes place on command entry and all +numeric arguments are expected to be in hex format. + +The Monitor allows access to all memory locations but ROM and +Flash memory cannot be written to. At startup, the Monitor will +select the default "User" bank. The `S` command is provided to +allow selecting alternate banks. + +There now follows a more detailed guide to using the RomWBW +Monitor program: + +### Command Summary + +**`?`** - Will display a summary of the available commands. + +``` +Monitor Commands (all values in hex): +B - Boot system +D xxxx [yyyy] - Dump memory from xxxx to yyyy +F xxxx yyyy zz - Fill memory from xxxx to yyyy with zz +H - Halt system +I xxxx - Input from port xxxx +K - Keyboard echo +L - Load Intel hex data +M xxxx yyyy zzzz - Move memory block xxxx-yyyy to zzzz +O xxxx yy - Output value yy to port xxxx +P xxxx - Program RAM at address xxxx +R xxxx [[yy] [zzzz]] - Run code at address xxxx + Pass yy and zzzz to register A and BC +S xx - Set bank to xx +U - Set bank to previous bank +T xxxx - X-modem transfer to memory location xxxx +X - Exit monitor +``` + +### Cold Boot + +**`B`** - Performs a cold boot of the RomWBW system. A complete +re-initialization of the system is performed and the system +returns to the Boot Loader prompt. + +### Dump Memory + +**`D xxxx [yyyy]`** - Dump memory from hex location xxxx to yyyy +on the screen as lines of 16 hexadecimal bytes with their +ASCII equivalents (if within a set range, else a '.' is +printed). If the end address is omitted then 256 bytes are +displayed. + +A good tool to see where code is located, check +for version id, obtain details for chip configurations and +execution paths. + +Example: `D 100 1FF` + +``` +0100: 10 0B 01 5A 33 45 4E 56 01 00 00 2A 06 00 F9 11 ...Z3ENV...*..ù. +0110: DE 38 37 ED 52 4D 44 0B 6B 62 13 36 00 ED B0 21 Þ87íRMD.kb.6.í°! +0120: 7D 32 E5 21 80 00 4E 23 06 00 09 36 00 21 81 00 }2Ã¥!..N#...6.!.. +0130: E5 CD 6C 1F C1 C1 E5 2A C9 8C E5 CD 45 05 E5 CD Ã¥Ãl.ÃÃÃ¥*É.Ã¥ÃE.åà +0140: 59 1F C3 00 00 C3 AE 01 C3 51 04 C3 4C 02 C3 57 Y.Ã..î.ÃQ.ÃL.ÃW +0150: 02 C3 64 02 C3 75 02 C3 88 02 C3 B2 03 C3 0D 04 .Ãd.Ãu.Ã..ò.Ã.. +0160: C3 19 04 C3 22 04 C3 2A 04 C3 35 04 C3 40 04 C3 Ã..Ã".Ã*.Ã5.Ã@.à +0170: 48 04 C3 50 04 C3 50 04 C3 50 04 C3 8F 02 C3 93 H.ÃP.ÃP.ÃP.Ã..Ã. +0180: 02 C3 94 02 C3 95 02 C3 85 04 C3 C7 04 C3 D1 01 .Ã..Ã..Ã..ÃÇ.ÃÑ. +0190: C3 48 02 C3 E7 04 C3 56 03 C3 D0 01 C3 D0 01 C3 ÃH.Ãç.ÃV.ÃÃ.ÃÃ.à +01A0: D0 01 C3 D0 01 C3 D0 01 C3 D0 01 01 02 01 CD 6B Ã.ÃÃ.ÃÃ.ÃÃ....Ãk +01B0: 04 54 68 69 73 20 66 75 6E 63 74 69 6F 6E 20 6E .This function n +01C0: 6F 74 20 73 75 70 70 6F 72 74 65 64 2E 0D 0A 00 ot supported.... +01D0: C9 3E FF 32 3C 00 3A 5D 00 FE 20 28 14 D6 30 32 É>ÿ2<.:].þ (.Ö02 +01E0: AB 01 32 AD 01 3A 5E 00 FE 20 28 05 D6 30 32 AC «.2­.:^.þ (.Ö02¬ +01F0: 01 C5 01 F0 F8 CF E5 26 00 0E 0A CD 39 02 7D 3C .Ã….ðøÃÃ¥&...Ã9.}< +``` + +### Fill Memory + +**`F xxxx yyyy zz`** - Fill memory from hex xxxx to yyyy with +a single value of zz over the full range. The Dump command +can be used to confirm that the fill completed as expected. A +good way to zero out memory areas before writing machine data +for debug purposes. + +### Halt System + +**`H`** - Halt system. A Z80 HALT instruction is executed. The +system remains in the halt state until the system is +physically rebooted. Interrupts will not restart the +system. On systems that support a HALT status LED, the +LED will be illuminated. + +### Input from Port + +**`I xxxx`** - Input data from port xxxx and display to the screen. +This command is used to read values from hardware I/O ports +and display the contents in hexadecimal. + +### Keyboard Echo + +**`K`** - Echo any key-presses from the terminal. Press 'ESC' key +to quit. This facility provides that any key stroke sent to +the computer will be echoed back to the terminal. File down +loads will be echoed as well while this facility is ‘on’. + +### Load Hex + +**`L`** - Load a Intel Hex data via the terminal program. +The load address is defined in the hex file of the +assembled code. + +The terminal emulator program should be configured to +give a delay at the end of each line to allow the monitor +enough time to parse the line and move the data to memory. + +Keep in mind that this will be transient unless the +system supports battery backed memory. Saving to memory drive +is not supported. + +### Move Memory + +**`M xxxx yyyy zzzz`** - Move hex memory block xxxx to yyyy to +memory starting at hex location zzzz. Care should be taken +to insure that there is enough memory at the destination so +that code does not get over-written or memory wrapped around. + +### Output to Port + +**`O xxxx yy`** - Output data byte xx to port xxxx. This command is +used to send hexadecimal values to hardware I/O ports to +verify their operation and is the companion to the I operation. +Use clip leaded LEDs to confirm the data written. + +### Program Memory + +**`P xxxx`** - Program memory location xxxx. This routine will +allow you to program a hexadecimal value 'into memory starting +at location xxxx. Press 'Enter' on a blank line to +return to the Monitor prompt. + +The limitation around programming memory is that it must be +entered in hexadecimal. An alternative is to use the L command +to load a program that has been assembled to a hex file on the +remote computer. + +An excellent online resource for looking up opcodes for entry +can be found here: . + +### Run Program + +**`R xxxx [[yy] [zzzz]]`** - Run program at location xxxx. If optional +arguments yy and zzzz are entered they are loaded into the +A and BC register respectively. The return address of the +Monitor is saved on the stack so the program can return +to the monitor. On return to the monitor, the contents of +the A, HL, DE and BC registers are displayed. + +### Set Bank + +**`S xx`** - Set the physical memory bank to the RomWBW Bank Id +indicated by xx. Memory addresses +0x0000-0x7FFF (i.e. bottom 32k) are affected. Because the +interrupt vectors are stored in the bottom page of this +range, this function is disabled when interrupt mode 1 is +being used (IM1). Interrupt mode 2 is not affected as the +associated jump vectors are stored in high memory. + +Changing the bank also impacts the restart vectors (RST), +so executing code that calls the HBIOS using the `RST 08` +assembly code will not work. + +The monitor stack resides in high memory and is not affected +but any code that changes the stack to low memory will be +affected. + +The U command may be used to undo the change and return the +selected memory bank back to the previously selected one. + +Section 4 of the $doc_sys$ provides detail on how Bank Ids map to the +physical memory of the system and also how specific banks are utilized +by RomWBW. + +### Undo Bank + +**`U`** - Change the bank in memory back to the previously selected bank. +This command should be used in conjunction with the S command. + +### X-Modem Transfer + +**`T xxxx`** - Receive an X-modem file transfer and load it into +memory starting at location xxxx. + +128 byte blocks and checksum mode is the only supported +protocol. + +### Exit Monitor + +**`X`** - Exit the monitor program back to the main boot menu. + +## CP/M 2.2 + +This option will boot the CP/M 2.2 disk operating system +from an image contained within the ROM. Please refer to the +CPM User Manual in the Doc/CPM folder of the distribution for +CP/M usage. There are also many online resources. + +During the build process the system will create a ROM disk +containing a number of curated CP/M applications, and also a +RAM drive. The capacity of each will depend upon the size +of the ROM and RAM available to the system. A more complete +set of utilities are provided within the disk image files +provided as part of RomWBW. + +A number of the applications provided are generic to +CP/M, while others rely on particular hardware or +aspects of RomWBW itself. + +Those that are written specific to RomWBW include: ASSIGN, +CPUSPD, FDU, FORMAT, FLASH, FDISK80, MODE, RTC, SYSCOPY, +TALK, TIMER, and XM. + +The CP/M utilities supplied with RomWBW warrant more detailed descriptions, +and so are described in some detail in their own section +of this user guide. In summary they provide the initial capability +to manage and update your RomWBW system, to create other +bootable media (hardware dependent) and to write/debug +code using assembler and BASIC. + +## Z-System + +Z-System is a complete alternative, but entirely compatible, disk +operating system to CP/M. + +Z-System is comprised of ZSDOS 1.1 which is a +replacement for CP/M's Basic Disk Operating System (BDOS), and ZCPR which +is a replacement for the Console Command Processor (CCP). Either or both +may be used, although using both together will allow ZCPR to make use of +specific ZSDOS features. + +Documentation for Z-System may be found in the Doc/CPM folder of the +RomWBW distribution and the reader is referred to those. + +## BASIC + +For those who are not familiar with BASIC, it stands for Beginners All Purpose Symbolic +Instruction Code. + +RomWBW contains two versions of ROM BASIC, a full implementation and a "tiny" BASIC. + +The full implementation is a version of Microsoft BASIC from the NASCOM Computer. + +A comprehensive instruction manual is available in the Doc/Contrib directory. + +### RomWBW specific features + +- Sound +- Graphics +- Terminal Support + +### RomWBW unsupported features + +- Cassette loading +- Cassette saving + +## TastyBASIC + +TastyBASIC offers a minimal implementation of BASIC that is only 2304 +bytes in size. It originates from Li-Chen Wang's Palo Alto Tiny BASIC +from around 1976. It's small size is suited the tiny memory capacities of +the time. This implementation is by Dimitri Theulings and his original +source can be found at . + +### Features / Limitations + +- Integer arithmetic, numbers -32767 to 32767 +- Singles letter variables A-Z +- 1-dimensional array support +- Strings are not supported + +### Direct Commands + +- `LIST`,`RUN`, `NEW`, `CLEAR`, `BYE` + +### Statements + +- `LET`, `IF`, `GOTO`, `GOSUB RETURN`, `REM`, `FOR TO NEXT STEP`, `INPUT`, `PRINT`, `POKE`, `END` + +### Functions + +- `PEEK`, `RND`, `ABS`, `USR`, `SIZE` + +### Operators + +- `>=`, `#`, `>`, `=`, `<=`, `<` + +- Operator precedence is supported. + +Type ***BYE*** to return to the boot menu. + +## FORTH + +CamelForth is the version of Forth included as part of the boot ROM in +RomWBW. It has been converted from the Z80 CP/M version published at +. The +author is Brad Rodriguez who is a prolific Forth enthusiast, whose work +can be found here: . + +For those are who are not familiar with Forth, I recommend the +wikipedia article +and the Forth Interest Group website . + +### Important things to know + +Forth is case sensitive. + +To exit back to the boot loader type ***bye*** + +To get a list of available words type ***WORDS*** + +To reset Forth to its initial state type ***COLD*** + +Most of the code you find on the internet will not run unless modified or additional Forth +words are added to the dictionary. + +This implementation does not support loading or saving of programs. All programs +need to be typed in. Additionally, screen editing and code blocks are not supported. + +### Structure of Forth source files + +File | Description +--------------|----------------------------- +camel80.azm | Code Primitives + camel80d.azm | CPU Dependencies + camel80h.azm | High Level words + camel80r.azm | RomWBW additions +glosshi.txt | Glossary of high level words +glosslo.txt | Glossary of low level words +glossr.txt | Glossary of RomWBW additions + +### RomWBW Additions + +Extensions and changes to this implementation compared to the original distribution are: + +- The source code has been converted from Z80mr assembler to Hector Peraza's zsm. + +- An additional file camel80r.azm has been added for including additional words to + the dictionary at build time. However, as currently configured there is very little space + allocated for addition words. Exceeding the allocated ROM space will generate an error + message when building. + +- James Bowman's double precision words have been added from his RC2014 version: + . + +Word | Syntax | Description +--------|----------------------------|--------------------------------- +D+ | d1 d2 -- d1+d2 | Add double numbers +2>R | d -- | 2 to R +2R> | d -- | fetch 2 from R +M*/ | d1 n2 u3 -- d=(d1*n2)/u3 | double precision mult. div +SVC | hl de bc n -- hl de bc af | Execute a RomWBW function +P! | n p -- | Write a byte to a I/O port +P@ | p -- n | Read a byte from and I/O port + +## Play a Game + +### 2048 + +2048 is a puzzle game that can be both mindless and challenging. It +appears deceptively simple but failure can creep up on you suddenly. + +It requires an ANSI/VT-100 compatible colour terminal to play. + +2048 is like a sliding puzzle game except the puzzle tiles are +numbers instead of pictures. Instead of moving a single tile all +tiles are moved simultaneously in the same direction. Where two +tiles of the same number collide, they are reduced to one tile with +the combined value. After every move a new tile is added with +a starting value of 2. + +The goal is to create a tile of 2048 before all tile locations are +occupied. Reaching the highest points score, which is the sum of all +the tiles is a secondary goal. The game will automatically end when +there are no more possible moves. + +Play consists of entering a direction to move. Directions can be entered +using any of three different keyboard direction sets. + +``` +Direction | Keys +----------|---------- +Up | w ^E 8 +Down | s ^X 2 +Left | a ^S 4 +Right | d ^D 6 +``` + +The puzzle board is a 4x4 grid. At start, the grid will be populated +with two 2 tiles. An example game sequence is shown below with new +tiles to the game shown in brackets. + +``` +Start Move 1 - Up Move 2 - Left Move 3 - Left ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| | | |(2)| | | | | 4 | | 4 | | | | | 4 | | | | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| | | | | | | | | | | | | |(4)| | 4 | | | | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| | | |(2)| | | | | | | | | | | | | | | | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| | | | | | | |(2)| | | 2 | | | | | 2 | |(2)| | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ + +Move 4 - Left Move 5 - Up Move 6 - Right Move 7 - Up ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| 4 | | | | | 8 | | | 4 | | | | 8 | 4 | | | | 8 | 8 | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| 4 | | |(4)| | 4 | | | | | | | | 4 | | | | | 2 | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| | | | | | | | | | | | | | | | | | | | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +| 4 | | | | |(2)| | | | |(2)| | | 2 | |(2)| | | | ++---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +``` + +This is how I lost this game: + +``` ++---+---+---+---+ +| 4 | 2 | 16| 4 | ++---+---+---+---+ +| 32| 64| 8 | 2 | ++---+---+---+---+ +| 4 | 8 |128| 32| ++---+---+---+---+ +|(2)| 16| 8 | 4 | ++---+---+---+---+ +``` + +Press Q at any time to bring up the option to Quit or Restart the game. + +## Network Boot + +If your RomWBW system is equipped with an RCBus MT011 module, it is +possible to boot into CP/M 2.2 directly from a CP/NET network server. +This means that the operating system will be loaded directly from the +network server and all of your drive letters will be provided by the +network server. + +This function requires substantial knowledge of CP/NET and it's +implementation within RomWBW. Section 10 of the $doc_user$ provides +complete instructions for setting up a CP/NET based network under RomWBW +including a section on network booting. + +## Xmodem Flash Updater + +The RomWBW Xmodem flash updater provides the capability to update RomWBW from the boot loader using an x-modem file transfer. It offers similar capabilities to Will Sowerbutts FLASH4 utility except that the flashing process occurs during the file transfer. + +These are the key differences between the two methods are: + +Xmodem Flash Updater | FLASH.COM (aka FLASH4) +--------------------------------|----------------- +Available from the boot loader | Well proven and tested +Xmodem transfer is integrated | Wider range of supported chips and hardware +Integrated checksum utilities | Wider range of supported platforms +Capability to copy a ROM image | Only reprograms sectors that have changed +More convenient one step process | Ability save and verify ROM images +No intermediate storage required | Progress display while flashing +. | Displays chip identification information +. | Faster file transfer + +The major disadvantages of the Updater is that it is new and relatively untested. There is the risk that a failed transfer will result in a partially flashed and unbootable ROM. There are some limitations on serial transfer speeds. + +The updater utility was initially intended to support the Retrobrew SBC-V2-005 platform using Atmel 39SF040 flash chips but has now been extended to be more generic in operation. + +Supported flash chips are +39SF040, 29F040, AT49F040, AT29C040, M29F040 , MX29F040, A29010B, A29040B + +The Atmel 39SF040 chip is recommended as it can erase and write 4Kb sectors. Other chips require the whole chip to be erased. + +### Usage + +In most cases, completing a ROM update is a simple as: + +1. Booting to the boot loader prompt +2. Selecting option X - Xmodem Flash Updater +3. Selecting option U - Update +4. Initiating an X-modem transfer of your ROM image on your console device +5. Selecting option R - Reboot + +If your console device is not able to transfer a ROM image i.e. your console is a VDU then you will have to use the console options to identify which character-input/output device is to be used as the serial device for transfer. + +When your console is the serial device used for the transfer, no progress information is displayed as this would disrupt the x-modem file transfer. If you use an alternate character-input/output devices as the serial device for the transfer then progress information will be displayed on the console device. + +Due to different platform processor speeds, serials speeds and flow control capabilities the default console or serial device speed may need to be reduced for a successful transfer and flash to occur. The **Set Console Interface/Baud code** option at the Boot Loader can be used to change the speed if required. Additionally, the Updater has options to set to and revert from a recommended speed. + +See the RomWBW Applications guide for additional information on performing upgrades. + +### Console Options +Option ( C ) - Set Console Device + +Option ( S ) - Set Serial Device + +By default the updater assumes that the current console is a serial device and that the ROM file to be flashed will also be transferred across this device, so the Console and Serial device are both the same. + +Either device can be can be change to another character-input/output device but the updater will always expect to receive the x-modem transfer on the **Serial Device** + +The advantage of transferring on a different device to the console is that progress information can be displayed during the transfer. + +Option ( > ) - Set Recommended Baud Rate + +Option ( < ) - Revert to Original Baud Rate + +### Programming options + +Option ( U ) - Begin Update + +The will begin the update process. The updater will expect to start receiving +an x-modem file on the serial device unit. + +X-modem sends the file in packets of 128 bytes. The updater will cache 32 +packets which is 1 flash sector and then write that sector to the +flash device. + +If using separate console, bank and sector progress information will shown + +``` +BANK 00 s00 s01 s02 s03 s04 s05 s06 s06 s07 +BANK 01 s00 s01 s02 s03 s04 s05 s06 s06 s07 +BANK 02 s00 s01 s02 s03 s04 s05 s06 s06 s07 etc +``` + +The x-modem file transfer protocol does not provide any filename or size +information for the transfer so the updater does not perform any checks +on the file suitability. + +The updater expects the file size to be a multiple of 4 kilobytes and +will write all data received to the flash device. A system update +file (128kb .img) or complete ROM can be received and written (512kb or +1024kb .rom) + +If the update fails it is recommended that you retry before rebooting or +exiting to the Boot loader as your machine may not be bootable. + +Option ( D ) - Duplicate flash #1 to flash #2 + +This option will make a copy of flash #1 onto flash #2. The purpose of this is to enable + making a backup copy of the current flash. Intended for systems using 2x512Kb Flash devices. + +Option ( V ) - Toggle Write Verify + +By default each flash sector will be verified after being written. Slight +performance improvements can be gained if turned off and could be used if +you are experiencing reliable transfers and flashing. + +### Exit options + +Option ( R ) - Reboot + +Execute a cold reboot. This should be done after a successful update. If +you perform a cold reboot after a failed update then it is likely that +your system will be unusable and removing and reprogramming the flash +will be required. + +Option ( Q ) - Quit to boot loader. + +The SBC Boot Loader is reloaded from ROM and +executed. After a successful update a Reboot should be performed. However, +in the case of a failed update this option could be used to attempt to +load CP/M and perform the normal x-modem / flash process to recover. + +### CRC Utility options + +Option ( 1 ) and ( 2 ) - Calculate and display CRC32 of 1st or 2nd 512k ROM. +Option ( 3 ) - Calculate and display CRC32 of a 1024k (2x512Kb) ROM. + +Can be used to verify if a ROM image has been transferred and flashed correctly. Refer to the Tera Term section below for details on configuring the automatic display of a files CRC after it has been transferred. + +In Windows, right clicking on a file should also give you a context menu option CRC SHA which will allow you to select a CRC32 calculation to be done on the selected file. + +### Tera Term macro configuration + +Macros are a useful tool for automatic common tasks. There are a number of instances where using macros to facilitate the update process could be worthwhile if you are: + +* Following the RomWBW development builds. +* Doing lots of configuration changes. +* Doing development on RomWBW drivers + +Macros can be used to automate sending ROM updates or images and for my own purposed I have set up a separate macro for transferring each of the standard build ROM, my own custom configuration ROM and update ROM. + +An example macro file to send an *.upd file, using checksum mode and display the crc32 value of the transmitted file: + +``` +Xmodem send, checksum, display crc32 +xmodemsend '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.upd' 1 +crc32file crc '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.rom' +sprintf '0x%08x' crc +messagebox inputstr 'crc32' +``` + +### Serial speed guidelines + +As identified in the introduction, there are limitations on serial speed depending on processor speed and flow control settings. Listed below are some of the results identified during testing. + +Configuration | Processor Speed | Maximum Serial Speed +-----------------------|-----------------|--------------------- +UART no flow control | 2MHz | 9600 +UART no flow control | 4MHz | 19200 +UART no flow control | 5MHz | 19200 +UART no flow control | 8MHz | 38400 +UART no flow control | 10MHz | 38400 +USB-fifo 2MHz+ | | n/a +ASCI no flow control | 18.432MHz | 9600 +ASCI with flow control | 18.432MHz | 38400 + +The **Set Recommend Baud Rate** option in the Updater menu follows the following guidelines. + +Processor Speed | Baud Rate +----------------|---------- +1MHz | 4800 +2-3MHz | 9600 +4-7MHz | 19200 +8-20MHz | 38400 + +These can be customized in the updater.asm source code in the CLKTBL table if desired. +Feedback to the RomWBW developers on these guidelines would be appreciated. + +### Notes + +All testing was done with Tera Term x-modem, Forcing checksum mode using macros was found to give the most reliable transfer. +Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before being written. +An SBC V2-005 MegaFlash or Z80 MBC required for 1mb flash support. The Updater assumes both chips are same type +Failure handling has not been tested. +Timing broadly calibrated on a Z80 SBC-v2 +Unabios not supported + +## User Application + +RomWBW provides the facility for a user to build, include and execute their +own custom application directly from the applications menu at boot-up. All that's +needed is for the user to create their custom code ready for inclusion, +recognising that there are certain constraints in doing this. + +In order to build properly, the build process requires that the file +`usrrom.asm` be found in the /Source/HBIOS folder of the RomWBW tree. + +This source file needs to assemble using TASM and it must start at +(ORG) address 00100H as the RomWBW HBIOS reserves locations 00000H +to 000FFH for internal use. Further, the user application must assemble to +a maximum of `USR-SIZ` bytes. + +During execution, the user application may make use of HBIOS calls as necessary, +and at exit it should return to the RomWBW boot loader +using the HBIOS warm reset. Note that no disk operating system (eg CP/M) +functions will be available as no disk operating system will have been loaded. + +There is a sample `usrrom.asm` supplied in Source/HBIOS and it is recommended +that, at least initially, users create their own application based on this as +a template because it already creates the necessary variables, starts at +(ORG) 00100H, and ensures that the assembled file is padded to create a +file `USR-SIZ` in length. Equally, should the the user's application prove +too large for the space available then assembly will be terminated with an error. +Users should not remove this check from the templated code. + +If required, the user application may make use of the Z80 interrupt system +but if the user application wishes to rely on HBIOS functionality then it +must adhere to the HBIOS framework for managing interupts. Alternatively, +if the user appliction has no need for the HBIOS then it may use its own +custom code for handling interrupts. In that case, a hard reset, rather +than an HBIOS warm start, would be necessary to return control to RomWBW. + +`\clearpage`{=latex} + +# CP/M Applications - ROM-Based & Disk-Based + +There now follows a more detailed guide to using the small suite of custom +applications included with RomWBW. In general, these applications are +operating system agnostic -- they run under any of the included operating systems. However, they all require RomWBW -- they are not generic CP/M applications. Most of the applications are custom written for RomWBW. However, some are standard CP/M applications that have been adapted to run under -RomWBW (e.g., XModem). The applications are generally matched to the +RomWBW (e.g. XM/XModem). The applications are generally matched to the version of RomWBW they are distributed with. So, if you upgrade the version of RomWBW in your system ROM, you will want to copy the corresponding applications to any storage devices you are using. @@ -27,37 +883,81 @@ data on your disk media, so don't do this if you are saving any data on the media. Most of the applications are included as source code in the RomWBW -distribution and are built in the normal build process. The source -code is found in the Source\\Apps directory of the distribution. The -binary executable applications are found in the Binary\\Apps directory. - -The following table clarifies where each of the applications can be -found: - -| Application | ROM Disk | Boot Disks | Apps Dir | -| ----------- | -------- | ---------- | -------- | -| ASSIGN | Yes | Yes | Yes | -| SYSCOPY | Yes | Yes | Yes | -| MODE | Yes | Yes | Yes | -| FDU | Yes | Yes | Yes | -| FORMAT | Yes | Yes | Yes | -| XM | Yes | Yes | Yes | -| FLASH | Yes | Yes | Yes | -| FDISK80 | Yes | Yes | Yes | -| TALK | Yes | Yes | Yes | -| RTC | Yes | Yes | Yes | -| TIMER | Yes | Yes | Yes | -| CPUSPD | Yes | Yes | Yes | -| FAT | Yes | Yes | Yes | -| CLRDIR | Yes | Yes | Yes | -| INTTEST | No | Yes | Yes | -| TUNE | No | Yes | Yes | -| WDATE | No | Yes | Yes | -| HTALK | No | Yes | Yes | +distribution and are built during the normal build process. The source +code is found in the Source/Apps directory of the distribution. The +binary executable applications are found in the Binary/Apps directory. + +The table below clarifies where each of the applications may be +found. It is not an exhaustive list, with further applications existing +on both the ROM-based and disk-based versions of CP/M. All of the Applications +incuded within RomWBW may be found with in the Binary/Apps directory. + +| Application | ROM Disk | Boot Disks | +| ----------- | :------: | :--------: | +| ASSIGN | Yes | Yes | +| CLRDIR | Yes | Yes | +| CPUSPD | Yes | Yes | +| FAT | No | Yes | +| FDISK80 | Yes | Yes | +| FDU | Yes | Yes | +| FLASH | Yes | Yes | +| FORMAT | Yes | Yes | +| HTALK | Yes | Yes | +| MODE | Yes | Yes | +| RTC | Yes | Yes | +| SURVEY | Yes | Yes | +| SYSCOPY | Yes | Yes | +| TALK | Yes | Yes | +| TIMER | Yes | Yes | +| TUNE | No | Yes | +| VGMPLAY | No | Yes | +| WDATE | No | Yes | +| XM | Yes | Yes | + +All of the CP/M applications may be found in the RomWBW Binary/Apps directory +and a user may copy those they need to their own customised disk/slice. + +Independantly of whether the CP/M system was started from ROM or a boot disk, +such as a floppy disk or a slice on a CF or uSD memory card, applications +may be located on and executed from either the ROM-disk itself or from other media. +There are multiple disk images available for CP/M (eg floppy, legacy hard-disk and new +hard-disk formats) and they all contain essentially the same set of applications. + +There are particular advantages for each method of booting into CP/M. + +ROM-based CP/M: + +- A clean and reliable copy of CP/M with no possibility of corruption +- No additional hardware required +- Fast to boot +- Rolled forward with new releases of RomWBW + +Disk-based CP/M: + +- Greater capacity allows for a larger number of applications +- Allows for user-customisation of applications available +- Allows individual disks to be tailored to a particular purpose, eg word processor + +For systems starting CP/M from a disk created from an image file, there are a small number +of additional applications stored in the ```USER 2``` area of the disk. These applications +do not form part of CP/M, but rather are small utilities used for test purposes during develpment work. +They may, or may not, fuction correctly with any given hardware or software configuration. +Documentation for these untilities is very limited, though the source files maybe found +in the /Source folder. Note that these utiltites are not available when starting CP/M +from the ROM image or from a floppy disk. + +A number of the CP/M applications available are described in more detail in +the following sections, each with an indication as to whether that application +may be found on the ROM-disk, a boot-disk, or both. `\clearpage`{=latex} -# ASSIGN +## ASSIGN + +| ASSIGN | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| RomWBW includes a flexible mechanism for associating the operating system drive letters (A: - P:) to the physical devices in the system. @@ -65,7 +965,7 @@ Drive letter assignments can be changed on a running operating system without rebooting. The ASSIGN command facilitates this by allowing you to display, assign, reassign, or remove the drive letter assignments. -## Syntax +#### Syntax | `ASSIGN /?` | `ASSIGN /L` @@ -73,7 +973,7 @@ to display, assign, reassign, or remove the drive letter assignments. | `ASSIGN `*``*`=[`*``*`:[`*``*`]],...` | `ASSIGN `*``*`=`*``*`,...` -## Usage +#### Usage `ASSIGN /?` will display brief command usage and version information. @@ -110,7 +1010,7 @@ When the command runs it will echo the resultant assignments to the console to confirm its actions. It will also display the remaining space available in disk buffers. -## Notes +#### Notes If the `ASSIGN` command encounters any rule violations or errors, it will abort with an error and **none** of the drive assignments will be @@ -183,314 +1083,377 @@ vs. CP/M 3. If you utilize an RSX that modifies the BDOS version returned, you are likely to have serious problems. In this case, be sure to use `ASSIGN` prior to loading the RSX or after it is unloaded. -## Etymology +#### Etymology The `ASSIGN` command is an original product and the source code is provided in the RomWBW distribution. `\clearpage`{=latex} -# SYSCOPY +## CLRDIR -To make disk media bootable, you must write a system boot image onto -the system tracks of the of the media. The `SYSCOPY` allows you to -read or write the system boot image of disk media. +| CLRDIR | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -## Syntax +The `CLRDIR` command is used to initialise the directory area of a drive. -| `SYSCOPY `*``*`=`*``* +#### Syntax -*``* is the drive to receive the operating system image or -alternatively a filename to save the operating system image +| `CLRDIR `*``* -*``* is the drive containing an operating system image or -alternatively a filename containing the system image to be placed on -the destination +#### Usage -## Usage +`CLRDIR `*``* will initialise the directory area of the specified drive. The +drive may take any form - eg floppy disk, hard-disk, CF, uSD etc. -Both *``* and *``* can refer to either a drive letter or a -file. If a drive letter is specified, the system boot image will be -read or written to the system tracks of the drive. If a filename is -specified, the system boot image will be read or written to the -specified filename. +The use of FDISK80 to reserve space, or slices, for CP/M use as drives will not +initialise the directory areas of those slices. The resultant directory areas will +contain garbage left over from a previous use of the disk (or media) and using +them in this state with CP/M will very likely lead to failed or corrupted data +storage. Use `CLRDIR` to initialise the directory properly. -`SYSCOPY C:=ZSYS.SYS` will read a system boot image from the file -ZSYS.SYS and write it onto the system tracks of drive C:. +FDU will initialise the directory of a floppy disk as part of the formatting process +and so `CLRDIR` is unnecessary for a floppy disk. `CLRDIR` is, therefore, primarily used +with other types such as hard-disk, CF and uSD. -`SYSCOPY A:OS.SYS=C:` will capture the system boot image from the -system tracks of drive C: and store it in the file A:OS.SYS. +The `CLRDIR` command may also be used to effectively 'reformat' a used disk +by reinitialising its directory area and effectively making it blank again. -`SYSCOPY D:=C:` will copy the system tracks from drive C: onto the -system tracks of drive D:. +Use `CLRDIR` with caution as changes made to disks by `CLRDIR` cannot be undone. -## Notes +#### Notes -The RomWBW ROM disk contains files with the system boot image for -Z-System and CP/M 2.2. These files are called CPM.SYS and ZSYS.SYS -respectively. These files can be used as the source of a `SYSCOPY` -command to make a disk bootable with the corresponding operating -system. +If `CLRDIR` is used on disk containing data then the directory area will be +reinitialised and the data previously stored will be lost. -CP/M 3 uses a two phase boot process. To make a CP/M 3 drive bootable, -you need to put "CPMLDR.SYS" on the boot tracks of the disk and be -sure that the drive also contains the "CPM.SYS" file. The "CPMLDR.SYS" -file is not included on the ROM disk, but is found on the CP/M 3 disk -image. +`\clearpage`{=latex} -ZPM3 is similar to CP/M 3. You also put "CPMLDR.SYS" on the system -tracks of the drive to make it bootable. The ZPM3 operating system is -in the file called "CPM3.SYS" on the ZPM3 disk image. It may seem -confusing that ZPM3 is in the file called CPM3.SYS, but it is normal -for ZPM3. +## CPUSPD -For the purposes of booting an operating system, each disk slice is -considered its own operating system. Each slice can be made bootable -with its own system tracks. +| CPUSPD | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -`SYSCOPY` uses drive letters to specify where to read/write the system -boot images. However, at startup, the boot loaded will require you to -enter the actual disk device and slice to boot from. So, you need to -be careful to pay attention to the device and slice that is assigned -to a drive letter so you will know what to enter at the boot loader -prompt. By way of explanation, the boot loader does not know about -drive letters because the operating system is not loaded yet. +The `CPUSPD` application is used to change the running speed and wait +states of a RomWBW system. It can also be used to invoke a warm or +cold reboot of the system. -If you want to put a boot system image on a device and slice that is -not currently assigned to a drive letter, you will need to assign a -drive letter first. +The functionality is highly dependent on the capabilities of your system. -Not all disk formats include space for system tracks. Such disk -formats cannot contains a system boot image and, therefore, cannot be -made bootable. The best example of such disk formats are the ROM and -RAM disks. To maximize usable file space on these drives, they do not -have system tracks. Obviously, ROM operating system is supported by -choosing a ROM operating system at the boot loader prompt. Any attempt -to write a system boot image to disk media with no system tracks will -cause SYSCOPY to fail with an error message. +At present, all Z180 systems can change their CPU speed and their +wait states. SBC and MBC systems may be able to change their CPU +speed if the hardware supports it and it is enabled in the HBIOS +configuration. -The system boot images are paired with the ROM version in your system. -So, you must take care to update the system tracks of any bootable -disk when you upgrade your ROM firmware. +#### Syntax -The system boot images are **not** tied to specific hardware -configurations. System boot images and operating systems provided with -RomWBW will work with any supported RomWBW platform or hardware as -long as they are the same version as the RomWBW firmware. +| `CPUSPD [`*``*`[,[`*``*`][,[`*``*`]]]` +| `CPUSPD (W)armBoot` +| `CPUSPD (C)oldBoot` -## Etymology +*``* is one of (H)alf, (F)ull, (D)ouble, or (Q)uad. +*``* is a number specifying the desired memory wait states. +*``* is a number specifying the desired I/O wait states. -The `SYSCOPY` command is an original product and the source code is -provided in the RomWBW distribution. +#### Usage -`\clearpage`{=latex} +Entering `CPUSPD` with no parameters will display the current CPU speed +and wait state information of the running system. Wait state +information is not available for all systems. -# MODE +To modify the running speed of a system, you can specify the +`*``*` parameter. To modify either or both of the wait +states, you can enter the desired number. Either or both of the wait +state parameters may be omitted and the current wait state settings +will remain in effect. -The MODE command allows you to adjust the operating characteristics -such as baud rate, data bits, stop bits, and parity bits of serial -ports dynamically. +#### Notes -## Syntax +The ability to modify the running speed and wait states of a system +varies widely depending on the hardware capabilities and the HBIOS +configuration settings. -`MODE /?` -`MODE COM`*``*`: [`*``*`[,`*``*`[,`*``*`[,`*``*`]]]] [/P]` +Note that it is frequently impossible to tell if a system is capable +of dynamic speed changes. This function makes the changes blindly. +If an attempt is made to change the speed of a system +that is definitely incapable of doing so, then an error result is +returned. -`/?` displays command usage and version information +The `CPUSPD` command makes no attempt to ensure that the new CPU +speed will actually work on the current hardware. Setting a CPU +speed that exceeds the capabilities of the system will result in +unstable operation or a system stall. -*``* is the character device unit number +Some peripherals are dependent on the CPU speed. For example, the Z180 +ASCI baud rate and system timer are derived from the CPU speed. The +CPUSPD application will attempt to adjust these peripherals for +correct operation after modifying the CPU speed. However, in some +cases this may not be possible. The baud rate of ASCI ports have a +limited set of divisors. If there is no satisfactory divisor to +retain the existing baud rate under the new CPU speed, then the baud +rate of the ASCI port(s) will be affected. -*``* is numerical baudrate +#### Etymology -*``* is (N)one, (O)dd, (E)ven, (M)ark, or (S)pace +The `CPUSPD` application was custom written for RomWBW. All of the +hardware interface code is specific to RomWBW and the application will +not operate correctly on non-RomWBW systems. -*``* is number of data bits, typically 7 or 8 +The source code is provided in the RomWBW distribution. -*``* is number of stop bits, typically 1 or 2 +`\clearpage`{=latex} -`/P` prompts user prior to setting new configuration +## FAT -## Usage +| FAT | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -`MODE /?` will display basic command usage and version information. +The operating systems included with RomWBW do not have any native +ability to access MS-DOS FAT filesystems. The FAT application can be +used overcome this. It will allow you to transfer files between CP/M +and FAT filesystems (wildcards supported). It can also erase files, +format, and list directories of FAT filesystems. -`MODE` with no parameters will list all devices and their current -configuration. +#### Syntax -`MODE <`*n*`>` will display the current configuration of the specified -character device unit. +| `FAT DIR `*``* +| `FAT COPY `*` `* +| `FAT REN `*` `* +| `FAT DEL `*`[|]`* +| `FAT MD `*``* +| `FAT FORMAT `*``* -`MODE COM`*``*`: [`*``*`[,`*``*`[,`*``*`[,` -*``*`]]]] [/P]` requests that the specified configuration -be set on the character device unit. You can use commas with no values -to leave some values unchanged. As an example, `MODE COM0: 9600,,,2` -will setup character device unit 0 for 9600 baud and 2 stop bits while -leaving data bits and stop bits as is. +| *``* is a FAT path +| *``*, *``* are FAT or CP/M filenames +| *``*, *``* are FAT filenames +| *``* is a FAT filename +| *``* is a FAT directory name +| *``* is a RomWBW disk unit number -Appending `/P` in a command specifying a new configuration will cause -the terminal output to pause and wait for the user to press a key. -This allows the user to change the local terminal setup before -continuing. +| CP/M filespec: *``*`:FILENAME.EXT` (*``* is CP/M drive letter A-P) +| FAT filespec: *``*`:/DIR/FILENAME.EXT` (*``* is RomWBW disk unit #) -## Notes +#### Usage -Specified baud rate and line characteristics must be supported by the -serial unit. Any parameters not specified will remain unchanged. +The `FAT` application determines whether you are referring to a CP/M +filesystem or a FAT filesystem based on the way you specify the file +or path. If the file or path is prefixed with a number (n:), then it +is assumed this is a FAT filesystem reference and is referring to the +FAT filesystem on RomWBW disk unit 'n'. Otherwise, the file +specification is assumed to be a normal CP/M file specification. -Changes are not persisted and will revert to system defaults at next -system boot. +If you wanted to list the directory of the FAT filesystem on RomWBW +disk unit 2, you would use `FAT DIR 2:`. If you only wanted to see the +".TXT" files, you would use `FAT DIR 2:*.TXT`. -Not all character devices support all `MODE` options. Some devices -(notably ASCI devices) have limited baud rate divisors. An attempt to -set a baud rate that the device cannot support will fail with an error -message. +If you wanted to copy all of the files on CP/M drive B: to the FAT +filesystem on RomWBW disk unit 4, you would use the command `FAT COPY +B:*.* 4:` If you wanted to copy the files to the "FOO" directory, then +you would use `FAT COPY B:*.* 4:\FOO`. To copy files in the opposite +direction, you just reverse the parameters. -## Etymology +To rename the file "XXX.DAT" to "YYY.DAT" on a FAT filesystem, you +could use a command like "FAT REN 2:XXX.DAT 2:YYY.DAT". -The `MODE` command is an original product and the source code is -provided in the RomWBW distribution. +To delete a file "XXX.DAT" on a FAT filesystem in directory "FOO", you +would use a command like `FAT DEL 2:\FOO\XXX.DAT`. -`\clearpage`{=latex} +To make a directory called "FOO2" on a FAT filesystem, you would use a +command line `FAT MD 2:\FOO2`. -# FDU +To format the filesystem on a FAT partition, you would use a command +like `FAT FORMAT 2:`. Use this with caution because it will destroy +all data on any pre-existing FAT filesystem on disk unit 2. -The FDU application is a Floppy Disk Utility that provides functions -to format and test floppy disk media. +#### Notes -## Syntax +Partitioned or non-partitioned media is handled automatically. A +floppy drive is a good example of a non-partitioned FAT filesystem and +will be recognized. Larger media will typically have a partition +table which will be recognized by the application to find the FAT +filesystem. -`FDU` +Although RomWBW-style CP/M media does not know anything about +partition tables, it is entirely possible to have media that +has both CP/M and FAT file systems on it. This is accomplished +by creating a FAT filesystem on the media that starts on a track +beyond the last track used by CP/M. Each CP/M slice can occupy +up to 8MB. So, make sure to start your FAT partition beyond +(slice count) * 9MB. -## Usage +The application infers whether you are attempting to reference a FAT +or CP/M filesystem via the drive specifier (char before ':'). A +numeric drive character specifies the HBIOS disk unit number for FAT +access. An alpha (A-P) character indicates a CP/M file system access +targeting the specified drive letter. If there is no drive character +specified, the current CP/M filesystem and current CP/M drive is +assumed. For example: -This application has an interactive user interface. At startup, you -will be prompted to select the floppy interface hardware in your -system. Following this, you will see the main menu of the program with -many functions to manage floppy disk drives. +| `2:README.TXT` refers to FAT file "README.TXT" on disk unit #2 +| `C:README.TXT` refers to CP/M file "README.TXT" on CP/M drive C +| `README.TXT` refers to CP/M file "README.TXT" on the current CP/M drive -The primary documentation for this application is in a file called -"FDU.txt" in the Doc directory of the RomWBW distribution. Please -consult this file for usage information. +Files with SYS, HIDDEN, or R/O only attributes are not given any +special treatment. Such files are found and processed like any other +file. However, any attempt to write to a read-only file will fail and +the application will abort. -## Notes +It is not currently possible to reference CP/M user areas other than +the current user. To copy files to alternate user areas, you must +switch to the desired user number first or use an additional step to +copy the file to the desired user area. -This application interfaces directly to the floppy hardware in your -system. It does not use the RomWBW HBIOS. This means that even if your -system is not configured for floppy drives, you can still use `FDU` -to test your floppy drives and format floppy media. This also means it -is critical that you choose the correct hardware interface from the -initial selection when starting the application. +Accessing FAT filesystems on a floppy requires the use of RomWBW HBIOS +v2.9.1-pre.13 or greater. -## Etymology +Only the first 8 RomWBW disk units (0-7) can be referenced. -The `FDU` command is an original product and the source code is -provided in the RomWBW distribution. +Files written are not verified. -`\clearpage`{=latex} +Wildcard matching in FAT filesystems is a bit unusual as implemented by +FatFs. See FatFs documentation. -# FORMAT +#### Etymology -This application is just a placeholder for a future version that will -make it simpler to format media including floppy disks. +The `FAT` application is an original RomWBW work, but utilizes the +FsFat library for all of the FAT filesystem work. This application is +written in C and requires SDCC to compile. As such it is not part of +the RomWBW build process. However, the full project and source code is +found in the [FAT GitHub Repository](https://github.com/wwarthen/FAT). -## Syntax +#### Known Issues -`FORMAT` +CP/M (and workalike) OSes have significant restrictions on filename +characters. The FAT application will block any attempt to create a +file on the CP/M filesystem containing any of these prohibited +characters: -## Notes +| `< > . , ; : ? * [ ] |/ \` -This application currently just displays a few lines of information -briefly instructing a user how to format media. It performs no actual -function beyond this display currently. +The operation will be aborted with "`Error: Invalid Path Name`" if such +a filename character is encountered. -## Etymology +Since MS-DOS does allow some of these characters, you can have +issues when copying files from MS-DOS to CP/M if the MS-DOS filenames +use these characters. Unfortunately, FAT is not yet smart enough to +substitute illegal characters with legal ones. So, you will need to +clean the filenames before trying to copy them to CP/M. -The `FORMAT` command is an original product and the source code is -provided in the RomWBW distribution. +The FAT application does try to detect the scenario where you are +copying a file to itself. However, this detection is not perfect and +can corrupt a file if it occurs. Be careful to avoid this. `\clearpage`{=latex} -# XM +## FDISK80 -An adaptation of Ward Christensen's X-Modem protocol for transferring -files between systems using a serial port. +| FDISK80 | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -## Syntax +`FDISK80` allows you to create and manage traditional partitions on +your hard disk media. Depending on the hard disk format and features +you are using, RomWBW may need hard disk partitions defined. -| `XM S `*``* -| `XM SK `*``* -| `XM L `*` `* -| `XM LK `*` `* -| `XM R `*``* +Please refer to the $doc_user$ for more information on the use of +partitions within RomWBW. It is very important to understand that +RomWBW slices are completely different from disk partitions. -`S`: Send a file -`L`: Send a file from a library -`R`: Receive a file -`K`: Use 1K blocksize for transfer +This application is provided by John Coffman. The primary +documentation is in the file "FDisk Manual.pdf" found in the +Doc directory of the RomWBW distribution. -*``* is the name of a file to send or receive +#### Usage -*``* is the name of a library (.lbr) to extract a file to send +`FDISK80` is an interactive application. At startup it will ask you +for the disk unit that you want to partition. When your RomWBW system +boots, it will display a table with the disk unit numbers. Use the +disk unit numbers from that table to enter the desired disk unit to +partition. -## Usage +`FDISK80` operates very much like other FDISK disk partitioning +applications. Please refer to the file called "FDisk Manual.pdf" in +the Doc directory of the RomWBW distribution for further instructions. -To transfer a file from your host computer to your RomWBW computer, do -the following: +If 'slices' for CP/M have been created using `FDISK80`, then these will +need to have their directory areas initialised properly using `CLRDIR`. +Failure to do this will likely result in corrupted data. -1. Enter one of the `XM` receive commands specifying the name you want -to give to the received file. +There is also more information on using FAT partitions with RomWBW in +the $doc_user$ document in the Doc directory of the distribution. -2. On your host computer select a file to send and initiate the XModem -send operation. +#### Notes -To transfer a file from your RomWBW computer to your host computer, do -the following: +Hard disk partition tables allow a maximum of 1024 cylinders when +defining partitions. However, RomWBW uses exclusively Logical Block +Addressing (LBA) which does not have this limitation. When defining +partitions is usually best to define the start and size of of the +partition using bytes or sectors. -1. Enter one of the `XM` send commands specifying the name of the file -to be sent. +#### Etymology -2. On your host computer, specify the name to assign to the received -file and initiate and XModem receive operation. +The source for this application was provided directly by John Coffman. +It is a C program and requires a build environment that includes the +SDCC compiler. As such, it is not included in the RomWBW build +process, only the binary executable is included. -Please refer to the documentation of your host computer's terminal -emulation software for specific instructions on how to use XModem. +Please contact John Coffman if you would like a copy of the source. -## Notes +`\clearpage`{=latex} -The XModem adaptation that comes with RomWBW will automatically use -the primary character device unit (character device unit 0) for the -file transfer. +## FDU -`XM` attempts to determine the best way to drive the serial port based -on your hardware configuration. When possible, it will bypass the -HBIOS for faster operation. However, in many cases, it will use HBIOS -so that flow control can be used. +| FDU | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -`XM` is dependent on a reliable communications channel. You must -ensure that the serial port can be serviced fast enough by either -using a baud rate that is low enough or ensuring that hardware flow -control is fully functional (end to end). +The FDU application is a Floppy Disk Utility that provides functions +to format and test floppy disk media. -## Etymology +#### Syntax -The `XM` application provided in RomWBW is an adaptation of a -pre-existing XModem application. Based on the source code comments, it -was originally adapted from Ward Christensen's MODEM2 by Keith -Petersen and is labelled version 12.5. +`FDU` -The original source of the application was found in the Walnut Creek -CD-ROM and is called XMDM125.ARK dated 7/15/86. +#### Usage + +This application has an interactive user interface. At startup, you +will be prompted to select the floppy interface hardware in your +system. Following this, you will see the main menu of the program with +many functions to manage floppy disk drives. + +The primary documentation for this application is in a file called +"FDU.txt" in the Doc directory of the RomWBW distribution. Please +consult this file for usage information. + +#### Notes + +This application interfaces directly to the floppy hardware in your +system. It does not use the RomWBW HBIOS. This means that even if your +system is not configured for floppy drives, you can still use `FDU` +to test your floppy drives and format floppy media. This also means it +is critical that you choose the correct hardware interface from the +initial selection when starting the application. -The actual application is virtually untouched in the RomWBW -adaptation. The majority of the work was in the modem driver which was -enhanced to detect the hardware being used and dynamically choose the -appropriate driver. +#### Etymology -The source code is provided in the RomWBW distribution. +The `FDU` command is an original product and the source code is +provided in the RomWBW distribution. `\clearpage`{=latex} -# FLASH +## FLASH + +| FLASH | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| Most of the hardware platforms that run RomWBW support the use of EEPROMs -- Electronically Erasable Programmable ROMs. The `FLASH` @@ -500,7 +1463,7 @@ removing the ROM from your system. This application is provided by Will Sowerbutts. -## Syntax +#### Syntax | `FLASH READ `*``*` [options]` | `FLASH VERIFY `*``*` [options]` @@ -523,7 +1486,7 @@ Options: | `/P112`: Force P112 bank switching | `/N8VEMSBC`: Force N8VEM SBC (v1, v2), Zeta (v1) SBC bank switching -## Usage +#### Usage To program your EEPROM ROM chip, first transfer the file to your RomWBW system. Then use the command `FLASH WRITE *``*. The @@ -541,12 +1504,12 @@ of the command. The author's documentation for the application is found in the RomWBW distribution in the Doc/Contrib directory. -## Notes +#### Notes The application supports a significant number of EEPROM parts. It should automatically detect your part. If it does not recognize your chip, make sure that you do not have a write protect jumper set -- -this jumper will prevent the ROM chip from being recognized. +this jumper can prevent the ROM chip from being recognized. Reprogramming a ROM chip in-place is inherently dangerous. If anything goes wrong, you will be left with a non-functional system and no @@ -554,7 +1517,7 @@ ability to run the `FLASH` application again. Use this application with caution and be prepared to use a hardware ROM programmer to restore your system if needed. -## Etymology +#### Etymology This application was written and provided by Will Sowerbutts. He provides it in binary format and is included in the RomWBW @@ -565,130 +1528,156 @@ GitHub repository](https://github.com/willsowerbutts/flash4). `\clearpage`{=latex} -# FDISK80 - -`FDISK80` allows you to create and manage traditional partitions on -your hard disk media. Depending on the hard disk format and features -you are using, RomWBW may need hard disk partitions defined. - -Please refer to the $doc_user$ for more information on the use of -partitions within RomWBW. It is very important to understand that -RomWBW slices are completely different from disk partitions. - -This application is provided by John Coffman. The primary -documentation is in the file "FDisk Manual.pdf" found in the -Doc directory of the RomWBW distribution. - -## Usage +## FORMAT -`FDISK80` is an interactive application. At startup it will ask you -for the disk unit that you want to partition. When your RomWBW system -boots, it will display a table with the disk unit numbers. Use the -disk unit numbers from that table to enter the desired disk unit to -partition. +| FORMAT | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -`FDISK80` operates very much like other FDISK disk partitioning -applications. Please refer to the file called "FDisk Manual.pdf" in -the Doc directory of the RomWBW distribution for further instructions. +This application is just a placeholder for a future version that will +make it simpler to format media including floppy disks. -There is also more information on using FAT partitions with RomWBW in -the $doc_user$ document in the Doc directory of the distribution. +#### Syntax -## Notes +`FORMAT` -Hard disk partition tables allow a maximum of 1024 cylinders when -defining partitions. However, RomWBW uses exclusively Logical Block -Addressing (LBA) which does not have this limitation. When defining -partitions is usually best to define the start and size of of the -partition using bytes or sectors. +#### Notes -## Etymology +This application currently just displays a few lines of information +briefly instructing a user how to format media. It performs no actual +function beyond this display currently. -The source for this application was provided directly by John Coffman. -It is a C program and requires a build environment that includes the -SDCC compiler. As such, it is not included in the RomWBW build -process, only the binary executable is included. +#### Etymology -Please contact John Coffman if you would like a copy of the source. +The `FORMAT` command is an original product and the source code is +provided in the RomWBW distribution. `\clearpage`{=latex} -# TALK +## HTALK -It is sometimes useful to direct your console input/output to a -designated serial port. For example, if you were to connect a modem -to your second serial port, you might want to connect directly to it -and have everything you type sent to it and everything it sends be -shown on your console. The `TALK` application does this. +| HTALK | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -## Syntax +`HTALK` is a variation of the `TALK` utility, but it works directly +against HBIOS Character Units. -`TALK [TTY:|CRT:|BAT:UC1:]` +#### Syntax -## Usage +`HTALK COMn:` -`TALK` operates at the operating system level (not HBIOS). +#### Usage -The parameter to `TALK` refers to logical CP/M serial devices. Upon +`HTALK` operates at the HBIOS level. + +The parameter to `TALK` refers to a HBIOS character unit. Upon execution all characters typed at the console will be sent to the device specified and all characters received by the specified device will be echoed on the console. Press Control+Z on the console to terminate the application. -## Notes +#### Notes -This application is designed for CP/M 2.2 or Z-System. Use on later -operating systems such as CP/M 3 is not supported. -## Etymology +#### Etymology -The `TALK` command is an original product and the source code is -provided in the RomWBW distribution. +The `TALK` command was created and donated to RomWBW by Tom Plano. It +is an original product designed specifically for RomWBW. `\clearpage`{=latex} -# HTALK +## MODE -`HTALK` is a variation of the `TALK` utility, but it works directly -against HBIOS Character Units. +| MODE | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -## Syntax +The MODE command allows you to adjust the operating characteristics +such as baud rate, data bits, stop bits, and parity bits of serial +ports dynamically. -`HTALK COMn:` +#### Syntax -## Usage +`MODE /?` +`MODE COM`*``*`: [`*``*`[,`*``*`[,`*``*`[,`*``*`]]]] [/P]` -`HTALK` operates at the HBIOS level. +`/?` displays command usage and version information -The parameter to `TALK` refers to a HBIOS character unit. Upon -execution all characters typed at the console will be sent to the -device specified and all characters received by the specified device -will be echoed on the console. +*``* is the character device unit number -Press Control+Z on the console to terminate the application. +*``* is numerical baudrate -## Notes +*``* is (N)one, (O)dd, (E)ven, (M)ark, or (S)pace +*``* is number of data bits, typically 7 or 8 -## Etymology +*``* is number of stop bits, typically 1 or 2 -The `TALK` command was created and donated to RomWBW by Tom Plano. It -is an original product designed specifically for RomWBW. +`/P` prompts user prior to setting new configuration + +#### Usage + +`MODE /?` will display basic command usage and version information. + +`MODE` with no parameters will list all devices and their current +configuration. + +`MODE <`*n*`>` will display the current configuration of the specified +character device unit. + +`MODE COM`*``*`: [`*``*`[,`*``*`[,`*``*`[,` +*``*`]]]] [/P]` requests that the specified configuration +be set on the character device unit. You can use commas with no values +to leave some values unchanged. As an example, `MODE COM0: 9600,,,2` +will setup character device unit 0 for 9600 baud and 2 stop bits while +leaving data bits and stop bits as is. + +Appending `/P` in a command specifying a new configuration will cause +the terminal output to pause and wait for the user to press a key. +This allows the user to change the local terminal setup before +continuing. + +#### Notes + +Specified baud rate and line characteristics must be supported by the +serial unit. Any parameters not specified will remain unchanged. + +Changes are not persisted and will revert to system defaults at next +system boot. + +Not all character devices support all `MODE` options. Some devices +(notably ASCI devices) have limited baud rate divisors. An attempt to +set a baud rate that the device cannot support will fail with an error +message. + +#### Etymology + +The `MODE` command is an original product and the source code is +provided in the RomWBW distribution. `\clearpage`{=latex} -# RTC +## RTC + +| RTC | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |yes| Many RomWBW systems provide real time clock hardware. The RTC application is a simple, interactive program allowing you to display and set the time and registers of the RTC. -## Syntax +#### Syntax `RTC` -## Usage +#### Usage After startup, the application provides the following options: @@ -709,7 +1698,7 @@ After startup, the application provides the following options: | `B)oot` | will reboot your system. | | `H)elp` | displays brief help. | -## Notes +#### Notes When using Get and Put options, the register number to read/write is entered in hex. The non-volatile ram register numbers are 0x20-0x3F. @@ -721,7 +1710,7 @@ the two hex characters. Yes, this should be improved. The `RTC` application interacts directly with the RTC hardware bypassing HBIOS. -## Etymology +#### Etymology The `RTC` application was originally written by Andrew Lynch as part of the original ECB SBC board development. It has since been modified to @@ -729,308 +1718,254 @@ support most of the hardware variations included with RomWBW. `\clearpage`{=latex} -# TIMER - -Most RomWBW systems have a 50Hz periodic system timer. A counter is -incremented every time a timer tick occurs. The `TIMER` application -displays the value of the counter. - -## Syntax - -`TIMER` -`TIMER /?` -`TIMER /C` +## SURVEY -## Usage +| SURVEY | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -Use `TIMER` to display the current value of the counter. +The `SURVEY` command interrogates the system for information on disk +usage, memory usage and I/O ports used, and reports it to the user. -Use `TIMER /C` to display the value of the counter continuously. +#### Syntax -The display of the counter will be something like this: +The `SURVEY` command takes no arguments. -`00045444 Ticks, 0000162A.10 Seconds` +| `SURVEY` -The first number is the total number of ticks since system startup. -The second number is the total number of seconds since system startup. +#### Usage -## Notes +The results presented by `SURVEY` include: -The seconds value is displayed with a fractional value which is not a -an actual fraction, but rather the number of ticks past the seconds -rollover. All values are in hex. +1. Information about any drives, within the first eight (ie A: to H:), +which have been logged by the system. This includes: the total number +of files; the storage capacity occupied by those files; and the capacity +remaining on that drive. -The primary use of the `TIMER` application is to test the system -timer functionality of your system. +1. Information about the the 64KByte CP/M memory map, which is shown +diagramatically, and includes: locations and sizes of the TPA (Transient Program Area), +CP/M's CCP (Console Command Processor),and BDOS (Basic Disk Operating System). -In theory, you could capture the value before and after some process -you want to time. +1. The addresses of active CPU I/O ports. -## Etymology +#### Notes -The `TIMER` command is an original product and the source code is -provided in the RomWBW distribution. +The mechanism by which `SURVEY` discovers I/O ports is very conservative and +therefore the list returned may not be exhaustive. In particular, it may fail to +discover ports that are 'write-only'. `\clearpage`{=latex} -# INTTEST - -RomWBW includes an API allowing applications to "hook" interrupts. -The `INTTEST` application allows you to test this functionality. - -## Syntax - -`INTTEST` - -## Usage - -`INTTEST` is an interactive application. At startup, it will display -a list of the interrupt vector slots in your system along with the -current vector address for each of them. +## SYSCOPY -It then prompts you to enter the slot number (in hex) of a vector to -hook. After entering this, the application will watch the hooked -vector and countdown from 0xFF to 0x00 as interrupts are noted. +| SYSCOPY | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -When the counter reaches 0x00, the interrupt is unhooked and the -application terminates. The application can also be terminated by -pressing . - -## Notes - -If your system is running without interrupts active, the application -will terminate immediately. - -All slots have vectors even if the corresponding interrupt is not -doing anything. In this case, the vector is pointing to the "bad -interrupt" handler. - -If you hook a vector that is not receiving any interrupts, the -downcounter will not do anything. - -## Etymology - -The `INTTEST` command is an original product and the source code is -provided in the RomWBW distribution. - -`\clearpage`{=latex} +To make disk media bootable, you must write a system boot image onto +the system tracks of the of the media. The `SYSCOPY` allows you to +read or write the system boot image of disk media. -# FAT +#### Syntax -The operating systems included with RomWBW do not have any native -ability to access MS-DOS FAT filesystems. The FAT application can be -used overcome this. It will allow you to transfer files between CP/M -and FAT filesystems (wildcards supported). It can also erase files, -format, and list directories of FAT filesystems. +| `SYSCOPY `*``*`=`*``* -## Syntax +*``* is the drive to receive the operating system image or +alternatively a filename to save the operating system image -| `FAT DIR `*``* -| `FAT COPY `*` `* -| `FAT REN `*` `* -| `FAT DEL `*`[|]`* -| `FAT MD `*``* -| `FAT FORMAT `*``* +*``* is the drive containing an operating system image or +alternatively a filename containing the system image to be placed on +the destination -| *``* is a FAT path -| *``*, *``* are FAT or CP/M filenames -| *``*, *``* are FAT filenames -| *``* is a FAT filename -| *``* is a FAT directory name -| *``* is a RomWBW disk unit number +#### Usage -| CP/M filespec: *``*`:FILENAME.EXT` (*``* is CP/M drive letter A-P) -| FAT filespec: *``*`:/DIR/FILENAME.EXT` (*``* is RomWBW disk unit #) +Both *``* and *``* can refer to either a drive letter or a +file. If a drive letter is specified, the system boot image will be +read or written to the system tracks of the drive. If a filename is +specified, the system boot image will be read or written to the +specified filename. -## Usage +`SYSCOPY C:=ZSYS.SYS` will read a system boot image from the file +ZSYS.SYS and write it onto the system tracks of drive C:. -The `FAT` application determines whether you are referring to a CP/M -filesystem or a FAT filesystem based on the way you specify the file -or path. If the file or path is prefixed with a number (n:), then it -is assumed this is a FAT filesystem reference and is referring to the -FAT filesystem on RomWBW disk unit 'n'. Otherwise, the file -specification is assumed to be a normal CP/M file specification. +`SYSCOPY A:OS.SYS=C:` will capture the system boot image from the +system tracks of drive C: and store it in the file A:OS.SYS. -If you wanted to list the directory of the FAT filesystem on RomWBW -disk unit 2, you would use `FAT DIR 2:`. If you only wanted to see the -".TXT" files, you would use `FAT DIR 2:*.TXT`. +`SYSCOPY D:=C:` will copy the system tracks from drive C: onto the +system tracks of drive D:. -If you wanted to copy all of the files on CP/M drive B: to the FAT -filesystem on RomWBW disk unit 4, you would use the command `FAT COPY -B:*.* 4:` If you wanted to copy the files to the "FOO" directory, then -you would use `FAT COPY B:*.* 4:\FOO`. To copy files in the opposite -direction, you just reverse the parameters. +#### Notes -To rename the file "XXX.DAT" to "YYY.DAT" on a FAT filesystem, you -could use a command like "FAT REN 2:XXX.DAT 2:YYY.DAT". +The RomWBW ROM disk contains files with the system boot image for +Z-System and CP/M 2.2. These files are called CPM.SYS and ZSYS.SYS +respectively. These files can be used as the source of a `SYSCOPY` +command to make a disk bootable with the corresponding operating +system. -To delete a file "XXX.DAT" on a FAT filesystem in directory "FOO", you -would use a command like `FAT DEL 2:\FOO\XXX.DAT`. +CP/M 3 uses a two phase boot process. To make a CP/M 3 drive bootable, +you need to put "CPMLDR.SYS" on the boot tracks of the disk and be +sure that the drive also contains the "CPM.SYS" file. The "CPMLDR.SYS" +file is not included on the ROM disk, but is found on the CP/M 3 disk +image. -To make a directory called "FOO2" on a FAT filesystem, you would use a -command line `FAT MD 2:\FOO2`. +ZPM3 is similar to CP/M 3. You also put "CPMLDR.SYS" on the system +tracks of the drive to make it bootable. The ZPM3 operating system is +in the file called "CPM3.SYS" on the ZPM3 disk image. It may seem +confusing that ZPM3 is in the file called CPM3.SYS, but it is normal +for ZPM3. -To format the filesystem on a FAT partition, you would use a command -like `FAT FORMAT 2:`. Use this with caution because it will destroy -all data on any pre-existing FAT filesystem on disk unit 2. +For the purposes of booting an operating system, each disk slice is +considered its own operating system. Each slice can be made bootable +with its own system tracks. -## Notes +`SYSCOPY` uses drive letters to specify where to read/write the system +boot images. However, at startup, the boot loaded will require you to +enter the actual disk device and slice to boot from. So, you need to +be careful to pay attention to the device and slice that is assigned +to a drive letter so you will know what to enter at the boot loader +prompt. By way of explanation, the boot loader does not know about +drive letters because the operating system is not loaded yet. -Partitioned or non-partitioned media is handled automatically. A -floppy drive is a good example of a non-partitioned FAT filesystem and -will be recognized. Larger media will typically have a partition -table which will be recognized by the application to find the FAT -filesystem. +If you want to put a boot system image on a device and slice that is +not currently assigned to a drive letter, you will need to assign a +drive letter first. -Although RomWBW-style CP/M media does not know anything about -partition tables, it is entirely possible to have media that -has both CP/M and FAT file systems on it. This is accomplished -by creating a FAT filesystem on the media that starts on a track -beyond the last track used by CP/M. Each CP/M slice can occupy -up to 8MB. So, make sure to start your FAT partition beyond -(slice count) * 9MB. +Not all disk formats include space for system tracks. Such disk +formats cannot contains a system boot image and, therefore, cannot be +made bootable. The best example of such disk formats are the ROM and +RAM disks. To maximize usable file space on these drives, they do not +have system tracks. Obviously, ROM operating system is supported by +choosing a ROM operating system at the boot loader prompt. Any attempt +to write a system boot image to disk media with no system tracks will +cause SYSCOPY to fail with an error message. -The application infers whether you are attempting to reference a FAT -or CP/M filesystem via the drive specifier (char before ':'). A -numeric drive character specifies the HBIOS disk unit number for FAT -access. An alpha (A-P) character indicates a CP/M file system access -targeting the specified drive letter. If there is no drive character -specified, the current CP/M filesystem and current CP/M drive is -assumed. For example: +The system boot images are paired with the ROM version in your system. +So, you must take care to update the system tracks of any bootable +disk when you upgrade your ROM firmware. -| `2:README.TXT` refers to FAT file "README.TXT" on disk unit #2 -| `C:README.TXT` refers to CP/M file "README.TXT" on CP/M drive C -| `README.TXT` refers to CP/M file "README.TXT" on the current CP/M drive +The system boot images are **not** tied to specific hardware +configurations. System boot images and operating systems provided with +RomWBW will work with any supported RomWBW platform or hardware as +long as they are the same version as the RomWBW firmware. -Files with SYS, HIDDEN, or R/O only attributes are not given any -special treatment. Such files are found and processed like any other -file. However, any attempt to write to a read-only file will fail and -the application will abort. +#### Etymology -It is not currently possible to reference CP/M user areas other than -the current user. To copy files to alternate user areas, you must -switch to the desired user number first or use an additional step to -copy the file to the desired user area. +The `SYSCOPY` command is an original product and the source code is +provided in the RomWBW distribution. -Accessing FAT filesystems on a floppy requires the use of RomWBW HBIOS -v2.9.1-pre.13 or greater. +`\clearpage`{=latex} -Only the first 8 RomWBW disk units (0-7) can be referenced. +## TALK -Files written are not verified. +| TALK | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -Wildcard matching in FAT filesystems is a bit unusual as implemented by -FatFs. See FatFs documentation. +It is sometimes useful to direct your console input/output to a +designated serial port. For example, if you were to connect a modem +to your second serial port, you might want to connect directly to it +and have everything you type sent to it and everything it sends be +shown on your console. The `TALK` application does this. -The `FAT FORMAT` command will not perform a physical format on floppy -disks. You must use FDU to do this prior to using `FAT FORMAT`. +#### Syntax -Formatting (`FAT FORMAT`) of floppies does not work well. The -underlying FatFs library uses some non-standard fields. The resulting -floppy may or may not be useable on other systems. It is best to format -a FAT floppy on a Windows or DOS system. You should have no problems -copying files to/from such a floppy using `FAT`. +`TALK [TTY:|CRT:|BAT:UC1:]` -## Etymology +#### Usage -The `FAT` application is an original RomWBW work, but utilizes the -FsFat library for all of the FAT filesystem work. This application is -written in C and requires SDCC to compile. As such it is not part of -the RomWBW build process. However, the full project and source code is -found in the [FAT GitHub Repository](https://github.com/wwarthen/FAT). +`TALK` operates at the operating system level (not HBIOS). -## Known Issues +The parameter to `TALK` refers to logical CP/M serial devices. Upon +execution all characters typed at the console will be sent to the +device specified and all characters received by the specified device +will be echoed on the console. -CP/M (and workalike) OSes have significant restrictions on filename -characters. The FAT application will block any attempt to create a -file on the CP/M filesystem containing any of these prohibited -characters: +Press Control+Z on the console to terminate the application. -| `< > . , ; : ? * [ ] |/ \` +#### Notes -The operation will be aborted with "`Error: Invalid Path Name`" if such -a filename character is encountered. +This application is designed for CP/M 2.2 or Z-System. Use on later +operating systems such as CP/M 3 is not supported. -Since MS-DOS does allow some of these characters, you can have -issues when copying files from MS-DOS to CP/M if the MS-DOS filenames -use these characters. Unfortunately, FAT is not yet smart enough to -substitute illegal characters with legal ones. So, you will need to -clean the filenames before trying to copy them to CP/M. +#### Etymology -The FAT application does try to detect the scenario where you are -copying a file to itself. However, this detection is not perfect and -can corrupt a file if it occurs. Be careful to avoid this. +The `TALK` command is an original product and the source code is +provided in the RomWBW distribution. `\clearpage`{=latex} -# CLRDIR - -`CLRDIR` is used to initialize a CP/M filesystem. This is frequently -used to prepare RomWBW disk slices for use. If there is any data -on the filesystem, it will be destroyed. `CLRDIR` works on CP/M -drive letters. To initialize a RomWBW slice, the slice must first be -assigned to a CP/M drive letter. +## TIMER +| TIMER | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| -This application is provided by Max Scane. - -## Syntax +Most RomWBW systems have a 50Hz periodic system timer. A counter is +incremented every time a timer tick occurs. The `TIMER` application +displays the value of the counter. -| `CLRDIR `*``*` [options]` +#### Syntax -*``* is the CP/M drive letter to be cleared (e.g., "A:") +`TIMER` +`TIMER /?` +`TIMER /C` +#### Usage -Options: +Use `TIMER` to display the current value of the counter. -| `-D`: Enable debug output -| `-Y`: Do not ask for confirmation +Use `TIMER /C` to display the value of the counter continuously. -## Usage +The display of the counter will be something like this: -This application has a command line interface only. Type an -appropriately formatted command at the command prompt at any of the -RomWBW CP/M operatings systems (CP/M 2.2, ZSDOS, CP/M 3, etc.). +`13426 Ticks 268.52 Seconds` -You will be prompted for confirmation to continue. You must type a -**capital** 'Y' to proceed. The application will confirm that the -drive has been cleared. +The first number is the total number of ticks since system startup, where +there are 50 ticks per second. The second number is the total number of +seconds since system startup. Numbers are displayed in decimal format. -If used under ZSDOS, you should issue a `RELOG` command after using -`CLRDIR` to ensure that CP/M relogs the cleared drive. +#### Notes -## Notes +The seconds value is displayed with a fractional value which is not a +an actual fraction, but rather the number of ticks past the seconds +rollover. All values are in hex. -This command is inherently dangerous. It will completely destroy the -directory area of the target drive. Be very careful to ensure you do -not target a drive that contains useful data. +The primary use of the `TIMER` application is to test the system +timer functionality of your system. -`CLRDIR` understands the directory formats of all of the RomWBW -CPM-like operating systems and devices including floppy disks, CF/SD -Cards, etc. +In theory, you could capture the value before and after some process +you want to time. -## Etymology +#### Etymology -This application was written and provided by Max Scane. He -provides it in binary format and is included in the RomWBW -distribution as a binary file. +The `TIMER` command is an original product and the source code is +provided in the RomWBW distribution. `\clearpage`{=latex} -# TUNE +## TUNE + +| TUNE | | +| --------------------|---| +| ROM-based |No | +| Disk-based |Yes| If your RomWBW system has a sound card based on either an AY-3-8190 or YM2149F sound chip, you can use the `TUNE` application to play PT or MYM sound files. -## Syntax +#### Syntax `TUNE `*``* *``* is the name of a sound file ending in .PT2, .PT3, or .MYM -## Usage +#### Usage The TUNE application supports PT and YM sound file formats. It determines the format of the file from the extension of the file, so @@ -1040,7 +1975,7 @@ To play a sound file, just use the command and specify the file to play after the command. So, for example, `TUNE ATTACK.PT2` will immediately begin playing the PT sound file "ATTACK.PT2". -## Notes +#### Notes The `TUNE` application automatically probes for compatible hardware at well known port addresses at startup. It will auto-configure itself @@ -1078,7 +2013,7 @@ The HBIOS mode also support other switch as described below. All RomWBW operating system boot disks include a selection of sound files in user area 3. -## Etymology +#### Etymology The `TUNE` application was custom written for RomWBW. All of the hardware interface code is specific to RomWBW. The sound file decoding @@ -1088,77 +2023,14 @@ is (c)2004-2007 S.V.Bulba . The source code is provided in the RomWBW distribution. -# CPUSPD - -The `CPUSPD` application is used to change the running speed and wait -states of a RomWBW system. - - The functionality is highly dependent on -the capabilities of your system. - -At present, all Z180 systems can change their CPU speed and their -wait states. SBC and MBC systems may be able to change their CPU -speed if the hardware supports it and it is enabled in the HBIOS -configuration. - -## Syntax - -| `CPUSPD [`*``*`[,[`*``*`][,[`*``*`]]]` - -*``* is one of HALF, FULL, or DOUBLE. -*``* is a number specifying the desired memory wait states. -*``* is a number specifying the desired I/O wait states. - -## Usage - -Entering `CPUSPD` with no parameters will display the current CPU speed -and wait state information of the running system. Wait state -information is not available for all systems. - -To modify the running speed of a system, you can specify the -`*``*` parameter. To modify either or both of the wait -states, you can enter the desired number. Either or both of the wait -state parameters may be omitted and the current wait state settings -will remain in effect. - -## Notes - -The ability to modify the running speed and wait states of a system -varies widely depending on the hardware capabilities and the HBIOS -configuration settings. - -Note that it is frequently impossible to tell if a system is capable -of dynamic speed changes. This function makes the changes blindly. -If an attempt is made to change the speed of a system -that is definitely incapable of doing so, then an error result is -returned. - -The `CPUSPD` command makes no attempt to ensure that the new CPU -speed will actually work on the current hardware. Setting a CPU -speed that exceeds the capabilities of the system will result in -unstable operation or a system stall. - -Some peripherals are dependent on the CPU speed. For example, the Z180 -ASCI baud rate and system timer are derived from the CPU speed. The -CPUSPD application will attempt to adjust these peripherals for -correct operation after modifying the CPU speed. However, in some -cases this may not be possible. The baud rate of ASCI ports have a -limited set of divisors. If there is no satisfactory divisor to -retain the existing baud rate under the new CPU speed, then the baud -rate of the ASCI port(s) will be affected. - -## Etymology - -The `CPUSPD` application was custom written for RomWBW. All of the -hardware interface code is specific to RomWBW and the application will -not operate correctly on non-RomWBW systems. - -The source code is provided in the RomWBW distribution. - - `\clearpage`{=latex} -# VGMPLAY +## VGMPLAY + +| VGMPLAY | | +| --------------------|---| +| ROM-based |No | +| Disk-based |Yes| This application will allow you to play Video Game Music files. VGM files contain music samples from a range of different sound chips @@ -1189,17 +2061,18 @@ Sound chips currently supported are: VGMPLAY supports playback of files with multiple combinations of these chips. -## Syntax +#### Syntax `VGMPLAY `*``* *``* is the name of a sound file ending in .VGM -## Usage +#### Usage VGMPLAY does not automatically detect the hardware platform or sound hardware that you are using. This means a version customized for your -system must be assembled before use. +system must be assembled before use. However, the version as distributed +will work with ECB bus SBC systems. To play a sound file, just use the VGMPLAY command and specify the file to play after the command. So, for example, `VGMPLAY TEDDY` will load @@ -1208,7 +2081,7 @@ the TEDDY.VGM sound file into memory and begin playing it. Playback can be stopped by pressing a key. There may be a delay before playback stops. -## Notes +#### Notes The default build configuration for VGMPLAY is: @@ -1235,16 +2108,21 @@ RomWBW distribution. `\clearpage`{=latex} -# WDATE +## WDATE + +| WDATE | | +| --------------------|---| +| ROM-based |No | +| Disk-based |Yes| `wdate` is a utility for CP/M systems that have Wayne Warthen's -ROMWBW firmware. It reads or sets the real-time clock, using function +RomWBW firmware. It reads or sets the real-time clock, using function calls in the BIOS. It should work on any RTC device that is supported by -ROMWBW, including the internal interrupt-driven timer that is is available +RomWBW, including the internal interrupt-driven timer that is is available on some systems. `wdate` differs from the `rtc.com` utility that is provided with the -ROMWBW version of CP/M in that it only gets and sets the date/time. +RomWBW version of CP/M in that it only gets and sets the date/time. `rtc.com` can also manipulate the nonvolatile RAM in certain clock devices, and modify the charge controller. However, `wdate` is (I would argue) easier to use, as it takes its input from the command line, which @@ -1259,14 +2137,14 @@ application for two reasons: first, the BIOS does not expose it. Second, there is no universally-accepted way to interpret it (which day does the week start on? Is '0' a valid day of the week?) -## Syntax +#### Syntax | `WDATE` | `WDATE ` *`
`* | `WDATE ` *`
`* | `WDATE ` *`
`* -## Usage +#### Usage A> wdate Saturday 27 May 13:14:39 2023 @@ -1292,25 +2170,112 @@ two-digit year starts at 2000. Show a summary of the command-line usage. -## Notes +#### Notes I've tested this utility with the DS1302 clock board designed by Ed Brindly, and on the interrupt-driven timer built into my Z180 board. However, it does not interact with hardware, only BIOS; I would expect it to work with other hardware. -wdate checks for the non-existence of ROMWBW, and also for failing +wdate checks for the non-existence of RomWBW, and also for failing operations on the RTC. It will display the terse "No RTC" message in both cases. -The ROMWBW functions that manipulate the date and time operate on BCD +The RomWBW functions that manipulate the date and time operate on BCD numbers, as RTC chips themselves usually do. wdate works in decimal, so that it can check that the user input makes sense. A substantial part of the program's code is taken up by number format conversion and range checking. -## Etymology +#### Etymology The `WDATE` application was written and contributed by Kevin Boone. The source code is available on GitHub at -[https://github.com/kevinboone/wdate-cpm/blob/main/README.md](https://github.com/kevinboone/wdate-cpm/blob/main/README.md). +. + +`\clearpage`{=latex} + +## XM + +| XM | | +| --------------------|---| +| ROM-based |Yes| +| Disk-based |Yes| + +An adaptation of Ward Christensen's X-Modem protocol for transferring +files between systems using a serial port. + +#### Syntax + +| `XM S `*``* +| `XM SK `*``* +| `XM L `*` `* +| `XM LK `*` `* +| `XM R `*``* + +`S`: Send a file +`L`: Send a file from a library +`R`: Receive a file +`K`: Use 1K blocksize for transfer + +*``* is the name of a file to send or receive + +*``* is the name of a library (.lbr) to extract a file to send + +#### Usage + +To transfer a file from your host computer to your RomWBW computer, do +the following: + +1. Enter one of the `XM` receive commands specifying the name you want +to give to the received file. + +2. On your host computer select a file to send and initiate the XModem +send operation. + +To transfer a file from your RomWBW computer to your host computer, do +the following: + +1. Enter one of the `XM` send commands specifying the name of the file +to be sent. + +2. On your host computer, specify the name to assign to the received +file and initiate and XModem receive operation. + +Please refer to the documentation of your host computer's terminal +emulation software for specific instructions on how to use XModem. + +#### Notes + +The XModem adaptation that comes with RomWBW will automatically use +the primary character device unit (character device unit 0) for the +file transfer. + +`XM` attempts to determine the best way to drive the serial port based +on your hardware configuration. When possible, it will bypass the +HBIOS for faster operation. However, in many cases, it will use HBIOS +so that flow control can be used. + +`XM` is dependent on a reliable communications channel. You must +ensure that the serial port can be serviced fast enough by either +using a baud rate that is low enough or ensuring that hardware flow +control is fully functional (end to end). + +#### Etymology + +The `XM` application provided in RomWBW is an adaptation of a +pre-existing XModem application. Based on the source code comments, it +was originally adapted from Ward Christensen's MODEM2 by Keith +Petersen and is labelled version 12.5. + +The original source of the application was found in the Walnut Creek +CD-ROM and is called XMDM125.ARK dated 7/15/86. + +The actual application is virtually untouched in the RomWBW +adaptation. The majority of the work was in the modem driver which was +enhanced to detect the hardware being used and dynamically choose the +appropriate driver. + +The source code is provided in the RomWBW distribution. + +`\clearpage`{=latex} diff --git a/Source/Doc/Basic.h b/Source/Doc/Basic.h index 4ab5106c..def9b838 100644 --- a/Source/Doc/Basic.h +++ b/Source/Doc/Basic.h @@ -11,7 +11,6 @@ $define{doc_orgurl}{www.retrobrewcomputers.org}$ $define{doc_user}{[RomWBW User Guide]($doc_root$/RomWBW User Guide.pdf)}$ $define{doc_sys}{[RomWBW System Guide]($doc_root$/RomWBW System Guide.pdf)}$ $define{doc_apps}{[RomWBW Applications]($doc_root$/RomWBW Applications.pdf)}$ -$define{doc_romapps}{[RomWBW ROM Applications]($doc_root$/RomWBW ROM Applications.pdf)}$ $define{doc_catalog}{[RomWBW Disk Catalog]($doc_root$/RomWBW Disk Catalog.pdf)}$ $define{doc_errata}{[RomWBW Errata]($doc_root$/RomWBW Errata.pdf)}$ diff --git a/Source/Doc/Build.cmd b/Source/Doc/Build.cmd index 14ac1187..3736b6b5 100644 --- a/Source/Doc/Build.cmd +++ b/Source/Doc/Build.cmd @@ -2,8 +2,12 @@ setlocal :: -:: NOTE: Pandoc and Latex (MiKTeX or TexLive) must be installed -:: and available on commandline for this build to work!!! +:: NOTE: Pandoc, LuaLatex (MiKTeX or TexLive), and Roboto Font +:: must be installed and available on commandline for this build to work!!! +:: +:: - Pandoc (https://pandoc.org/) +:: - MiKTeX (https://miktex.org/) +:: - Install Roboto font from MiKTeX Console :: set TOOLS=..\..\Tools @@ -11,20 +15,18 @@ set PATH=%TOOLS%\gpp;%PATH% if not "%1"=="" (call :GenDoc %1 & goto :eof) -call :GenDoc ReadMe -call :GenDoc UserGuide -call :GenDoc SystemGuide -call :GenDoc Applications -call :GenDoc ROM_Applications -call :GenDoc Catalog -call :GenDoc Errata +call :GenDoc ReadMe || exit /b +call :GenDoc UserGuide || exit /b +call :GenDoc SystemGuide || exit /b +call :GenDoc Applications || exit /b +call :GenDoc Catalog || exit /b +call :GenDoc Errata || exit /b if exist ReadMe.gfm copy Readme.gfm ..\..\ReadMe.md || exit /b if exist ReadMe.txt copy ReadMe.txt ..\..\ReadMe.txt || exit /b if exist UserGuide.pdf copy UserGuide.pdf "..\..\Doc\RomWBW User Guide.pdf" || exit /b if exist SystemGuide.pdf copy SystemGuide.pdf "..\..\Doc\RomWBW System Guide.pdf" || exit /b if exist Applications.pdf copy Applications.pdf "..\..\Doc\RomWBW Applications.pdf" || exit /b -if exist ROM_Applications.pdf copy ROM_Applications.pdf "..\..\Doc\RomWBW ROM Applications.pdf" || exit /b if exist Catalog.pdf copy Catalog.pdf "..\..\Doc\RomWBW Disk Catalog.pdf" || exit /b if exist Errata.pdf copy Errata.pdf "..\..\Doc\RomWBW Errata.pdf" || exit /b @@ -37,9 +39,6 @@ echo. echo Processing document %1... -::gpp -o %1.tmp %1.md -::gpp -o %1.tmp -U "\\" "" "{" "}{" "}" "{" "}" "#" "" %1.md -::gpp -o %1.tmp -U "" "" "(" "," ")" "(" ")" "#" "" -M "#" "\n" " " " " "\n" "(" ")" %1.md gpp -o %1.tmp -U "$" "$" "{" "}{" "}$" "{" "}" "@@@" "" -M "$" "$" "{" "}{" "}$" "{" "}" %1.md || exit /b ::pandoc %1.tmp -f markdown -t latex -s -o %1.tex --default-image-extension=pdf || exit /b diff --git a/Source/Doc/Catalog.md b/Source/Doc/Catalog.md index 8250a8b8..c878dc49 100644 --- a/Source/Doc/Catalog.md +++ b/Source/Doc/Catalog.md @@ -217,9 +217,9 @@ on using the applications and files listed. | `INITDIR.COM` | ZSDOS | ZSDOS Prepare disks for P2DOS Stamps | | `KERMIT.COM` | -- | Generic CP/M 2.2 Kermit communication application | | `LBREXT.COM` | -- | Extract library files | -| `LDDS.COM` | ZSDOS | Clock driver | -| `LDNZT.COM` | ZSDOS | Clock driver | -| `LDP2D.COM` | ZSDOS | Clock driver | +| `LDDS.COM` | ZSDOS | Load DateStamper date/time stamping resident extension | +| `LDNZT.COM` | ZSDOS | Load NZT date/time stamping resident extension | +| `LDP2D.COM` | ZSDOS | Load P2DOS date/time stamping resident extension | | `LIB.COM` | -- | DRI Library manager | | `LINK.COM` | -- | DRI CPM relocatable linker | | `LOAD.COM` | -- | DRI hex file loader into memory | @@ -229,7 +229,7 @@ on using the applications and files listed. | `PMARC.COM` | -- | LHA file compressor | | `PMEXT.COM` | -- | Extractor for PMARC archives | | `PUTBG.COM` | ZSDOS | ZSDOS Prepare disk for backgrounder | -| `PUTDS.COM` | ZSDOS | ZSDOS Prepare disk for datestamper | +| `PUTDS.COM` | ZSDOS | ZSDOS Prepare disk for datestamper date/time stamping| | `RELOG.COM` | ZSDOS | ZSDOS relog disks after program that bypasses BDOS | | `RMAC.COM` | -- | DRI Relocatable Macro Assembler | | `SETTERM.COM` | ZSDOS | ZSDOS Installs terminal control codes into DateSamper utilities | diff --git a/Source/Doc/Graphics/BankSwitchedMemory.pdf b/Source/Doc/Graphics/BankSwitchedMemory.pdf index 42db138c..ba027b47 100644 Binary files a/Source/Doc/Graphics/BankSwitchedMemory.pdf and b/Source/Doc/Graphics/BankSwitchedMemory.pdf differ diff --git a/Source/Doc/Graphics/BankSwitchedMemory.png b/Source/Doc/Graphics/BankSwitchedMemory.png index f617cb0d..fd74851b 100644 Binary files a/Source/Doc/Graphics/BankSwitchedMemory.png and b/Source/Doc/Graphics/BankSwitchedMemory.png differ diff --git a/Source/Doc/Graphics/BankSwitchedMemory.svg b/Source/Doc/Graphics/BankSwitchedMemory.svg new file mode 100644 index 00000000..ef18a94e --- /dev/null +++ b/Source/Doc/Graphics/BankSwitchedMemory.svg @@ -0,0 +1,366 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page-1 + + Data block.13 + + Sheet.14 + + + + Sheet.15 + + + + Sheet.16 + + + + + Data block.9 + + Sheet.10 + + + + Sheet.11 + + + + Sheet.12 + + + + + Data block + + Sheet.6 + + + + Sheet.7 + + + + Sheet.8 + + + + + Sheet.2 + $FE00 + + + $FE00 + + Sheet.3 + $D000 + + + $D000 + + Sheet.17 + $8000 + + + $8000 + + 3D stack middle + + Sheet.19 + + + + Sheet.20 + + + + + 3D stack middle.21 + + Sheet.22 + + + + Sheet.23 + + + + + 3D stack middle.24 + + Sheet.25 + + + + Sheet.26 + + + + + Sheet.27 + HBIOS Proxy (RST 08) + + HBIOS Proxy (RST 08) + + Sheet.28 + Application Area (TPA) + + Application Area (TPA) + + Sheet.29 + Operating System CP/M or ZSYS + + Operating System CP/M or ZSYS + + Sheet.30 + CBIOS + + CBIOS + + Sheet.31 + BDOS + + BDOS + + Sheet.32 + CCP + + CCP + + Data block.33 + + Sheet.34 + + + + Sheet.35 + + + + Sheet.36 + + + + + Sheet.37 + + + + Sheet.38 + HBIOS (Hardware Drivers) + + HBIOS (Hardware Drivers) + + Sheet.39 + + + + Sheet.40 + + + + Sheet.43 + Z80 CPU Address Space + + Z80 CPU Address Space + + Sheet.41 + Banked Lower 32K + + Banked Lower 32K + + Sheet.42 + Fixed Upper 32K + + Fixed Upper 32K + + Sheet.1 + $10000 + + + $10000 + + Sheet.4 + $0000 + + + $0000 + + Bracket + + + + Sheet.45 + Bank 0 + + Bank 0 + + Sheet.47 + App/OS Banks + + App/OS Banks + + Sheet.48 + Bank N-1 + + Bank N-1 + + Sheet.49 + Bank N + + Bank N + + Sheet.50 + • • • + + • • • + + Bracket.51 + + + + Sheet.55 + + + + Sheet.56 + Physical RAM (32K per bank) + + Physical RAM (32K per bank) + + Bracket.57 + ` + + + ` + + Sheet.58 + + + + 3D stack top + RAM Disk + + Sheet.61 + + + + Sheet.62 + + + + Sheet.63 + + + + RAM Disk + + + Pointer (1-D) + + + + Pointer (1-D).65 + + + + Pointer (1-D).66 + + + + Pointer (1-D).67 + + + + Sheet.70 + + + + Sheet.68 + HBIOS Function Call w/ Bank Switch + + HBIOS Function Call w/ Bank Switch + + Sheet.69 + RomWBW Bank Switched Memory Layout + + RomWBW Bank Switched Memory Layout + + Sheet.59 + + + + Sheet.52 + Fixed Mapping of Upper 32K to Last Bank + + Fixed Mapping of Upper 32K to Last Bank + + Sheet.72 + + + + Sheet.74 + + + + diff --git a/Source/Doc/Graphics/BankSwitchedMemory.vsd b/Source/Doc/Graphics/BankSwitchedMemory.vsd index 36dedadf..636558d2 100644 Binary files a/Source/Doc/Graphics/BankSwitchedMemory.vsd and b/Source/Doc/Graphics/BankSwitchedMemory.vsd differ diff --git a/Source/Doc/Graphics/CharacterEmulationVideoServices.pdf b/Source/Doc/Graphics/CharacterEmulationVideoServices.pdf index fadac746..3c763700 100644 Binary files a/Source/Doc/Graphics/CharacterEmulationVideoServices.pdf and b/Source/Doc/Graphics/CharacterEmulationVideoServices.pdf differ diff --git a/Source/Doc/Graphics/CharacterEmulationVideoServices.png b/Source/Doc/Graphics/CharacterEmulationVideoServices.png index 4ccb3cc8..f6621411 100644 Binary files a/Source/Doc/Graphics/CharacterEmulationVideoServices.png and b/Source/Doc/Graphics/CharacterEmulationVideoServices.png differ diff --git a/Source/Doc/Graphics/CharacterEmulationVideoServices.svg b/Source/Doc/Graphics/CharacterEmulationVideoServices.svg new file mode 100644 index 00000000..6632a956 --- /dev/null +++ b/Source/Doc/Graphics/CharacterEmulationVideoServices.svg @@ -0,0 +1,830 @@ + + + + + + + + + + + + + + + + Page-1 + + Sheet.81 + + + + Sheet.80 + + + + Sheet.1 + Character I/O Services + + Character I/O Services + + Sheet.2 + + + + Sheet.8 + + + + Sheet.9 + Emulation Services + + Emulation Services + + Sheet.10 + TTY + + TTY + + Sheet.11 + ANSI + + ANSI + + Sheet.12 + + + + Sheet.13 + + + + Sheet.14 + Video Display Adapter Services + + Video Display Adapter Services + + Sheet.18 + + + + Sheet.27 + UART + + UART + + Sheet.34 + ASCI + + ASCI + + Terminal.20 + + Sheet.36 + + + + Sheet.37 + + + + Sheet.38 + + + + Sheet.39 + + + + + Sheet.40 + CVDU + + CVDU + + Sheet.41 + + + + Sheet.47 + UPD7220 + + UPD7220 + + Sheet.54 + N8 + + N8 + + Sheet.56 + CIOXXX + + CIOXXX + + Sheet.57 + VDAXXX + + VDAXXX + + Sheet.58 + Operating System / Utilities + + Operating System / Utilities + + Sheet.59 + Others... + + Others... + + Sheet.60 + + + + Sheet.61 + + + + Sheet.62 + EMUXXX + + EMUXXX + + Sheet.15 + + + + Terminal.16 + + Sheet.42 + + + + Sheet.43 + + + + Sheet.44 + + + + Sheet.45 + + + + + Sheet.46 + + + + Terminal.48 + + Sheet.49 + + + + Sheet.50 + + + + Sheet.51 + + + + Sheet.52 + + + + + Sheet.53 + + + + Terminal.22 + + Sheet.23 + + + + Sheet.24 + + + + Sheet.25 + + + + Sheet.26 + + + + + Sheet.28 + + + + Terminal.29 + + Sheet.30 + + + + Sheet.31 + + + + Sheet.32 + + + + Sheet.33 + + + + + Sheet.35 + + + + Sheet.55 + RS-232 + + RS-232 + + Sheet.63 + RS-232 + + RS-232 + + Sheet.64 + VGA + + VGA + + Sheet.65 + VGA + + VGA + + Sheet.66 + NTSC + + NTSC + + Sheet.67 + UART + + UART + + Sheet.68 + ASCI + + ASCI + + Sheet.69 + VDU + + VDU + + Sheet.74 + SY6545 + + SY6545 + + Sheet.75 + MC8563 + + MC8563 + + Sheet.76 + uPD7220 + + uPD7220 + + Sheet.79 + Character / Emulation / Video Services + + Character / Emulation / Video Services + + Sheet.82 + HBIOS + + HBIOS + + Sheet.83 + HARDWARE + + HARDWARE + + Sheet.84 + TMS9918 + + TMS9918 + + Terminal.87 + + Sheet.88 + + + + Sheet.89 + + + + Sheet.90 + + + + Sheet.91 + + + + + Sheet.92 + VDU + + VDU + + Sheet.93 + + + + Sheet.94 + NTSC + + NTSC + + Sheet.96 + + + + Sheet.7 + + + + Sheet.17 + + + + Sheet.3 + + + + Sheet.4 + + + + diff --git a/Source/Doc/Graphics/CharacterEmulationVideoServices.vsd b/Source/Doc/Graphics/CharacterEmulationVideoServices.vsd index 9f01ad06..8f752b79 100644 Binary files a/Source/Doc/Graphics/CharacterEmulationVideoServices.vsd and b/Source/Doc/Graphics/CharacterEmulationVideoServices.vsd differ diff --git a/Source/Doc/Graphics/Hard Disk Anatomy.vsd b/Source/Doc/Graphics/Hard Disk Anatomy.vsd index e335b109..a9c89c08 100644 Binary files a/Source/Doc/Graphics/Hard Disk Anatomy.vsd and b/Source/Doc/Graphics/Hard Disk Anatomy.vsd differ diff --git a/Source/Doc/Graphics/Logo.pdf b/Source/Doc/Graphics/Logo.pdf index 0921f91a..f7fedf9c 100644 Binary files a/Source/Doc/Graphics/Logo.pdf and b/Source/Doc/Graphics/Logo.pdf differ diff --git a/Source/Doc/Graphics/Logo.png b/Source/Doc/Graphics/Logo.png index 3d43ff31..6832b2a8 100644 Binary files a/Source/Doc/Graphics/Logo.png and b/Source/Doc/Graphics/Logo.png differ diff --git a/Source/Doc/Graphics/Logo.svg b/Source/Doc/Graphics/Logo.svg index da51b423..586d6f1f 100644 --- a/Source/Doc/Graphics/Logo.svg +++ b/Source/Doc/Graphics/Logo.svg @@ -1,15 +1,9 @@ - + - - - - - - + width="3.76042in" height="1.26042in" viewBox="0 0 270.75 90.75" xml:space="preserve" color-interpolation-filters="sRGB" + class="st3"> - + Page-1 - - + Sheet.34 - + - + Sheet.35 - + - + Sheet.36 - + - + Sheet.38 - + - + Sheet.39 - + - + Sheet.44 - + - + Sheet.48 - + - + Sheet.49 - + - + Sheet.50 - + - + Sheet.52 - + - + Sheet.53 - + diff --git a/Source/Doc/Graphics/WBW.vsdx b/Source/Doc/Graphics/Logo.vsdx similarity index 100% rename from Source/Doc/Graphics/WBW.vsdx rename to Source/Doc/Graphics/Logo.vsdx diff --git a/Source/Doc/Graphics/Panel.pdf b/Source/Doc/Graphics/Panel.pdf index 2ec8d559..49604071 100644 Binary files a/Source/Doc/Graphics/Panel.pdf and b/Source/Doc/Graphics/Panel.pdf differ diff --git a/Source/Doc/Graphics/Panel.png b/Source/Doc/Graphics/Panel.png index 488d258f..5bb28b12 100644 Binary files a/Source/Doc/Graphics/Panel.png and b/Source/Doc/Graphics/Panel.png differ diff --git a/Source/Doc/Graphics/Panel.svg b/Source/Doc/Graphics/Panel.svg new file mode 100644 index 00000000..ca83e5d7 --- /dev/null +++ b/Source/Doc/Graphics/Panel.svg @@ -0,0 +1,369 @@ + + + + + + + + Page-1 + + Sheet.1 + + + + Sheet.2 + + + + Sheet.3 + + + + Sheet.8 + + + + Sheet.9 + + + + Sheet.10 + + + + Sheet.11 + + + + Sheet.12 + + + + Sheet.13 + + + + Sheet.14 + + + + Sheet.18 + + + + Sheet.19 + + + + Sheet.20 + + + + Sheet.21 + + + + Sheet.22 + + + + Sheet.23 + + + + Sheet.24 + + + + Sheet.25 + + + + Sheet.26 + + + + Sheet.27 + + + + Sheet.28 + + + + Sheet.29 + + + + Sheet.30 + + + + Sheet.31 + + + + Sheet.32 + + + + Sheet.33 + + + + Sheet.34 + + + + Sheet.35 + 8 + + 8 + + Sheet.36 + 4 + + 4 + + Sheet.37 + 2 + + 2 + + Sheet.38 + 1 + + 1 + + Sheet.39 + High + + High + + Sheet.40 + + + + Sheet.41 + + + + Sheet.42 + + + + Sheet.43 + 8 + + 8 + + Sheet.44 + 4 + + 4 + + Sheet.45 + 2 + + 2 + + Sheet.46 + 1 + + 1 + + Sheet.47 + Low + + Low + + Sheet.48 + 7 + + 7 + + Sheet.49 + 6 + + 6 + + Sheet.50 + 5 + + 5 + + Sheet.52 + 4 + + 4 + + Sheet.53 + 3 + + 3 + + Sheet.54 + 2 + + 2 + + Sheet.55 + 1 + + 1 + + Sheet.56 + 0 + + 0 + + Sheet.57 + + + + Sheet.58 + Auto + + Auto + + Sheet.59 + Menu + + Menu + + Sheet.61 + + + + Sheet.62 + CRT + + CRT + + Sheet.63 + Serial + + Serial + + Sheet.64 + + + + Sheet.65 + Sec + + Sec + + Sheet.66 + Pri + + Pri + + Sheet.67 + + + + Sheet.68 + Disk + + Disk + + Sheet.69 + ROM + + ROM + + Sheet.70 + + + + Sheet.71 + Floppy + + Floppy + + Sheet.72 + Hard + + Hard + + Sheet.73 + + + + Sheet.74 + 4 + + 4 + + Sheet.75 + 2 + + 2 + + Sheet.76 + 1 + + 1 + + Sheet.78 + ROM App / Boot Slice + + ROM App / Boot Slice + + Sheet.79 + ROM Apps: 0=Monitor 1=BASIC 2=Forth 3=Game 4=CP/M 2.2 5=Z-Sys... + + ROM Apps: 0=Monitor 1=BASIC 2=Forth 3=Game 4=CP/M 2.2 5=Z-System 6=Net Boot 7=User + + Sheet.80 + + + + Sheet.81 + + + + Sheet.82 + + + + Sheet.84 + Console + + Console + + Sheet.85 + + + + Sheet.86 + + + + Sheet.87 + + + + Sheet.88 + Boot + + Boot + + diff --git a/Source/Doc/Graphics/hd1k.pdf b/Source/Doc/Graphics/hd1k.pdf new file mode 100644 index 00000000..1bd7dd83 Binary files /dev/null and b/Source/Doc/Graphics/hd1k.pdf differ diff --git a/Source/Doc/Graphics/hd1k.png b/Source/Doc/Graphics/hd1k.png new file mode 100644 index 00000000..2b66b260 Binary files /dev/null and b/Source/Doc/Graphics/hd1k.png differ diff --git a/Source/Doc/Graphics/hd1k.svg b/Source/Doc/Graphics/hd1k.svg new file mode 100644 index 00000000..2581bfe1 --- /dev/null +++ b/Source/Doc/Graphics/hd1k.svg @@ -0,0 +1,1088 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page-1 + + + + Sheet.95 + 0 + + + + 0 + + Sheet.101 + 1 + + + + 1 + + Sheet.102 + 2 + + + + 2 + + Sheet.103 + 3 + + + + 3 + + Sheet.105 + . . . + + + + . . . + + Sheet.104 + N + + + + N + + Sheet.201 + + + + Sheet.69 + RomWBW Hard Disk Anatomy (Modern / hd1k) + + + + RomWBW Hard Disk Anatomy (Modern / hd1k) + + Sheet.106 + RomWBW Hard Disk (IDE/ATA/ATAPI/CF/SD/USB) + + + + RomWBW Hard Disk (IDE/ATA/ATAPI/CF/SD/USB) + + Sheet.107 + FAT Partition + + + + FAT Partition + + Sheet.119 + Sector 0 + + + + Sector 0 + + Sheet.120 + + + + Sheet.121 + + + + Sheet.122 + Type 2E + + + + Type 2E + + Sheet.123 + Type 06 + + + + Type 06 + + Sheet.124 + + + + Sheet.125 + + + + Sheet.126 + Partition Table + + + + Partition Table + + Sheet.131 + + + + Bracket.132 + + + + + + + Sheet.135 + + + + Sheet.139 + CP/M System Area (16 KB) + + + + CP/M System Area (16 KB) + + Sheet.141 + + + + Sheet.142 + + + + Sheet.143 + + + + Sheet.144 + + + + Sheet.165 + + + + Sheet.166 + + + + Sheet.167 + + + + Sheet.168 + + + + Stack pointer.179 + + + + + + + Sheet.202 + RomWBW Partition (8MB * N) + + + + RomWBW Partition (8MB * N) + + Sheet.205 + Prefix (1 MB typical) + + + + Prefix (1 MB typical) + + Dynamic connector + + + + Dynamic connector.207 + + + + Sheet.118 + MBR + + + + MBR + + Sheet.208 + + + + Sheet.128 + Slice (8 MB) + + + + Slice (8 MB) + + Bracket.146 + + + + + + + Sheet.581 + + + + Sheet.582 + CP/M File System (8,176 KB) + + + + CP/M File System (8,176 KB) + + Sheet.583 + + + + Sheet.590 + + + + Bracket.301 + + + + + + + Bracket.592 + + + + + + + diff --git a/Source/Doc/Graphics/hd512.pdf b/Source/Doc/Graphics/hd512.pdf new file mode 100644 index 00000000..30fed811 Binary files /dev/null and b/Source/Doc/Graphics/hd512.pdf differ diff --git a/Source/Doc/Graphics/hd512.png b/Source/Doc/Graphics/hd512.png new file mode 100644 index 00000000..63fdfdeb Binary files /dev/null and b/Source/Doc/Graphics/hd512.png differ diff --git a/Source/Doc/Graphics/hd512.svg b/Source/Doc/Graphics/hd512.svg new file mode 100644 index 00000000..c4cfa578 --- /dev/null +++ b/Source/Doc/Graphics/hd512.svg @@ -0,0 +1,236 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + Page-1 + + Sheet.69 + RomWBW Hard Disk Anatomy (Classic / hd512) + + RomWBW Hard Disk Anatomy (Classic / hd512) + + Sheet.259 + 0 + + 0 + + Sheet.260 + 1 + + 1 + + Sheet.261 + 2 + + 2 + + Sheet.262 + 3 + + 3 + + Sheet.263 + . . . + + . . . + + Sheet.264 + N + + N + + Sheet.265 + + + + Sheet.266 + RomWBW Hard Disk (IDE/ATA/ATAPI/CF/SD/USB) + + RomWBW Hard Disk (IDE/ATA/ATAPI/CF/SD/USB) + + Sheet.267 + FAT Partition + + FAT Partition + + Sheet.268 + Sector 0 + + Sector 0 + + Sheet.269 + + + + Sheet.270 + + + + Sheet.271 + Type 06 + + Type 06 + + Sheet.272 + + + + Sheet.273 + + + + Sheet.274 + + + + Sheet.275 + Partition Table + + Partition Table + + Sheet.276 + + + + Bracket.132 + + + + Sheet.278 + + + + Sheet.279 + CP/M System Area (128 KB) + + CP/M System Area (128 KB) + + Sheet.280 + + + + Sheet.281 + + + + Sheet.282 + + + + Sheet.283 + + + + Sheet.284 + + + + Sheet.285 + + + + Sheet.286 + + + + Sheet.287 + + + + Stack pointer.179 + + + + Sheet.289 + RomWBW Data (8,320 KB * N) + + RomWBW Data (8,320 KB * N) + + Dynamic connector.207 + + + + Sheet.294 + MBR + + MBR + + Sheet.295 + + + + Sheet.296 + Slice (8,320 KB) + + Slice (8,320 KB) + + Sheet.298 + + + + Sheet.299 + CP/M File System (8 MB) + + CP/M File System (8 MB) + + Sheet.300 + + + + Bracket.301 + + + + Bracket.302 + + + + diff --git a/Source/Doc/Makefile b/Source/Doc/Makefile index 11e4c600..04c8df4a 100644 --- a/Source/Doc/Makefile +++ b/Source/Doc/Makefile @@ -1,13 +1,19 @@ # -# NOTE: gpp, Pandoc, and Latex (MiKTeX or TexLive) must be installed +# NOTE: gpp, Pandoc, LuaLatex (MiKTeX or TexLive), and Roboto Font must be installed # and available on commandline for this build to work!!! -# Typically "sudo apt install gpp pandoc texlive-latex-extra texlive-luatex texlive-fonts-extra fonts-roboto" # -OBJECTS = ReadMe.gfm ReadMe.txt UserGuide.pdf SystemGuide.pdf Applications.pdf ROM_Applications.pdf Catalog.pdf Errata.pdf +# On MacOS: +# brew install gpp pandoc texlive +# brew install --cask font-roboto +# +# On Ubuntu Linux: +# apt install gpp pandoc texlive texlive-luatex texlive-fonts-extra +# +OBJECTS = ReadMe.gfm ReadMe.txt UserGuide.pdf SystemGuide.pdf Applications.pdf Catalog.pdf Errata.pdf # DEST = ../../Doc TOOLS = ../../Tools OTHERS = *.tmp - + include $(TOOLS)/Makefile.inc all :: deploy @@ -36,6 +42,5 @@ deploy : cp UserGuide.pdf "../../Doc/RomWBW User Guide.pdf" cp SystemGuide.pdf "../../Doc/RomWBW System Guide.pdf" cp Applications.pdf "../../Doc/RomWBW Applications.pdf" - cp ROM_Applications.pdf "../../Doc/RomWBW ROM Applications.pdf" cp Catalog.pdf "../../Doc/RomWBW Disk Catalog.pdf" - cp Errata.pdf "../../Doc/RomWBW Errata.pdf" + cp Errata.pdf "../../Doc/RomWBW Errata.pdf" diff --git a/Source/Doc/ROM_Applications.md b/Source/Doc/ROM_Applications.md deleted file mode 100644 index cfb8ae5f..00000000 --- a/Source/Doc/ROM_Applications.md +++ /dev/null @@ -1,635 +0,0 @@ -$define{doc_title}{ROM Applications}$ -$define{doc_author}{Phillip Summers}$ -$define{doc_authmail}{}$ -$include{"Book.h"}$ - -# Summary - -RomWBW includes a small selection of built in utilities and -programming languages. - -`\clearpage`{=latex} - -# RomWBW Monitor - -The Monitor program is a low level utility that can be used -for testing and programming. It allows programs to be entered, -memory to be examined, and input/output devices to be read or -written to. - -It's key advantage is that is available at boot up. - -Its key disadvantages are that code cannot be entered in assembly -language and there is no ability to save to memory devices. - -The available memory area for programming is `0200-EDFFh`. -The following areas are reserved: - -Memory Area | Function -------------|----------------------------------- -`0000-00FFh`| Jump and restart (RST) vectors -`0100-01FFh`| HBIOS configuration block -`EE00-FDFFh`| MONITOR -`FE00-FFFFh`| HBIOS proxy - -Commands can be entered at the command prompt `>` -Automatic case conversion takes place on command entry and all -arguments are expected to be in hex format. - -The current memory bank in low memory is displayed before the prompt i.e.: - -`8E>` - -The Monitor allows access to all memory locations but ROM and -Flash memory cannot be written to. Memory outside the normal -address range can be accessed using the B command. The first -256 bytes `0000-01FF` is critical for the HBIOS operation. -Changing banks may make this information inaccessible. - -Refer to the RomWBW Architecture manual for details memory banking. - -A quick guide to using the Monitor program follows: - -## ? - Displays a summary of available commands. - -``` -Monitor Commands (all values in hex): -B - Boot system -D xxxx [yyyy] - Dump memory from xxxx to yyyy -F xxxx yyyy zz - Fill memory from xxxx to yyyy with zz -H - Halt system -I xxxx - Input from port xxxx -K - Keyboard echo -L - Load Intel hex data -M xxxx yyyy zzzz - Move memory block xxxx-yyyy to zzzz -O xxxx yy - Output value yy to port xxxx -P xxxx - Program RAM at address xxxx -R xxxx [[yy] [zzzz]] - Run code at address xxxx - Pass yy and zzzz to register A and BC -T xxxx - X-modem transfer to memory location xxxx -S xx - Set bank to xx -X - Exit monitor -``` - -## Cold Boot - -B - Performs a cold boot of the ROMWBW system. A complete -re-initialization of the system is performed and the system -returns to the Boot Loader prompt. - -## Dump Memory - -D xxxx [yyyy] - Dump memory from hex location xxxx to yyyy -on the screen as lines of 16 hexadecimal bytes with their -ASCII equivalents (if within a set range, else a '.' is -printed). If the end address is omitted then 256 bytes is -displayed. - -A good tool to see where code is located, check -for version id, obtain details for chip configurations and -execution paths. - -Examples: `D 100 1FF` - -``` -0100: 10 0B 01 5A 33 45 4E 56 01 00 00 2A 06 00 F9 11 ...Z3ENV...*..ù. -0110: DE 38 37 ED 52 4D 44 0B 6B 62 13 36 00 ED B0 21 Þ87íRMD.kb.6.í°! -0120: 7D 32 E5 21 80 00 4E 23 06 00 09 36 00 21 81 00 }2Ã¥!..N#...6.!.. -0130: E5 CD 6C 1F C1 C1 E5 2A C9 8C E5 CD 45 05 E5 CD Ã¥Ãl.ÃÃÃ¥*É.Ã¥ÃE.åà -0140: 59 1F C3 00 00 C3 AE 01 C3 51 04 C3 4C 02 C3 57 Y.Ã..î.ÃQ.ÃL.ÃW -0150: 02 C3 64 02 C3 75 02 C3 88 02 C3 B2 03 C3 0D 04 .Ãd.Ãu.Ã..ò.Ã.. -0160: C3 19 04 C3 22 04 C3 2A 04 C3 35 04 C3 40 04 C3 Ã..Ã".Ã*.Ã5.Ã@.à -0170: 48 04 C3 50 04 C3 50 04 C3 50 04 C3 8F 02 C3 93 H.ÃP.ÃP.ÃP.Ã..Ã. -0180: 02 C3 94 02 C3 95 02 C3 85 04 C3 C7 04 C3 D1 01 .Ã..Ã..Ã..ÃÇ.ÃÑ. -0190: C3 48 02 C3 E7 04 C3 56 03 C3 D0 01 C3 D0 01 C3 ÃH.Ãç.ÃV.ÃÃ.ÃÃ.à -01A0: D0 01 C3 D0 01 C3 D0 01 C3 D0 01 01 02 01 CD 6B Ã.ÃÃ.ÃÃ.ÃÃ....Ãk -01B0: 04 54 68 69 73 20 66 75 6E 63 74 69 6F 6E 20 6E .This function n -01C0: 6F 74 20 73 75 70 70 6F 72 74 65 64 2E 0D 0A 00 ot supported.... -01D0: C9 3E FF 32 3C 00 3A 5D 00 FE 20 28 14 D6 30 32 É>ÿ2<.:].þ (.Ö02 -01E0: AB 01 32 AD 01 3A 5E 00 FE 20 28 05 D6 30 32 AC «.2­.:^.þ (.Ö02¬ -01F0: 01 C5 01 F0 F8 CF E5 26 00 0E 0A CD 39 02 7D 3C .Ã….ðøÃÃ¥&...Ã9.}< -``` - -## Fill Memory - -F xxxx yyyy zz - Fill memory from hex xxxx to yyyy with -a single value of zz over the full range. The Dump command -can be used to confirm that the fill completed as expected. A -good way to zero out memory areas before writing machine data -for debug purposes. - -## Halt System - -H - Halt system. A Z80 HALT instruction is executed. The -system remains in the halt state until the system is -physically rebooted. Interrupts will not restart the -system. On systems that support a HALT status LED, the -LED will be illuminated. - -## Input from port - -I xxxx - Input data from port xxxx and display to the screen. -This command is used to read values from hardware I/O ports -and display the contents in hexadecimal. - -## Keyboard Echo - -K - Echo any key-presses from the terminal. Press 'ESC' key -to quit. This facility provides that any key stroke sent to -the computer will be echoed back to the terminal. File down -loads will be echoed as well while this facility is ‘on’. - -## Load Hex format file into memory - -L - Load a Intel Hex format file via the terminal program. -The load address is defined in the hex file of the -assembled code. - -The terminal emulator program should be configured to -give a delay at the end of each line to allow the monitor -enough time to parse the line and move the data to memory. - -Keep in mind that this will be a transient unless the -system support battery backed memory. Saving to memory drive -is not supported. - -## Move memory - -M xxxx yyyy zzzz - Move hex memory block xxxx to yyyy to -memory starting at hex location zzzz. Care should be taken -to insure that there is enough memory at the destination so -that code does not get over-written or memory wrapped around. - -## Output to port - -O xxxx yy - Output data byte xx to port xxxx. This command is -used to send hexadecimal values to hardware I/O ports to -verify their operation and is the companion to the I operation. -Use clip leaded LEDs to confirm the data written. - -## Program memory location - -P xxxx - Program memory location xxxx. This routine will -allow you to program a hexadecimal value 'into memory starting -at location xxxx. Press 'Enter' on a blank line to -return to the Monitor prompt. - -The limitation around programming memory is that it must be -entered in hexadecimal. An alternative is to use the L command -to load a program that has been assembled to a hex file on the -remote computer. - -An excellent online resource for looking up opcodes for entry -can be found here: [https://clrhome.org/table](https://clrhome.org/table) - -## Run program - -R xxxx [[yy] [zzzz]] - Run program at location xxxx. If optional -arguments yy and zzzz are entered they are loaded into the -A and BC register respectively. The return address of the -Monitor is saved on the stack so the program can return -to the monitor. On return to the monitor, the contents of -the A, HL, DE and BC registers are displayed. - -## Set bank - -S xx - Change the bank in memory to xx. Memory addresses -0000-7FFF (i.e. bottom 32k) are affected. Because the -interrupt vectors are stored in the bottom page of this -range, this function is disable when interrupt mode 1 is -being used (IM1). Interrupt mode 2 is not affected as the -associated jump vectors are stored in high memory. - -Changing the bank also impacts the restart vectors (RST), -so executing code that call the HBIOS using the RST 08 -assembly code will not work. - -The monitor stack resides in high memory and is not affected -but any code that changes the stack to low memory will be -affected. - -### Bank codes and descriptions - -TYPE | DESCRIPTION |BANK| DETAILS ------|--------------------|----|--------------------- -RAM | COMMON BANK | 9F | 1024K RAM SYSTEM -RAM | USER BANK | 9E | 1024K RAM SYSTEM -RAM | BIOS BANK | 9D | 1024K RAM SYSTEM -RAM | AUX BANK | 9C | 1024K RAM SYSTEM -RAM | OS BUFFERS END | 9B | 1024K RAM SYSTEM -RAM | OS BUFFERS START | 98 | 1024K RAM SYSTEM -RAM | RAM DRIVE END | 97 | 1024K RAM SYSTEM -RAM | COMMON BANK | 8F | 512K RAM SYSTEM -RAM | USER BANK | 8E | 512K RAM SYSTEM -RAM | BIOS BANK | 8D | 512K RAM SYSTEM -RAM | AUX BANK | 8C | 512K RAM SYSTEM -RAM | OS BUFFERS | 8B | 512K RAM SYSTEM -RAM | OS BUFFERS | 8A | 512K RAM SYSTEM -RAM | OS BUFFERS | 89 | 512K RAM SYSTEM -RAM | OS BUFFERS | 88 | 512K RAM SYSTEM -RAM | RAM DRIVE END | 87 | 512K RAM SYSTEM -RAM | RAM DRIVE START | 80 | -ROM | BOOT BANK | 00 | COLD START & HBIOS -ROM | LOADER & IMAGES | 01 | MONITOR, FORTH -ROM | ROM IMAGES CONTD. | 02 | BASIC, ETC -ROM | FAT FILESYSTEM | 03 | UNA ONLY, ELSE UNUSED -ROM | ROM DRIVE START | 04 | -ROM | ROM DRIVE END | 0F | 512K ROM SYSTEM -ROM | ROM DRIVE END | 1F | 1024K ROM SYSTEM - -## X-modem transfer - -T xxxx - Receive an X-modem file transfer and load it into -memory starting at location xxxx. - -128 byte blocks and checksum mode is the only supported -protocol. - -If the monitor is assembled with the DSKY functionality, -this feature will be exclude due to space limitations. - - -## NOTES: - -The RTC utility on the CP/M ROM disk provides facilities -to manipulate the Real Time Clock non-volatile Memory. -Use the C or Z option from the Boot Loader to load CP/M -and then run RTC to see the options list. - -# FORTH - -CamelForth is the version of Forth included as part of the boot -ROM in ROMWBW. It has been converted from the Z80 CP/M version -published here [www.camelforth.com/page.php?5](www.camelforth.com/page.php?5). The author is Brad -Rodriguez who is a prolific Forth enthusiast, whose work can be -found here: [www.bradrodriguez/papers/index.html](www.bradrodriguez/papers/index.html) - -For those are who are not familiar with Forth, I recommend the -wikipedia article [en.wikipedia.org/wiki/Forth_(programming_language](en.wikipedia.org/wiki/Forth_(programming_language)) -and the Forth Interest Group website [www.forth.org](www.forth.org) - -## Important things to know - -Forth is case sensitive. - -To exit back to the boot loader type ***bye*** - -To get a list of available words type ***WORDS*** - -To reset Forth to its initial state type ***COLD*** - -Most of the code you find on the internet will not run unless modified or additional Forth -words are added to the dictionary. - -This implementation does not support loading or saving of programs. All programs -need to be typed in. Additionally, screen editing and code blocks are not supported. - -## Structure of Forth source files - -File | Description ---------------|----------------------------- -camel80.azm | Code Primitives - camel80d.azm | CPU Dependencies - camel80h.azm | High Level words - camel80r.azm | ROMWBW additions -glosshi.txt | Glossary of high level words -glosslo.txt | Glossary of low level words -glossr.txt | Glossary of ROMWBW additions - -## ROMWBW Additions - -Extensions and changes to this implementation compared to the original distribution are: - -The source code has been converted from Z80mr assembler to Hector Peraza's zsm. - -An additional file camel80r.azm has been added for including additional words to -the dictionary at build time. However, as currently configured there is very little space -allocated for addition words. Exceeding the allocated ROM space will generate an error -message when building. - -James Bowman's double precision words have been added from his RC2014 version: -[https://github.com/jamesbowman/camelforth-z80](https://github.com/jamesbowman/camelforth-z80) - -Word | Syntax | Description ---------|----------------------------|--------------------------------- -D+ | d1 d2 -- d1+d2 | Add double numbers -2>R | d -- | 2 to R -2R> | d -- | fetch 2 from R -M*/ | d1 n2 u3 -- d=(d1*n2)/u3 | double precision mult. div -SVC | hl de bc n -- hl de bc af | Execute a ROMWBW function -P! | n p -- | Write a byte to a I/O port -P@ | p -- n | Read a byte from and I/O port - -# BASIC - -For those who are not familiar with BASIC, it stands for Beginners All purpose Symbolic -Instruction Code. - -ROMWBW contains two versions of ROM BASIC, a full implementation and a "tiny" BASIC. - -The full implementation is a version of Microsoft BASIC from the NASCOM Computer. - -A comprehensive instruction manual is available in the Doc\\Contrib directory. - -## ROMWBW specific features - -- Sound -- Graphics -- Terminal Support - -## ROMWBW unsupported features - -- This ROM-hosted implementation does not support cassette or disk - access for loading and saving programs. - -# TastyBASIC - -TastyBASIC offers a minimal implementation of BASIC that is only 2304 bytes in size. -It originates from Li-Chen Wang's Palo Alto Tiny BASIC from around 1976. It's small size suited the tiny memory capacities of the time. This implementation is by Dimitri Theulings and his -original source can be found here [https://github.com/dimitrit/tastybasic](https://github.com/dimitrit/tastybasic) - -## Features / Limitations - -- This ROM-hosted implementation does not support disk access for - loading and saving programs. -- Integer arithmetic, numbers -32767 to 32767 -- Singles letter variables A-Z -- 1-dimensional array support -- Strings are not supported - -## Direct Commands - -- `LIST`,`RUN`, `NEW`, `CLEAR`, `BYE` - -## Statements - -- `LET`, `IF`, `GOTO`, `GOSUB RETURN`, `REM`, `FOR TO NEXT STEP`, `INPUT`, `PRINT`, `POKE`, `END` - -## Functions - -- `PEEK`, `RND`, `ABS`, `USR`, `SIZE` - -## Operators - -- `>=`, `#`, `>`, `=`, `<=`, `<` - -- Operator precedence is supported. - -Type ***BYE*** to return to the monitor. - -# Play a Game - -## 2048 - -2048 is a puzzle game that can be both mindless and challenging. It -appears deceptively simple but failure can creep up on you suddenly. - -It requires an ANSI/VT-100 compatible colour terminal to play. - -2048 is like a sliding puzzle game except the puzzle tiles are -numbers instead of pictures. Instead of moving a single tile all -tiles are moved simultaneously in the same direction. Where two -tiles of the same number collide, they are reduced to one tile with -the combined value. After every move a new tile is added with -a starting value of 2. - -The goal is to create a tile of 2048 before all tile locations are -occupied. Reaching the highest points score, which is the sum of all -the tiles is a secondary goal. The game will automatically end when -there are no more possible moves. - -Play consists of entering a direction to move. Directions can be entered -using any of three different keyboard direction sets. - -``` -Direction | Keys -----------|---------- -Up | w ^E 8 -Down | s ^X 2 -Left | a ^S 4 -Right | d ^D 6 -``` -The puzzle board is a 4x4 grid. At start, the grid will be populated -with two 2 tiles. An example game sequence is shown below with new -tiles to the game shown in brackets. - -``` -Start Move 1 - Up Move 2 - Left Move 3 - Left -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| | | |(2)| | | | | 4 | | 4 | | | | | 4 | | | | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| | | | | | | | | | | | | |(4)| | 4 | | | | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| | | |(2)| | | | | | | | | | | | | | | | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| | | | | | | |(2)| | | 2 | | | | | 2 | |(2)| | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ - -Move 4 - Left Move 5 - Up Move 6 - Right Move 7 - Up -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| 4 | | | | | 8 | | | 4 | | | | 8 | 4 | | | | 8 | 8 | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| 4 | | |(4)| | 4 | | | | | | | | 4 | | | | | 2 | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| | | | | | | | | | | | | | | | | | | | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -| 4 | | | | |(2)| | | | |(2)| | | 2 | |(2)| | | | -+---+---+---+---+ +---+---+---+---+ +---+---+---+---+ +---+---+---+---+ -``` -This is how I lost this game: -``` -+---+---+---+---+ -| 4 | 2 | 16| 4 | -+---+---+---+---+ -| 32| 64| 8 | 2 | -+---+---+---+---+ -| 4 | 8 |128| 32| -+---+---+---+---+ -|(2)| 16| 8 | 4 | -+---+---+---+---+ -``` -Press Q at any time to bring up the option to Quit or Restart the game. - -# Network Boot - -# Xmodem Flash Updater - -The ROMWBW Xmodem flash updater provides the capability to update ROMWBW from the boot loader using an x-modem file transfer. It offers similar capabilities to Will Sowerbutts FLASH4 utility except that the flashing process occurs during the file transfer. - -These are the key differences between the two methods are: - -Xmodem Flash Updater | FLASH4 ---------------------------------|----------------- -Available from the boot loader | Well proven and tested -Xmodem transfer is integrated | Wider range of supported chips and hardware -Integrated checksum utilities | Wider range of supported platforms -Capability to copy a ROM image | Only reprograms sectors that have changed -More convenient one step process | Ability save and verify ROM images -No intermediate storage required | Progress display while flashing -. | Displays chip identification information -. | Faster file transfer - -The major disadvantages of the Updater is that it is new and relatively untested. There is the risk that a failed transfer will result in a partially flashed and unbootable ROM. There are some limitations on serial transfer speeds. - -The updater utility was initially intended to support the Retrobrew SBC-V2-005 platform using Atmel 39SF040 flash chips but has now been extended to be more generic in operation. - -Supported flash chips are -39SF040, 29F040, AT49F040, AT29C040, M29F040 , MX29F040, A29010B, A29040B - -The Atmel 39SF040 chip is recommended as it can erase and write 4Kb sectors. Other chips require the whole chip to be erased. - -## Usage - -In most cases, completing a ROM update is a simple as: - -1. Booting to the boot loader prompt -2. Selecting option X - Xmodem Flash Updater -3. Selecting option U - Update -4. Initiating an X-modem transfer of your ROM image on your console device -5. Selecting option R - Reboot - -If your console device is not able to transfer a ROM image i.e. your console is a VDU then you will have to use the console options to identify which character-input/output device is to be used as the serial device for transfer. - -When your console is the serial device used for the transfer, no progress information is displayed as this would disrupt the x-modem file transfer. If you use an alternate character-input/output devices as the serial device for the transfer then progress information will be displayed on the console device. - -Due to different platform processor speeds, serials speeds and flow control capabilities the default console or serial device speed may need to be reduced for a successful transfer and flash to occur. The **Set Console Interface/Baud code** option at the Boot Loader can be used to change the speed if required. Additionally, the Updater has options to set to and revert from a recommended speed. - -See the ROMWBW Applications guide for additional information on performing upgrades. - -## Console Options - -Option ( C ) - Set Console Device - -Option ( S ) - Set Serial Device - -By default the updater assumes that the current console is a serial device and that the ROM file to be flashed will also be transferred across this device, so the Console and Serial device are both the same. - -Either device can be can be change to another character-input/output device but the updater will always expect to receive the x-modem transfer on the **Serial Device** - -The advantage of transferring on a different device to the console is that progress information can be displayed during the transfer. - -Option ( > ) - Set Recommended Baud Rate - -Option ( < ) - Revert to Original Baud Rate - -## Programming options - -Option ( U ) - Begin Update - -The will begin the update process. The updater will expect to start receiving -an x-modem file on the serial device unit. - -X-modem sends the file in packets of 128 bytes. The updater will cache 32 -packets which is 1 flash sector and then write that sector to the -flash device. - -If using separate console, bank and sector progress information will shown - -``` -BANK 00 s00 s01 s02 s03 s04 s05 s06 s06 s07 -BANK 01 s00 s01 s02 s03 s04 s05 s06 s06 s07 -BANK 02 s00 s01 s02 s03 s04 s05 s06 s06 s07 etc -``` - -The x-modem file transfer protocol does not provide any filename or size -information for the transfer so the updater does not perform any checks -on the file suitability. - -The updater expects the file size to be a multiple of 4 kilobytes and -will write all data received to the flash device. A system update -file (128kb .img) or complete ROM can be received and written (512kb or -1024kb .rom) - -If the update fails it is recommended that you retry before rebooting or -exiting to the Boot loader as your machine may not be bootable. - -Option ( D ) - Duplicate flash #1 to flash #2 - -This option will make a copy of flash #1 onto flash #2. The purpose of this is to enable - making a backup copy of the current flash. Intended for systems using 2x512Kb Flash devices. - -Option ( V ) - Toggle Write Verify - -By default each flash sector will be verified after being written. Slight -performance improvements can be gained if turned off and could be used if -you are experiencing reliable transfers and flashing. - -## Exit options - -Option ( R ) - Reboot - -Execute a cold reboot. This should be done after a successful update. If -you perform a cold reboot after a failed update then it is likely that -your system will be unusable and removing and reprogramming the flash -will be required. - -Option ( Q ) - Quit to boot loader. - -The SBC Boot Loader is reloaded from ROM and -executed. After a successful update a Reboot should be performed. However, -in the case of a failed update this option could be used to attempt to -load CP/M and perform the normal x-modem / flash process to recover. - -## CRC Utility options - -Option ( 1 ) and ( 2 ) - Calculate and display CRC32 of 1st or 2nd 512k ROM. -Option ( 3 ) - Calculate and display CRC32 of a 1024k (2x512Kb) ROM. - -Can be used to verify if a ROM image has been transferred and flashed correctly. Refer to the Teraterm section below for details on configuring the automatic display of a files CRC after it has been transferred. - -In Windows, right clicking on a file should also give you a context menu option CRC SHA which will allow you to select a CRC32 calculation to be done on the selected file. - -## Tera Term macro configuration - -Macros are a useful tool for automatic common tasks. There are a number of instances where using macros to facilitate the update process could be worthwhile if you are: - -* Following the ROMWBW development builds. -* Doing lots of configuration changes. -* Doing development on ROMWBW drivers - -Macros can be used to automate sending ROM updates or images and for my own purposed I have set up a separate macro for transferring each of the standard build ROM, my own custom configuration ROM and update ROM. - -An example macro file to send an *.upd file, using checksum mode and display the crc32 value of the transmitted file: - -``` -Xmodem send, checksum, display crc32 -xmodemsend '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.upd' 1 -crc32file crc '\\desktop\users\phillip\documents\github\romwbw\binary\sbc_std_cust.rom' -sprintf '0x%08x' crc -messagebox inputstr 'crc32' -``` - -## Serial speed guidelines - -As identified in the introduction, there are limitations on serial speed depending on processor speed and flow control settings. Listed below are some of the results identified during testing. - -Platform / Configuration | Processor Speed | Maximum Serial Speed --------------------------------|-----------------|--------------------- -SBC-V2 UART no flow control | 2mhz | 9600 -SBC-V2 UART no flow control | 4mhz | 19200 -SBC-V2 UART no flow control | 5mhz | 19200 -SBC-V2 UART no flow control | 8mhz | 38400 -SBC-V2 UART no flow control | 10mhz | 38400 -SBC-V2 USB-FIFO 2mhz+ | | n/a -SBC-MK4 ASCI no flow control | 18.432mhz | 9600 -SBC-MK4 ASCI with flow control | 18.432mhz | 38400 - -The **Set Recommend Baud Rate** option in the Updater menu follows the following guidelines. - -Processor Speed | Baud Rate -----------------|---------- -1Mhz | 4800 -2-3Mhz | 9600 -4-7Mhz | 19200 -8-20Mhz | 38400 - -These can be customized in the updater.asm source code in the CLKTBL table if desired. -Feedback to the ROMWBW developers on these guidelines would be appreciated. - -## Notes: -- All testing was done with Teraterm x-modem, Forcing checksum mode using macros was found to give the most reliable transfer. -- Partial writes can be completed with 39SF040 chips. Other chips require entire flash to be erased before being written. -- An SBC V2-005 MegaFlash or Z80 MBC required for 1mb flash support. The Updater assumes both chips are same type -- Failure handling has not been tested. -- Timing broadly calibrated on a Z80 SBC-v2 -- UNA BIOS not supported diff --git a/Source/Doc/ReadMe.md b/Source/Doc/ReadMe.md index 61783118..aff3f449 100644 --- a/Source/Doc/ReadMe.md +++ b/Source/Doc/ReadMe.md @@ -114,7 +114,6 @@ Documentation for $doc_product$ includes: * $doc_user$ * $doc_sys$ * $doc_apps$ -* $doc_romapps$ * $doc_errata$ # Acknowledgments @@ -188,6 +187,9 @@ please let me know if I missed you! compendium. * Martin R has provided substantial help reviewing and improving the + User Guide and Applications documents. + +* Mark Pruden has also contributed a great deal of content to the User Guide. * Jacques Pelletier has contributed the DS1501 RTC driver code. diff --git a/Source/Doc/RomWBW Disk Layouts.xlsx b/Source/Doc/RomWBW Disk Layouts.xlsx new file mode 100644 index 00000000..ccfebb5f Binary files /dev/null and b/Source/Doc/RomWBW Disk Layouts.xlsx differ diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md index 07e32b77..cd8fbc98 100644 --- a/Source/Doc/SystemGuide.md +++ b/Source/Doc/SystemGuide.md @@ -126,6 +126,243 @@ execution. ![Bank Switched Memory Layout](Graphics/BankSwitchedMemory){ width=100% } + +## Bank Id + +RomWBW utilizes a specific assignment of memory banks for dedicated +purposes. A numeric Bank Id is used to refer to the memory banks. The +Bank Id is a single byte. In general, the Bank Id simply refers to each +of the 32K banks in sequential order. In other words, Bank Id 0 is the +first physical 32K, Bank Id 1 is the second, etc. However, the high +order bit of the Bank Id has a special meaning. If it is 0, it indicates +a ROM bank is being referred to. If it is 1, it indicates a RAM bank +is being referred to. + +For example, let's say we have a typical system with 512KB of ROM and +512KB of RAM. The Bank Ids would look like this: + +| Physical Memory | Type | Physical Bank | Bank Id | +|-------------------|------|---------------|-----------| +| 0x000000-0x007FFF | ROM | 0 | 0x00 | +| 0x008000-0x00FFFF | ROM | 1 | 0x01 | +| 0x010000-0x07FFFF | ROM | 2-15 | 0x02-0x0F | +| 0x080000-0x087FFF | RAM | 16 | 0x80 | +| 0x088000-0x08FFFF | RAM | 17 | 0x81 | +| 0x090000-0x0FFFFF | RAM | 18-31 | 0x82-0x8F | + +Note that Bank Id 0x00 is **always** the first bank of ROM and 0x80 is +**always** the first bank of RAM. If there were more banks of physical ROM, +they would be assigned Bank Ids starting with 0x10. Likewise, additional +bank of physical RAM would be assigned Bank Ids starting with 0x90. + +The Bank Id is used in all RomWBW API functions when referring to +the mapping of banks to the lower 32K bank area of the processor. In +this way, all RomWBW functions can refer to a generic Bank Id without +needing to understand how a specific hardware platform accesses the +physical memory areas. A single routine within the HBIOS is implemented +for each memory manager that maps Bank Ids to physical memory. + +## Bank Assignments + +RomWBW requires dedicated banks of memory for specific purposes. It +uses Bank Ids via an algorithm to make these assignments. The following +table describes the way the banks are assigned. The Typical column +shows the specific values that would be assigned for a common system +with 512KB of ROM and 512KB of RAM (nROM=16, nRAM=16). + +| Bank Id | Identity | Typical | Purpose | +|-------------------|-----------|---------|------------------------------------------| +| 0x00 |BID_BOOT | 0x00 | Boot Bank (HBIOS image) | +| 0x01 |BID_IMG0 | 0x01 | Boot Loader, Monitor, ROM OSes, ROM Apps | +| 0x02 |BID_IMG1 | 0x02 | ROM Apps | +| 0x03 |BID_IMG2 | 0x03 | \ | +| 0x04 |BID_ROMD0 | 0x04 | First ROM Disk Bank | +| nROM - 1 | | 0x0F | Last ROM Disk Bank | +| 0x80 |BID_BIOS | 0x80 | HBIOS (working copy) | +| 0x81 |BID_RAMD0 | 0x81 | First RAM Disk Bank | +| 0x80 + nRAM - 8 | | 0x88 | Last RAM Disk Bank | +| 0x80 + nRAM - 7 |BID_APP0 | 0x89 | First Application Bank | +| 0x80 + nRAM - 5 | | 0x8B | Last Application Bank | +| 0x80 + nRAM - 4 |BID_BUF | 0x8C | OS Disk Buffers | +| 0x80 + nRAM - 3 |BID_AUX | 0x8D | OS Code Bank | +| 0x80 + nRAM - 2 |BID_USR | 0x8E | User Bank (CP/M TPA) | +| 0x80 + nRAM - 1 |BID_COM | 0x8F | Common Bank | + +In this table, nROM and nRAM refer to the number of corresponding +ROM and RAM banks in the the system. + +The contents of the banks referred to above are described in more detail +below: + +Boot Bank: + +: The Boot Bank receives control when a system is first powered +on. It contains a ROM (read-only) copy of the HBIOS. At boot, it does +minimal hardware initialization, then copies itself to the HBIOS bank +in RAM, then resumes execution from the RAM bank. + +Boot Loader: + +: The application that handles loading of ROM or Disk based applications +including operating systems. It copies itself to a RAM bank at the +start of it's execution. + +Monitor: + +: The application that implements the basic system monitor functions. +It copies itself to a RAM bank at the start of it's execution. + +ROM OSes: + +: Code images of CP/M 2.2 and Z-System which are copied to RAM and +executed when a ROM-based operating system is selected in the Boot +Loader. + +ROM Applications: + +: Various ROM-based application images such as BASIC, FORTH, etc. They +can be selected in the Boot Loader. The Boot Loader will copy the +application image to a RAM bank, then transfer control to it. + +ROM Disk: + +: A sequential series of banks assigned to provide the system ROM Disk +contents. + +HBIOS: + +: This bank hosts the running copy of the RomWBW HBIOS. + +RAM Disk: + +: A sequential series of banks assigned to provide the system RAM Disk. + +Application Bank: + +: A sequential series of banks that are available for use by applications +that wish to utilize banked memory. + +OS Disk Buffers: + +: This bank is used by CP/M 3 and ZPM3 for disk buffer storage. + +OS Code Bank: + +: This bank is used by CP/M 3 and ZPM3 as an alternate bank for code. +This allows these operating systems to make additional TPA space +available for applications. + +User Bank: + +: This is the default bank for applications to use. This includes the +traditional TPA space for CP/M. + +Common Bank: + +: This bank is mapped to the upper 32K of the processors memory space. +It is a fixed mapping that is never changed in normal RomWBW operation +hence the name "Common". + +# Disk Layout + +RomWBW supports two hard disk layouts: the Classic layout used by +RomWBW with 512 directory entries per slice and a Modern layout with +1024 directory entries per slice. These layouts are referred to as +hd512 and hd1k respectively. + +WARNING: You **can not** mix the two hard disk layouts on one hard +disk device. You can use different layouts on different hard disk +devices in a single system though. + +RomWBW determines which of the hard disk layouts to use for a given +hard disk device based on whether there is a RomWBW hard disk +partition on the disk containing the slices. If there is no RomWBW +partition, then RomWBW will assume the 512 directory entry format for +all slices and will assume the slices start at the first sector of +the hard disk. If there is a RomWBW partition on the hard disk +device, then RomWBW will assume the 1024 directory entry format for +all slices and will assume the slices are located in the defined +partition. + +RomWBW supports up to 256 CP/M slices (0-255). Under hd512, the slices +begin at the start of the hard disk. Under hd1k, the slices reside +within partition type 0x2E. + +RomWBW accesses all hard disks using Logical Block Addressing (pure +sector offset). When necessary, RomWBW simulates the following disk +geometry for operating systems: + +- Sector = 512 Bytes +- Track = 16 Sectors (8KB per Track) +- Cylinder = 16 Tracks (256 Sectors per Cylinder, 128KB per Cylinder) + +If one is used, the FAT Partition must not overlap the CP/M slices. +The FAT partition does not need to start immediately after the CP/M +slices nor does it need to extend to the end of the hard disk. Its +location and size are entirely determined by its corresponding +partition table entry. + +Drive letters in CP/M are ASSIGNed to the numbered slices as desired. +At boot, RomWBW automatically assigns up to 8 slices to drive letters +starting with the first available drive letter (typically C:). + +Microsoft Windows will assign a single drive letter to the FAT partition +when the CF/SD Card is inserted. The drive letter assigned has no +relationship to the CP/M drive letters assigned to CP/M slices. + +In general, Windows, MacOS, or Linux know nothing about the CP/M slices +and CP/M knows nothing about the FAT partition. However, the FAT +application can be run under CP/M to access the FAT partition +programmatically. + +A CP/M slice is (re)initialized using the CP/M command CLRDIR. A CP/M +slice can be made bootable by copying system image to the System Area +using SYSCOPY. + +The FAT partition can be created from CP/M using the FDISK80 application. + +The FAT partition can be initialized using the FAT application from CP/M +using the command `FAT FORMAT n:` where n is the RomWBW disk unit +number containing the FAT partition to be formatted. + +## Modern Disk Layout (hd1k) + +![Modern Disk Layout](Graphics/hd1k) + +The CP/M filesystem on a Modern disk will accommodate 1,024 directory +entries. + +The CP/M slices reside entirely within a hard disk partition of type +0x2E. The number of slices is determined by the number of slices that +fit within the partition spaces allocated up to the maximum of 256. + +## Classic Disk Layout (hd512) + +![Classic Disk Layout](Graphics/hd512) + +The CP/M filesystem on a Classic disk will accommodate 512 directory +entries. + +The CP/M slices reside on the hard disk starting at the first sector +of the hard disk. The number of CP/M slices is not explicitly recorded +anywhere on the hard disk. It is up to the system user to know how +many slices are being used based on the size of the hard disk media +and/or the start of a FAT partition. + +A partition table may exist within the first sector of the first +slice. For Classic disks, the partition table defines only the +location and size of the FAT partition. The Partition Table does +not control the location or number of CP/M slices in any way. + +The Partition Table resides in a sector that is shared with the System +Area of CP/M Slice 0. However, the RomWBW implementation of CP/M takes +steps to avoid changing or corrupting the Partition Table area. + +The FAT partition can be created from CP/M using the FDISK80 +application. The user is responsible for ensuring that the start of the +FAT partition does not overlap with the area they intend to use for +CP/M slices. FDISK80 has a Reserve option to assist with this. + # System Boot Process A multi-phase boot strategy is employed. This is necessary because at @@ -410,7 +647,7 @@ below enumerates these values. | CIODEV_ESPCON | 0x0B | ESP32 VGA Console | esp.asm | | CIODEV_ESPSER | 0x0B | ESP32 Serial Port | esp.asm | | CIODEV_SCON | 0x0B | S100 Console | scon.asm | -| CIODEV_EZ80UART | 0x10 | eZ80 Built-in UART0 Interface | ez80uart.asm | +| CIODEV_EZ80UART | 0x11 | eZ80 Built-in UART0 Interface | ez80uart.asm | Character devices can usually be configured with line characteristics such as speed, framing, etc. A word value (16 bit) is used to describe @@ -611,12 +848,19 @@ more of the defined media types. | MID_FD111 | 9 | 8" 1.11M Floppy | | MID_HD1K | 10 | Hard Disk (LBA) w/ 1024 directory entries | +**NOTE**: HBIOS does not actually differentiate between MID_HD512 and +MID_HD1K. The use of these two formats is determined by the use of a +partition table on the media and is implemented by the operating +system itself. HBIOS treats all hard disks as raw sectors. See +[Function 0x18 -- Disk Media (DIOMEDIA)] for more information on the +Media ID byte returned. + HBIOS supports both Cylinder/Head/Sector (CHS) and Logical Block Addresses (CHS) when locating a sector for I/O (see DIOSEEK function). For devices that are natively CHS (e.g., floppy disk), the HBIOS driver can convert LBA values to CHS values according to the geometry of the current media. For devices that are natively LBA (e.g., hard disk), the - HBIOS driver simulates CHS using a fictitious geometry provided by the +HBIOS driver simulates CHS using a fictitious geometry provided by the driver (typically 16 sectors per track and 16 heads per cylinder). ### Function 0x10 -- Disk Status (DIOSTATUS) @@ -829,6 +1073,12 @@ Report the Media ID (E) for the for media in the specified Disk Unit will be performed. The Status (A) is a standard HBIOS result code. If there is no media in device, function will return an error status. +**NOTE**: This function will always return MID_HD512 for hard disk +devices. MID_HD1K is provided for use internally by operating systems +that provide different filsystem formats depending on the partition +table. This function cannot be used to determine if an HD1K formatted +partition exists on the hard disk. + ### Function 0x19 -- Disk Define Media (DIODEFMED) | **Entry Parameters** | **Returned Values** | @@ -862,7 +1112,7 @@ DIOMEDIA function to force this if desired. | **Entry Parameters** | **Returned Values** | |----------------------------------------|----------------------------------------| | B: 0x1B | A: Status | -| C: Disk Unit | D: Heads | +| C: Disk Unit | D: Heads / LBA | | | E: Sectors | | | HL: Cylinder Count | | | BC: Block Size | @@ -872,7 +1122,11 @@ device uses LBA mode addressing natively, then the drivers simulated geometry will be returned. The Status (A) is a standard HBIOS result code. If the media is unknown, an error will be returned. -Heads (D) refers to the number of heads per cylinder. Sectors (E) +LBA capability is indicated by D:7. When set, the device is capable +of LBA addressing. Refer to [Function 0x12 -- Disk Seek (DIOSEEK)] +for more information on specifying LBA vs. CHS addresses. + +Heads (D:6-0) refers to the number of heads per cylinder. Sectors (E) refers to the number of sectors per track. Cylinder Count (HL) is the total number of cylinders addressable for the media. Block Size (BC) is the number of bytes in one sector. @@ -897,7 +1151,7 @@ unit. The table below enumerates these values. | RTCDEV_INT | 0x03 | Interrupt-based Real Time Clock | intrtc.asm | | RTCDEV_DS7 | 0x04 | Maxim DS1307 PCF I2C RTC w/ NVRAM | ds7rtc.asm | | RTCDEV_RP5 | 0x05 | Ricoh RPC01A Real-Time Clock w/ NVRAM | rp5rtc.asm | -| RTCDEV_EZ80 | 0x06 | eZ80 on-chip RTC | ez80rtc.asm | +| RTCDEV_EZ80 | 0x07 | eZ80 on-chip RTC | ez80rtc.asm | The time functions to get and set the time (RTCGTM and RTCSTM) require a 6 byte date/time buffer in the following format. Each byte is BCD @@ -1881,7 +2135,7 @@ sound will play for the duration defined in HL and then return. | **Entry Parameters** | **Returned Values** | |----------------------------------------|----------------------------------------| | B: 0x57 | A: Status | -| C: Disk Unit | C: Device Attributes | +| C: Sound Unit | C: Device Attributes | | | D: Device Type | | | E: Device Number | | | H: Device Unit Mode | @@ -1904,6 +2158,17 @@ is servicing the specified unit. Both of these values are considered driver specific. Refer to the associated hardware driver for the values used. +### Function 0x58 -- Sound Beep (SNDBEEP) + +| **Entry Parameters** | **Returned Values** | +|----------------------------------------|----------------------------------------| +| B: 0x58 | A: Status | +| C: Sound Unit | | + +Play a beep tone on the specified Sound Unit (C). The beep will +normally be about 1/3 second in duration and the tone will be +approximately B5. + `\clearpage`{=latex} ## System (SYS) @@ -1964,7 +2229,6 @@ The hardware Platform (L) is identified as follows: | PLT_MK4 |5 | MARK IV | | PLT_UNA |6 | UNA BIOS | | PLT_RCZ80 |7 | RCBUS W/ Z80 | -| PLT_RCEZ80 |7 | RCBUS W/ eZ80 | | PLT_RCZ180 |8 | RCBUS W/ Z180 | | PLT_EZZ80 |9 | EASY/TINY Z80 | | PLT_SCZ180 |10 | RCBUS SC126, SC130, SC131, SC140 | @@ -1975,6 +2239,7 @@ The hardware Platform (L) is identified as follows: | PLT_Z80RETRO |15 | Z80 RETRO COMPUTER | | PLT_S100 |16 | S100 COMPUTERS Z180 | | PLT_DUO |17 | DUODYNE Z80 SYSTEM | +| PLT_RCEZ80 |24 | RCBUS W/ eZ80 | ### Function 0xF2 -- System Set Bank (SYSSETBNK) @@ -2265,6 +2530,9 @@ a double-word binary value. The frequency of the system timer in Hertz is returned in Frequency (C). The returned Status (A) is a standard HBIOS result code. +The tick count is a 32 bit binary value. It will rollover to zero +if the maximum value for a 32 bit number is reached. + Note that not all hardware configuration have a system timer. You can determine if a timer exists by calling this function repeatedly to see if it is incrementing. @@ -2275,14 +2543,19 @@ to see if it is incrementing. |----------------------------------------|----------------------------------------| | B: 0xF8 | A: Status | | C: 0xD1 | DEHL: Seconds Count | -| | C: Ticks per Second | +| | C: Remainder Ticks | -Return the a Seconds Count (DEHL) with the number of seconds that have +Return the Seconds Count (DEHL) with the number of seconds that have elapsed since the system was started. This is a double-word binary -value. Additionally, the number of Ticks per Second (C) is returned. -The returned Status (A) is a standard HBIOS result code. +value. Additionally, Remainder Ticks (C) is returned and contains the number +of ticks that have elapsed within the current second. + +Note that Remainder Ticks (C) will have a value from 0 to 49 since there are +50 ticks per second. So, Remainder Ticks does not represent a fraction of the +current second. Remainder Ticks (C) can be doubled to derive the hundredths of +milliseconds elapsed within the current second. -This availability of the Seconds Count (DEHL) is dependent on having a +The availability of the Seconds Count (DEHL) is dependent on having a system timer active. If the hardware configuration has no system timer, then Seconds Count (DEHL) will not increment. diff --git a/Source/Doc/UserGuide.md b/Source/Doc/UserGuide.md index d6102efc..91dced48 100644 --- a/Source/Doc/UserGuide.md +++ b/Source/Doc/UserGuide.md @@ -11,11 +11,8 @@ companion documents you should refer to as appropriate: of RomWBW. It includes a reference for the RomWBW HBIOS API functions. -* $doc_romapps$ is a reference for the ROM-hosted applications provided - with RomWBW including the monitor, programming languages, etc. - -* $doc_apps$ is a reference for the OS-hosted proprietary command - line applications that were created to enhance RomWBW. +* $doc_apps$ is a reference for the ROM-hosted and OS-hosted applications + created or customized to enhance the operation of RomWBW. * $doc_catalog$ is a reference for the contents of the disk images provided with RomWBW. It is somewhat out of date at this time. @@ -225,45 +222,47 @@ by RomWBW along with the standard pre-built ROM image(s). RomWBW does allow for the creation of ROM images with custom configurations. This is discussed in [Customizing RomWBW]. -| **Description** | **Bus** | **ROM Image File** | **Baud Rate** | -|----------------------------------------------------------------|---------|-----------------------|--------------:| -| [RetroBrew Z80 SBC]^1^ | ECB | SBC_std.rom | 38400 | -| [RetroBrew Z80 SimH]^1^ | - | SBC_simh.rom | 38400 | -| [RetroBrew N8 Z180 SBC]^1^ (date code >= 2312) | ECB | N8_std.rom | 38400 | -| [Zeta Z80 SBC]^2^, ParPortProp | - | ZETA_std.rom | 38400 | -| [Zeta V2 Z80 SBC]^2^, ParPortProp | - | ZETA2_std.rom | 38400 | -| [Mark IV Z180 SBC]^3^ | ECB | MK4_std.rom | 38400 | -| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 | -| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM, KIO | RCBus | RCZ80_kio.rom | 115200 | -| [RCBus Z180 CPU Module]^4^ w/ external banking | RCBus | RCZ180_ext.rom | 115200 | -| [RCBus Z180 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat.rom | 115200 | -| [RCBus Z280 CPU Module]^4^ w/ external banking | RCBus | RCZ180_ext.rom | 115200 | -| [RCBus Z280 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat.rom | 115200 | -| [Easy Z80 SBC]^2^ | RCBus | RCZ80_easy.rom | 115200 | -| [Tiny Z80 SBC]^2^ | RCBus | RCZ80_tiny.rom | 115200 | -| [Z80-512K CPU/RAM/ROM Module]^2^ | RCBus | RCZ80_skz.rom | 115200 | -| [Small Computer SC126 Z180 SBC]^5^ | BP80 | SCZ180_sc126.rom | 115200 | -| [Small Computer SC130 Z180 SBC]^5^ | RCBus | SCZ180_sc130.rom | 115200 | -| [Small Computer SC131 Z180 Pocket Computer]^5^ | - | SCZ180_sc131.rom | 115200 | -| [Small Computer SC140 Z180 CPU Module]^5^ | Z50 | SCZ180_sc140.rom | 115200 | -| [Small Computer SC503 Z180 CPU Module]^5^ | Z50 | SCZ180_sc503.rom | 115200 | -| [Small Computer SC700 Z180 CPU Module]^5^ | RCBus | SCZ180_sc700.rom | 115200 | -| [Dyno Z180 SBC]^6^ | Dyno | DYNO_std.rom | 38400 | -| [Nhyodyne Z80 MBC]^1^ | MBC | MBC_std.rom | 38400 | -| [Rhyophyre Z180 SBC]^1^ | - | RPH_std.rom | 38400 | -| [Z80 ZRC CPU Module]^7^ | RCBus | RCZ80_zrc.rom | 115200 | -| [Z80 ZRC CPU Module]^7^ ROMless | RCBus | RCZ80_zrc_ram.rom | 115200 | -| [Z80 ZRC512 CPU Module]^7^ | RCBus | RCZ80_zrc512.rom | 115200 | -| [Z180 Z1RCC CPU Module]^7^ | RCBus | RCZ180_z1rcc.rom | 115200 | -| [Z280 ZZRCC CPU Module]^7^ | RCBus | RCZ280_zzrcc.rom | 115200 | -| [Z280 ZZRCC CPU Module]^7^ ROMless | RCBus | RCZ280_zzrcc_ram.rom | 115200 | -| [Z280 ZZ80MB SBC]^7^ | RCBus | RCZ280_zz80mb.rom | 115200 | -| [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 | -| [S100 Computers Z180]^9^ | S100 | S100_std.rom | 57600 | -| [Duodyne Z80 System]^1^ | Duo | DUO_std.rom | 38400 | -| [Heath H8 Z80 System]^10^ | H8 | HEATH_std.rom | 115200 | -| [EP Mini-ITX Z180]^11^ | RCBus? | EPITX_std.rom | 115200 | -| [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 | +| **Description** | **Bus** | **ROM Image File** | **Baud Rate** | +|-------------------------------------------------------------|---------|------------------------------|--------------:| +| [RetroBrew Z80 SBC]^1^ | ECB | SBC_std.rom | 38400 | +| [RetroBrew Z80 SimH]^1^ | - | SBC_simh.rom | 38400 | +| [RetroBrew N8 Z180 SBC]^1^ (date >= 2312) | ECB | N8_std.rom | 38400 | +| [Zeta Z80 SBC]^2^, ParPortProp | - | ZETA_std.rom | 38400 | +| [Zeta V2 Z80 SBC]^2^, ParPortProp | - | ZETA2_std.rom | 38400 | +| [Mark IV Z180 SBC]^3^ | ECB | MK4_std.rom | 38400 | +| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 | +| [RCBus Z80 CPU Module]^4^, 512K w/KIO | RCBus | RCZ80_kio_std.rom | 115200 | +| [RCBus Z180 CPU Module]^4^ w/ ext banking | RCBus | RCZ180_ext_std.rom | 115200 | +| [RCBus Z180 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat_std.rom | 115200 | +| [RCBus Z280 CPU Module]^4^ w/ ext banking | RCBus | RCZ180_ext_std.rom | 115200 | +| [RCBus Z280 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat_std.rom | 115200 | +| [Easy Z80 SBC]^2^ | RCBus | RCZ80_easy_std.rom | 115200 | +| [Tiny Z80 SBC]^2^ | RCBus | RCZ80_tiny_std.rom | 115200 | +| [Z80-512K CPU/RAM/ROM Module]^2^ | RCBus | RCZ80_skz_std.rom | 115200 | +| [Small Computer SC126 Z180 SBC]^5^ | BP80 | SCZ180_sc126_std.rom | 115200 | +| [Small Computer SC130 Z180 SBC]^5^ | RCBus | SCZ180_sc130_std.rom | 115200 | +| [Small Computer SC131 Z180 Pocket Comp]^5^ | - | SCZ180_sc131_std.rom | 115200 | +| [Small Computer SC140 Z180 CPU Module]^5^ | Z50 | SCZ180_sc140_std.rom | 115200 | +| [Small Computer SC503 Z180 CPU Module]^5^ | Z50 | SCZ180_sc503_std.rom | 115200 | +| [Small Computer SC700 Z180 CPU Module]^5^ | RCBus | SCZ180_sc700_std.rom | 115200 | +| [Dyno Z180 SBC]^6^ | Dyno | DYNO_std.rom | 38400 | +| [Nhyodyne Z80 MBC]^1^ | MBC | MBC_std.rom | 38400 | +| [Rhyophyre Z180 SBC]^1^ | - | RPH_std.rom | 38400 | +| [Z80 ZRC CPU Module]^7^ | RCBus | RCZ80_zrc_std.rom | 115200 | +| [Z80 ZRC CPU Module]^7^ ROMless | RCBus | RCZ80_zrc_ram_std.rom | 115200 | +| [Z80 ZRC512 CPU Module]^7^ | RCBus | RCZ80_zrc512_std.rom | 115200 | +| [Z180 Z1RCC CPU Module]^7^ | RCBus | RCZ180_z1rcc_std.rom | 115200 | +| [Z280 ZZRCC CPU Module]^7^ | RCBus | RCZ280_zzrcc_std.rom | 115200 | +| [Z280 ZZRCC CPU Module]^7^ ROMless | RCBus | RCZ280_zzrcc_ram_std.rom | 115200 | +| [Z280 ZZ80MB SBC]^7^ | RCBus | RCZ280_zz80mb_std.rom | 115200 | +| [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 | +| [S100 Computers Z180]^9^ | S100 | S100_std.rom | 57600 | +| [Duodyne Z80 System]^1^ | Duo | DUO_std.rom | 38400 | +| [Heath H8 Z80 System]^10^ | H8 | HEATH_std.rom | 115200 | +| [EP Mini-ITX Z180]^11^ | RCBus? | EPITX_std.rom | 115200 | +| [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 | +| [S100 FPGA Z80]^9^ | S100 | FZ80_std.rom | 9600 | +| [Genesis STD Z180]^12^ | STD | GMZ180_std.rom | 115200 | | ^1^Designed by Andrew Lynch | ^2^Designed by Sergey Kiselev @@ -276,6 +275,7 @@ is discussed in [Customizing RomWBW]. | ^9^Designed by John Monahan | ^10^Designed by Les Bird | ^11^Designed by Alan Cox +| ^12^Designed by Doug Jackson RCBus refers to Spencer Owen's RC2014 bus specification and derivatives including RC26, RC40, RC80, and BP80. @@ -390,7 +390,7 @@ At the Boot Loader prompt, you can type `H ` for help. You can type `L ` to list the available built-in ROM applications. If your terminal supports ANSI escape sequences, you can try the 'P' command to play a simple on-screen game. Instructions for the -game are found in $doc_romapps$. +game are found in $doc_apps$. If all of this seems fine, your ROM has been successfully programmed. See the [Boot Loader Operation] section of this document for further @@ -644,7 +644,7 @@ return to the Boot Loader menu. If you are interested in creating a custom application to run here, review the "usrrom.asm" file in the Source/HBIOS folder of the distribution. -Each of the ROM Applications is documented in $doc_romapps$. Some +Each of the ROM Applications is documented in $doc_apps$. Some of the applications (such as BASIC) also have their own independent manual in the Doc directory of the distribution. The OSes included in the ROM (CP/M 2.2 & Z-System) are described in the Operating Systems @@ -785,23 +785,62 @@ the [Disk Images] section of this document. ### Auto-Submit Batch Files -All of the operating systems supplied with RomWBW have the ability to -execute a "batch" of commands by creating a batch submission file -containing the commands to be executed. The specifics of using -batch files in a specific operating system is covered in its specific -documentation. +All of the operating systems supplied with RomWBW have the ability to +execute a "batch" of commands by creating a batch submission file +containing the commands to be executed. The mechanism for running +commands automatically at startup varies by operating system. In some +cases, it was built into the original operating system. In other cases, +I have added this capability in the RomWBW BIOS of the operating +system. -At boot, the operating system will look for a specific batch file -(`PROFILE.SUB` for CP/M 2.2 and 3) on the boot drive and execute that -batch file automatically. This allows you to automatically customize -your operating system with any commands desired at boot. CP/M 2.2 did -not originally have the ability to automatically excute a batch file at -boot, but the CBIOS in RomWBW has added this capability. +In all cases, the file containing the commands to run at startup must +be on the boot drive (A:). RomWBW automatically assigns A: to the +disk slice you choose to boot. Adding a startup command file to the +ROM Disk is not recommended because it would require customizing and +building a new ROM. Use of bootable disk slices is preferred since +the startup command files can be added/edited without any special +system customization. + +Here is an overview for each operating system: + +- **CP/M 2.2** - Will run PROFILE.SUB as a SUBMIT file if it exists in + A: at startup. Note that original CP/M 2.2 itself did not have this + ability -- it was added to the RomWBW CP/M 2.2 BIOS. The use of SUBMIT + files is documented in Section 1.6.7 SUBMIT Command of the CPM Manual + included in the Doc/CPM folder of the RomWBW distribution. + +- **Z-System (ZSDOS 1.1)** - Will run run PROFILE.SUB as a SUBMIT file + if it exists in A: at startup. Works exactly the same as CP/M 2.2. + The original Z-System ZSDOS 1.1 did not have this ability -- it was + added to the RomWBW Z-System BIOS. The Z-System documentation does + not cover the use of SUBMIT files -- please refer to the CP/M 2.2 + documentation. + +- **NZCOM** - Will run the command STARTZCM at startup. This is + normally an alias file. You use SALIAS to edit such files. Please see + Section 3.1 Creating an Alias of the NZCOM Users Manual included in the + Doc/CPM folder of the RomWBW distribution. Note that the NZCOM + distribution includes a PROFILE.SUB file. NZCOM itself is launched from + ZSDOS. The included PROFILE.SUB accomplishes this. Do not modify this + file unless you fully understand the NZCOM boot process. + +- **CP/M 3** - Will run PROFILE.SUB as a SUBMIT file if it exists in A: + at startup. This mechanism is built into the CP/M 3 operating system. + Please see Section 4.5 Executing Multiple Commands and Section 5.2.74 + Executing the SUBMIT Command of the CPM3 Users Guide included in the + Doc/CPM folder of the RomWBW distribution. + +- **ZPM3** - Will run the command STARTZPM at startup. This is normally + an alias file. You use SALIAS to edit such files. ZPM3 has no real + documentation. The NZCOM documentation of STARTZCM is generally correct + for ZPM3. Since RomWBW can utilize many disk slices, it is very easy to create slices for specific workflows (editing, software development, games, etc.). You can then just boot to the slice that is optimized for the -task you want to perform. +task you want to perform. Each such slice may have its own startup +command batch file that customizes the environment for the specific +workflow desired. ## System Management @@ -984,34 +1023,77 @@ switches can be used to select any of the first 8 slices. # Disk Management -The systems supported by RomWBW all have the ability to use persistent -disk media. A wide variety of disk devices are supported including -floppy drives, hard disks, CF Cards, SD Cards, etc. RomWBW also -supports the use of extra RAM and ROM memory as pseudo-disk devices. +The systems supported by RomWBW all have the ability to use persistent +disk media. Some systems have disk interfaces built-in, while others +will require add-in cards. You will need to refer to the documentation +for your system for your specific options. + +The RomWBW firmware provides a hardware abstraction layer, +All disks will work on all hardware variations. +This means you can remove disk media from one RomWBW system and +put it in a different RomWBW system. The only constraint is that the +applications on the disk media must be up to date with the firmware on +the system being used. + +## Key Terminology/Concepts + +The following important terminology applies + +#### Disk (or Disk Drive) + +The hardware storage device that RomWBW talks to. +RomWBW supports a variety of storage disk device types. + +* ROM Disk - RomWBW firmware - containing CPM utilities +* RAM Disk - A section of system RAM initially empty +* Floppy Disk(s) - Removable media +* Hard Disk(s) - Includes CF Cards, SD Cards, USB Stick, etc. + +The different disk types are further defined in the section [Disk Types]. + +#### Media + +The storage device inserted into a disk drive, e.g. a floppy disk, CF +Card, SD Card, etc. + +#### Slice + +For hard disks a Slice is a smaller logical block of disk space that is +allocated and formatted with a filesystem and typically allocated to a +Drive letter. Slices allow large modern storage media to be sliced up +into smaller units compatible with CP/M. Slices should not be confused +with partitions, a slice is not a partition. + +The concept of slices is described in detail in the section +[Hard Disk Slices]. + +#### Drive -RomWBW supports a variety of storage devices which will be discussed -in more detail later. +The mapping of a hardware disk (and slice) to a Drive letter +in an operating system. A Drive has a file system installed on it -* ROM Disk -* RAM Disk -* Floppy Disk -* Hard Disk (includes CF Cards, SD Cards, USB Drives, etc.) +#### Disk Image -We will start by discussing each of these types of storage devices and -how to prepare them so files can be stored on them. Subsequently, we -will describe how to install the pre-built disk images with bootable -operating systems and ready-to-run content. +A disk image is a predefined image of a complete CP/M filesystem, +or filesystem(s), including any partition tables (for hard disk images). +Each disk image has the complete set of normal applications and tools +distributed with the associated operating system or application suite. + +This comes in for form of a file which is suitable for copying directly +onto target media, using a modern computer. It is generally easier to +use these disk images than transferring files over individually. +See the section [Disk Images] for further details. -Some systems have disk interfaces built-in, while others will require -add-in cards. You will need to refer to the documentation for your -system for your specific options. +## Startup Hardware Discovery + +During startup RomWBW performs detection for hardware supported by your +platform. During startup you will see messages for any disk +interface(s), listing device types (e.g. FD:, IDE:, SD:), and any media +that has been found on these interfaces. The messages you see will vary +depending on your hardware and the media you have installed. -In the RomWBW boot messages, you will see hardware discovery messages. -If you have a disk drive interface, you should see messages listing -device types like FD:, IDE:, PPIDE:, SD:. Additionally, you will see -messages indicating the media that has been found on the interfaces. As an example, here are the messages you might see if you have an IDE -interface in your system with a single CF Card inserted in the +interface in your system with a single disk drive connected to the primary side of the interface: ``` @@ -1020,72 +1102,45 @@ IDE0: 8-BIT LBA BLOCKS=0x00773800 SIZE=3815MB IDE1: NO MEDIA ``` -The messages you see will vary depending on your hardware and the -media you have installed. But, they will all have the same general -format as the example above. +See [Appendix B - Device Summary] for a complete list of the different +device types supported. + +If you do not see drive letters assigned as expected, refer to the prior +system boot messages to ensure media has been detected in the interface. + +Each drive letter refers back to a specific disk hardware interface like +IDE0. This is important as it is telling you what each drive letter +refers to. + +Mass storage disks (like IDE) will normally have multiple drive letters +assigned. The extra drive letters refer to additional "slices" on the +disk. Once your system has working disk devices, they will be accessible from any operating system you choose to run. Disk storage is available whether you boot your OS from ROM or from the disk media itself. -Referring back to [Starting Applications from ROM], you could start CP/M -2.2 using the 'C' command. As the operating system starts up, you -should see a list of drive letters assigned to the disk media you have -installed. Here is an example of this: - -``` -Configuring Drives... - - A:=MD1:0 - B:=MD0:0 - C:=IDE0:0 - D:=IDE0:1 -``` +## Drive Letter Assignment -You will probably see more drive letters than this. The drive letter -assignment process is described below in the [Drive Letter Assignment] -section. Be aware that RomWBW will only assign drive letters to disk -interfaces that actually have media in them. If you do not see drive -letters assigned as expected, refer to the prior system boot messages -to ensure media has been detected in the interface. Actually, there -is one exception to this rule: floppy drives will be assigned a drive -letter regardless of whether there is any media inserted at boot. - -Notice how each drive letter refers back to a specific disk hardware -interface like IDE0. This is important as it is telling you what each -drive letter refers to. Also notice that mass storage disks (like IDE) -will normally have multiple drive letters assigned. The extra drive -letters refer to additional "slices" on the disk. The concept of slices -is described below in the [Slices] section. +In legacy CP/M operating systems only 16 drive letters (A:-P:) available + to be assigned to disks Drive letters were generally mapped to disk +drives in a completely fixed way. For example, drive A: would **always** + refer to the first floppy disk drive. -## Drive Letter Assignment +RomWBW implements a much more flexible drive letter assignment mechanism +so that any drive letter can dynamically be assigned to any disk device, +or slice of media. -In legacy CP/M-type operating systems, drive letters were generally -mapped to disk drives in a completely fixed way. For example, drive A: -would **always** refer to the first floppy drive. Since RomWBW -supports a wide variety of hardware configurations, it implements a -much more flexible drive letter assignment mechanism so that any drive -letter can be assigned to any disk device. - -At boot, you will notice that RomWBW automatically assigns drive -letters to the available disk devices. These assignments are -displayed during the startup of the selected operating system. -Additionally, you can review the current drive assignments at any -time using the `ASSIGN` command. CP/M 3 and ZPM3 do not automatically -display the assignments at startup, but you can use `ASSIGN` to -display them. Refer to $doc_apps$ for more information on -use of the `ASSIGN` command. +For clarification, CP/M **cannot** refer directly to disk devices, +CP/M only understands drive letters, so to access a given disk device +it must first be assigned to a drive letter. +As the operating system starts up, you should see a list of drive letters +assigned to the disk media you have installed. Here is an example of the list of drive letter assignments made during the startup of Z-System: ``` -Loading Z-System... - -CBIOS v3.1.1-pre.194 [WBW] - -Formatting RAMDISK... - Configuring Drives... A:=MD0:0 @@ -1096,65 +1151,53 @@ Configuring Drives... F:=IDE0:1 G:=IDE0:2 H:=IDE0:3 +``` - 1081 Disk Buffer Bytes Free +Above you can see that: -ZSDOS v1.1, 54.0K TPA -``` +- Drive A: has been assigned to MD0 which is the RAM disk device. +- Drive B: has been assigned to MD1 which is the ROM disk device. +- Drives C: and D: have been assigned to floppy disk drives. +- Drives E: thru H: have been assigned to the IDE0 hard disk device. + The 4 entries for IDE0 are referring to the first 4 slices on that disk. -Above you can see that drive A: has been assigned to MD0 which is the -RAM Disk device. Drives C: and D: have been assigned to floppy drives. -Drives E: thru L: have been assigned to the IDE0 hard disk device. The -4 entries for IDE0 are referring to 4 slices on that disk. Slices are -discussed later. +CP/M 3 and ZPM3 do not automatically display the assignments at startup, +but you can use `ASSIGN` to display them. -**WARNING**: Drive letter assignments do **not** ensure that the slice -referenced by the drive letter actually fits on the media you are using. -For example, a typical 64MB CF Card (which is typically a bit smaller -than 64MB) will only fit 7 slices. At startup, you will typically see -8 drive letters assigned to the CF Card. Attempting to access the -last drive letter will result in a "no disk" error from the operating -system. +The assignments at boot will stay the same on each boot +as long as you do not make changes to your hardware configuration. +i.e. If you insert or remove an SD Card, CF Card or USB Stick, the drive +assignments will change at next boot. -The drive letter assignments **do not** change during an OS session -unless you use the `ASSIGN` command yourself to do it. Additionally, the -assignments at boot will stay the same on each boot as long as you do -not make changes to your hardware configuration. Note that the -assignments **are** dependent on the media currently inserted in hard -disk drives when the operating system is started. So, notice that if you -insert or remove an SD Card, CF Card or USB Drive, the drive -assignments will change. Since drive letter assignments can change, you -must be careful when doing destructive things like using `CLRDIR` to +Since drive letter assignments can change, you +must be careful when doing destructive things like using `CLRDIR` to make sure the drive letter you use is referring to the desired media. -When performing a ROM boot of an operating system, note that A: will -be your RAM disk and B: will be your ROM disk. When performing a disk -boot, the disk you are booting from will be assigned to A: and the -rest of the drive letters will be offset to accommodate this. This is -done because most legacy operating systems expect that A: will be the -boot drive. +Drive assignments can be changed at any time, by the `ASSIGN` command. +Please see the section [Assign Drive Letters] for further details. -### Default Drive Letter Assignment +### Default Drive Letters -As shown above, when an operating system is booted, RomWBW will -automatically assign drive letters to physical disk devices. The -assignment process varies depending on: 1) the drive/slice you choose to -boot from, and 2) the number and type of physical drives in your -system. +When an operating system is booted, RomWBW will automatically assign +drive letters to disk devices. The assignment process varies depending on: -If you boot an operating system from ROM, then the first two drive -letters will be assigned to your RAM disk (A:) and your ROM disk (B:). -It may seem odd that the RAM disk is assigned to A: in this case. The -reason for this is to accommodate certain functions that require that A: -be a writable disk drive. For example, A: **must** be writable in order -to submit batch files. +* the disk/slice you choose to boot from, and +* the number, type, and sizes of mass storage devices available at boot + +The A: drive letter is considered special by most CP/M operating systems +and is automatically used in some cases. e.g. submitting batch files, +and is expected to be a writable volume. If you boot to a physical disk device, then the first drive letter (A:) -will be assigned to the disk/slice that you chose to boot from. The A: -drive letter is considered special by most operating systems and is -automatically used in some cases. By making the selected disk/slice the -A: drive, you can setup different disks/slices for specific uses and -just boot to it. +will be assigned to the disk/slice that you are booting from, +and the rest of the drive letters will be offset to accommodate this. +By making the selected disk/slice the A: drive, you can setup different +disks/slices for specific uses and just boot it, +and the booted operating system will be the A: drive + +However when performing a ROM boot of an operating system, the first two +drive letters will be assigned to your RAM disk (A:) and your ROM disk +(B:). This provides the maximum compatibility with CP/M. After the first drive letter is assigned (as well as the second drive letter in the case of a ROM boot), RomWBW will assign additional drive @@ -1169,9 +1212,8 @@ letters will be assigned in the following order: If a disk/slice was already assigned as the A: (or B:) drive letter, then it will not be assigned again. -In the case of floppy, RAM, and ROM disks, a single drive letter will be -assigned to each physical disk (even if there is no disk media in the -drive). +Floppy or removable disk drives will be assigned a drive letter +regardless of whether there is any media inserted at the time of boot. In the case of hard disks, 1-8 drive letters will be assigned to the initial 1-8 slices of the disk drive. The number of drive letters @@ -1186,18 +1228,122 @@ This somewhat complicated algorithm is used to try and maximize the limited number of operating system drive letters available (16) to the available disk devices as evenly as possible. -Note that for hard disk devices, drive letters will only be assigned -to disk devices that actually contain media. So, for example, if you -have an SD Card slot in your system, but it has no SD Card inserted, then -no drive letters will be assigned to it. +For hard disk devices which are treated as non-removable media, drive +letters will only be assigned to disk devices that actually contain +media. i.e. No drive letters will be assigned to an SD Card slot that +has no SD Card inserted. -Since drive letter assignments are easily changed at any time using the -`ASSIGN` command, you can customize your assignments as desired after -starting the operating system. Even better, you can use an auto-submit -batch file to customzie the assignments at startup without any user +### Assign Drive Letters + +The `ASSIGN` command is used to view or change the current +drive letter mappings. Any changes made to drive letter mappings take +immediate effect + +Refer to $doc_apps$ for more information on use of the `ASSIGN` command. + +Since drive letter assignments are easily changed at any time using the +`ASSIGN` command, you can customize your assignments as desired after +starting the operating system. Even better, you can use an auto-submit +batch file to customzie the assignments at startup without any user intervention. -## ROM & RAM Disks +## Disk Operations/Commands + +With some understanding of how RomWBW presents disk space to the +operating systems, we need to go over the options for actually setting +up your disk(s) with content. + +### Preparing Media for First Use + +You can initialize the media in-place using your RomWBW system. +Essentially, this means you are creating a set of blank directories on +your disk so that files can be saved there. +This is somewhat analogous to partitioning of a hard disk +or doing a low level format of a floppy disk. + +Initilizing a Floppy disk is covered in the section [Floppy Disk Formatting], +or for a Hard disk the section [Hard Disk Preparation] covers the steps to +manually setup a hard disk for first use. + +### Clearing (Formatting) Drives + +This is somewhat analogous to doing a FORMAT operation on other systems. + +With RomWBW you use the `CLRDIR` command to do this. +This command is merely "clearing out" the directory space of the drive +referred to by a drive letter and setting up the new empty directory. + +Refer to $doc_apps$ for more information on use of the `CLRDIR` command. + +Since `CLRDIR` works on drive letters, make +absolutely sure you know what media and slice are assigned to that +drive letter before using `CLRDIR` because `CLRDIR` will wipe out any +pre-existing contents of the slice. + +After `CLRDIR` completes, the slice should be ready to use by the operating +system via the drive letter assigned. +Start by using the `DIR` command on the drive. +This should return without error, but list no files. + +Here is an example of using `CLRDIR`. In this example, the `ASSIGN` +command is used to show the current drive letter assignments. Then +the `CLRDIR` command is used to initialize the directory of drive 'G' +which is slice 2 of hard disk device IDE0 ("IDE0:2"). + +``` +B>ASSIGN + + A:=MD0:0 + B:=MD1:0 + C:=FD0:0 + D:=FD1:0 + E:=IDE0:0 + F:=IDE0:1 + G:=IDE0:2 + H:=IDE0:3 + +B>CLDIR G: +CLRDIR Version 1.2B May 2024 by Max Scane + +Warning - this utility will overwrite the directory sectors of Drive: G +Type CAPITAL Y to proceed, any key other key to exit. Y +Directory cleared. +B> +``` + +### Checking Disk Layout + +If you are not sure which disk layout is used for your existing +media, you can use the CP/M 2.2 `STAT` command to display information +including the number of "32 Byte Directory Entries" +for a drive letter on the corresponding hard disk. + +- If it indicates 512, your disk layout is legacy (hd512). +- If it indicates 1024, your disk layout is modern (hd1k). + +Here is an example of checking the disk layout. + +``` +B>STAT E:DSK: + + E: Drive Characteristics +65408: 128 Byte Record Capacity + 8176: Kilobyte Drive Capacity + 1024: 32 Byte Directory Entries + 0: Checked Directory Entries + 256: Records/ Extent + 32: Records/ Block + 64: Sectors/ Track + 2: Reserved Tracks +``` + +It is critical that you include `DSK:` after the drive letter in the +`STAT` command line. The important line to look at is labeled "32 Byte +Directory Entries". + +# Disk Types + +## RAM & ROM Disks A typical RomWBW system has 512KB of ROM and 512KB of RAM. Some portions of each are dedicated to loading and running applications @@ -1205,10 +1351,23 @@ and operating system. The space left over is available for an operating system to use as a pseudo-disk device (ROM Disk and RAM Disk). +Unlike other types of disk devices, ROM and RAM Disks do not contain an +actual operating system and are not "bootable". However, they are +accessible to any operating system (whether the operating system is +loaded from ROM or a different disk device). + +Neither RAM nor ROM disks require explicit formatting or initialization. +ROM disks are pre-formatted and RAM disks are formatted automatically +with an empty directory when first used. + +#### RAM Disk + The RAM disk provides a small CP/M filesystem that you can use for the temporary storage of files. Unless your system has a battery backed mechanism for persisting your RAM contents, the RAM disk contents will -be lost at each power-off. However, the RAM disk is an excellent +be lost at each power-off. + +The RAM disk is an excellent choice for storing temporary files because it is very fast. You will notice that the first time an operating system is started after the power was turned off, you will see a message indicating that the @@ -1216,10 +1375,14 @@ RAM disk is being formatted. If you reset your system without turning off power, the RAM disk will not be reformatted and it's contents will still be intact. +#### ROM Disk + Like the RAM disk, the ROM disk also provides a small CP/M filesystem, but it's contents are static -- they are part of the ROM. As such, you cannot save files to the ROM disk. Any attempt to -do this will result in a disk I/O error. The contents of the ROM +do this will result in a disk I/O error. + +The contents of the ROM disk have been chosen to provide a core set of tools and applications that are helpful for either CP/M 2.2 or ZSDOS. Since ZSDOS is CP/M 2.2 compatible, this works fairly well. However, you @@ -1227,15 +1390,6 @@ will find some files on the ROM disk that will work with ZSDOS, but will not work on CP/M 2.2. For example, `LDDS`, which loads the ZSDOS date/time stamper will only run under ZSDOS. -Unlike other types of disk devices, ROM and RAM Disks do not contain an -actual operating system and are not "bootable". However, they are -accessible to any operating system (whether the operating system is -loaded from ROM or a different disk device). - -Neither RAM nor ROM disks require explicit formatting or initialization. -ROM disks are pre-formatted and RAM disks are formatted automatically -with an empty directory when first used. - #### Flash ROM Disks The limitation of ROM disks being read-only can be overcome on some @@ -1258,102 +1412,11 @@ derived from the IBM PC floppy disk formats: * 3.5" 720K Double-sided, Double-density * 3.5" 1.44M Double-sided, High-density -When supported, RomWBW is normally configured for 2 3.5" floppy drives. -If a high-density drive is used, then RomWBW automatically detects and +When supported, RomWBW is normally configured for 2 3.5" floppy disk drives. +If a high-density disk drive is used, then RomWBW automatically detects and adapts to double-density or high-density media. It cannot automatically -detect 3.5" vs. 5.25" drive types -- the ROM must be pre-configured -for the drive type. - -Floppy media must be physically formatted before it can be used. This -is normally accomplished by using the supplied Floppy Disk Utility (FDU) -application. This application interacts directly with your hardware -and therefore you must specify your floppy interface hardware at -application startup. Additionally, you need to specify the floppy drive -and media format to use for formatting. - -Below is a sample session using FDU to format a 1.44M floppy disk in -the first (primary) floppy disk drive: - -``` -B>fdu - -Floppy Disk Utility (FDU) v5.8, 26-Jul-2021 [HBIOS] -Copyright (C) 2021, Wayne Warthen, GNU GPL v3 - -SELECT FLOPPY DISK CONTROLLER: - (A) Disk IO ECB Board - (B) Disk IO 3 ECB Board - (C) Zeta SBC Onboard FDC - (D) Zeta 2 SBC Onboard FDC - (E) Dual IDE ECB Board - (F) N8 Onboard FDC - (G) RCBus SMC (SMB) - (H) RCBus WDC (SMB) - (I) SmallZ80 Expansion - (J) Dyno-Card FDC, D1030 - (K) RCBus EPFDC - (L) Multi-Board Computer FDC - (X) Exit -=== OPTION ===> D-IDE - -===== D-IDE ===========<< FDU MAIN MENU >>====================== -(S)ETUP: UNIT=00 MEDIA=720KB DS/DD MODE=POLL TRACE=00 ----------------------------------------------------------------- -(R)EAD (W)RITE (F)ORMAT (V)ERIFY -(I)NIT BUFFER (D)UMP BUFFER FDC (C)MDS E(X)IT -=== OPTION ===> SETUP -ENTER UNIT [00-03] (00): -00: 3.5" 720KB - 9 SECTORS, 2 SIDES, 80 TRACKS, DOUBLE DENSITY -01: 3.5" 1.44MB - 18 SECTORS, 2 SIDES, 80 TRACKS, HIGH DENSITY -02: 5.25" 320KB - 8 SECTORS, 2 SIDES, 40 TRACKS, DOUBLE DENSITY -03: 5.25" 360KB - 9 SECTORS, 2 SIDES, 40 TRACKS, DOUBLE DENSITY -04: 5.25" 1.2MB - 15 SECTORS, 2 SIDES, 80 TRACKS, HIGH DENSITY -05: 8" 1.11MB - 15 SECTORS, 2 SIDES, 77 TRACKS, DOUBLE DENSITY -06: 5.25" 160KB - 8 SECTORS, 1 SIDE, 40 TRACKS, DOUBLE DENSITY -07: 5.25" 180KB - 9 SECTORS, 1 SIDE, 40 TRACKS, DOUBLE DENSITY -08: 5.25" 320KB - 8 SECTORS, 1 SIDE, 80 TRACKS, DOUBLE DENSITY -09: 5.25" 360KB - 9 SECTORS, 1 SIDE, 80 TRACKS, DOUBLE DENSITY -ENTER MEDIA [00-09] (00): 01 -00: POLLING (RECOMMENDED) -01: INTERRUPT (!!! READ MANUAL !!!) -02: FAST INTERRUPT (!!! READ MANUAL !!!) -03: INT/WAIT (!!! READ MANUAL !!!) -04: DRQ/WAIT (!!! NOT YET IMPLEMENTED!!!) -ENTER MODE [00-04] (00): -ENTER TRACE LEVEL [00-01] (00): - -===== D-IDE ===========<< FDU MAIN MENU >>====================== -(S)ETUP: UNIT=00 MEDIA=1.44MB DS/HD MODE=POLL TRACE=00 ----------------------------------------------------------------- -(R)EAD (W)RITE (F)ORMAT (V)ERIFY -(I)NIT BUFFER (D)UMP BUFFER FDC (C)MDS E(X)IT -=== OPTION ===> FORMAT (T)RACK, (D)ISK ===> DISK -ENTER INTERLEAVE [01-12] (02): - - - -RESET DRIVE... -PROGRESS: TRACK=4F HEAD=01 SECTOR=01 - -===== D-IDE ===========<< FDU MAIN MENU >>====================== -(S)ETUP: UNIT=00 MEDIA=1.44MB DS/HD MODE=POLL TRACE=00 ----------------------------------------------------------------- -(R)EAD (W)RITE (F)ORMAT (V)ERIFY -(I)NIT BUFFER (D)UMP BUFFER FDC (C)MDS E(X)IT -=== OPTION ===> EXIT -``` - -Since the physical format of floppy media is the same as that used -in a standard MS-DOS/Windows computer, you can also physical format -floppy media in a modern computer. However, the directory format -itself will not be compatible with CP/M OSes. In this case, you -can use the `CLRDIR` application supplied with RomWBW to reformat -the directory area. - -Once a floppy disk is formatted, you can read/write files on it -using any of the RomWBW operating systems. The specific commands -will depend on the operating system or application in use -- refer to -the appropriate OS/application documentation as needed. +detect 3.5" vs. 5.25" disk drive types -- the ROM must be pre-configured +for the disk drive type. **WARNING:** Some of the operating systems provided with RomWBW require that a soft-reset be performed when swapping floppy disk media. For @@ -1364,17 +1427,31 @@ disk directory corruption. ## Hard Disks -Under RomWBW, a hard disk is similar to a floppy disk in that it is -considered a disk unit. However, RomWBW has multiple features that -allow its legacy operating systems to take advantage of modern -mass storage media. - -To start with, the concept of a hard disk in RomWBW applies to any +The concept of a hard disk in RomWBW applies to any storage device that provides at least 8MB of space. The actual media can be a real spinning hard disk, a CompactFlash Card, a SD Card, etc. In this document, the term hard disk will apply equally to all of these. +The vintage operating systems included with RomWBW were produced at a +time when mass storage devices were quite small. CP/M 2.2 could only +handle filesystems up to 8MB. + +Since storage devices today are quite large, RomWBW implements a +mechanism called slicing (see [Hard Disk Slices]) to allow +up to 256 8MB CP/M filesystems on a single large storage device, +where each slice can be assigned to a drive letter in CPM, +and be treated as its own hard disk drive (from a CPM perspective). + +In order to achieve compatibility across +all of the operating systems supported by RomWBW, the hard disk +filesystem format used is 8MB. This ensures any filesystem will be +accessible to any of the operating systems. + +While hard disks while often implemented by removable media, are treated +as non-removable. e.g. Removing an SD card is like unplugging a hard +drive in a modern sense. + RomWBW uses Logical Block Addressing (LBA) to interact with all hard disks. The RomWBW operating systems use older Cylinder/Head/Sector (CHS) addressing. To accommodate the operating systems, RomWBW emulates @@ -1382,425 +1459,558 @@ CHS addressing. Specifically, it makes all hard disks look like they have 16 sectors and 16 heads. The number of tracks varies with the size of the physical hard disk. -It is recommended that hard disk media used with RomWBW be 1GB or -greater in capacity. The reasons for this are discussed later, but it -allows you to use the recommended disk layout for RomWBW that -accommodates 64 CP/M filesystem slices and a 384KB FAT filesystem. +### Hard Disk Layouts ->>> Although we have not yet discussed how to get content on your disk ->>> units, it is necessary to have a basic understanding of how RomWBW ->>> handles disk devices as background. The following sections explain how ->>> disk units are managed within the operating systems. We will ->>> subsequently discuss how to actually setup disk devices with usable ->>> content. +When RomWBW uses a hard disk, it utilizes an area of the physical hard +disk drive space to store a sequential series of slices that contain the +actual CP/M filesystems referred to by drive letters by the operating +system. -## Slices +Two physical layout schemes exist: -The vintage operating systems included with RomWBW were produced at a -time when mass storage devices were quite small. CP/M 2.2 could only -handle filesystems up to 8MB. In order to achieve compatibility across -all of the operating systems supported by RomWBW, the hard disk -filesystem format used is 8MB. This ensures any filesystem will be -accessible to any of the operating systems. +* Modern (hd1k) +* Legacy (hd512) -Since storage devices today are quite large, RomWBW implements a -mechanism called slicing to allow up to 256 8MB CP/M filesystems on a -single large storage device. To say it another way, the media is -"sliced up" into many 8MB CP/M filesystems. Each slice is a complete -CP/M filesystem. This allows up to 2GB of usable space on -one media. You can think of slices as a way to refer to any of -the first 256 8MB chunks of space on a single media. Each chunk -is a CP/M filesystem. - -Note that slices are **not** the same thing as a hard disk partition. -In fact, these slices all live inside of a single hard disk partition. -Normally, a RomWBW hard disk will have one partition (called the -RomWBW partition) containing 64 slices. Optionally, there may be -a second partition which contains a FAT filesystem. For now, we -are just talking about the slices within the single RomWBW partition. +You **cannot** mix disk layouts on a single disk device, +however It is perfectly fine for one system to have +multiple hard disks with different layouts -- each physical disk +device is handled separately. -Although you can use up to 256 slices per physical disk, this large -number of slices is rarely used. The recommended RomWBW disk layout -provides for 64 slices which is more than enough for most use cases. - -Of course, the problem is that CP/M-like operating systems have only -16 drive letters (A:-P:) available. Under the covers, RomWBW allows -you to use any drive letter to refer to any slice of any media. The -`ASSIGN` command is used to view or change the current drive letter -mappings at any time. At startup, the operating system will -automatically allocate a reasonable number of drive letters to the -available storage devices. The allocation will depend on the number of -mass storage devices available at boot. For example, if you have -only one hard disk type media, you will see that 8 drive letters are -assigned to the first 8 slices of that media. If you have two large -storage devices, you will see that each device is allocated 4 drive -letters. +If you are setting up a new disk, the modern (hd1k) layout is +recommended for the following reasons: -Referring to slices within a storage device is done by appending a -`:` where \ is the device relative slice number from 0-255. -For example, if you have an IDE device, it will show up as IDE0: in the -boot messages meaning the first IDE device. To refer to the fourth slice -of IDE0, you would type "IDE0:3". Here are some examples: +* Larger number of directory entries per filesystem +* Simplifies creation of coresident FAT filesystem +* Reduces chances of data corruption -| | | -|----------|------------------------------| -| `IDE0:0` | First slice of disk in IDE0 | -| `IDE0:` | First slice of disk in IDE0 | -| `IDE0:3` | Fourth slice of disk in IDE0 | +Both the legacy and modern disk layouts continue to be fully supported +by RomWBW. There are no plans to deprecate the legacy layout. -So, if you wanted to use drive letter L: to refer to the fourth slice of -IDE0, you could use the command `ASSIGN L:=IDE0:3`. There are a couple -of rules to be aware of when assigning drive letters. First, you may -only refer to a specific device/slice with one drive letter at a time. -Said another way, you cannot have multiple drive letters referring to a -the same device/slice at the same time. Second, there must always be a -drive assigned to A:. Any attempt to violate these rules will be blocked -by the `ASSIGN` command. +#### Modern Layout -As you see, the name of a slice does not reference the hard disk -partition containing the slices. Since there can only be a single -RomWBW partition containing slices on any disk, the partition is -determined automatically. +RomWBW (Starting with v3.2) supports the use of disk partitioning, +utilising a Master Boot Record (MBR) partition tables. +The Wikipedia article on the +[Master Boot Record](https://en.wikipedia.org/wiki/Master_boot_record) +is excellent if you are not familiar with them. -In case this wasn't already clear, you **cannot** refer directly -to slices using CP/M. CP/M only understands drive letters, so -to access a given slice, you must assign a drive letter to it first. +RomWBW uses the partition type id `0x2E`. This partition type id +does not equate to any existing well-known +partition types -- it was chosen because it is not generally used. +RomWBW does not support extended partitions -- only a single +primary partition can be used. -While it may be obvious, you cannot use slices on any media less than -8MB in size. Specifically, you cannot slice RAM disks, ROM disks, floppy - disks, etc. All of these are considered to have a single slice (slice -0) and any attempt to ASSIGN a drive letter to a slice beyond that will -fail and produce an error message. +The existence of a partition table entry for RomWBW on +a hard disk makes it behave in the modern mode. Removing the RomWBW +partition entry from a modern hard disk layout +will cause the existing data to be unavailable and/or corrupted -It is very important to understand that RomWBW slices are not -individually created or allocated on your hard disk. RomWBW uses a -single, large chunk of space (partition) on your hard disk to contain -the slices. You should think of slices as just an index into a -sequential set of 8MB areas that exist in this large chunk of space. -The next section will go into more detail on how slices are located on -your hard disk. - -Although you do not need to allocate slices individually, you do need to -initialize each slice for CP/M to use it. This is somewhat analogous -to doing a FORMAT operation on other systems. With RomWBW you use the -`CLRDIR` command to do this. This command is merely "clearing out" the -directory space of the slice referred to by a drive letter and setting -up the new empty directory. Since `CLRDIR` works on drive letters, make -absolutely sure you know what media and slice are assigned to that -drive letter before using `CLRDIR` because CLRDIR will wipe out any -pre-existing contents of the slice. +The CP/M filesystem in the slices of the modern disk layout +contain 1024 directory entries. -**WARNING**: Earlier versions of the `CLRDIR` application does not -appear to check for disk errors when it runs. If you attempt to run -`CLRDIR` on a drive that is mapped to a slice that does not actually fit -on the physical disk, it may behave erratically. - -Here is an example of using `CLRDIR`. In this example, the `ASSIGN` -command is used to show the current drive letter assignments. Then -the `CLRDIR` command is used to initialize the directory of drive 'G' -which is slice 2 of hard disk device IDE0 ("IDE0:2"). - -``` -B>assign - - A:=MD0:0 - B:=MD1:0 - C:=FD0:0 - D:=FD1:0 - E:=IDE0:0 - F:=IDE0:1 - G:=IDE0:2 - H:=IDE0:3 - -B>clrdir G: -CLRDIR Version 1.2B May 2024 by Max Scane - -Warning - this utility will overwrite the directory sectors of Drive: G -Type CAPITAL Y to proceed, any key other key to exit. Y -Directory cleared. -B> -``` - -## Hard Disk Layouts - -As previously discussed, when RomWBW uses a hard disk, it utilizes a -chunk of space for a sequential series of slices that contain the -actual CP/M filesystems referred to by drive letters. +#### Legacy Layout Originally, RomWBW always used the very start of the hard disk media for the location of the slices. In this layout, slice 0 referred to the first chunk of ~8MB on the disk, slice 1 referred to the second -chunk of ~8MB on the disk, and so on. The number of slices is limited +chunk of ~8MB on the disk, and so on. The number of slices is limited to the size of the disk media -- if you attempted to read/write to a -slice that would exceed the disk size, you would see I/O errors. This -is considered the "legacy" disk layout for RomWBW. - -Starting with v3.2, RomWBW has been enhanced to support the concept of -partitioning. The partition mechanism is entirely compliant with Master -Boot Record (MBR) Partition Tables introduced by IBM for the PC. The -Wikipedia article on the -[Master Boot Record](https://en.wikipedia.org/wiki/Master_boot_record) -is excellent if you are not familiar with them. This is considered the -"modern" disk layout for RomWBW. RomWBW uses the partition type id -0x2E. This partition type id does not equate to any existing well-known -partition types -- it was chosen because it is not generally used. -RomWBW does not support extended partitions -- only a single -primary partition can be used. +slice that would exceed the disk size, you would see I/O errors. -Both the legacy and modern disk layouts continue to be fully supported -by RomWBW. There are no plans to deprecate the legacy layout. In fact, -the legacy format takes steps to allow a partition table to still be +The legacy format takes steps to allow a partition table to still be used for other types of filesystems such as DOS/FAT. It just does not use a partition table entry to determine the start of the RomWBW slices. -There is one more difference between the legacy and modern disk layouts -that should be highlighted. The CP/M filesystem in the slices of -the legacy disk layout contain 512 directory entries. The modern disk -layout filesystems provide 1024 directory entries. In fact, you will -subsequently see that the prefixes "hd512" and "hd1k" are used to -identify disk images appropriate for the legacy and modern format. -These prefixes were chosen specifically to highlight the number of -directory entries supported. - -You **cannot** mix disk layouts on a single disk device. To say it -another way, the existence of a partition table entry for RomWBW on -a hard disk makes it behave in the modern mode. The lack of a RomWBW -partition table entry will cause legacy behavior. Adding a partition -table entry on an existing legacy RomWBW hard disk will cause the -existing data to be unavailable and/or corrupted. Likewise, removing -the RomWBW partition entry from a modern hard disk layout will cause -the same problems. It is perfectly fine for one system to have -multiple hard disks with different layouts -- each physical disk -device is handled separately. - -If you are setting up a new disk, the modern (hd1k) layout is -recommended for the following reasons: - -* Larger number of directory entries per filesystem -* Simplifies creation of coresident FAT filesystem -* Reduces chances of data corruption - -### Checking Hard Disk Layout +The lack of a RomWBW partition table entry will cause legacy behaviour. +Adding a partition table entry on an existing legacy RomWBW hard disk +will cause the existing data to be unavailable and/or corrupted. -If you are not sure which hard disk layout was used for your existing -media, you can use the OSes command to display the number of directory -entries for a drive letter on the corresponding hard disk. For example, -the `STAT` command is used in CP/M 2.2 to determine this. This -command displays the number of directory entries on a filesystem. If -it indicates 512, your disk layout is legacy (hd512). If it indicates -1024, your disk layout is modern (hd1k). +The CP/M filesystem in the slices of the legacy disk layout +contain 512 directory entries. -Here is an example of checking the disk layout. We want to check the -CompactFlash Card inserted in IDE interface 0. We start the system -and boot to Z-System in ROM by using the 'Z' command at the Boot Loader. -As Z-System starts, we see the following disk assignments: +### Hard Disk Slices -``` -Boot [H=Help]: c +RomWBW implements a mechanism called slicing to allow multiple CP/M +filesystem on a single large storage device. To say it another way, the +media is "sliced up" into many CP/M filesystems. -Loading CP/M 2.2... +You cannot use slices on any media less than 8MB in size. +Specifically, you cannot slice RAM disks, ROM disks, floppy +disks, etc. All of these are considered to have a single slice (0) -CBIOS v3.1.1-pre.194 [WBW] - -Configuring Drives... +It is very important to understand that RomWBW slices are not +individually created or allocated on your hard disk. +RomWBW uses a single partition on your hard disk to contain +the slices. You should think of slices as just an index into a +sequential set of 8MB areas that exist in this partition. - A:=MD0:0 - B:=MD1:0 - C:=FD0:0 - D:=FD1:0 - E:=IDE0:0 - F:=IDE0:1 - G:=IDE0:2 - H:=IDE0:3 - I:=PRPSD0:0 - J:=PRPSD0:1 - K:=PRPSD0:2 - L:=PRPSD0:3 +RomWBW allows up to up to 256 slices each of 8MB in size on a single +large storage device. This allows the use of up to 2GB of usable space +on one media device. - 1081 Disk Buffer Bytes Free +It is possible to create other partitions (typically FAT), for now, we +are just talking about the slices within the single RomWBW partition. -CP/M-80 v2.2, 54.0K TPA -``` +### Slice Assignment -You can see that the IDE0 interface (which contains the CF Card) has -been assigned to drive letters E: to H:. We can use the STAT command -on any of these drive letters. So, for example: +When assigning Hard disks to drive letters you also need to assign the +slice. -``` -B>stat e:dsk: +Referring to slices within a storage device is done by appending a +`:` where \ is the device relative slice number from 0-255. +For example, if you have an IDE device, it will show up as IDE0: in the +boot messages meaning the first IDE device. To refer to the fourth slice +of IDE0, you would type "IDE0:3". Here are some examples: - E: Drive Characteristics -65408: 128 Byte Record Capacity - 8176: Kilobyte Drive Capacity - 1024: 32 Byte Directory Entries - 0: Checked Directory Entries - 256: Records/ Extent - 32: Records/ Block - 64: Sectors/ Track - 2: Reserved Tracks -``` +| | | +|----------|------------------------------| +| `IDE0:0` | First slice of disk in IDE0 | +| `IDE0:` | First slice of disk in IDE0 | +| `IDE0:3` | Fourth slice of disk in IDE0 | -It is critical that you include "dsk:" after the drive letter in the -`STAT` command line. The important line to look at is labelled "32 Byte -Directory Entries". In this case, the value is 1024 which implies that -this drive is located on a modern (hd1k) disk layout. If the value -was 512, it would indicate a legacy (hd512) disk layout. +So, if you wanted to use drive letter L: to refer to the fourth slice of +IDE0, you could use the command `ASSIGN L:=IDE0:3`. There are a couple +of rules to be aware of when assigning drive letters. First, you may +only refer to a specific device/slice with one drive letter at a time. +Said another way, you cannot have multiple drive letters referring to a +the same device/slice at the same time. Second, there must always be a +drive assigned to A:. Any attempt to violate these rules will be blocked +by the `ASSIGN` command. -## Hard Disk Capacity +As you see, the name of a slice does not reference the hard disk +partition containing the slices. Since there can only be a single +RomWBW partition containing slices on any disk, the partition is +determined automatically. -Although RomWBW can support many CP/M filesystem slices on a single -hard disk, you are still constrained by the physical capacity of the -actual hard disk. RomWBW does not prevent you from assigning slices +RomWBW does not prevent you from assigning slices to drive letters even if the location of the slice does not fit on the physical disk. Any attempt to access a drive letter mapped to a slice that does not fit will result in an error such as "no disk" from the operating system. -The exact number of CP/M filesystem slices that will fit on your +For example, a 64MB CF Card (which is typically a bit smaller +than 64MB) will only fit 7 slices. At startup, you will typically see +8 drive letters assigned to the CF Card. Attempting to access the +last drive letter will result in a "no disk" error from the operating +system. + +### Hard Disk Capacity + +The exact number of CP/M filesystem slices that will fit on your specific physical hard disk can be determined as follows: -- For hd512 disk layouts, it is slices * 8,320KB. -- For hd1k disk layouts, it is 1024KB + (slices * 8192KB). Since - 1024KB is exactly 1MB, it is equivalent to say 1MB + (slices * 8MB). +- For modern (hd1k) disk layouts, it is 1024KB + (slices * 8192KB). + Or equivalent to say 1MB + (slices * 8MB). +- For legacy (hd512) disk layouts, it is slices * 8,320KB. -**WARNING**: In this document KB means 1024 bytes and MB means 1048576 +**WARNING**: In this document KB means 1024 bytes and MB means 1048576 bytes (frequently expressed as KiB and MiB in modern terminology). In general, hard disk capacities use KB to mean 1000 bytes and MB to mean 1,000,000 bytes. -As an example, hardware distributors frequently supply a "64MB" -CF Card with a RomWBW system. Such a hard disk probably has +As an example, A "64MB" CF Card probably has less than 62.5MB of actual space (using the RomWBW definition that 1MB is 1048576 bytes). Such a drive will not support 8 slices. It -will support 7 slices just fine because 7 * 8,320KB = 58.24MB (hd512) -or 1024KB + (7 * 8192MB) = 57MB (hd1k). +will support 7 slices just fine because +1024KB + (7 * 8192MB) = 57MB (hd1k) or +7 * 8,320KB = 58.24MB (hd512) -The cost of high capacity CF/SD/USB Media has become very reasonable. -I highly recommend upgrading to 1GB or greater media. This size will -support all features of the RomWBW Combo Disk Image with 64 slices -and a 384MB FAT filesystem (see [Combo Hard Disk Image]). +Although you can use up to 256 slices per physical disk, +equating to 2GB of storage this large number of slices is rarely used. +It is recommended that hard disk media used with RomWBW be 1GB or +greater in capacity. +This will support the RomWBW Combo Disk Image (see [Combo Hard Disk Image]) +that allows you to use 64 CP/M filesystem slices and a 384KB FAT filesystem. -# Disk Content Preparation +# Disk Preparation -With some understanding of how RomWBW presents disk space to the -operating systems, we need to go over the options for actually setting -up your disk(s) with content. +There are two approaches to preparing disks for use by RomWBW. -Since it would be quite a bit of work to transfer over all the files you -might want initially to your disk(s), RomWBW provides a much easier way -to get initial contents on your disks. You can use your modern -Windows, Linux, or Mac computer to copy a disk image onto the disk -media, then just move the media over to your RomWBW computer. RomWBW -comes with a variety of disk images that are ready to use and have a -much more complete set of files than you will find on the ROM disk. This -process is covered below under [Disk Images]. +- **Manual**: Use RomWBW itself to format empty disks and then transfer + files over to the disks. +- **Images**: Use a modern computer to write a pre-built disk image + including files to a disk. -If you do not want to start with pre-built disk images, you can -alternatively initialize the media in-place using your RomWBW system. -Essentially, this means you are creating a set of blank directories on -your disk so that files can be saved there. This process is described -below under Disk Initialization. In this scenario, you will need to -subsequently copy any files you want to use onto the newly initialized -disk (see [Transferring Files]). - -You will notice that in the following instructions there is no mention -of specific hardware. Because the RomWBW firmware provides a hardware -abstraction layer, all disk images will work on all hardware variations. -Yes, this means you can remove disk media from one RomWBW system and -put it in a different RomWBW system. The only constraint is that the -applications on the disk media must be up to date with the firmware on -the system being used. +This section of the document describes the manual process of preparing +empty disks that are ready for use by an operating system. + +Alternatively, you can use the pre-built RomWBW disk images to quickly +create disk media that already has a large selection of files and +bootable operating system slices. Using images to prepare a disk +is documented in [Disk Images]. You do not need to follow the +instructions in this section if you want to use disk images. -## Disk Images +## Floppy Disk Formatting -As mentioned previously, RomWBW includes a variety of disk images -that contain a full set of applications for the operating systems -supported. It is generally easier to use these disk images than -transferring your files over individually. You use your modern -computer (Windows, Linux, MacOS) to write the disk image onto the -disk media, then just move the media over to your system. +Floppy media must be physically formatted before it can be used. This +is normally accomplished by using the supplied Floppy Disk Utility `FDU` +application. This application interacts directly with your hardware +and therefore you must specify your floppy interface hardware at +application startup. Additionally, you need to specify the floppy disk drive +and media format to use for formatting. + +Refer to $doc_apps$ for more information on use of the `FDU` command. -The disk image files are found in the Binary directory of the -distribution. Floppy disk images are prefixed with "fd_" and hard disk -images are prefixed with either "hd512_" or "hd1k_" depending on the -hard disk layout they are for. +Since the physical format of floppy media is the same as that used +in a standard MS-DOS/Windows computer, you can also format +floppy disk media in a standard computer. However there are caveats: -Each disk image has the complete set of normal applications and tools +* The directory format itself will **NOT** be compatible with CP/M OSes. + You **WILL** need to use the `CLRDIR` command to reformat the directory area + from CP/M. See section [Clearing (Formatting) Drives] +* FDU allows you to specify physical sector interleaving (defaults to 2) + which will result in faster floppy disk I/O. + Formatting on a modern computer may not optimize this. + +Below is a sample session using `FDU` to format a 1.44M floppy disk in +the first (primary) floppy disk drive: + +``` +B>FDU + +Floppy Disk Utility (FDU) v5.8, 26-Jul-2021 [HBIOS] +Copyright (C) 2021, Wayne Warthen, GNU GPL v3 + +SELECT FLOPPY DISK CONTROLLER: + (A) Disk IO ECB Board + (B) Disk IO 3 ECB Board + (C) Zeta SBC Onboard FDC + (D) Zeta 2 SBC Onboard FDC + (E) Dual IDE ECB Board + (F) N8 Onboard FDC + (G) RCBus SMC (SMB) + (H) RCBus WDC (SMB) + (I) SmallZ80 Expansion + (J) Dyno-Card FDC, D1030 + (K) RCBus EPFDC + (L) Multi-Board Computer FDC + (X) Exit +=== OPTION ===> D-IDE + +===== D-IDE ===========<< FDU MAIN MENU >>====================== +(S)ETUP: UNIT=00 MEDIA=720KB DS/DD MODE=POLL TRACE=00 +---------------------------------------------------------------- +(R)EAD (W)RITE (F)ORMAT (V)ERIFY +(I)NIT BUFFER (D)UMP BUFFER FDC (C)MDS E(X)IT +=== OPTION ===> SETUP +ENTER UNIT [00-03] (00): +00: 3.5" 720KB - 9 SECTORS, 2 SIDES, 80 TRACKS, DOUBLE DENSITY +01: 3.5" 1.44MB - 18 SECTORS, 2 SIDES, 80 TRACKS, HIGH DENSITY +02: 5.25" 320KB - 8 SECTORS, 2 SIDES, 40 TRACKS, DOUBLE DENSITY +03: 5.25" 360KB - 9 SECTORS, 2 SIDES, 40 TRACKS, DOUBLE DENSITY +04: 5.25" 1.2MB - 15 SECTORS, 2 SIDES, 80 TRACKS, HIGH DENSITY +05: 8" 1.11MB - 15 SECTORS, 2 SIDES, 77 TRACKS, DOUBLE DENSITY +06: 5.25" 160KB - 8 SECTORS, 1 SIDE, 40 TRACKS, DOUBLE DENSITY +07: 5.25" 180KB - 9 SECTORS, 1 SIDE, 40 TRACKS, DOUBLE DENSITY +08: 5.25" 320KB - 8 SECTORS, 1 SIDE, 80 TRACKS, DOUBLE DENSITY +09: 5.25" 360KB - 9 SECTORS, 1 SIDE, 80 TRACKS, DOUBLE DENSITY +ENTER MEDIA [00-09] (00): 01 +00: POLLING (RECOMMENDED) +01: INTERRUPT (!!! READ MANUAL !!!) +02: FAST INTERRUPT (!!! READ MANUAL !!!) +03: INT/WAIT (!!! READ MANUAL !!!) +04: DRQ/WAIT (!!! NOT YET IMPLEMENTED!!!) +ENTER MODE [00-04] (00): +ENTER TRACE LEVEL [00-01] (00): + +===== D-IDE ===========<< FDU MAIN MENU >>====================== +(S)ETUP: UNIT=00 MEDIA=1.44MB DS/HD MODE=POLL TRACE=00 +---------------------------------------------------------------- +(R)EAD (W)RITE (F)ORMAT (V)ERIFY +(I)NIT BUFFER (D)UMP BUFFER FDC (C)MDS E(X)IT +=== OPTION ===> FORMAT (T)RACK, (D)ISK ===> DISK +ENTER INTERLEAVE [01-12] (02): + +RESET DRIVE... +PROGRESS: TRACK=4F HEAD=01 SECTOR=01 + +===== D-IDE ===========<< FDU MAIN MENU >>====================== +(S)ETUP: UNIT=00 MEDIA=1.44MB DS/HD MODE=POLL TRACE=00 +---------------------------------------------------------------- +(R)EAD (W)RITE (F)ORMAT (V)ERIFY +(I)NIT BUFFER (D)UMP BUFFER FDC (C)MDS E(X)IT +=== OPTION ===> EXIT +``` + +You can confirm a floppy disk is ready for content by simply running a `DIR` +command on it. The `DIR` command should complete without error and +should list no files. + +## Hard Disk Preparation + +This section deals with initializing hard disk media entirely from +your RomWBW system. The following instructions are one way to proceed. +This does not mean to imply it is the only possible way. + +First you need to understand + +* The disk layout approach (either hd1k or the legacy hd512). + See [Hard Disk Layouts] section if you are not sure. + hd1k should be the preferred layout. +* The number of 8MB slices that you want to allocate, preferred is 64 slices. + At least 1 slice of 8MB is required +* If you want to leave space for a FAT partition. See [FAT Filesystem Preparation] +* The total capacity of your drive, to hold the CP/M (and other) partition(s) + +Then you will need to start by inserting the disk media, +booting RomWBW, and confirming that the media is being recognized. +If RomWBW recognizes the media, it will indicate this in the +boot messages even though the media may not yet been prepared for use. + +Then launch either CP/M 2.2 or Z-System from ROM using the +Boot Loader `C` or `Z` commands respectively. +You can now use the tools on the ROM disk to prepare your disks. + +Note that you may see the operating system assign disks/slices to +drives letters even though the disks/slices are not yet initialized. This is +normal and does not mean the disks/slices are ready to use. + +### Partition Setup + +To setup a partition you must run the `FDISK80` utility. +After FDISK80 starts, enter the disk unit number of the new media. +The disk unit number was assigned at boot See [Device Unit Assignments] + +Refer to $doc_apps$ for more information on use of the `FDISK80` utility. + +If you want to use the legacy hd512 layout skip down to the [Legacy (hd512)] section + +#### Modern (hd1k) + +At this point, use the `I` command to initialize (reset) +the partition table to an empty state. + +You must create a partition for the RomWBW CP/M slices. +Then create a partition using the `N` command. Importantly: + +* The partition number should typically be `1` the first partition +* The partition can be placed anywhere you want, + The typical location for the RomWBW partition is at 1MB. +* The partition size should be the total size of all the slices you require, + and must be at least 8MB in size, in increments of 8MB makes sense. + +You **must** then set the type of partition to `2E` using the `T` command. +The `P` command can be used to display the partition before it is written +Finally the partition can be written to disk using the `W` write command. + +**WARNING**: Modifying the partition table of existing media will +make any data on the media inaccessible. + +Below is an example of creating a RomWBW +partition following these guidelines. + +``` +FDISK80 for RomWBW, UNA, Mini-M68k, KISS-68030, SBC-188 ---- + Version 1.1-22 created 7-May-2020 + (Running under RomWBW HBIOS) + +HBIOS unit number [0..11]: 4 +Capacity of disk 4: ( 4G) 7813120 Geom 77381010 +Nr ---Type- A -- Start End LBA start LBA count Size + 1 00 *** empty *** + 2 00 *** empty *** + 3 00 *** empty *** + 4 00 *** empty *** +>>i +>>n +New partition number: 1 +Starting Cylinder (default 0): 1Mb +Ending Cylinder (or Size= "+nnn"): +512Mb +>>t +Change type of partition number: 1 +New type (in hex), "L" lists types: 2e +>>p +Nr ---Type- A -- Start End LBA start LBA count Size + 1 RomWBW 2e 8:0:1 1023:15:16 2048 1048576 512M + 2 00 *** empty *** + 3 00 *** empty *** + 4 00 *** empty *** +>>w +Do you really want to write to disk? [N/y]: y +Okay +FDISK exit. +``` + +At this point, it is best to restart your system to make sure that +the operating system is aware of the partition table updates. Start +CP/M 2.2 or Z-System from ROM again. + +#### Legacy (hd512) + +At this point, use the `I` command to initialize (reset) +the partition table to an empty state. + +To use the hd512 layout, use `W` to write the empty table to the disk +and exit. Remember that the lack of a partition for RomWBW implies the +legacy (hd512) layout. + +At this point, it is best to restart your system to make sure that +the operating system is aware of the partition table updates. Start +CP/M 2.2 or Z-System from ROM again. + +#### FAT Partition + +At this point you may want to consider creating a FAT partition +Please see the section [FAT Filesystem Preparation] for detils on how +to setup the FAT partition. + +### Slice Initialization + +You need to initialize each slice for CP/M to use it. +This is somewhat analogous to doing a FORMAT operation on other systems, +and is done using the `CLRDIR` command. + +This is covered in the section [Clearing (Formatting) Drives] + +**WARNING**: Earlier versions of the `CLRDIR` application do not +appear to check for disk errors when it runs. If you attempt to run +`CLRDIR` on a drive that is mapped to a slice that does not actually fit +on the physical disk, it may behave erratically. + +Assuming you want to use additional slices, you should initialize them +using the same process. You may need to reassign drive letters to +access some slices that are beyond the ones automatically assigned. +You can use the `ASSIGN` command to handle this. + +## Post Disk Preparation + +Once a disk (either floppy or hard disk) has been initialised and +formattted you may optionally; +* Make the disk bootable +* Copy system (or other) files to the disk + +### Making a Disk Bootable + +To make a disk bootable you will need to follow the specific instructions +in [Operating Systems], as each operating system will be different. + +Generally you will need to use `SYSCOPY` to setup the system track(s) +of the disk.As an example, If you wanted to setup C: as a bootable +Z-System disk you would use: + +``` +B>SYSCOPY C:=B:ZSYS.SYS + +SYSCOPY v2.0 for RomWBW CP/M, 17-Feb-2020 (CP/M 2 Mode) +Copyright 2020, Wayne Warthen, GNU GPL v3 + +Transfer system image from B:ZSYS.SYS to C: (Y/N)? Y +Reading image... Writing image... Done +``` + +Once this process succeeds, you will be able to boot directly to the +disk slice from the boot loader prompt. See the instructions in +[Starting Operating Systems from Disk] for details on this. + +### Copying System Files + +As well as making the disk bootable, you may need to transfer other +system and application files to your disks. +Refer to [Transferring Files] for more information on getting +files onto your disks. + +# Disk Images + +Since it would be quite a bit of work to transfer over all the files you +might want initially to your disk(s), It is generally easier to use +these disk images than transferring your files over individually. RomWBW +comes with a variety of ready to use disk images. + +You can use your modern +Windows, Linux, or Mac computer to copy a disk image onto the disk +media, then just move the media over to your RomWBW computer. + +The disk image files are found in the Binary directory of the +distribution. + +Each disk image has the complete set of normal applications and tools distributed with the associated operating system or application suite. The following table shows the disk images available. -| **Disk Image** | **Description** | **Boot** | -|-----------------|----------------------------------------|----------| -| xxx_cpm22.img | DRI CP/M 2.2 Operating System | Yes | -| xxx_zsdos.img | ZCPR-DJ & ZSDOS 1.1 Operating System | Yes | -| xxx_nzcom.img | NZCOM ZCPR 3.4 Operating System | Yes | -| xxx_cpm3.img | DRI CP/M 3 Operating System | Yes | -| xxx_zpm3.img | ZPM3 Operating System | Yes | -| xxx_qpm.img | QPM Operating System | Yes | -| xxx_dos65.img | DOS/65 Operating System | Yes | -| xxx_ws4.img | WordStar v4 & ZDE Applications | No | +| **Disk Image** | **Description** | **Boot** | +|-------------------|--------------------------------------|----------| +| xxx_aztec.img | Aztec C Compiler | No | +| xxx_bascomp.img | Microsoft Basic-80 Compiler | No | +| xxx_blank.img | _empty image_ | No | +| xxx_cowgol.img | Cowgol 2.0 Compiler | No | +| xxx_cpm22.img | DRI CP/M 2.2 Operating System | Yes | +| xxx_cpm3.img | DRI CP/M 3 Operating System | Yes | +| xxx_dos65.img | DOS/65 Operating System | Yes | +| xxx_fortran.img | Microsoft Fortran-80 Compiler | No | +| xxx_games.img | Games Disk for CP/M | No | +| xxx_hitechc.img | HI-TECH Z80 CP/M C compiler | No | +| xxx_msxroms1.img | MSX ROMs Disk 1 | No | +| xxx_msxroms2.img | MSX ROMs Disk 2 | No | +| xxx_nzcom.img | NZCOM ZCPR 3.4 Operating System | Yes | +| xxx_qpm.img | QPM Operating System | Yes | +| xxx_tpascal.img | Borland Turbo Pascal Compiler | No | +| xxx_ws4.img | WordStar v4 & ZDE Applications | No | +| xxx_z80asm.img | Relocating macro assembler for CP/M | No | +| xxx_zpm3.img | ZPM3 Operating System | Yes | +| xxx_zsdos.img | ZCPR-DJ & ZSDOS 1.1 Operating System | Yes | You will find 3 sets of these .img files in the distribution. The -"xxx" portion of the filename will be "fd_" for a floppy image, -"hd512" for a legacy layout hard disk image, and "hd1K" for a modern -layout hard disk image. +"xxx" portion of the filename will be: + +* "fd_" for a floppy image. +* "hd1k_" for a modern layout hard disk image. +* "hd512_" for a legacy layout hard disk image. In the case of xxx_dos65.img, only an hd512 variant is provided. This is a constraint of the DOS65 distribution. -There is also an image file called "psys.img" which contains a bootable +There is also an image file called "psys.img" which contains a bootable p-System hard disk image. It contains 6 p-System filesystem slices, but these are not interoperable with the CP/M slices described above. This -file is discussed separately under p-System in the [Operating Systems] +file is discussed separately under [UCSD p-System] in Operating Systems section. -### Floppy Disk Images +## Floppy Disk Images The floppy disk images are all intended to be used with 3.5" high-density, double-sided 1.44 MB floppy disk media. This is ideal for the default -floppy drive support included in RomWBW standard ROMs. +floppy disk drive support included in RomWBW standard ROMs. -For floppy disks, the .img file is written directly to the floppy media -as is. The floppy .img files are 1.44 MB which is the exact size of a +For floppy disks, the .img file is written directly to the floppy media +as is. The floppy .img files are 1.44 MB which is the exact size of a single 3.5" high density floppy disk. You will need a floppy disk drive of the same type connected to your modern computer to write this -image. Although modern computers do not come equipped with a floppy +image. Although modern computers do not come equipped with a floppy disk drive, you can still find USB floppy drives that work well for this. The floppy disk must be physically formatted **before** writing the -image onto it. You can do this with RomWBW using FDU as described -in the [Floppy Disks] section of this document. You can also format -the floppy using your modern computer, but using FDU on RomWBW is -preferable because it will allow you to use optimal physical sector -interleaving. FDU defaults to a sector interleave of 2 which will -result in faster floppy disk I/O. Other interleaves will work, but -will be slower. - -RomWBW includes a Windows application called RawWriteWin in the Tools -directory of the distribution. This simple application will let you -choose a file and write it to an attached floppy drive. For Linux/MacOS, -I think you can use the dd command (but I have not actually tried -this). It is probably obvious, but writing an image to a floppy disk +image onto it. You can do this with RomWBW using `FDU` as described +in the [Floppy Disk Formatting] section of this document. +While you can also format the floppy using your modern computer, +using `FDU` is preferable. + +RomWBW includes a Windows application called RawWriteWin in the Tools +directory of the distribution. This simple application will let you +choose a file and write it to an attached floppy disk drive. For Linux/MacOS, +I think you can use the dd command (but I have not actually tried +this). It is probably obvious, but writing an image to a floppy disk will overwrite and destroy all previous contents. Once the image has been written to the floppy disk, you can insert the floppy disk in your RomWBW floppy disk and read/write files on it according to the specific operating system instructions. If the image is bootable, then you will be able to boot from it by entering -the floppy drive's corresponding unit number at the RomWBW Boot Loader +the floppy disk drive's corresponding unit number at the RomWBW Boot Loader command prompt. -### Hard Disk Images +## Hard Disk Images Keeping in mind that a RomWBW hard disk (including CF/SD/USB devices) allows you to have multiple slices (CP/M filesystems), there are a -couple ways to image hard disk media. The easiest approach is to +couple ways to image hard disk media. The easiest approach is to use the "combo" disk image. This image is already prepared with 6 slices containing 5 ready-to-run OSes and a slice with -the WordStar application files. Alternatively, you can create your own +the WordStar application files. + +Alternatively, you can create your own hard disk image with the specific slice contents you choose. -#### Standard Hard Disk Physical Layout +### Standard Hard Disk Physical Layout As previously described in [Hard Disk Layouts], the exact placement of slices and optional FAT partition will vary depending on which disk @@ -1881,80 +2091,101 @@ of the individual filesystem images (slices) already concatenated together. The combo disk image contains the following 6 slices in the positions indicated: -| **Slice** | **Description** | -|-----------|------------------------------------------------------------------| -| Slice 0 | DRI CP/M 2.2 Operating System | -| Slice 1 | ZCPR-DJ & ZSDOS 1.1 Operating System | -| Slice 2 | NZCOM ZCPR 3.4 Operating System | -| Slice 3 | DRI CP/M 3 Operating System | -| Slice 4 | ZPM3 Operating System | -| Slice 5 | WordStar v4 & ZDE Applications | - -You will notice that there are actually 2 combo disk images in the +| **Slice** | **Description** | +|------------|-----------------------------------------| +| Slice 0 | DRI CP/M 2.2 Operating System | +| Slice 1 | ZCPR-DJ & ZSDOS 1.1 Operating System | +| Slice 2 | NZCOM ZCPR 3.4 Operating System | +| Slice 3 | DRI CP/M 3 Operating System | +| Slice 4 | ZPM3 Operating System | +| Slice 5 | WordStar v4 & ZDE Applications | +| Slice 6-63 | _blank unformatted_ | + +There are actually 2 primary combo disk images in the distribution. One for an hd512 disk layout (hd512_combo.img) and one for an hd1k disk layout (hd1k_combo.img). Simply use the image file that corresponds to your desired hard disk layout. Review the information in [Hard Disk Layouts] if you need more information of the disk layout options. -Although the combo disk images contain only 6 slices of content, they -reserve space to store 64 CP/M filesystem slices as well as a -single 384MB FAT filesystem. Keep in mind that the slices beyond the -first 6 are not yet initialized. You will need to use the `CLRDIR` -application to initialize them before their first use. Likewise, the -pre-allocated FAT partition must still be formatted using `FAT FORMAT` -in order to actually use it (see [FAT Filesystem Preparation]). -Alternatively, the FAT partition can be formatted on a modern computer. +> **Note**: Apart from the hd512 and hd1k combo disk images (mentioned above) +> there are actaully a number of other `hd1k_*_combo.img` files. These +> additional combo files are platform (generally romless) specific, +> and should be ignored unless you are on one of these platforms. +> If you are on one of these platforms you must use the correct combo file + +The combo disk image actaully only contains the initial partition table, +and the first 6 slices (Slice 0 to 5), this is approximately 49MB in size. +While the partition table reserves space to store 64 CP/M filesystem +slices as well as a single 384MB FAT filesystem, these area remain +empty, and must be manuall initialized manually. + +#### Combo Image Capacity The combo disk image layout was designed to fit well on a 1GB hard disk. The 64 CP/M slices (approximately 512MB) and 384MB FAT filesystem all fit well within a 1GB hard disk. This size choice was a bit arbitrary, but based on the idea that 1GB CF/SD/USB Media is easy and cheap to -acquire. It is fine if your hard disk is smaller than 1GB. It just -means that it will not be possible to use the pre-allocated FAT -filesystem partition and any CP/M filesystem slices that don't fit. You -will get "no disk" errors if you attempt to access a slice past the -end of the physical hard disk. +acquire. -**WARNING**: Your hard disk may be too small to contain the full 64 -CP/M filesystem slices. The true number of CP/M filesystem slices that +It is fine if your hard disk is smaller than 1GB. It just +means that it will not be possible to use the pre-allocated FAT +filesystem partition and any CP/M filesystem slices that don't fit. +The true number of CP/M filesystem slices that will fit on your specific physical hard disk can be calculated as described in [Hard Disk Capacity]. -For RomWBW systems with a single hard disk (typical), you will notice -that the OS will pre-allocate 8 drive letters to the hard disk. If the -combo disk image is being used, only the first 6 drive letters -(typically C: - H:) will have any content because the combo disk image -only provides 6 slices. The subsequent drives (typically I: - J:) will -have no content and will not be pre-initialized. If you want to use any -slices beyond the first 6 on the hard disk, then you must initialize -them using `CLRDIR` first. +If you attempt to access a slice past the end of the +physical hard disk you will get "no disk" errors. +You should calculate the maximum number of slices your hard disk +will support and do not exceed this number. + +#### Combo Image Advice A great way to maintain your own data on a hard disk is to put this data in slices beyond the first 6. By doing so, you can always -"re-image" your drive with the combo image without overlaying the data +"re-image" your drive media with the combo image without overlaying the data stored in the slices beyond the first 6. Just be very careful to use the same combo image layout (hd512 or hd1k) as you used originally. -Also remember to calculate the maximum number of slices your hard disk -will support and do not exceed this number. - -**WARNING**: The combo disk image includes a partition table at the -start of the image. If you re-image drive with the combo image, you -will overwrite this partition table. This is fine as long as you don't -make any changes to the partition table. If you manually customize the -partition table (using `FDISK80` or other partition management -software), those changes will be lost if you re-image your disk with a -new combo disk image. -#### Custom Hard Disk Image - -If you want to use specific slices in a specific order, you can easily -generate a custom hard disk image file. +### Custom Hard Disk Image For hard disks, each .img file represents a single slice (CP/M filesystem). Since a hard disk can contain many slices, you can just concatenate the slices (.img files) together to create your desired hard -disk image. For example, if you want to create a hard disk image that +disk image. + +If you look in the Binary directory of the distribution, you will see +that there are more disk (slice) images than the 6 that are included +in the "combo" disk images. These images are identified by looking +for the files that start with hd1k_ or hd512_. + +#### Adding Slices to Combo Image + +You can add slices to the combo disk images simply by tacking +slices onto the end. For example, if you want to add a slice +containing the MSX ROMs to the end of the combo image, you could +use one of the following command lines depending on your operating +system: + +Windows: + +`COPY /B hd1k_combo.img + hd1k_msxroms.img my_hd.img` + +Linus/MaxOS: + +`cat hd1k_combo.img hd1k_msxroms.img >my_hd.img` + +Note that you **must** be sure to use either the hd1k_ or hd512_ +prefixed files together. You cannot mix them. + +#### Creating a new Custom Image + +If you want to create a completely custom hard disk image that is not +based on the existing combo image, you can generate a disk image entirely +from scratch using whatever slices you want in whatever order you like. + +For example, if you want to create a hard disk image that has slices for CP/M 2.2, CP/M 3, and WordStar in the hd512 format, you would use the command line of your modern computer to create the final image: @@ -1979,6 +2210,12 @@ Linux/MacOS: `cat hd1k_prefix.dat hd1k_cpm22.img hd1k_cpm3.img hd1k_ws >hd.img` +> **Note**: Apart from the hd1k_prefix.dat file (mentioned above) +> there are actaully a number of other `hd1k_*_prefix.dat` files. These +> additional prefix files are platform (generally romless) specific, +> and should be ignored unless you are on one of these platforms. +> If you are on one of these platforms you must use the correct prefix file + In all of the examples above, the resulting file (hd.img) would now be written to your hard disk media and would be ready to use in a RomWBW system. @@ -1986,35 +2223,26 @@ system. If you wish to further customize or create new disk image definitions, please refer to the ReadMe.txt file in the Source/Images directory. -#### Writing Hard Disk Images +### Writing Hard Disk Images Once you have chosen a combo hard disk image file or prepared your own custom hard disk image file, it will need to be written to the media -using your modern computer. Note that you **do not** run `CLRDIR` or -`SYSCOPY` on the slices that contain the data. When using this method, +using your modern computer. When using this method, the disk will be partitioned and setup with 1 or more slices containing -ready-to-run bootable operating systems. You **do** need to run -`CLRDIR` and optionally `SYSCOPY` on slices that are not part of the -image (slices beyond the ones included with the image). +ready-to-run bootable operating systems. To write a hard disk image file onto your actual media (actual hard disk or CF/SD/USB Media), you need to use an image writing utility on your modern computer. Your modern computer will need to have an appropriate -interface or slot that accepts the media. To actually copy the image, -you can use the `dd` command on Linux or MacOS. On Windows, in the -"Tools" directory of the distribution, there is an application called -Win32DiskImager. In all cases, the image file should be written to the -media starting at the very first block or sector of the media. +interface or slot that accepts the media. To actually copy the image -You are not limited to the number of slices that are contained in the -image that you write to your hard disk media. You can use additional -slices as long your media has room for them. However, writing the disk -image will not initialize the additional slices. If these additional -slices were previously initialized, they will not be corrupted when you -write the new image and will still contain their previous contents. If -the additional slices were not previously initialized, you can use -`CLRDIR` to do so and optionally `SYSCOPY` if you want them to be -bootable. +* On Linux or MacOS , you can use the `dd` command. +* On Windows, in the "Tools" directory of the distribution, there is + an application called Win32DiskImager. + +In all cases, the image file should be written to the +media starting at the very first block or sector of the media. +This is the default behaviour on all software. To be entirely clear, writing a disk image file to your hard disk media will overwrite an pre-existing partition table and the number of slices @@ -2024,180 +2252,120 @@ slices as a place to maintain your personal data because these slices will survive re-imaging of the media. If you setup a FAT partition on your media, it will also survive the imaging process. -**WARNING**: In order for your additional slices and/or FAT partition to -survive re-imaging, you **must** follow these rules: - -* Do not modify the partition table of the media using FDISK80 or any - other partition management tools. -* Ensure that your hard disk image file uses the same disk layout - approach (hd512 or hd1k) as previously used on the media. +#### Media Usage and Initialization Once you have copied the image onto the hard disk media, you can move the media over to your RomWBW system. You can then boot to the -operating system slices by specifying "." at the +operating system slices by specifying (***\.\***) at the RomWBW Boot Loader command prompt. +See the section [Starting Operating Systems from Disk] for further details + +You are not limited to the number of slices that are contained in the +image that you write to your hard disk media. You can use additional +slices as long your media has room for them. + +However, writing the disk image will not initialize the additional slices. +You will need to use the `CLRDIR` application to initialize +any un-initialized slice before its first use, +and and optionally `SYSCOPY` if you want th slice to be bootable. +If you use the combo image this applies to slices 6 thru 63. +The procedure for this is documented in the +[Clearing (Formatting) Drives] section. + +Likewise, the pre-allocated FAT partition must still be formatted using +`FAT FORMAT` in order to actually use it (see [FAT Filesystem Preparation]). +Alternatively, the FAT partition can be formatted on a modern computer. -## In-situ Disk Preparation - -If you do not wish to use the pre-built disk images, it is entirely -possible to setup your disks manually and transfer contents to them. - -In this scenario, you will initialize the disk media entirely from -your RomWBW system. So, you need to start by inserting the disk -media, booting RomWBW, and confirming that the media is being -recognized. If RomWBW recognizes the media, it will indicate this -in the boot messages even though the media has not yet been prepared -for use. - -The following instructions are one way to proceed. This does not mean -to imply it is the only possible way. Also, note that RAM/ROM disk -media is prepared automatically. ROM disks are part of the ROM image -and RAM disks are initialized when an operating system is started. +#### Re-Imaging Existing Media -Start by booting RomWBW and launching either CP/M 2.2 or Z-System -from ROM using the Boot Loader 'C' or 'Z' commands respectively. You -can now use the tools on the ROM disk to prepare your disks. Note -that you will see the operating system assign disks/slices to -drives even though the disks/slices are not yet initialized. This is -normal and does not mean the disks/slices are ready to use. +In order for your additional slices and/or FAT partition to +survive re-imaging, you **must** follow these rules: -Preparation of floppy disk media is very simple. The floppy disk must -be physically formatted as discussed in [Floppy Disks] previously using -`FDU`. If a floppy is already physically formatted, you can wipe out -it's contents (make it empty again) by running `CLRDIR` on it. You can -confirm a floppy disk is ready for content by simply running a `DIR` -command on it. The `DIR` command should complete without error and -should list no files. At this point, you can proceed to copy files to -the floppy disk and (optionally) make the floppy bootable using -`SYSCOPY`. +* Do not modify the partition table of the media using FDISK80 or any + other partition management tools. +* Ensure that your hard disk image file uses the same disk layout + approach (hd512 or hd1k) as previously used on the media. -The rest of this section will cover preparation of hard disk media. To -start, it is critical that you decide which disk layout approach to use -(either hd512 or hd1k). Review the [Hard Disk Layouts] section if you -are not sure. +### Writing Hard Disk Slices -#### Partition Setup +This section covers techniques to copy partial images onto pre-existing media, +in effect performing a selective slice copy. These techniques currently **only** apply to +hd1k formatted media, which has a convienient 1MB size metric. +However adapting to hd512 is possible. -**WARNING**: Modifying the partition table of existing media will -make the data on the media inaccessible. - -Since the disk layout is determined by the existence (or lack) of -a RomWBW partition, you must start by running `FDISK80`. When FDISK80 -starts, enter the disk unit number of the new media. At this point, -use the 'I' command to initialize (reset) the partition table to an -empty state. If you are going to use the hd512 layout, then use 'W' to -write the empty table to the disk and exit. Remember that the lack of a -partition for RomWBW implies the legacy (hd512) layout. - -If you are going to use an hd1k layout, then you must create a partition -for the RomWBW CP/M slices. The partition can be placed anywhere you -want and can be any size >= 8MB. Keeping the size of the partition to -increments of 8MB makes sense. The partition type **must** be set to -'2e'. The typical location for the RomWBW partition is at 1MB with a -size of 512MB (64 slices). Below is an example of creating a RomWBW -partition following these guidelines. +On Linux/MacOS the `dd` command can be used to write data in a controlled manner. +The `dd` command supports options to define precisly souce +and destination offsets and sizes to copy. +From the documentation of `dd` the following options are important. ``` -FDISK80 for RomWBW, UNA, Mini-M68k, KISS-68030, SBC-188 ---- - Version 1.1-22 created 7-May-2020 - (Running under RomWBW HBIOS) + if=file Read input from file instead of the standard input. + of=file Write output to file instead of the standard output. + skip=n Skip n blocks from the beginning of the input before + copying. + seek=n Seek n blocks from the beginning of the output before + copying. + count=n Copy only n input blocks. + bs=n Set both input and output block size to n bytes instead + of the default 512 + ``` + +In the following examples we use the above options, noting the `of=` option +is specific to your computer but defines the block device that the target +media is mounted to in the operating system, +and `bs=1MB` defines the block size used in other parameters which is convienient +since it aligns perfectly with slices which are exactly 8MB +and the initial partition table is exactly 1MB. + +The commands in the examples below are run from the `Binary` folder of RomWBW distribution. + +#### Example 1 : Copy the Combo Image without replacing partition table + +In this example we will copy the (hd1k) combo image over our media +without replacing the partition table. In this example we assume the media +has already been formated with the combo image, and we have modified +the partition table, which we do not want to overrite. -HBIOS unit number [0..11]: 4 -Capacity of disk 4: ( 4G) 7813120 Geom 77381010 -Nr ---Type- A -- Start End LBA start LBA count Size - 1 00 *** empty *** - 2 00 *** empty *** - 3 00 *** empty *** - 4 00 *** empty *** ->>i ->>n -New partition number: 1 -Starting Cylinder (default 0): 1Mb -Ending Cylinder (or Size= "+nnn"): +512Mb ->>t -Change type of partition number: 1 -New type (in hex), "L" lists types: 2e ->>p -Nr ---Type- A -- Start End LBA start LBA count Size - 1 RomWBW 2e 8:0:1 1023:15:16 2048 1048576 512M - 2 00 *** empty *** - 3 00 *** empty *** - 4 00 *** empty *** ->>w -Do you really want to write to disk? [N/y]: y -Okay -FDISK exit. ``` +Binary % sudo dd if=hd1k_combo.img of=/dev/disk9 skip=1 seek=1 bs=1M -At this point, it is best to restart your system to make sure that -the operating system is aware of the partition table updates. Start -CP/M 2.2 or Z-System from ROM again. - -You are now ready to initialize the individual slices of your hard disk -media. On RomWBW, slice initialization is done using the CLRDIR -application. Since the CLRDIR application works on OS drive letters, -you must pay attention to how the OS drive letters are mapped to your -disk devices which is listed when the OS starts. Let's assume that C: -has been assigned to slice 0 of the disk you are initializing. You -would use `CLRDIR C:` to initialize C: and prepare it hold files. Note -that CLRDIR will prompt you for confirmation and you must respond with a -**capital** 'Y' to confirm. - -After CLRDIR completes, the slice should be ready to use by the operating -system via the drive letter assigned. Start by using the `DIR` command -on the drive (`DIR C:`). This should return without error, but list -no files. Next, use the `STAT` command to confirm that the disk is -using the layout you intended. For example, use `STAT C:DSK:` and -look at the number of "32 Byte Directory Entries". It should say -512 for a legacy (hd512) disk layout and 1024 for a modern (hd1024) -disk layout. - -Assuming you want to use additional slices, you should initialize them -using the same process. You may need to reassign OS drive letters to -access some slices that are beyond the ones automatically assigned. -You can use the `ASSIGN` command to handle this. +Password: -Once you have your slice(s) initialized, you can begin transferring -files to the associated drive letters. Refer to the [Transferring -Files] chapter for options to do this. If you want to make a slice -bootable, you will need to use `SYSCOPY` to setup the system track(s) -of the slice. The use of `SYSCOPY` depends on the operating system -and is described in the [Operating Systems] chapter of this document. +48+0 records in +48+0 records out +50331648 bytes transferred in 11.503776 secs (4745528 bytes/sec) +``` -As an example, let's assume you want to setup C: as a bootable -Z-System disk and add to it all the files from the ROM disk. To -setup the system track you would use: +The `skip=1` skips the first 1MB in the input file, and likewise +`seek=1` skips the first 1MB of the target media file we are writing to, +tus in effect we are skipping the first 1MB, which contains the +partition table itself. -``` -B>SYSCOPY C:=B:ZSYS.SYS +#### Example 2 : Copy the Games image to an empty slice of our media -SYSCOPY v2.0 for RomWBW CP/M, 17-Feb-2020 (CP/M 2 Mode) -Copyright 2020, Wayne Warthen, GNU GPL v3 +In this example we will copy the (hd1k) games image to Slice 6 (free) +of our existing media. In this example we assume the media +has already been formated with the combo image, which already +contains 6 slices (numbered from 0 to 5) +We are just coping the needed slice to this existing media +as a new slice (number 6) after the existing slices making it the 7th slice. -Transfer system image from B:ZSYS.SYS to C: (Y/N)? Y -Reading image... Writing image... Done ``` +Binary % sudo dd if=hd1k_games.img of=/dev/disk9 seek=49 bs=1M -Then, to copy all of the files from the ROM disk to C:, you could use -the `COPY` command as shown below. In this example, the list of files -being copied has been truncated. +Password: -``` -B>copy *.* m: -COPY Version 1.73 (for ZSDOS) 2 Jul 2001 -Copying B0:????????.??? to M0: - -> ASM .COM..Ok Verify..Ok - -> ASSIGN .COM..Ok Verify..Ok - -> CLRDIR .COM..Ok Verify..Ok - -> COMPARE .COM..Ok Verify..Ok - -> COPY .COM..Ok Verify..Ok - -> CPM .SYS..Ok Verify..Ok - 0 Errors +8+0 records in +8+0 records out +8388608 bytes transferred in 1.917296 secs (4375228 bytes/sec) ``` -Once this process succeeds, you will be able to boot directly to the -disk slice from the boot loader prompt. See the instructions in -[Starting Operating Systems from Disk] for details on this. +The `seek=49` skips the first 49MB of the media file we are writing to. +49 is calculated as `(slice number * 8) + 1`, +where 8 is the size of a slice +and 1 is the size of the partition table im megabytes. +Thus we are skipping 6 slices (in the combo image) +and writing to the 7th slice. # Operating Systems @@ -2222,8 +2390,8 @@ same basic filesystem format from DRI CP/M 2.2 (except for p-System). As a result, a formatted filesystem will be accessible to any operating system. The only possible issue is that if you turn on date/time stamping using the newer OSes, the older OSes will not understand this. -Files will not be corrupted, but the date/time stamps will not be -maintained. +The older OS will not corrupt the files, but the date/time stamps will +not be maintained. The following sections briefly describe the operating system options currently available and brief operating notes. @@ -2312,32 +2480,16 @@ call "ZSYS.SYS". For example: * ZSDOS has a concept of fast relog of drives. This means that after a warm start, it avoids the overhead of relogging all the disk drives. - There are times when this causes issues. After using tools like CLRDIR + There are times when this causes issues. After using tools like `CLRDIR` or MAP, you may need to run “RELOG†to get the drive properly recognized by ZSDOS. -* RomWBW fully supports both DateStamper and P2DOS file date/time - stamping. You must load the desired stamping module (`LDDS` for - DateStamper or `LDP2D` for P2DOS). This could be automated using - a `PROFILE.SUB` file. Follow the ZSDOS documentation to initialize - a disk for stamping. - * ZSVSTAMP expects to be running under the ZCPR 3.X command processor. By default, RomWBW uses ZCPR 1.0 (intentionally, to reduce space usage) and ZSVSTAMP will just abort in this case. It will work fine if you implement NZCOM. ZSVSTAMP is included solely to facilitate usage if/when you install NZCOM. -* FILEDATE only works with DateStamper style date stamping. If you run - it on a drive that is not initialized for DateStamper, it will complain - `FILEDATE, !!!TIME&.DAT missing`. This is normal and just means that - you have not initialized that drive for DateStamper (using PUTDS). - -* ZXD will handle either DateStamper or P2DOS type date stamping. - However, it **must** be configured appropriately. As distributed, it will - look for P2DOS date stamps. Use ZCNFG to reconfigure it for P2DOS if - that is what you are using. - * Many of the tools can be configured (using either ZCNFG or DSCONFIG). The configuration process modifies the actual application file itself. This will fail if you try to modify one that is on the ROM disk because @@ -2348,10 +2500,6 @@ call "ZSYS.SYS". For example: SETTERM. So, run SETTERM on DSCONFIG before using DSCONFIG to configure DATSWEEP! -* After using PUTDS to initialize a directory for ZDS date stamping, I - am finding that it is necessary to run RELOG before the stamping - routines will actually start working. - * Generic CP/M PIP and ZSDOS path searching do not mix well if you use PIP to copy to or from a directory in the ZSDOS search path. Best to use COPY from the ZSDOS distribution. @@ -2846,212 +2994,26 @@ therefore, globally available. | TIMER | Display value of running periodic system timer. | | CPUSPD | Change the running CPU speed and wait states of the system. | -Some custom applications do not fit on the ROM disk. They are found on the -disk image files or the individual files can be found in the Binary/Apps -directory of the distribution. They are also included on the -floppy disk and hard disk images. - -| **Application** | **Description** | -|-----------------|--------------------------------------------------------------------| -| TUNE | Play .PT2, .PT3, .MYM audio files. | -| INTTEST | Test interrupt vector hooking. | - -# FAT Filesystem - -The FAT filesystem format that originated with MS-DOS is almost -ubiquitous across modern computers. Virtually all operating systems -now support reading and writing files to a FAT filesystem. For this -reason, RomWBW now has the ability to read and write files on FAT -filesystems. - -This is accomplished by running a RomWBW custom application called `FAT`. -This application understands both FAT filesystems as well as CP/M filesystems. - -* Files can be copied between a FAT filesystem and a CP/M filesystem, - but you cannot execute files directly from a FAT filesystem. -* FAT12, FAT16, and FAT32 formats are supported. -* Long filenames are not supported. Files with long filenames will - show up with their names truncated into the older 8.3 convention. -* A FAT filesystem can be located on floppy or hard disk media. For - hard disk media, a valid FAT Filesystem partition must exist. -* Note that CP/M (and compatible) OSes do not support all of the - filename characters that a modern computer does. The following - characters are **not permitted** in a CP/M filename: - - `< > . , ; : = ? * [ ] _ % | ( ) / \` - - The FAT application does not auto-rename files when it encounters - invalid filenames. It will just issue an error and quit. - Additionally, the error message is not very clear about the problem. - -## FAT Filesystem Preparation - -In general, you can create media formatted with a FAT filesystem on -your RomWBW computer or on your modern computer. We will only be -discussing the RomWBW-based approach here. - -In the case of a floppy disk, you can use the `FAT` application to -format the floppy disk. The floppy disk must already be physically -formatted using RomWBW FDU or equivalent. If your floppy disk is on -RomWBW disk unit 2, you could use `FAT FORMAT 2:`. This will overwrite -the floppy with a FAT filesystem and all previous contents will be lost. -Once formatted this way, the floppy disk can be used in a floppy drive -attached to a modern computer or it can be used on RomWBW using the -other `FAT` tool commands. - -In the case of hard disk media, it is necessary to have a FAT -partition. If you prepared your RomWBW hard disk media using the -disk image process, then this partition will already be defined and -you do not need to recreate it. This default FAT partition is located -at approximately 512MB from the start of your disk and it is 384MB in -size. So, your hard disk media must be 1GB or greater to use this -default FAT partition. - -You can confirm the existence of the FAT partition with `FDISK80` by -using the 'P' command to show the current partition table. Here is an -example of a partition table listing from `FDISK80` that includes the -FAT partition (labelled "FAT16"): - -``` -Capacity of disk 4: ( 4G) 7813120 Geom 77381010 -Nr ---Type- A -- Start End LBA start LBA count Size - 1 RomWBW 2e 8:0:1 1023:15:16 2048 1048576 512M - 2 FAT16 06 1023:0:1 1023:15:16 1050624 786432 384M - 3 00 *** empty *** - 4 00 *** empty *** -``` - -If your hard disk media does not have a FAT partition already defined, -you will need to define one using FDISK80 by using the 'N' command. -Ensure that the location and size of the FAT partition does not -overlap any of the CP/M slice area and that it fits within the size -of your media. - -Once the partition is defined, you will still need to format it. Just -as with a floppy disk, you use the `FAT` tool to do this. If your -hard disk media is on RomWBW disk unit 4, you would use `FAT FORMAT 4:`. -This will look something like this: - -``` -E>fat format 4: - -About to format FAT Filesystem on Disk Unit #4. -All existing FAT partition data will be destroyed!!! - -Continue (y/n)? - -Formatting... Done -``` - -Your FAT filesystem is now ready to use. - -If your RomWBW system has multiple disk drives/slots, you can also just -create a disk with your modern computer that is a dedicated FAT -filesystem disk. You can use your modern computer to format the disk -(floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW -computer and access it using `FAT` based on its RomWBW unit number. - -**WARNING**: Microsoft Windows will sometimes suggest reformatting -partitions that it does not recognize. If you are prompted to format a -partition of your SD/CF/USB Media when inserting the card into a Windows -computer, you probably want to select Cancel. - -## FAT Application Usage - -Complete instructions for the `FAT` application are found in $doc_apps$. -Here, we will just provide a couple of simple examples. Note that the -FAT application is not on the ROM disk because it is too large to -include there. - -The most important thing to understand about the `FAT` application is -how it refers to FAT filesystems vs. CP/M filesystems. It infers this -based on the file specification provided. If you use a specification -like `C:SAMPLE.TXT`, it will use the C: drive of your CP/M operating -system. If you use a specification like `4:SAMPLE.TXT`, it will use -the FAT filesystem on the disk in RomWBW disk unit 4. Basically, if -you start your file or directory specification with a number followed -by a colon, it means FAT filesystem. Anything else will mean CP/M -filesystem. - -Here are a few examples. This first example shows how to get a FAT -directory listing from RomWBW disk unit 4: - -``` -E>fat dir 4: - -Directory of 4: - - -E> -``` - -As you can see, there are currently no files there. Now let's copy -a file from CP/M to the FAT directory: - -``` -E>fat copy sample.txt 4: - -Copying... - -SAMPLE.TXT ==> 4:/SAMPLE.TXT ... [OK] - - 1 File(s) Copied -``` - -If we list the FAT directory again, you will see the file: - -``` -E>fat dir 4: - -Directory of 4: - -01/30/2023 17:50:14 29952 ---A SAMPLE.TXT - -``` - -Now let's copy the file from the FAT filesystem back to CP/M. This -time we will get a warning about overwriting the file. For this -example, we don't want to do that, so we abort and reissue the -command specifying a new filename to use: - -``` -E>fat copy 4:sample.txt e: - -Copying... - -4:/SAMPLE.TXT ==> E:SAMPLE.TXT Overwrite? (Y/N) [Skipped] - - 0 File(s) Copied - -E>fat copy 4:sample.txt e:sample2.txt - -Copying... - -4:/SAMPLE.TXT ==> E:SAMPLE2.TXT ... [OK] - - 1 File(s) Copied -``` - -Finally, let's try using wildcards: - -``` -E>fat copy sample*.* 4: - -Copying... - -SAMPLE.TXT ==> 4:/SAMPLE.TXT Overwrite? (Y/N) ... [OK] -SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK] +Some custom applications do not fit on the ROM disk. They are found on the +disk image files or the individual files can be found in the Binary/Apps +directory of the distribution. They are also included on the +floppy disk and hard disk images. - 2 File(s) Copied -``` +| **Application** | **Description** | +|-----------------|--------------------------------------------------------------------| +| TUNE | Play .PT2, .PT3, .MYM audio files. | +| INTTEST | Test interrupt vector hooking. | # Real Time Clock RomWBW supports a variety of real time clock hardware. If your system has this hardware, then it will be able to maintain the current date and time even while your system is turned off. + Additionally, depending on the operating system being used, you may be able to utilize date/time stamping of files. +To facilitate this a CP/M clock driver (WBWCLK) has been included +inside `CLOCKS.DAT` that will read the clock via a RomWBW HBIOS call You can determine if your system has a real time clock present (and functioning) by looking at the boot messages. Here is an example of @@ -3077,6 +3039,8 @@ RomwWBW includes two utilities for displaying or setting the date/time stored by the RTC. They are both a bit different and are briefly described below. +A third utility `TESTCLOK` is also included as part of ZSDOS + ### WDATE Utility The `WDATE` utility (contributed by Kevin Boone) is an application @@ -3156,6 +3120,57 @@ Do **not** enable charging unless you are sure that your system supports this. If your RTC is being powered by a normal battery, it would be dangerous to enable charging. +### TESTCLOK Utility + +The `TESTCLOK` utility is used to test a selected CPM clock driver +loaded from the CLOCKS.DAT file. After selecting the location of CLOCKS.DAT +and the clock driver (45. WBWCLK) it displays the currently configured time +until a key is pressed. + +``` +A>testclok + +TESTCLOK V1.0 Copyright (C) 1988 H.F. Bower / C.W. Cotrill + +Extract Clock from Library ([Y]/N) : Y +Location of CLOCKS.DAT [A0:] : + + 1. ACTRIX 2. ALSPA 3. AMPRO-LB + 4. ANLYTCL-PRD 5. AP2-CDZ180 6. AP2-THND/MT + 7. AP2-TIMASTR 8. AP2E+PCP-TM 9. AP2E+PCPI + 10. AP2E-THUNDR 11. AP2E-TMASTR 12. BIG-BD-II + 13. BP-BIOS 14. CCS-WALLCLK 15. CPUPRO-SSB1 + 16. ELECTR-MFIO 17. EPSON-QX10 18. ETS180IO+ + 19. H19-SUPER19 20. H19-ULTRA 21. H19-WATZMAN + 22. H89-BITZERO 23. H89-PC12 24. H89-WIDGET + 25. H89-WISE 26. H89UTI 27. HEATH-BIOS + 28. HOUSEMASTER 29. K83-HOLMES 30. KAYPRO-84 + 31. KENMOR-ZTIM 32. KPRO-ADVENT 33. KPRO-LEGACY + 34. MD3-MACK 35. MTN100K-DAY 36. ONEAC-ON! + 37. OTRANA-ATCH 38. P&T-HEARTBT 39. QTSYS-S100 + 40. RELATIVE 41. S100-5832 42. SB180-HRTBT + 43. SB180-XBIOS 44. SIMHCLOK 45. WBWCLK + 46. XEROX-820 47. ZSDOS-BIOS + +Enter Clock Driver Selection : 45 + +..Loading : WBWCLK ... +Linking Clock Module... OK +RomWBW HBIOS Clock 1.1 + +RomWBW Series HBIOS Clock + +Press any key to quit... + + 19 Oct 2023 14:24:34 +``` + +Since this runs at the CPM driver level it is useful as an end-to-end test +to prove that date time stamping is able to read the correct time + +The `TESTCLOK` utility is provided by ZSDOS, plese see the ZSDOS Manual +for further information + ## Date/Time File Stamping If an RTC is available in your system, then most operating systems @@ -3164,10 +3179,16 @@ date/time of file creation, update, and or access in the directory. This capability is available in all of the RomWBW operating system except the original DRI CP/M 2.2. -In some cases (such as ZSDOS), you must load an RSX (memory resident -utility) to enable date/time stamping of files. Additionally, you -will need to initialize the directory. The procedure varies in each -operation system, so you must review the associated documentation. +Three types of date/time stamping are supported using realtime clock +supported by RomWBW HBIOS. DateStamper, NZT and P2DOS. + +In some cases (such as ZSDOS), you must load an RSX (memory resident +utility) to enable date/time stamping of files. This could be automated +using a `PROFILE.SUB` file. +Preconfigured loaders are provided, bypassing the need to use SETUPZST. + +Additionally, you will need to initialize the directory. The procedure varies +depending on the date/time stamping mechanism, so you must review the associated documentation. The date/time stamping mechanisms for each operating system are generally not compatible. If you initialize a directory for a type @@ -3178,6 +3199,71 @@ mechanism. Doing so may corrupt the directory. The RomWBW disk images do not have date/time stamping initialized. This is to avoid any chance of directory corruption. +### DateStamper + +DateStamper datestamping follows the standard set by Plu*Perfect Systems. +This method stores stamps in a disk file named `!!!TIME&.DAT`. +Only DateStamper stamping stores full time and date stamps for +file Creation, Last Modification, and Last Access, +and may be used with any CP/M diskette format. In addition, +the DateStamper protocol is supported by a mature set of compatible utilities. + +Key Utilities + +* LDDS.COM - Load DateStamper date/time stamping resident extension. (RomWBW Provided) +* PUTDS.COM - Prepare disk for DateStamper date/time stamping. + +After using PUTDS to initialize a directory for ZDS date stamping, +it may be necessary to run RELOG before the stamping routines +will actually start working. + +### P2DOS (CP/M Plus compatible) + +CP/M Plus-type datestamping is also widely used due to the popularity +of CP/M Plus (also know as CP/M 3). CP/M Plus-type file datestamping uses +directory sectors to store file datestamps which may be accessed more quickly +by programs, but there is no Last File Access stamp. Finally, the range of +utilities for this type of stamps is more limited than for the DateStamper protocol. + +Key Utilities + +* LDP2D.COM - Load P2DOS date/time stamping resident extension. (RomWBW Provided) +* INITDIR.COM - Prepares disks for P2DOS-type file stamping. + +### NZT + +_The use of NZT needs to be further documented_ + +Key Utilities + +* LDNZT.COM - Load NZT date/time stamping resident extension. (RomWBW Provided) + +### Additional Notes + +The following files have been provided, customised and tested for for use in RomWBW + +* `CLOCKS.DAT` - Library of clock drivers, which has been updated to include + the RomWBW clock driver WBWCLK, and also includes the SIMHCLOK clock driver. + The file is just a standard LU type library and is easily updated using NULU. + The members are the relocatable binaries, but with the .REL extension removed. +* `STAMPS.DAT` - Library of available date/time stamping modules for SETUPZST. + The file has been replaced with an updated version from the Walnut Creek CP/M CDROM. + The original version has a bug that prevents RSX (resident system extension) mode + to load properly. + +Additional Notes + +* `SETUPZST` (provided by ZSDOS) Should not normally be needed since the + creation of the appropriate LDTIM loaders has already been performed. +* `FILEDATE` only works with DateStamper style date stamping. If you run + it on a drive that is not initialized for DateStamper, it will complain + `FILEDATE, !!!TIME&.DAT missing`. This is normal and just means that + you have not initialized that drive for DateStamper (using PUTDS). +* `ZXD` will handle either DateStamper or P2DOS type date stamping. + However, it **must** be configured appropriately. As distributed, it will + look for P2DOS date stamps. Use ZCNFG to reconfigure it for P2DOS if + that is what you are using. + ## Timezone None of the operating systems distributed with RomWBW have any concept @@ -3694,35 +3780,222 @@ detail in the Source/Images directory of the distribution. ## FAT Filesystem Transfers -The ability to interact with FAT filesystems was covered in -[FAT Filesystem]. This capability means that you can generally use your - modern computer to make an SD Card, CF Card, or USB Drive with a -standard FAT32 filesystem on it, then place that media in your RomWBW -computer and access the files. +The FAT filesystem format that originated with MS-DOS is almost +ubiquitous across modern computers. Virtually all operating systems +now support reading and writing files to a FAT filesystem. For this +reason, RomWBW now has the ability to read and write files on FAT +filesystems. + +This capability means that you can generally use your modern computer +to make an SD Card, CF Card, or USB Drive with a standard FAT filesystem +on it, then place that media in your RomWBW computer and access the files. + +* Files can be copied between a FAT filesystem and a CP/M filesystem, + but you cannot execute files directly from a FAT filesystem. + +* FAT12, FAT16, and FAT32 formats are supported. + +* Long filenames are not supported. Files with long filenames will + show up with their names truncated into the older 8.3 convention. + If you have files on your modern computer with long filenames, + it is usually easiest to rename them on the modern computer. + +* A FAT filesystem can be located on floppy or hard disk media. For + hard disk media, a valid FAT Filesystem partition must exist. + +Some additional **Notes** and **WARNINGS** Things to be careful about + +* CP/M (and compatible) OSes do not support all of the + filename characters that a modern computer does. The following + characters are **not permitted** in a CP/M filename: + + `< > . , ; : = ? * [ ] _ % | ( ) / \` + + The FAT application does not auto-rename files when it encounters + invalid filenames. It will just issue an error and quit. + Additionally, the error message is not very clear about the problem. + +* Microsoft Windows will sometimes suggest **reformatting** + partitions that it does not recognize (e.g. RomWBW). + If you are using media that contains both a FAT partition + and a RomWBW partition you may prompted to format a partition of your + SD/CF/USB Media when inserting the card into a Windows computer, + you probably want to select Cancel. + +### FAT Filesystem Preparation + +In general, you can create media formatted with a FAT filesystem on +your RomWBW computer or on your modern computer. We will only be +discussing the RomWBW-based approach here. + +#### Floppy Disk + +In the case of a floppy disk, you can use the `FAT` application to +format the floppy disk. The floppy disk must already be physically +formatted using RomWBW FDU or equivalent. If your floppy disk is on +RomWBW disk unit 2, you could use `FAT FORMAT 2:`. This will overwrite +the floppy with a FAT filesystem and all previous contents will be lost. +Once formatted this way, the floppy disk can be used in a floppy drive +attached to a modern computer or it can be used on RomWBW using the +other `FAT` tool commands. + +#### Hard Disk + +In the case of hard disk media, it is necessary to have a FAT +partition. If you prepared your RomWBW hard disk media using the +disk image process, then this partition will already be defined and +you do not need to recreate it. This default FAT partition is located +at approximately 512MB from the start of your disk and it is 384MB in +size. So, your hard disk media must be 1GB or greater to use this +default FAT partition. + +You can confirm the existence of the FAT partition with `FDISK80` by +using the 'P' command to show the current partition table. Here is an +example of a partition table listing from `FDISK80` that includes the +FAT partition (labelled "FAT16"): + +``` +Capacity of disk 4: ( 4G) 7813120 Geom 77381010 +Nr ---Type- A -- Start End LBA start LBA count Size + 1 RomWBW 2e 8:0:1 1023:15:16 2048 1048576 512M + 2 FAT16 06 1023:0:1 1023:15:16 1050624 786432 384M + 3 00 *** empty *** + 4 00 *** empty *** +``` + +If your hard disk media does not have a FAT partition already defined, +you will need to define one using FDISK80 by using the 'N' command. +Ensure that the location and size of the FAT partition does not +overlap any of the CP/M slice area and that it fits within the size +of your media. + +Once the partition is defined, you will still need to format it. Just +as with a floppy disk, you use the `FAT` tool to do this. If your +hard disk media is on RomWBW disk unit 4, you would use `FAT FORMAT 4:`. +This will look something like this: + +``` +E>fat format 4: + +About to format FAT Filesystem on Disk Unit #4. +All existing FAT partition data will be destroyed!!! + +Continue (y/n)? + +Formatting... Done +``` + +Your FAT filesystem is now ready to use. + +If your RomWBW system has multiple disk drives/slots, you can also just +create a disk with your modern computer that is a dedicated FAT +filesystem disk. You can use your modern computer to format the disk +(floppy, CF Card, SD Card, etc.), then insert the disk in your RomWBW +computer and access it using `FAT` based on its RomWBW unit number. + +### FAT Application Usage -When formatting the media on your modern computer, be sure to pick the -FAT filesystem. NTFS and other filesystems will not work. As previously -mentioned, the `FAT` application does not understand long filenames, -only the traditional 8.3 filenames. If you have files on your modern -computer with long filenames, it is usually easiest to rename them on -the modern computer. +Transferring files is accomplished by running a RomWBW custom application +called `FAT`. This application understands both FAT filesystems as well +as CP/M filesystems. To copy files from your modern computer to your RomWBW computer, start by putting the disk media with the FAT filesystem in your modern computer. The modern computer should recognize it. Then copy the files you want to get to your RomWBW computer onto this media. Once done, remove the media from your modern computer and insert it in the RomWBW -computer. Finally, use the `FAT` tool to copy the files onto a CP/M -drive. +computer. -This process works just fine in reverse if you want to copy files from a +Finally, use the `FAT` tool to copy the files onto a CP/M +drive. This process works just fine in reverse if you want to copy files from a CP/M filesystem to your modern computer. -**WARNING**: If you are using media that contains both a FAT partition -and a RomWBW partition, your modern computer may be confused by the -RomWBW partition. In some cases, it will prompt you to format the -RomWBW partition because it doesn't know what it is. You will be -prompted before it does this -- just be careful not to allow it. +Complete instructions for the `FAT` application are found in $doc_apps$. +Here, we will just provide a couple of simple examples. Note that the +FAT application is not on the ROM disk because it is too large to +include there. + +The most important thing to understand about the `FAT` application is +how it refers to FAT filesystems vs. CP/M filesystems. It infers this +based on the file specification provided. If you use a specification +like `C:SAMPLE.TXT`, it will use the C: drive of your CP/M operating +system. If you use a specification like `4:SAMPLE.TXT`, it will use +the FAT filesystem on the disk in RomWBW disk unit 4. Basically, if +you start your file or directory specification with a number followed +by a colon, it means FAT filesystem. Anything else will mean CP/M +filesystem. + +Here are a few examples. This first example shows how to get a FAT +directory listing from RomWBW disk unit 4: + +``` +E>fat dir 4: + +Directory of 4: + + +E> +``` + +As you can see, there are currently no files there. Now let's copy +a file from CP/M to the FAT directory: + +``` +E>fat copy sample.txt 4: + +Copying... + +SAMPLE.TXT ==> 4:/SAMPLE.TXT ... [OK] + + 1 File(s) Copied +``` + +If we list the FAT directory again, you will see the file: + +``` +E>fat dir 4: + +Directory of 4: + +01/30/2023 17:50:14 29952 ---A SAMPLE.TXT + +``` + +Now let's copy the file from the FAT filesystem back to CP/M. This +time we will get a warning about overwriting the file. For this +example, we don't want to do that, so we abort and reissue the +command specifying a new filename to use: + +``` +E>fat copy 4:sample.txt e: + +Copying... + +4:/SAMPLE.TXT ==> E:SAMPLE.TXT Overwrite? (Y/N) [Skipped] + + 0 File(s) Copied + +E>fat copy 4:sample.txt e:sample2.txt + +Copying... + +4:/SAMPLE.TXT ==> E:SAMPLE2.TXT ... [OK] + + 1 File(s) Copied +``` + +Finally, let's try using wildcards: + +``` +E>fat copy sample*.* 4: + +Copying... + +SAMPLE.TXT ==> 4:/SAMPLE.TXT Overwrite? (Y/N) ... [OK] +SAMPLE2.TXT ==> 4:/SAMPLE2.TXT ... [OK] + + 2 File(s) Copied +``` # Customizing RomWBW @@ -3832,7 +4105,7 @@ for more information on UNA. - The disk images created and distributed with RomWBW do not have the correct system track code for UNA. In order to boot to disk under - UNA, you must first use SYSCOPY to update the system track of the + UNA, you must first use `SYSCOPY` to update the system track of the target disk. The UNA ROM disk has the correct system track files for UNA: `CPM.SYS` and `ZSYS.SYS`. So, you can boot a ROM OS and then use one of these files to update the system track. @@ -4190,6 +4463,9 @@ please let me know if I missed you! compendium. * Martin R has provided substantial help reviewing and improving the + User Guide and Applications documents. + +* Mark Pruden has also contributed a great deal of content to the User Guide. * Jacques Pelletier has contributed the DS1501 RTC driver code. @@ -4611,7 +4887,7 @@ the RomWBW HBIOS configuration. `\clearpage`{=latex} -#### ROM Image File: RCZ80_kio.rom +#### ROM Image File: RCZ80_kio_std.rom | | | |-------------------|---------------| @@ -4654,7 +4930,7 @@ the RomWBW HBIOS configuration. ### RCBus Z180 CPU Module -#### ROM Image File: RCZ180_ext.rom +#### ROM Image File: RCZ180_ext_std.rom | | | |-------------------|---------------| @@ -4699,7 +4975,7 @@ the RomWBW HBIOS configuration. `\clearpage`{=latex} -#### ROM Image File: RCZ180_nat.rom +#### ROM Image File: RCZ180_nat_std.rom | | | |-------------------|---------------| @@ -4746,7 +5022,7 @@ the RomWBW HBIOS configuration. ### RCBus Z280 CPU Module -#### ROM Image File: RCZ280_ext.rom +#### ROM Image File: RCZ280_ext_std.rom | | | |-------------------|---------------| @@ -4789,7 +5065,7 @@ the RomWBW HBIOS configuration. `\clearpage`{=latex} -#### ROM Image File: RCZ280_nat.rom +#### ROM Image File: RCZ280_nat_std.rom | | | |-------------------|---------------| @@ -4833,7 +5109,7 @@ the RomWBW HBIOS configuration. ### Easy Z80 SBC -#### ROM Image File: RCZ80_easy.rom +#### ROM Image File: RCZ80_easy_std.rom | | | |-------------------|---------------| @@ -4878,7 +5154,7 @@ the RomWBW HBIOS configuration. ### Tiny Z80 SBC -#### ROM Image File: RCZ80_tiny.rom +#### ROM Image File: RCZ80_tiny_std.rom | | | |-------------------|---------------| @@ -4922,7 +5198,7 @@ the RomWBW HBIOS configuration. ### Z80-512K CPU/RAM/ROM Module -#### ROM Image File: RCZ80_skz.rom +#### ROM Image File: RCZ80_skz_std.rom | | | |-------------------|---------------| @@ -4967,7 +5243,7 @@ the RomWBW HBIOS configuration. ### Small Computer SC126 Z180 SBC -#### ROM Image File: SCZ180_sc126.rom +#### ROM Image File: SCZ180_sc126_std.rom | | | |-------------------|---------------| @@ -5015,7 +5291,7 @@ the RomWBW HBIOS configuration. ### Small Computer SC130 Z180 SBC -#### ROM Image File: SCZ180_sc130.rom +#### ROM Image File: SCZ180_sc130_std.rom | | | |-------------------|---------------| @@ -5061,9 +5337,9 @@ the RomWBW HBIOS configuration. `\clearpage`{=latex} -### Small Computer SC131 Z180 Pocket Computer +### Small Computer SC131 Z180 Pocket Comp -#### ROM Image File: SCZ180_sc131.rom +#### ROM Image File: SCZ180_sc131_std.rom | | | |-------------------|---------------| @@ -5090,7 +5366,7 @@ the RomWBW HBIOS configuration. ### Small Computer SC140 Z180 CPU Module -#### ROM Image File: SCZ180_sc140.rom +#### ROM Image File: SCZ180_sc140_std.rom | | | |-------------------|---------------| @@ -5137,7 +5413,7 @@ the RomWBW HBIOS configuration. ### Small Computer SC503 Z180 CPU Module -#### ROM Image File: SCZ180_sc503.rom +#### ROM Image File: SCZ180_sc503_std.rom | | | |-------------------|---------------| @@ -5184,7 +5460,7 @@ the RomWBW HBIOS configuration. ### Small Computer SC700 Z180 CPU Module -#### ROM Image File: SCZ180_sc700.rom +#### ROM Image File: SCZ180_sc700_std.rom | | | |-------------------|---------------| @@ -5213,7 +5489,7 @@ the RomWBW HBIOS configuration. - CH: IO=60 - CHUSB: IO=62 - CHUSB: IO=60 -S- MD: TYPE=RAM +- MD: TYPE=RAM - MD: TYPE=ROM - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD @@ -5344,7 +5620,7 @@ S- MD: TYPE=RAM ### Z80 ZRC CPU Module -#### ROM Image File: RCZ80_zrc.rom +#### ROM Image File: RCZ80_zrc_std.rom | | | |-------------------|---------------| @@ -5391,7 +5667,7 @@ S- MD: TYPE=RAM `\clearpage`{=latex} -#### ROM Image File: RCZ80_zrc_ram.rom +#### ROM Image File: RCZ80_zrc_ram_std.rom | | | |-------------------|---------------| @@ -5438,7 +5714,7 @@ S- MD: TYPE=RAM ### Z80 ZRC512 CPU Module -#### ROM Image File: RCZ80_zrc512.rom +#### ROM Image File: RCZ80_zrc512_std.rom | | | |-------------------|---------------| @@ -5485,7 +5761,7 @@ S- MD: TYPE=RAM ### Z180 Z1RCC CPU Module -#### ROM Image File: RCZ180_z1rcc.rom +#### ROM Image File: RCZ180_z1rcc_std.rom | | | |-------------------|---------------| @@ -5531,7 +5807,7 @@ S- MD: TYPE=RAM ### Z280 ZZRCC CPU Module -#### ROM Image File: RCZ280_zzrcc.rom +#### ROM Image File: RCZ280_zzrcc_std.rom | | | |-------------------|---------------| @@ -5577,7 +5853,7 @@ S- MD: TYPE=RAM `\clearpage`{=latex} -#### ROM Image File: RCZ280_zzrcc_ram.rom +#### ROM Image File: RCZ280_zzrcc_ram_std.rom | | | |-------------------|---------------| @@ -5623,7 +5899,7 @@ S- MD: TYPE=RAM ### Z280 ZZ80MB SBC -#### ROM Image File: RCZ280_zz80mb.rom +#### ROM Image File: RCZ280_zz80mb_std.rom | | | |-------------------|---------------| @@ -5891,6 +6167,73 @@ S- MD: TYPE=RAM `\clearpage`{=latex} +### S100 FPGA Z80 + +#### ROM Image File: FZ80_std.rom + +| | | +|-------------------|---------------| +| Default CPU Speed | 8.000 MHz | +| Interrupts | None | +| System Timer | None | +| Serial Default | 9600 Baud | +| Memory Manager | Z2 | +| ROM Size | 0 KB | +| RAM Size | 512 KB | + +##### Supported Hardware (see [Appendix B - Device Summary]): + +FP: LEDIO=255 +SSER: IO=52 +SCON: IO=0 +MD: TYPE=RAM +PPIDE: IO=48, MASTER +PPIDE: IO=48, SLAVE + + +FP: LEDIO=255 +DS5RTC: RTCIO=104, IO=104 +SSER: IO=52 +SCON: IO=0 +MD: TYPE=RAM +PPIDE: IO=48, MASTER +PPIDE: IO=48, SLAVE +SD: MODE=FZ80, IO=108, UNITS=2 + +##### Notes: + +- Requires matching FPGA code + +### Genesis STD Z180 + +#### ROM Image File: GMZ180_std.rom + +| | | +|-------------------|---------------| +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +##### Supported Hardware (see [Appendix B - Device Summary]): + +DSRTC: MODE=STD, IO=132 +INTRTC: ENABLED +ASCI: IO=192, INTERRUPTS ENABLED +ASCI: IO=193, INTERRUPTS ENABLED +MD: TYPE=RAM +MD: TYPE=ROM +IDE: MODE=GIDE, IO=32, MASTER +IDE: MODE=GIDE, IO=32, SLAVE +SD: MODE=GM, IO=132, UNITS=1 + +##### Notes: + +- CPU speed will be dynamically measured at startup if DSRTC is present + ## Appendix B - Device Summary The table below briefly describes each of the possible devices that @@ -5908,7 +6251,8 @@ may be discovered by RomWBW in your system. | CTC | System | Zilog Clock/Timer | | CVDU | Video | MC8563-based Video Display Controller | | DMA | System | Zilog DMA Controller | -| DS1307 | RTC | Maxim DS1307 PCF I2C Real-Time Clock w/ NVRAM | +| DS5RTC | RTC | Maxim DS1305 SPI Real-Time Clock w/ NVRAM | +| DS7RTC | RTC | Maxim DS1307 PCF I2C Real-Time Clock w/ NVRAM | | DS1501RTC | RTC | Maxim DS1501/DS1511 Watchdog Real-Time Clock | | DSRTC | RTC | Maxim DS1302 Real-Time Clock w/ NVRAM | | DUART | Char | SCC2681 or compatible Dual UART | @@ -5916,6 +6260,7 @@ may be discovered by RomWBW in your system. | EMM | Disk | Disk drive on Parallel Port emm interface (Zip Drive) | | FD | Disk | 8272 or compatible Floppy Disk Controller | | FP | System | Simple LED & Switch Front Panel | +| FV | Video | S100 FPGA Z80 Onboard VGA/Keyboard | | GDC | Video | uPD7220 Video Display Controller | | HDSK | Disk | SIMH Simulator Hard Disk | | ICM | DsKy | ICM7218-based Display/Keypad on PPI | @@ -5924,6 +6269,7 @@ may be discovered by RomWBW in your system. | INTRTC | RTC | Interrupt-based Real Time Clock | | KBD | Keyboard | 8242 PS/2 Keyboard Controller | | KIO | System | Zilog Serial/ Parallel Counter/Timer | +| LCD | System | Hitachi HD44780-based LCD Display | | LPT | Char | Parallel I/O Controller | | MD | Disk | ROM/RAM Disk | | MSXKYB | Keyboard | MSX Compliant Matrix Keyboard | @@ -5948,6 +6294,7 @@ may be discovered by RomWBW in your system. | SN76489 | Sound | SN76489 Programmable Sound Generator | | SPK | Sound | Bit-bang Speaker | | SYQ | Disk | Iomega SparQ Drive on PPI | +| SSER | Char | Simple Serial Interface | | TMS | Video | TMS9918/38/58 Video Display Controller | | UART | Char | 16C550 Family Serial Interface | | USB-FIFO | Char | FT232H-based ECB USB FIFO | diff --git a/Source/FZ80/Bank Layout.txt b/Source/FZ80/Bank Layout.txt new file mode 100644 index 00000000..e911afb7 --- /dev/null +++ b/Source/FZ80/Bank Layout.txt @@ -0,0 +1,18 @@ +FPGA Z80 has no real ROM. It has a single 512K RAM chip. + +The ROMless startup mode treats the entire 512KB as RAM. 384KB of RAM +must be preloaded by the FPGA Monitor CF Loader. There will be no ROM +disk available under RomWBW. There will be a RAM Disk and it's initial +contents will be seeded by the image loaded by the CF Loader. + +Bank Contents Description +-------- -------- ----------- +0x0 BIOS HBIOS Bank (operating) +0x1 IMG0 ROM Loader, Monitor, ROM OSes +0x2 IMG1 ROM Applications +0x3 IMG2 Reserved +0x4-0xB RAMD RAM Disk Banks +0xC BUF OS Buffers (CP/M3) +0xD AUX Aux Bank (CP/M 3, BPBIOS, etc.) +0xE USR User Bank (CP/M TPA, etc.) +0xF COM Common Bank, Upper 32KB diff --git a/Source/FZ80/Build.cmd b/Source/FZ80/Build.cmd new file mode 100644 index 00000000..8ca4f6c3 --- /dev/null +++ b/Source/FZ80/Build.cmd @@ -0,0 +1,24 @@ +@echo off +setlocal + +set TOOLS=../../Tools + +set PATH=%TOOLS%\srecord;%PATH% + +for %%f in (..\..\Binary\FZ80_*.rom) do call :build %%~nf + +goto :eof + +:build +echo. +echo Creating %1 disk image... +echo. + +srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary +srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary +srec_cat temp.dat -binary -exclude 0x80000 0xE0000 ..\..\Binary\%1.rom -binary -offset 0x80000 -o temp.dat -binary +move temp.dat ..\..\Binary\%1_hd1k_prefix.dat + +copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b + +goto :eof diff --git a/Source/FZ80/Clean.cmd b/Source/FZ80/Clean.cmd new file mode 100644 index 00000000..fa12c5c7 --- /dev/null +++ b/Source/FZ80/Clean.cmd @@ -0,0 +1,3 @@ +@echo off +setlocal + diff --git a/Source/FZ80/FZ80 Disk Layout.txt b/Source/FZ80/FZ80 Disk Layout.txt new file mode 100644 index 00000000..61f1db1e --- /dev/null +++ b/Source/FZ80/FZ80 Disk Layout.txt @@ -0,0 +1,19 @@ +FZ80 Disk Prefix Layout +======================= + +---- Bytes ---- --- Sectors --- +Start Length Start Length Description +------- ------- ------- ------- --------------------------- +0x00000 0x001BE 0 1 Unused +0x001B8 0x00048 RomWBW Partition Table +0x00200 0x1EE00 1 7FE00 Unused +0x80000 0x60000 1024 768 RomWBW +0x100000 2048 Start of slices (partition 0x1E) + +Notes +----- + +- FPGA Z80 Monitor reads 384KB (RomWBW) from sectors 1024-1791 of CF into first 384KB of physical RAM +- FPGA Z80 ZRC Monitor maps first 32KB of physical RAM to first 32KB of CPU RAM and starts execution at 0x0000 + +-- WBW 3:18 PM 6/30/2024 \ No newline at end of file diff --git a/Source/FZ80/Makefile b/Source/FZ80/Makefile new file mode 100644 index 00000000..3614280f --- /dev/null +++ b/Source/FZ80/Makefile @@ -0,0 +1,25 @@ +DEST=../../Binary + +HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \ + $(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img + +ROMS := $(wildcard $(DEST)/FZ80_*.rom) +ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS)) + +OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS)) +OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS)) + +TOOLS = ../../Tools + +include $(TOOLS)/Makefile.inc + +DIFFPATH = $(DIFFTO)/Binary + +%_hd1k_prefix.dat: $(DEST)/%.rom + srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary + srec_cat temp.dat -binary -exclude 0x1B8 0x200 fz80_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary + srec_cat temp.dat -binary -exclude 0x80000 0xE0000 $< -binary -offset 0x80000 -o temp.dat -binary + mv temp.dat $@ + +%_hd1k_combo.img: %_hd1k_prefix.dat $(HD1KIMGS) + cat $^ > $@ diff --git a/Source/FZ80/fz80_ptbl.bin b/Source/FZ80/fz80_ptbl.bin new file mode 100644 index 00000000..5e9fc41d Binary files /dev/null and b/Source/FZ80/fz80_ptbl.bin differ diff --git a/Source/HBIOS/Bank Layout.txt b/Source/HBIOS/Bank Layout.txt index a3a40d57..f7f957cb 100644 --- a/Source/HBIOS/Bank Layout.txt +++ b/Source/HBIOS/Bank Layout.txt @@ -43,8 +43,8 @@ Standard RAM Bank Layout (512K) Bank ID Usage ------- ------ 0x80 RomWBW HBIOS -0x81-0x88 RAM Disk Data (3) -0x89-0x8B App Banks (8) +0x81-0x88 RAM Disk Data (8) +0x89-0x8B App Banks (3) 0x8C CP/M 3 Buffers 0x8D CP/M 3 OS 0x8E User TPA diff --git a/Source/HBIOS/Build.cmd b/Source/HBIOS/Build.cmd index 76c4f829..7c8ccda7 100644 --- a/Source/HBIOS/Build.cmd +++ b/Source/HBIOS/Build.cmd @@ -204,45 +204,45 @@ goto :eof :dist call Build SBC std || exit /b -call Build SBC simh || exit /b +call Build SBC simh_std || exit /b call Build MBC std || exit /b call Build ZETA std || exit /b call Build ZETA2 std || exit /b call Build N8 std || exit /b call Build MK4 std || exit /b call Build RCZ80 std || exit /b -call Build RCZ80 kio || exit /b -call Build RCZ80 easy || exit /b -call Build RCZ80 tiny || exit /b -call Build RCZ80 skz || exit /b -:: call Build RCZ80 mt || exit /b -:: call Build RCZ80 duart || exit /b -call Build RCZ80 zrc || exit /b -call Build RCZ80 zrc_ram || exit /b -call Build RCZ80 zrc512 || exit /b -call Build RCZ180 ext || exit /b -call Build RCZ180 nat || exit /b -call Build RCZ180 z1rcc || exit /b -call Build RCZ280 ext || exit /b -call Build RCZ280 nat || exit /b -call Build RCZ280 zz80mb || exit /b -call Build RCZ280 zzrcc || exit /b -call Build RCZ280 zzrcc_ram || exit /b -call Build SCZ180 sc126 || exit /b -call Build SCZ180 sc130 || exit /b -call Build SCZ180 sc131 || exit /b -call Build SCZ180 sc140 || exit /b -call Build SCZ180 sc503 || exit /b -call Build SCZ180 sc700 || exit /b +call Build RCZ80 kio_std || exit /b +call Build RCZ80 easy_std || exit /b +call Build RCZ80 tiny_std || exit /b +call Build RCZ80 skz_std || exit /b +call Build RCZ80 zrc_std || exit /b +call Build RCZ80 zrc_ram_std || exit /b +call Build RCZ80 zrc512_std || exit /b +call Build RCZ180 ext_std || exit /b +call Build RCZ180 nat_std || exit /b +call Build RCZ180 z1rcc_std || exit /b +call Build RCZ280 ext_std || exit /b +call Build RCZ280 nat_std || exit /b +call Build RCZ280 zz80mb_std || exit /b +call Build RCZ280 zzrcc_std || exit /b +call Build RCZ280 zzrcc_ram_std || exit /b +call Build SCZ180 sc126_std || exit /b +call Build SCZ180 sc130_std || exit /b +call Build SCZ180 sc131_std || exit /b +call Build SCZ180 sc140_std || exit /b +call Build SCZ180 sc503_std || exit /b +call Build SCZ180 sc700_std || exit /b +call Build GMZ180 std || exit /b call Build DYNO std || exit /b -call Build UNA std || exit /b call Build RPH std || exit /b call Build Z80RETRO std || exit /b call Build S100 std || exit /b call Build DUO std || exit /b call Build HEATH std || exit /b call Build EPITX std || exit /b -call Build NABU std || exit /b :: call Build MON std || exit /b +call Build NABU std || exit /b +call Build FZ80 std || exit /b +call Build UNA std || exit /b goto :eof diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index ec8bf51d..e7ef3e63 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -27,8 +27,8 @@ $ErrorAction = 'Stop' # UNA BIOS is simply imbedded, it is not built here. # -$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU" -$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX" +$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80" +$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180" $PlatformListZ280 = "RCZ280" # diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh index 892640d0..1684d8d5 100755 --- a/Source/HBIOS/Build.sh +++ b/Source/HBIOS/Build.sh @@ -11,47 +11,47 @@ export CPUFAM if [ "${ROM_PLATFORM}" == "dist" ] ; then echo "!!!DISTRIBUTION BUILD!!!" - ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext"; bash Build.sh - ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat"; bash Build.sh - ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc"; bash Build.sh - ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext"; bash Build.sh - ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat"; bash Build.sh - ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb"; bash Build.sh - ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc"; bash Build.sh - ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_ram"; bash Build.sh -# ROM_PLATFORM="RCZ80"; ROM_CONFIG="mt"; bash Build.sh -# ROM_PLATFORM="RCZ80"; ROM_CONFIG="duart"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="easy"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="tiny"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512"; bash Build.sh - ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="SBC"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="SBC"; ROM_CONFIG="simh"; bash Build.sh + ROM_PLATFORM="SBC"; ROM_CONFIG="simh_std"; bash Build.sh ROM_PLATFORM="MBC"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc126"; bash Build.sh - ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc130"; bash Build.sh - ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131"; bash Build.sh - ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140"; bash Build.sh - ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503"; bash Build.sh - ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700"; bash Build.sh - ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="ZETA"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="ZETA2"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="N8"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="MK4"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio_std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="easy_std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="tiny_std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz_std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram_std"; bash Build.sh + ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc512_std"; bash Build.sh + ROM_PLATFORM="RCZ180"; ROM_CONFIG="ext_std"; bash Build.sh + ROM_PLATFORM="RCZ180"; ROM_CONFIG="nat_std"; bash Build.sh + ROM_PLATFORM="RCZ180"; ROM_CONFIG="z1rcc_std"; bash Build.sh + ROM_PLATFORM="RCZ280"; ROM_CONFIG="ext_std"; bash Build.sh + ROM_PLATFORM="RCZ280"; ROM_CONFIG="nat_std"; bash Build.sh + ROM_PLATFORM="RCZ280"; ROM_CONFIG="zz80mb_std"; bash Build.sh + ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_std"; bash Build.sh + ROM_PLATFORM="RCZ280"; ROM_CONFIG="zzrcc_ram_std"; bash Build.sh + ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc126_std"; bash Build.sh + ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc130_std"; bash Build.sh + ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc131_std"; bash Build.sh + ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc140_std"; bash Build.sh + ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc503_std"; bash Build.sh + ROM_PLATFORM="SCZ180"; ROM_CONFIG="sc700_std"; bash Build.sh + ROM_PLATFORM="GMZ180"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="DYNO"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="RPH"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="Z80RETRO"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="S100"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="DUO"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="HEATH"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="EPITX"; ROM_CONFIG="std"; bash Build.sh - ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh # ROM_PLATFORM="MON"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="NABU"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="FZ80"; ROM_CONFIG="std"; bash Build.sh + ROM_PLATFORM="UNA"; ROM_CONFIG="std"; bash Build.sh exit fi diff --git a/Source/HBIOS/Config/DUO_std.asm b/Source/HBIOS/Config/DUO_std.asm index f6e91f0b..2078b07e 100644 --- a/Source/HBIOS/Config/DUO_std.asm +++ b/Source/HBIOS/Config/DUO_std.asm @@ -1,51 +1,66 @@ ; ;================================================================================================== -; DUODYNE STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR DUODYNE ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. ; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. ; -#include "cfg_duo.asm" +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). ; -CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. ; -INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). ; -DMAENABLE .SET TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_DUO.asm" ; BATCOND .SET TRUE ; ENABLE LOW BATTERY WARNING MESSAGE +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; -ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) ; PCFENABLE .SET TRUE ; ENABLE PCF8584 I2C CONTROLLER ; -MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM -; +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -; -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM ; CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER ; -ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +DMAENABLE .SET TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM) diff --git a/Source/HBIOS/Config/DYNO_std.asm b/Source/HBIOS/Config/DYNO_std.asm index bc4b677d..91e72918 100644 --- a/Source/HBIOS/Config/DYNO_std.asm +++ b/Source/HBIOS/Config/DYNO_std.asm @@ -1,37 +1,57 @@ ; ;================================================================================================== -; DYNO STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR DYNO ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_dyno.asm" +#INCLUDE "cfg_DYNO.asm" ; CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ; diff --git a/Source/HBIOS/Config/EPITX_std.asm b/Source/HBIOS/Config/EPITX_std.asm index 62dc73e7..b5f9f8fa 100644 --- a/Source/HBIOS/Config/EPITX_std.asm +++ b/Source/HBIOS/Config/EPITX_std.asm @@ -1,34 +1,52 @@ ; ;================================================================================================== -; Z180 Mini ITX STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR Z180 MINI ITX ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE PLATFORM_NAME "Z180 MiniITX" ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_epitx.asm" -; -CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +#INCLUDE "cfg_EPITX.asm" ; CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ ; @@ -36,9 +54,8 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; -HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -; -LEDENABLE .SET FALSE ; ENABLE STATUS LED (SINGLE LED) +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) @@ -50,10 +67,8 @@ SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) ; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -FDMODE .SET FDMODE_EPFDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3] +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_EPFDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) ; @@ -62,3 +77,4 @@ PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) ; PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER diff --git a/Source/HBIOS/Config/FZ80_std.asm b/Source/HBIOS/Config/FZ80_std.asm new file mode 100644 index 00000000..baf75793 --- /dev/null +++ b/Source/HBIOS/Config/FZ80_std.asm @@ -0,0 +1,50 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR S100 FPGA Z80 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_FZ80.asm" +; +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP diff --git a/Source/HBIOS/Config/GMZ180_std.asm b/Source/HBIOS/Config/GMZ180_std.asm new file mode 100644 index 00000000..eef7023c --- /dev/null +++ b/Source/HBIOS/Config/GMZ180_std.asm @@ -0,0 +1,90 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR GENESIS STD Z180 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_GMZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/HEATH_std.asm b/Source/HBIOS/Config/HEATH_std.asm index 4ca7f5b9..1f4cd3c8 100644 --- a/Source/HBIOS/Config/HEATH_std.asm +++ b/Source/HBIOS/Config/HEATH_std.asm @@ -1,69 +1,47 @@ ; ;================================================================================================== -; HEATH H8 Z80 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR HEATH H8 Z80 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. ; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz80.asm" -; -CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -DSKYENABLE .SET TRUE ; ENABLES DSKY FUNCTIONALITY -H8PENABLE .SET TRUE ; ENABLES HEATH H8 FRONT PANEL +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. ; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). ; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. ; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). ; -LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR] -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +#INCLUDE "cfg_HEATH.asm" diff --git a/Source/HBIOS/Config/MBC_std.asm b/Source/HBIOS/Config/MBC_std.asm index 9ae980c8..b12d382e 100644 --- a/Source/HBIOS/Config/MBC_std.asm +++ b/Source/HBIOS/Config/MBC_std.asm @@ -1,59 +1,75 @@ ; ;================================================================================================== -; MBC CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR NHYODYNE ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. ; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. ; -#include "cfg_mbc.asm" +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). ; -CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. ; -INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). ; -DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; -BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_MBC.asm" ; +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE CPUSPDDEF .SET SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; -ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -; -MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) ; DSKYENABLE .SET TRUE ; ENABLES DSKY FUNCTIONALITY ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) PKDENABLE .SET TRUE ; ENABLES DSKY NG PKD DRIVER (8259) ; +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 ; -ESPENABLE .SET TRUE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) ; CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +ESPENABLE .SET TRUE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) diff --git a/Source/HBIOS/Config/MK4_std.asm b/Source/HBIOS/Config/MK4_std.asm index a37a7f87..8ec298e6 100644 --- a/Source/HBIOS/Config/MK4_std.asm +++ b/Source/HBIOS/Config/MK4_std.asm @@ -1,57 +1,74 @@ ; ;================================================================================================== -; MARK IV STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR MARK IV ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_mk4.asm" +#INCLUDE "cfg_MK4.asm" ; CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTCAS .SET TRUE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .SET TRUE ; UART: AUTO-DETECT MF/PIC UART -UART4 .SET TRUE ; UART: AUTO-DETECT 4UART UART SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) VGAENABLE .SET TRUE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_DIDE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_DIDE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC] +SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] ; PRPENABLE .SET TRUE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/MON_std.asm b/Source/HBIOS/Config/MON_std.asm index 5a9ca047..b7b19578 100644 --- a/Source/HBIOS/Config/MON_std.asm +++ b/Source/HBIOS/Config/MON_std.asm @@ -1,30 +1,50 @@ ; ;================================================================================================== -; MONSPUTER Z80 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR MONSPUTER Z80 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_mon.asm" +#INCLUDE "cfg_MON.asm" ; CPUOSC .SET 4000000 ; CPU OSC FREQ IN MHZ CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP diff --git a/Source/HBIOS/Config/N8_std.asm b/Source/HBIOS/Config/N8_std.asm index 9c632cdb..d0a7215e 100644 --- a/Source/HBIOS/Config/N8_std.asm +++ b/Source/HBIOS/Config/N8_std.asm @@ -1,44 +1,65 @@ ; ;================================================================================================== -; N8 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR N8 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_n8.asm" +#INCLUDE "cfg_N8.asm" ; CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) ; PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDMODE .SET SDMODE_CSIO ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) ; -AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER +SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +; +AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER diff --git a/Source/HBIOS/Config/NABU_std.asm b/Source/HBIOS/Config/NABU_std.asm index 8731dc6a..6a5c40a5 100644 --- a/Source/HBIOS/Config/NABU_std.asm +++ b/Source/HBIOS/Config/NABU_std.asm @@ -1,32 +1,51 @@ ; ;================================================================================================== -; NABU Z80 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR NABU Z80 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_nabu.asm" +#INCLUDE "cfg_NABU.asm" ; CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; -TMSMODE .SET TMSMODE_NABU80 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] - +TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm index a8ff8340..f0a7cd92 100644 --- a/Source/HBIOS/Config/RCEZ80_std.asm +++ b/Source/HBIOS/Config/RCEZ80_std.asm @@ -40,9 +40,10 @@ DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) ; -TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX9958 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) diff --git a/Source/HBIOS/Config/RCZ180_ext.asm b/Source/HBIOS/Config/RCZ180_ext.asm deleted file mode 100644 index 3f8c7744..00000000 --- a/Source/HBIOS/Config/RCZ180_ext.asm +++ /dev/null @@ -1,69 +0,0 @@ -; -;================================================================================================== -; RCBUS Z180 STANDARD CONFIGURATION (EXTERNAL MMU ON 512K RAM/ROM BANKED MEMORY MODULE) -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ180_ext_std.asm b/Source/HBIOS/Config/RCZ180_ext_std.asm new file mode 100644 index 00000000..76d9d400 --- /dev/null +++ b/Source/HBIOS/Config/RCZ180_ext_std.asm @@ -0,0 +1,88 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 W/ EXTERNAL Z2 MMU +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ180_nat.asm b/Source/HBIOS/Config/RCZ180_nat.asm deleted file mode 100644 index d8bd155b..00000000 --- a/Source/HBIOS/Config/RCZ180_nat.asm +++ /dev/null @@ -1,68 +0,0 @@ -; -;================================================================================================== -; RCBUS Z180 STANDARD CONFIGURATION (NATIVE Z180 MMU W/ LINEAR MEMORY MODULE) -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ180_nat_std.asm b/Source/HBIOS/Config/RCZ180_nat_std.asm new file mode 100644 index 00000000..aa985d40 --- /dev/null +++ b/Source/HBIOS/Config/RCZ180_nat_std.asm @@ -0,0 +1,88 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 W/ NATIVE Z180 MMU +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC]] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ180_z1rcc.asm b/Source/HBIOS/Config/RCZ180_z1rcc_std.asm similarity index 50% rename from Source/HBIOS/Config/RCZ180_z1rcc.asm rename to Source/HBIOS/Config/RCZ180_z1rcc_std.asm index 5556b6ac..89707e10 100644 --- a/Source/HBIOS/Config/RCZ180_z1rcc.asm +++ b/Source/HBIOS/Config/RCZ180_z1rcc_std.asm @@ -1,50 +1,67 @@ ; ;================================================================================================== -; RCBUS Z180 Z1RCC CONFIGURATION (ROMLESS) +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z180 ROMLESS Z1RCC ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE PLATFORM_NAME "Z1RCC", " [", CONFIG, "]" ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz180.asm" +#INCLUDE "cfg_RCZ180.asm" ; CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] ; RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] ; Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; -MDROM .SET FALSE ; MD: ENABLE ROM DISK -MDRAM .SET TRUE ; MD: ENABLE RAM DISK +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) @@ -55,23 +72,25 @@ ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; ; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +MDROM .SET FALSE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY ; PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ280_ext.asm b/Source/HBIOS/Config/RCZ280_ext.asm deleted file mode 100644 index 035b37a1..00000000 --- a/Source/HBIOS/Config/RCZ280_ext.asm +++ /dev/null @@ -1,67 +0,0 @@ -; -;================================================================================================== -; RCBUS Z280 STANDARD CONFIGURATION (EXTERNAL MMU ON 512K RAM/ROM BANKED MEMORY MODULE) -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz280.asm" -; -CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] -; -Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) -Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) -Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) -; -Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ280_ext_std.asm b/Source/HBIOS/Config/RCZ280_ext_std.asm new file mode 100644 index 00000000..ddf384a4 --- /dev/null +++ b/Source/HBIOS/Config/RCZ280_ext_std.asm @@ -0,0 +1,87 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 W/ EXTERNAL Z2 MMU +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ280.asm" +; +CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +; +Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) +Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) +Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ280_nat.asm b/Source/HBIOS/Config/RCZ280_nat.asm deleted file mode 100644 index 2d74551c..00000000 --- a/Source/HBIOS/Config/RCZ280_nat.asm +++ /dev/null @@ -1,67 +0,0 @@ -; -;================================================================================================== -; RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY) -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz280.asm" -; -CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280] -; -Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) -Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) -Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) -; -Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ280_nat_std.asm b/Source/HBIOS/Config/RCZ280_nat_std.asm new file mode 100644 index 00000000..8d19c52e --- /dev/null +++ b/Source/HBIOS/Config/RCZ280_nat_std.asm @@ -0,0 +1,88 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 W/ NATIVE Z280 MMU +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ280.asm" +; +CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +; +Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) +Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) +Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ280_zz80mb.asm b/Source/HBIOS/Config/RCZ280_zz80mb.asm deleted file mode 100644 index 7a54bc23..00000000 --- a/Source/HBIOS/Config/RCZ280_zz80mb.asm +++ /dev/null @@ -1,72 +0,0 @@ -; -;================================================================================================== -; RCBUS Z280 STANDARD CONFIGURATION (NATIVE Z280 MMU W/ LINEAR MEMORY ON ZZ80MB) -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "ZZ80MB", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz280.asm" -; -CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280] -; -RAMBIAS .SET 8192 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -; -Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) -Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) -Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) -; -Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -Z2U0HFC .SET TRUE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ280_zz80mb_std.asm b/Source/HBIOS/Config/RCZ280_zz80mb_std.asm new file mode 100644 index 00000000..31a17a72 --- /dev/null +++ b/Source/HBIOS/Config/RCZ280_zz80mb_std.asm @@ -0,0 +1,91 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS ZZ80MB Z280 W/ NATIVE Z280 MMU +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "ZZ80MB", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ280.asm" +; +CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET 8192 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +; +Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) +Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) +Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +Z2U0HFC .SET TRUE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ280_zzrcc_ram.asm b/Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm similarity index 50% rename from Source/HBIOS/Config/RCZ280_zzrcc_ram.asm rename to Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm index 957535d2..99ee7dc1 100644 --- a/Source/HBIOS/Config/RCZ280_zzrcc_ram.asm +++ b/Source/HBIOS/Config/RCZ280_zzrcc_ram_std.asm @@ -1,44 +1,60 @@ ; ;================================================================================================== -; RCBUS Z280 ZZRCC CONFIGURATION (ROMLESS) +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 ROMLESS ZZRCC W/ NATIVE Z280 MMU ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]" ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz280.asm" +#INCLUDE "cfg_RCZ280.asm" ; CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ -INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280] +INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +; RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE ; Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) @@ -46,33 +62,38 @@ Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) ; -MDROM .SET FALSE ; MD: ENABLE ROM DISK -MDRAM .SET TRUE ; MD: ENABLE RAM DISK +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) Z2UOSC .SET (CPUOSC / 16) ; Z2U: OSC FREQUENCY IN MHZ Z2U0HFC .SET TRUE ; Z2U0: ENABLE HARDWARE FLOW CONTROL -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +MDROM .SET FALSE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY ; PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ280_zzrcc.asm b/Source/HBIOS/Config/RCZ280_zzrcc_std.asm similarity index 50% rename from Source/HBIOS/Config/RCZ280_zzrcc.asm rename to Source/HBIOS/Config/RCZ280_zzrcc_std.asm index db8067b8..d7a6bec0 100644 --- a/Source/HBIOS/Config/RCZ280_zzrcc.asm +++ b/Source/HBIOS/Config/RCZ280_zzrcc_std.asm @@ -1,44 +1,60 @@ ; ;================================================================================================== -; RCBUS Z280 ZZRCC CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z280 ZZRCC W/ NATIVE Z280 MMU ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE PLATFORM_NAME "ZZRCC", " [", CONFIG, "]" ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz280.asm" +#INCLUDE "cfg_RCZ280.asm" ; CPUOSC .SET 29491200 ; CPU OSC FREQ IN MHZ -INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280] +INTMODE .SET 3 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; RAMSIZE .SET 256 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .SET 256 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +MEMMGR .SET MM_Z280 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +; RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE ; Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) @@ -46,33 +62,39 @@ Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) ; -MDROM .SET TRUE ; MD: ENABLE ROM DISK -MDRAM .SET TRUE ; MD: ENABLE RAM DISK +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) Z2UENABLE .SET TRUE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) Z2UOSC .SET (CPUOSC / 16) ; Z2U: OSC FREQUENCY IN MHZ Z2U0HFC .SET TRUE ; Z2U0: ENABLE HARDWARE FLOW CONTROL -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY ; PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_easy.asm b/Source/HBIOS/Config/RCZ80_easy_std.asm similarity index 56% rename from Source/HBIOS/Config/RCZ80_easy.asm rename to Source/HBIOS/Config/RCZ80_easy_std.asm index ae6a1d8b..c9a526a1 100644 --- a/Source/HBIOS/Config/RCZ80_easy.asm +++ b/Source/HBIOS/Config/RCZ80_easy_std.asm @@ -1,52 +1,74 @@ ; ;================================================================================================== -; EASY Z80 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR EASY Z80 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE PLATFORM_NAME "Easy-Z80", " [", CONFIG, "]" ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz80.asm" +#INCLUDE "cfg_RCZ80.asm" +; +PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] ; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH] CPUOSC .SET 10000000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCOSC .SET 921600 ; CTC CLOCK FREQUENCY WDOGMODE .SET WDOG_EZZ80 ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] WDOGIO .SET $6F ; WATCHDOG REGISTER ADR +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) ; -CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT -CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER -CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCOSC .SET 921600 ; CTC CLOCK FREQUENCY +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) @@ -56,27 +78,28 @@ SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372 SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) ; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_jbl.asm b/Source/HBIOS/Config/RCZ80_jbl_std.asm similarity index 62% rename from Source/HBIOS/Config/RCZ80_jbl.asm rename to Source/HBIOS/Config/RCZ80_jbl_std.asm index e43b54a8..1e84ef5b 100644 --- a/Source/HBIOS/Config/RCZ80_jbl.asm +++ b/Source/HBIOS/Config/RCZ80_jbl_std.asm @@ -1,8 +1,49 @@ ; ;================================================================================================== -; RCBUS Z80 COLECOVISION-COMPATIBLE CONFIGURATION FOR J.B. LANGSTON'S GAME BOARDS +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ JBL GAME BOARDS ;================================================================================================== ; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +; NOTES: +; ; THIS CONFIGURATION ENABLES DRIVERS FOR THE TMS9918 AND SN76489 BOARDS BY J.B. LANGSTON ; AND THE YM2149 BOARD BY ED BRINDLEY. THE TMS9918 IS CONFIGURED TO USE THE COLECOVISION ; PORTS AND HAS INTERRUPTS DISABLED BECAUSE COLECOVISION USES NMI, WHICH WOULD BREAK CP/M @@ -22,34 +63,21 @@ ; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY ; YOUR FILE IN THE BUILD PROCESS. ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; #DEFINE BOOT_DEFAULT "Z" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz80.asm" +#INCLUDE "Config/RCZ80_std.asm" ; CPUOSC .SET 3686400 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -;BOOTCON .SET 1 ; BOOT CONSOLE DEVICE ; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +VDAEMU_SERKBD .SET 1 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; -UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG @@ -59,22 +87,18 @@ SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_COLECO ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_COLECO ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 1 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET TRUE ; SN: ENABLE SN76489 SOUND DRIVER ; FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY ; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET TRUE ; SN: ENABLE SN76489 SOUND DRIVER +; +AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] diff --git a/Source/HBIOS/Config/RCZ80_kio.asm b/Source/HBIOS/Config/RCZ80_kio.asm deleted file mode 100644 index df822ed8..00000000 --- a/Source/HBIOS/Config/RCZ80_kio.asm +++ /dev/null @@ -1,78 +0,0 @@ -; -;================================================================================================== -; RCBUS Z80 STANDARD CONFIGURATION W/ KIO -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz80.asm" -; -CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ -INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -KIOENABLE .SET TRUE ; ENABLE ZILOG KIO SUPPORT -; -CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT -CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER -CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIO0MODE .SET SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] -SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCTCC .SET 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ80_kio_std.asm b/Source/HBIOS/Config/RCZ80_kio_std.asm new file mode 100644 index 00000000..f2fea1fb --- /dev/null +++ b/Source/HBIOS/Config/RCZ80_kio_std.asm @@ -0,0 +1,65 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ KIO +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "Config/RCZ80_std.asm" +; +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +KIOENABLE .SET TRUE ; ENABLE ZILOG KIO SUPPORT +; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCBASE .SET KIOBASE+$04 ; CTC BASE I/O ADDRESS +CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIO0MODE .SET SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET KIOBASE+$08 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCTCC .SET 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE diff --git a/Source/HBIOS/Config/RCZ80_skz.asm b/Source/HBIOS/Config/RCZ80_skz_std.asm similarity index 52% rename from Source/HBIOS/Config/RCZ80_skz.asm rename to Source/HBIOS/Config/RCZ80_skz_std.asm index b2b804c6..b7911fd8 100644 --- a/Source/HBIOS/Config/RCZ80_skz.asm +++ b/Source/HBIOS/Config/RCZ80_skz_std.asm @@ -1,73 +1,90 @@ ; ;================================================================================================== -; RCBUS Z80 STANDARD CONFIGURATION W/ SERGEY KISELEV Z80 + 512K CPU +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 W/ SERGEY KISELEL Z80+512K CPU ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz80.asm" +#INCLUDE "cfg_RCZ80.asm" ; CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES ; SKZENABLE .SET TRUE ; ENABLE SERGEY'S Z80-512K FEATURES SKZDIV .SET DIV_12 ; UART CLK (CLK2) DIVIDER FOR Z80-512K WDOGMODE .SET WDOG_SKZ ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) LEDPORT .SET $6E ; STATUS LED PORT ADDRESS +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) ; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) SIO0BCLK .SET CPUOSC / 12 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0BCFG .SET SER_38400_8N1 ; SIO 0B: SERIAL LINE CONFIG -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) ; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_std.asm b/Source/HBIOS/Config/RCZ80_std.asm index 964a5ad5..a486258a 100644 --- a/Source/HBIOS/Config/RCZ80_std.asm +++ b/Source/HBIOS/Config/RCZ80_std.asm @@ -1,67 +1,90 @@ ; ;================================================================================================== -; RCBUS Z80 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz80.asm" +#INCLUDE "cfg_RCZ80.asm" ; CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) ; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) ; TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET TRUE ; SN: ENABLE SN76489 SOUND DRIVER ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|USR] -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) ; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_tiny.asm b/Source/HBIOS/Config/RCZ80_tiny_std.asm similarity index 57% rename from Source/HBIOS/Config/RCZ80_tiny.asm rename to Source/HBIOS/Config/RCZ80_tiny_std.asm index 81935820..1e6f2cab 100644 --- a/Source/HBIOS/Config/RCZ80_tiny.asm +++ b/Source/HBIOS/Config/RCZ80_tiny_std.asm @@ -1,88 +1,108 @@ ; ;================================================================================================== -; TINY Z80 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR TINY Z80 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE PLATFORM_NAME "Tiny-Z80", " [", CONFIG, "]" ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rcz80.asm" +#INCLUDE "cfg_RCZ80.asm" +; +PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] ; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH] CPUOSC .SET 16000000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCBASE .SET $10 ; CTC BASE I/O ADDRESS +CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCOSC .SET 921600 ; CTC CLOCK FREQUENCY EIPCENABLE .SET TRUE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION WDOGMODE .SET WDOG_EZZ80 ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] WDOGIO .SET $6F ; WATCHDOG REGISTER ADR -; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) LEDPORT .SET $6E ; STATUS LED PORT ADDRESS +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) ; -CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT -CTCBASE .SET $10 ; CTC BASE I/O ADDRESS -CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER -CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCOSC .SET 921600 ; CTC CLOCK FREQUENCY +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIO0MODE .SET SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP] +SIO0MODE .SET SIOMODE_STD ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] SIO0BASE .SET $18 ; SIO 0: REGISTERS BASE ADR SIO0ACLK .SET 1843200 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO0BCLK .SET 1843200 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS +; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) ; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_user.asm b/Source/HBIOS/Config/RCZ80_user.asm new file mode 100644 index 00000000..9966f297 --- /dev/null +++ b/Source/HBIOS/Config/RCZ80_user.asm @@ -0,0 +1,57 @@ +; +;================================================================================================== +; ROMWBW CUSTOM USER BUILD SETTINGS EXAMPLE FOR RCBUS Z80 +;================================================================================================== +; +; THIS FILE IS AN EXAMPLE OF A CUSTOM USER SETTINGS FILE. THESE +; SETTINGS OVERRIDE THE DEFAULT SETTINGS OF THE INHERITED FILES AS +; DESIRED BY A USER. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; THIS FILE EXEMPLIFIES THE IDEAL WAY TO CREATE A USER SPECIFIC BUILD +; CONFIGURATION. NOTICE THAT IT INCLUDES THE DEFAULT BUILD SETTINGS +; FILE AND OVERRIDES SOME DESIRED SETTINGS. +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +; THIS EXAMPLE CUSTOM USER SETTINGS FILE DOES THE FOLLOWING: +; +; 1. SETS A CUSTOM NAME USED IN THE BOOT LOADER BANNER +; 2. BOOTS ZSDOS BY DEFAULT AFTER 10 SECOND DELAY +; 3. ENABLES LPT PRINTER SUPPORT +; +#DEFINE PLATFORM_NAME "My Custom RCBus Computer", " [", CONFIG, "]" +#DEFINE BOOT_DEFAULT "Z" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "Config/RCZ80_std.asm" ; INHERIT FROM OFFICIAL BUILD SETTINGS +; +BOOT_TIMEOUT .SET 10 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +; +LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) diff --git a/Source/HBIOS/Config/RCZ80_zrc.asm b/Source/HBIOS/Config/RCZ80_zrc.asm deleted file mode 100644 index 35770df3..00000000 --- a/Source/HBIOS/Config/RCZ80_zrc.asm +++ /dev/null @@ -1,67 +0,0 @@ -; -;================================================================================================== -; RCBUS Z80 ZRC CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz80.asm" -; -CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -RAMSIZE .SET 1536 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -MEMMGR .SET MM_ZRC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ80_zrc512.asm b/Source/HBIOS/Config/RCZ80_zrc512.asm deleted file mode 100644 index cf1eed89..00000000 --- a/Source/HBIOS/Config/RCZ80_zrc512.asm +++ /dev/null @@ -1,69 +0,0 @@ -; -;================================================================================================== -; RCBUS Z80 ZRC512 CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "ZRC512", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz80.asm" -; -CPUOSC .SET 22000000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -MEMMGR .SET MM_ZRC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] -; -MDROM .SET FALSE ; MD: ENABLE ROM DISK -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ80_zrc512_std.asm b/Source/HBIOS/Config/RCZ80_zrc512_std.asm new file mode 100644 index 00000000..452ec099 --- /dev/null +++ b/Source/HBIOS/Config/RCZ80_zrc512_std.asm @@ -0,0 +1,91 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ZRC512 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "ZRC512", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ80.asm" +; +CPUOSC .SET 22000000 ; CPU OSC FREQ IN MHZ +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +MEMMGR .SET MM_ZRC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +MDROM .SET FALSE ; MD: ENABLE ROM DISK +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_zrc_ram.asm b/Source/HBIOS/Config/RCZ80_zrc_ram.asm deleted file mode 100644 index 3e3e3ef4..00000000 --- a/Source/HBIOS/Config/RCZ80_zrc_ram.asm +++ /dev/null @@ -1,69 +0,0 @@ -; -;================================================================================================== -; RCBUS Z80 ZRC CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_rcz80.asm" -; -CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -MEMMGR .SET MM_ZRC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] -; -MDROM .SET FALSE ; MD: ENABLE ROM DISK -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/RCZ80_zrc_ram_std.asm b/Source/HBIOS/Config/RCZ80_zrc_ram_std.asm new file mode 100644 index 00000000..8f1d73d9 --- /dev/null +++ b/Source/HBIOS/Config/RCZ80_zrc_ram_std.asm @@ -0,0 +1,90 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ROMLESS ZRC +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ80.asm" +; +CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +MEMMGR .SET MM_ZRC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +MDROM .SET FALSE ; MD: ENABLE ROM DISK +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RCZ80_zrc_std.asm b/Source/HBIOS/Config/RCZ80_zrc_std.asm new file mode 100644 index 00000000..d0a6531e --- /dev/null +++ b/Source/HBIOS/Config/RCZ80_zrc_std.asm @@ -0,0 +1,88 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR RCBUS Z80 ZRC +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "ZRC", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_RCZ80.asm" +; +CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ +; +RAMSIZE .SET 1536 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +MEMMGR .SET MM_ZRC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VRCENABLE .SET TRUE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/RPH_std.asm b/Source/HBIOS/Config/RPH_std.asm index 3dedea59..cfffc3c9 100644 --- a/Source/HBIOS/Config/RPH_std.asm +++ b/Source/HBIOS/Config/RPH_std.asm @@ -1,40 +1,59 @@ ; ;================================================================================================== -; RHYOPHYRE STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR RHYOPHYRE ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_rph.asm" +#INCLUDE "cfg_RPH.asm" ; CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; -RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) diff --git a/Source/HBIOS/Config/S100_std.asm b/Source/HBIOS/Config/S100_std.asm index e3846c73..92b43a18 100644 --- a/Source/HBIOS/Config/S100_std.asm +++ b/Source/HBIOS/Config/S100_std.asm @@ -1,38 +1,58 @@ ; ;================================================================================================== -; S100 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR S100 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_s100.asm" +#INCLUDE "cfg_S100.asm" ; CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 Z180_MEMWAIT .SET 1 ; Z180: MEMORY WAIT STATES (0-3) Z180_IOWAIT .SET 2 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) ; +CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) ; @@ -42,5 +62,5 @@ SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR] -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY +SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY diff --git a/Source/HBIOS/Config/SBC_max.asm b/Source/HBIOS/Config/SBC_max.asm deleted file mode 100644 index f2ff533d..00000000 --- a/Source/HBIOS/Config/SBC_max.asm +++ /dev/null @@ -1,72 +0,0 @@ -; -;================================================================================================== -; SBC MAXIMUM CONFIGURATION -;================================================================================================== -; -; THIS CONFIGURATION FILE IS *NOT* MEANT TO GENERATE A FUNCTIONAL ROM. -; IT IS USED TO HELP TEST BUILDS WITH MOST FEATURES ENABLED. -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .SET OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .SET BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_sbc.asm" -; -BATCOND .SET TRUE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .SET TRUE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION -; -KIOENABLE .SET TRUE ; ENABLE ZILOG KIO SUPPORT -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -DSKYENABLE .SET TRUE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) -ICMENABLE .SET TRUE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -PKDENABLE .SET TRUE ; ENABLES DSKY NG PKD DRIVER (8259) -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -; -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -VDUENABLE .SET TRUE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -VGAENABLE .SET TRUE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -; -RFENABLE .SET TRUE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -; -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -; -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -; -PRPENABLE .SET TRUE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -; -AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER (AY38910.ASM) -; -SN76489ENABLE .SET TRUE ; SN: ENABLE SN76489 SOUND DRIVER (SN76489.ASM) -; -YM2612ENABLE .SET TRUE ; YM2612: ENABLE ECB VGM YM2612 SOUND DRIVER (YM2612.ASM) diff --git a/Source/HBIOS/Config/SBC_simh.asm b/Source/HBIOS/Config/SBC_simh.asm deleted file mode 100644 index 328d6eed..00000000 --- a/Source/HBIOS/Config/SBC_simh.asm +++ /dev/null @@ -1,39 +0,0 @@ -; -;================================================================================================== -; SBC SIMH EMULATOR CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_sbc.asm" -; -INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -; -HTIMENABLE .SET TRUE ; ENABLE SIMH TIMER SUPPORT -; -SIMRTCENABLE .SET TRUE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTSBCFORCE .SET TRUE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -; -HDSKENABLE .SET TRUE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) diff --git a/Source/HBIOS/Config/SBC_simh_std.asm b/Source/HBIOS/Config/SBC_simh_std.asm new file mode 100644 index 00000000..a07330c6 --- /dev/null +++ b/Source/HBIOS/Config/SBC_simh_std.asm @@ -0,0 +1,65 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR N8VEM SBC W/SIMH SUPPORT +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_SBC.asm" +; +INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +HTIMENABLE .SET TRUE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET TRUE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $6D ; SSER: STATUS PORT +SSERDATA .SET $68 ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00100000 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +; +HDSKENABLE .SET TRUE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) diff --git a/Source/HBIOS/Config/SBC_std.asm b/Source/HBIOS/Config/SBC_std.asm index 27c0f5fd..0a519655 100644 --- a/Source/HBIOS/Config/SBC_std.asm +++ b/Source/HBIOS/Config/SBC_std.asm @@ -1,55 +1,70 @@ ; ;================================================================================================== -; SBC STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR N8VEM SBC ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_sbc.asm" +#INCLUDE "cfg_SBC.asm" ; CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTSBC .SET TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART -UARTCAS .SET TRUE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .SET TRUE ; UART: AUTO-DETECT MF/PIC UART -UART4 .SET TRUE ; UART: AUTO-DETECT 4UART UART -UARTRC .SET FALSE ; UART: AUTO-DETECT RC UART SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) ; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) VGAENABLE .SET TRUE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC] +SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] ; PRPENABLE .SET TRUE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/SCZ180_sc126.asm b/Source/HBIOS/Config/SCZ180_sc126.asm deleted file mode 100644 index 785580e9..00000000 --- a/Source/HBIOS/Config/SCZ180_sc126.asm +++ /dev/null @@ -1,71 +0,0 @@ -; -;================================================================================================== -; SC126 STANDARD CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "Small Computer SC126", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_scz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -FPLED_IO .SET $0D ; FP: PORT ADDRESS FOR FP LEDS -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR] -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/SCZ180_sc126_std.asm b/Source/HBIOS/Config/SCZ180_sc126_std.asm new file mode 100644 index 00000000..85978ec5 --- /dev/null +++ b/Source/HBIOS/Config/SCZ180_sc126_std.asm @@ -0,0 +1,92 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR SC126 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Small Computer SC126", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_SCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $0D ; FP: PORT ADDRESS FOR FP LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/SCZ180_sc130.asm b/Source/HBIOS/Config/SCZ180_sc130.asm deleted file mode 100644 index 9987bf39..00000000 --- a/Source/HBIOS/Config/SCZ180_sc130.asm +++ /dev/null @@ -1,72 +0,0 @@ -; -;================================================================================================== -; SC130 STANDARD CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "Small Computer SC130", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_scz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -; -LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR] -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/SCZ180_sc130_std.asm b/Source/HBIOS/Config/SCZ180_sc130_std.asm new file mode 100644 index 00000000..7d73f2f8 --- /dev/null +++ b/Source/HBIOS/Config/SCZ180_sc130_std.asm @@ -0,0 +1,93 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR SC130 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Small Computer SC130", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_SCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +; +LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/SCZ180_sc131.asm b/Source/HBIOS/Config/SCZ180_sc131.asm deleted file mode 100644 index 8d224875..00000000 --- a/Source/HBIOS/Config/SCZ180_sc131.asm +++ /dev/null @@ -1,55 +0,0 @@ -; -;================================================================================================== -; SC131 STANDARD CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "Small Computer SC131", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_scz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS -FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES -; -LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) -; -DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR] -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY -CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT diff --git a/Source/HBIOS/Config/SCZ180_sc131_std.asm b/Source/HBIOS/Config/SCZ180_sc131_std.asm new file mode 100644 index 00000000..9029c0d7 --- /dev/null +++ b/Source/HBIOS/Config/SCZ180_sc131_std.asm @@ -0,0 +1,79 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR SC131 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Small Computer SC131", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_SCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +; +; +LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +; +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT diff --git a/Source/HBIOS/Config/SCZ180_sc140.asm b/Source/HBIOS/Config/SCZ180_sc140.asm deleted file mode 100644 index 755975d4..00000000 --- a/Source/HBIOS/Config/SCZ180_sc140.asm +++ /dev/null @@ -1,66 +0,0 @@ -; -;================================================================================================== -; SC140 STANDARD CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "Small Computer SC140", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_scz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .SET $A0 ; FP: PORT ADDRESS FOR FP LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .SET $A0 ; FP: PORT ADDRESS FOR FP SWITCHES -; -LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_LINC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -; -IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS diff --git a/Source/HBIOS/Config/SCZ180_sc140_std.asm b/Source/HBIOS/Config/SCZ180_sc140_std.asm new file mode 100644 index 00000000..fb754bbd --- /dev/null +++ b/Source/HBIOS/Config/SCZ180_sc140_std.asm @@ -0,0 +1,87 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR PLATFORM: SBC +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Small Computer SC140", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_SCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $A0 ; FP: PORT ADDRESS FOR FP LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $A0 ; FP: PORT ADDRESS FOR FP SWITCHES +; +LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_LINC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/SCZ180_sc503.asm b/Source/HBIOS/Config/SCZ180_sc503.asm deleted file mode 100644 index 543d2be7..00000000 --- a/Source/HBIOS/Config/SCZ180_sc503.asm +++ /dev/null @@ -1,66 +0,0 @@ -; -;================================================================================================== -; SC503 STANDARD CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "Small Computer SC503", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_scz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .SET $A0 ; FP: PORT ADDRESS FOR FP LEDS -FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .SET $A0 ; FP: PORT ADDRESS FOR FP SWITCHES -; -LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -AY38910ENABLE .SET FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_LINC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -; -IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS diff --git a/Source/HBIOS/Config/SCZ180_sc503_std.asm b/Source/HBIOS/Config/SCZ180_sc503_std.asm new file mode 100644 index 00000000..ea11038d --- /dev/null +++ b/Source/HBIOS/Config/SCZ180_sc503_std.asm @@ -0,0 +1,89 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR SC503 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Small Computer SC503", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_SCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $A0 ; FP: PORT ADDRESS FOR FP LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $A0 ; FP: PORT ADDRESS FOR FP SWITCHES +; +LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +; +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDE0BASE .SET $90 ; IDE 0: IO BASE ADDRESS +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_LINC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/SCZ180_sc700.asm b/Source/HBIOS/Config/SCZ180_sc700.asm deleted file mode 100644 index d3d6284c..00000000 --- a/Source/HBIOS/Config/SCZ180_sc700.asm +++ /dev/null @@ -1,73 +0,0 @@ -; -;================================================================================================== -; SC700 STANDARD CONFIGURATION -;================================================================================================== -; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. -; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. -; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! -; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). -; -#DEFINE PLATFORM_NAME "Small Computer SC700", " [", CONFIG, "]" -; -#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT -; -#include "cfg_scz180.asm" -; -CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ -CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -; -Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -; -LEDENABLE .SET TRUE ; ENABLE STATUS LED (SINGLE LED) -LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .SET $0E ; STATUS LED PORT ADDRESS -; -FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS -; -DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO] -MKYENABLE .SET FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -; -AY38910ENABLE .SET TRUE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC] -SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER -; -FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC] -; -IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR] -SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY -; -PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) diff --git a/Source/HBIOS/Config/SCZ180_sc700_std.asm b/Source/HBIOS/Config/SCZ180_sc700_std.asm new file mode 100644 index 00000000..486dfdce --- /dev/null +++ b/Source/HBIOS/Config/SCZ180_sc700_std.asm @@ -0,0 +1,92 @@ +; +;================================================================================================== +; ROMWBW DEFAULT BUILD SETTINGS FOR SC700 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Small Computer SC700", " [", CONFIG, "]" +; +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT +; +#INCLUDE "cfg_SCZ180.asm" +; +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +; +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +VDAEMU_SERKBD .SET 0 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPWDC] +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] diff --git a/Source/HBIOS/Config/UNA_std.asm b/Source/HBIOS/Config/UNA_std.asm index ee28f83a..ba3e6b18 100644 --- a/Source/HBIOS/Config/UNA_std.asm +++ b/Source/HBIOS/Config/UNA_std.asm @@ -1,27 +1,47 @@ ; ;================================================================================================== -; UNA STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR UNA ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_una.asm" +#INCLUDE "cfg_UNA.asm" diff --git a/Source/HBIOS/Config/Z80RETRO_std.asm b/Source/HBIOS/Config/Z80RETRO_std.asm index 29475b6a..c3a920c5 100644 --- a/Source/HBIOS/Config/Z80RETRO_std.asm +++ b/Source/HBIOS/Config/Z80RETRO_std.asm @@ -1,33 +1,54 @@ ; ;================================================================================================== -; ZETA2 STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR Z80 RETRO ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_z80retro.asm" +#INCLUDE "cfg_Z80RETRO.asm" ; CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 +; CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) diff --git a/Source/HBIOS/Config/ZETA2_std.asm b/Source/HBIOS/Config/ZETA2_std.asm index 0245bfd5..413457db 100644 --- a/Source/HBIOS/Config/ZETA2_std.asm +++ b/Source/HBIOS/Config/ZETA2_std.asm @@ -1,40 +1,57 @@ ; ;================================================================================================== -; ZETA2 STANDARD CONFIGURATION +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA 2 ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_zeta2.asm" +#INCLUDE "cfg_ZETA2.asm" ; CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTSBC .SET TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART -; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) diff --git a/Source/HBIOS/Config/ZETA_std.asm b/Source/HBIOS/Config/ZETA_std.asm index d422cab9..3984e5a1 100644 --- a/Source/HBIOS/Config/ZETA_std.asm +++ b/Source/HBIOS/Config/ZETA_std.asm @@ -1,40 +1,58 @@ ; ;================================================================================================== -; ZETA STANDARD CONFIGURATION +; ROMWBW DEFAULT BUILD SETTINGS FOR ZETA ;================================================================================================== ; -; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE -; CFG_.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS -; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE -; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. -; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE _XXX.ASM AND SPECIFY -; YOUR FILE IN THE BUILD PROCESS. +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THESE SETTINGS DEFINE THE OFFICIAL BUILD FOR THIS +; PLATFORM AS DISTRIBUTED IN ROMWBW RELEASES. ; -; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. -; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO -; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON -; SETTINGS. +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: ; -; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, -; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING -; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS ; -; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO -; DIRECTORIES ABOVE THIS ONE). +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. +; +; TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THIS FILE, THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE +; SOURCE DIRECTORY (TWO DIRECTORIES ABOVE THIS ONE). +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". ; #DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD ON OR AUTO BOOT ; -#include "cfg_zeta.asm" +#INCLUDE "cfg_ZETA.asm" ; CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ -INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 -CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) ; -UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTSBC .SET TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART +CRTACT .SET TRUE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP ; FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .SET FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC] +FDMODE .SET FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] ; PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) diff --git a/Source/HBIOS/Makefile.new b/Source/HBIOS/Makefile.new index 16d7f26e..9beb9d79 100644 --- a/Source/HBIOS/Makefile.new +++ b/Source/HBIOS/Makefile.new @@ -5,7 +5,7 @@ DIST_OBJECTS := \ RCZ80_zrc_ram RCZ80_zrc512 RPH_std SBC_std SBC_simh MBC_std \ DUO_std SCZ180_sc126 SCZ180_sc130 SCZ180_sc131 SCZ180_sc140 \ SCZ180_sc503 SCZ180_sc700 S100_std UNA_std Z80RETRO_std \ - ZETA_std ZETA2_std HEATH_std EPITX_std + ZETA_std ZETA2_std HEATH_std EPITX_std GMZ180_std # RCZ80_mt RCZ80_duart MON_std OBJECTS := $(DIST_OBJECTS) diff --git a/Source/HBIOS/ay38910.asm b/Source/HBIOS/ay38910.asm index 5fb150e2..6006b2a9 100644 --- a/Source/HBIOS/ay38910.asm +++ b/Source/HBIOS/ay38910.asm @@ -19,6 +19,15 @@ ; UNUSED BITS CAN BE READ BACK AND WRITTEN ON YM. ; VOLTAGE LEVEL OUTPUT ON A AY-3-8910 IS LOW AND AROUND 2V ON YM2149. ; +; THERE ARE TWO VARIANTS OF AY-3-8910 SOUND CARDS THAT HAVE BEEN +; PRODUCED FOR THE RCBUS. THE ONE PRODUCED BY ED BRINDLEY (EB) USES +; THE SAME PORT FOR REGISTER SELECT (RSEL) AND REGISTER IN (RIN). +; THE ONE PRODUCED BY MARTEN FELDTMANN (MF) USES THE PORT FOLLOWING +; REGISTER SELECT (RSEL) FOR THE REGISTER IN (RIN) PORT. THE FOLLOWING +; EQUATE MUST BE SET CORRECTLY FOR THE HARDWARE BEING USED. THIS +; HAS NOT BEEN MOVED TO A CONFIG VARIABLE BECAUSE THE MF MODULE IS +; RARELY ENCOUNTERED IN THE WILD. +; AY_RCSND .EQU 0 ; 0 = EB MODULE, 1=MF MODULE ; DEVECHO "AY38910: MODE=" @@ -118,6 +127,7 @@ AY_FNTBL: .DW AY_QUERY .DW AY_DURATION .DW AY_DEVICE + .DW AY_BEEP ; #IF (($ - AY_FNTBL) != (SND_FNCNT * 2)) .ECHO "*** INVALID SND FUNCTION TABLE ***\n" @@ -147,7 +157,6 @@ AY_NOISECNT .EQU 1 ; COUNT NUMBER OF NOISE CHANNELS ; ; ANNOUNCE DEVICE ON CONSOLE. ACTIVATE DEVICE IF REQUIRED. ; SETUP FUNCTION TABLES. SETUP THE DEVICE. -; ANNOUNCE DEVICE WITH BEEP. SET VOLUME OFF. ; RETURN INITIALIZATION STATUS ; AY38910_INIT: @@ -212,77 +221,22 @@ AY38910_INIT: LD A,$FF ; UNSUCCESSFULL INIT RET ; -AY_FND: LD IY, AY_IDAT ; SETUP FUNCTION TABLE +AY_FND: + LD IY, AY_IDAT ; SETUP FUNCTION TABLE LD BC, AY_FNTBL ; POINTER TO INSTANCE DATA LD DE, AY_IDAT ; BC := FUNCTION TABLE ADDRESS CALL SND_ADDENT ; DE := INSTANCE DATA PTR ; - CALL AY_INIT ; SET DEFAULT CHIP CONFIGURATION -; - LD E,$08 ; SET VOLUME TO 50% - CALL AY_SETV ; ON ALL CHANNELS -; -; LD DE,(AY_R2CHBP*256)+$55 ; BEEP ON CHANNEL B (CENTER) -; CALL AY_WRTPSG ; R02 = $55 = 01010101 - LD DE,(AY_R3CHBP*256)+$00 - CALL AY_WRTPSG ; R03 = $00 = XXXX0000 -; -#IF (SYSTIM != TM_NONE) - LD A, TICKFREQ / 3 ; SCHEDULE IN 1/3 SECOND TO TURN OFF SOUND - LD (AY_TIMTIK), A -; - ; RESET THE AY_TIMER BYPASS - LD HL,AY_TIMER1 - LD (AY_TIMER + 1),HL -; - ; HOOK THE TICK VECTOR - LD HL,(VEC_TICK + 1) ; GET CUR TICKS VECTOR - LD (AY_TIMHOOK + 1),HL ; SAVE IT INTERNALLY - LD HL,AY_TIMER ; INSTALL TIMER HOOK HANDLER - LD (VEC_TICK + 1),HL -; - LD A, $02 ; NOT READY & IN INTERUPT HANDLER - LD (AY_READY), A -#ELSE - CALL LDELAY ; HALF SECOND DELAY - LD E,$00 ; SET VOLUME OFF - CALL AY_SETV ; ON ALL CHANNELS - LD A, $01 ; READY & NOT IN INTERUPT HANDLER - LD (AY_READY), A -#ENDIF -; + CALL AY_RESET ; SET DEFAULT CHIP CONFIGURATION XOR A ; SUCCESSFULL INIT RET ; -#IF (SYSTIM != TM_NONE) -AY_TIMER: - JP AY_TIMER1 ; SELF MODIFIED TO BYPASS HANDLER -AY_TIMER1: - LD A,(AY_TIMTIK) - DEC A - LD (AY_TIMTIK), A - JR NZ,AY_TIMHOOK -; - LD E,$00 ; SET VOLUME OFF - CALL AY_SETV ; ON ALL CHANNELS - LD A, $01 ; READY & NOT IN INTERUPT HANDLER - LD (AY_READY), A -; - ; MAKE AY_TIMER A NO-OP HANDLER - LD HL,(AY_TIMHOOK + 1) - LD (AY_TIMER + 1),HL -; -AY_TIMHOOK: - JP 0 ; OVERWRITTEN WITH NEXT HANDLER -; -AY_TIMTIK .DB 0 ; COUNT DOWN TO FINISH BOOT BEEP -#ENDIF -; ;====================================================================== ; INITIALIZE DEVICE ;====================================================================== ; AY_INIT: + ; HANDLE R7 SPECIAL #IF (AYMODE == AYMODE_NABU) ; I/O B=INPUT, I/O A=OUTPUT, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A ENABLE LD DE,(AY_R7ENAB*256)+$78 ; SET MIXER CONTROL / IO ENABLE. $78 - 01 111 000 @@ -290,29 +244,21 @@ AY_INIT: ; I/O PORTS = OUTPUT, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A ENABLE LD DE,(AY_R7ENAB*256)+$F8 ; SET MIXER CONTROL / IO ENABLE. $F8 - 11 111 000 #ENDIF - JP AY_WRTPSG -; -AY_CHKREDY: - LD A, (AY_READY) - BIT 0, A - RET NZ - - POP HL ; REMOVE LAST RETURN ADDRESS - OR $FF - RET ; RETURN NZ -; -;====================================================================== -; SET VOLUME ALL CHANNELS -;====================================================================== -; -AY_SETV: - PUSH BC - LD B,AY_TONECNT ; NUMBER OF CHANNELS - LD D,AY_R8AVOL ; BASE REGISTER FOR VOLUME -AY_SV: CALL AY_WRTPSG ; CYCLING THROUGH ALL CHANNELS - INC D - DJNZ AY_SV - POP BC + CALL AY_WRTPSG ; SETUP R7 +; + ; THEN JUST SET ALL OTHER REGISTERS TO ZERO + LD E,0 ; VALUE ZERO + LD D,0 ; START W/ R0 + LD B,7 ; DO 7 REGISTERS (R0-R6) + CALL AY_INIT1 ; DO IT + INC D ; SKIP R7 + LD B,6 ; DO 6 MORE REGISTERS (R8-R13) + ; FALL THRU TO DO IT +; +AY_INIT1: + CALL AY_WRTPSG ; WRITE REGISTER + INC D ; BUMP TO NEXT + DJNZ AY_INIT1 ; LOOP RET ; ;====================================================================== @@ -324,25 +270,15 @@ AY_SV: CALL AY_WRTPSG ; CYCLING THROUGH ALL CHANNELS ; AY_RESET: AUDTRACE(AYT_INIT) - CALL AY_CHKREDY ; RETURNS TO OUR CALLER IF NOT READY -; - PUSH DE - PUSH HL CALL AY_INIT ; SET DEFAULT CHIP CONFIGURATION ; - AUDTRACE(AYT_VOLOFF) - LD E,0 ; SET VOLUME OFF - CALL AY_SETV ; ON ALL CHANNELS -; + ; RESET DEFAULTS IN CASE OF AN IN-PLACE HBIOS RESTART + LD HL,0 + LD (AY_PENDING_PERIOD),HL ; SET TONE PERIOD TO ZERO + LD (AY_PENDING_DURATION),HL; SET DURATION TO ZERO XOR A ; SIGNAL SUCCESS LD (AY_PENDING_VOLUME),A ; SET VOLUME TO ZERO - LD H,A - LD L,A - LD (AY_PENDING_PERIOD),HL ; SET TONE PERIOD TO ZERO -; - POP HL - POP DE - RET + RET ; DONE, A=0 ABOVE ; ;====================================================================== ; SOUND DRIVER FUNCTION - VOLUME @@ -405,12 +341,14 @@ AY_PLAY: AUDTRACE(AYT_PLAY) AUDTRACE_D AUDTRACE_CR - CALL AY_CHKREDY ; RETURNS TO OUR CALLER IF NOT READY ; LD A, (AY_PENDING_PERIOD + 1) ; CHECK THE HIGH BYTE OF THE PERIOD INC A - JR Z, AY_PLAY1 ; PERIOD IS TOO LARGE, UNABLE TO PLAY + JR NZ, AY_PLAY1 ; PERIOD IS OK, CONTINUE + OR $FF ; ELSE TOO LARGE, SIGNAL FAILURE + RET ; AND RETURN ; +AY_PLAY1: PUSH HL PUSH DE LD A,D ; LIMIT CHANNEL 0-2 @@ -423,7 +361,7 @@ AY_PLAY: AUDTRACE_CR ; LD HL,AY_PENDING_PERIOD ; WRITE THE LOWER - ld E,(HL) ; 8-BITS OF THE TONE PERIOD + LD E,(HL) ; 8-BITS OF THE TONE PERIOD CALL AY_WRTPSG INC D ; NEXT REGISTER INC HL ; NEXT BYTE @@ -458,18 +396,6 @@ AY_PLAY: XOR A ; SIGNAL SUCCESS RET ; -AY_PLAY1: - PUSH DE ; TURN VOLUME OFF TO STOP PLAYING - LD A,D ; LIMIT CHANNEL 0-2 - AND $3 ; AND INDEX TO THE - ADD A,AY_R8AVOL ; CHANNEL VOLUME - LD D,A ; REGISTER - LD E,0 - CALL AY_WRTPSG ; SET VOL (E) IN CHANNEL REG (D) - POP DE - OR $FF ; SIGNAL FAILURE - RET -; ;====================================================================== ; SOUND DRIVER FUNCTION - QUERY AND SUBFUNCTIONS ;====================================================================== @@ -537,22 +463,11 @@ AY_DEVICE: RET ; ;====================================================================== -; NON-BLOCKING INTERRUPT CODE +; SOUND DRIVER FUNCTION - BEEP ;====================================================================== ; -AY_DI: - LD A, (AY_READY) - BIT 1, A - RET NZ - HB_DI - RET -; -AY_EI: - LD A, (AY_READY) - BIT 1, A - RET NZ - HB_EI - RET +AY_BEEP: + JP SND_BEEP ; DEFER TO GENERIC CODE IN HBIOS ; ;====================================================================== ; @@ -562,7 +477,6 @@ AY_EI: ;====================================================================== ; AY_WRTPSG: - CALL AY_DI #IFDEF SBCV2004 LD A,(HB_RTCVAL) ; GET CURRENT RTC LATCH VALUE OR %00001000 ; SBC-V2-004 CHANGE @@ -588,14 +502,13 @@ AY_WRTPSG: LD A,(HB_RTCVAL) ; SBC-V2-004 CHANGE TO OUT (RTCIO),A ; NORMAL CLOCK SPEED #ENDIF - JP AY_EI + RET ; ;====================================================================== ; ; READ FROM REGISTER D AND RETURN WITH RESULT IN E ; AY_RDPSG: - CALL AY_DI #IFDEF SBCV2004 LD A,(HB_RTCVAL) ; GET CURRENT RTC LATCH VALUE OR %00001000 ; SBC-V2-004 CHANGE @@ -621,15 +534,13 @@ AY_RDPSG: LD A,(HB_RTCVAL) ; SBC-V2-004 CHANGE TO OUT (RTCIO),A ; NORMAL CLOCK SPEED #ENDIF - JP AY_EI + RET ; ;====================================================================== ; AY_PENDING_PERIOD .DW 0 ; PENDING PERIOD (12 BITS) ; ORDER AY_PENDING_VOLUME .DB 0 ; PENDING VOL (8 BITS) ; SIGNIFICANT AY_PENDING_DURATION .DW 0 ; PENDING DURATION (16 BITS) -AY_READY .DB 0 ; BIT 0 -> NZ DRIVER IS READY TO RECEIVE PLAY COMMAND - ; BIT 1 -> NZ EXECUTING WITHIN TIMER HANDLER = DO NOT DIS/ENABLE INT ; #IF AUDIOTRACE AYT_INIT .DB "\r\nAY_INIT\r\n$" diff --git a/Source/HBIOS/cfg_DUO.asm b/Source/HBIOS/cfg_DUO.asm new file mode 100644 index 00000000..80d62dcd --- /dev/null +++ b/Source/HBIOS/cfg_DUO.asm @@ -0,0 +1,381 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: DUO +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET FALSE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_UNSUP ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $50 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $51 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $52 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $53 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $54 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $94 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $60 ; CTC BASE I/O ADDRESS +CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET (7372800/8) ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $56 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $42 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $42 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $88 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET TRUE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $88 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 7372800 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $58 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $A8 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $70 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $78 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $60 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET (7372800/4) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET (7372800/4) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +CVDUMODE .SET CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] +CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_DUO ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_DUO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $88 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET TRUE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 1 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $4E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET TRUE ; CH 0: ENABLE SD DISK +CH1BASE .SET $FF ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET FALSE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +ESPCONENABLE .SET TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +; +PIOENABLE .SET TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $68 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $6C ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $48 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $EC ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .SET $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_DUO ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_DUO ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $40 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_DUO ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_DYNO.asm b/Source/HBIOS/cfg_DYNO.asm new file mode 100644 index 00000000..29e533c7 --- /dev/null +++ b/Source/HBIOS/cfg_DYNO.asm @@ -0,0 +1,361 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: DYNO +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Dyno", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +RTCIO .SET $0C ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET TRUE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_DYNO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $4C ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_EPITX.asm b/Source/HBIOS/cfg_EPITX.asm new file mode 100644 index 00000000..f9ba6fb3 --- /dev/null +++ b/Source/HBIOS/cfg_EPITX.asm @@ -0,0 +1,387 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: EPITX +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "MiniITX" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +; +Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +RTCIO .SET $0C ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +; TODO - ADD PS/2 BITBANGER +VDAEMU_SERKBD .SET $00 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 2 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $A0 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $A8 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_EPFDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $40 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 2 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_FZ80.asm b/Source/HBIOS/cfg_FZ80.asm new file mode 100644 index 00000000..1b5d2bf5 --- /dev/null +++ b/Source/HBIOS/cfg_FZ80.asm @@ -0,0 +1,396 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: FZ80 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "S100 FPGA Z80", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_FZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 0 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6E ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $FF ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET TRUE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET TRUE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $34 ; SSER: STATUS PORT +SSERDATA .SET $35 ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET TRUE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET TRUE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET TRUE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET FALSE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $30 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_FZ80 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_S100 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $C7 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_GMZ180.asm b/Source/HBIOS/cfg_GMZ180.asm new file mode 100644 index 00000000..fbee4244 --- /dev/null +++ b/Source/HBIOS/cfg_GMZ180.asm @@ -0,0 +1,393 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: GMZ180 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "GM STD BUS Z180", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_GMZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +RTCIO .SET $84 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET TRUE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +GM7303BASE .SET $30 ; BASE ADDRESS FOR GM3703 BOARD +GM7303DSKACT .SET TRUE ; ENABLE DISK ACTIVITY OF GM7303 LCD DISPLAY +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET TRUE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_GIDE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_GM ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_HEATH.asm b/Source/HBIOS/cfg_HEATH.asm new file mode 100644 index 00000000..0bc354ed --- /dev/null +++ b/Source/HBIOS/cfg_HEATH.asm @@ -0,0 +1,386 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: HEATH +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "HEATHKIT", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 16384000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6E ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET TRUE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $E8 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $E0 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $D8 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $D0 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE]] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_MSX ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_MASTER.asm similarity index 75% rename from Source/HBIOS/cfg_master.asm rename to Source/HBIOS/cfg_MASTER.asm index 7632256f..f5a89051 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_MASTER.asm @@ -1,34 +1,68 @@ ; ;================================================================================================== -; ROMWBW 3.X CONFIGURATION MASTER +; ROMWBW GLOBAL MASTER CONFIGURATION FILE ;================================================================================================== ; -; THIS FILE IS *NOT* A REAL CONFIGURATION FILE. IT IS A MASTER TEMPLATE FILE -; CONTAINING ALL POSSIBLE CONFIGURATION SETTINGS ACROSS ALL PLATFORMS. IT IS -; USED ONLY AS A REFERENCE TO HELP MANAGE THE FULL SET OF POSSIBLE SETTINGS AND -; KEEP THINGS CONSISTENT. +; THIS FILE IS THE GLOBAL MASTER CONFIGURATION FILE FOR THE ROMWBW +; BUILD PROCESS. IT DEFINES ALL POSSIBLE CONFIGURATION SETTINGS +; AVAILABLE WITHIN ROMWBW. MANY SETTINGS WILL NOT BE APPLICABLE TO +; ALL OF THE DIFFERENT ROMWBW PLATFORMS. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; EACH FILE BELOW THIS TOP MASTER CONFIGURATION FILE INHERITS THE +; CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY OVERRIDE THESE +; SETTINGS AS DESIRED. +; +; OTHER THAN THIS TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE. THE TOP TWO FILES SHOULD NOT BE MODIFIED. TO CUSTOMIZE YOUR +; BUILD SETTINGS, YOU SHOULD MODIFY THE DEFAULT BUILD SETTINGS +; (Config/_std.asm) OR PREFERABLY CREATE AN OPTIONAL CUSTOM +; USER SETTINGS FILE THAT INCLUDES THE DEFAULT BUILD SETTINGS FILE (SEE +; EXAMPLE Config/SBC_custom.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** NOTE: THIS FILE USES ".EQU" TO DEFINE ALL SETTINGS. ALL OTHER +; CONFIGURATION FILES BELOW THIS FILE MUST USE ".SET" TO OVERRIDE +; SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT TO USE ".EQU" +; TO REDEFINE A PREVIOUS DEFINITION. ; #DEFINE PLATFORM_NAME "RomWBW", " [", CONFIG, "]" ; #INCLUDE "hbios.inc" ; -PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +PLATFORM .EQU PLT_NONE ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .EQU CPU_NONE ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] +BIOS .EQU BIOS_NONE ; HARDWARE BIOS: BIOS_[WBW|UNA] BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION +USELZSA2 .EQU FALSE ; ENABLE FONT COMPRESSION TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) ; BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +AUTOCON .EQU FALSE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT ; CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ +CPUOSC .EQU 1000000 ; CPU OSC FREQ IN MHZ INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +DEFSERCFG .EQU SER_9600_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) ; RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) @@ -101,7 +135,7 @@ WDOGIO .EQU $6F ; WATCHDOG REGISTER ADR FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED @@ -111,16 +145,22 @@ DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +LEDDISKIO .EQU FALSE ; ENABLES DISK I/O ACTIVITY ON STATUS LED ; DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +DSKYDSKACT .EQU FALSE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .EQU FALSE ; ENABLE LCD DISPLAY +LCDBASE .EQU $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .EQU FALSE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .EQU FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +GM7303BASE .EQU $30 ; BASE ADDRESS FOR GM3703 BOARD +GM7303DSKACT .EQU FALSE ; ENABLE DISK ACTIVITY OF GM7303 LCD DISPLAY ; BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE @@ -132,11 +172,10 @@ PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 8255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] ; DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] +DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) ; DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) @@ -153,7 +192,18 @@ HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] +; +DS5RTCENABLE .EQU FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .EQU FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .EQU SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .EQU $FF ; SSER: STATUS PORT +SSERDATA .EQU $FF ; SSER: DATA PORT +SSERIRDY .EQU %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .EQU FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .EQU %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .EQU FALSE ; SSER: OUTPUT READY BIT INVERTED ; DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) @@ -165,18 +215,27 @@ DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG ; UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .EQU 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART +UART4UART .EQU FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .EQU $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .EQU $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .EQU DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .EQU $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .EQU DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .EQU $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .EQU DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .EQU $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .EQU DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .EQU $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .EQU DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .EQU $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .EQU DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .EQU $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .EQU DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .EQU $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .EQU DEFSERCFG ; UART 7: SERIAL LINE CONFIG ; ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 @@ -237,13 +296,15 @@ GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) GDCMODE .EQU GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH] GDCMON .EQU GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA] TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] +TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .EQU FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .EQU FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) ; MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) MDROM .EQU TRUE ; MD: ENABLE ROM DISK @@ -265,19 +326,19 @@ RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_NONE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE0MODE .EQU IDEMODE_NONE ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] +IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O @@ -298,7 +359,7 @@ PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER ; SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] +SDMODE .EQU SDMODE_NONE ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) @@ -311,25 +372,25 @@ CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK +CH0USBENABLE .EQU FALSE ; CH 0: ENABLE USB DISK CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK +CH1USBENABLE .EQU FALSE ; CH 1: ENABLE USB DISK CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK ; PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +PRPCONENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT ; PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS -PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT +PPPSDENABLE .EQU FALSE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT +PPPCONENABLE .EQU FALSE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT ; ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -ESPCONENABLE .EQU TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT +ESPCONENABLE .EQU FALSE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT ; HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) @@ -349,21 +410,21 @@ LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPAMODE .EQU PPAMODE_NONE ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA ; IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMMMODE .EQU IMMMODE_NONE ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM ; SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQMODE .EQU IMMMODE_NONE ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ ; @@ -381,7 +442,7 @@ SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] +SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] ; AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD diff --git a/Source/HBIOS/cfg_MBC.asm b/Source/HBIOS/cfg_MBC.asm new file mode 100644 index 00000000..83fefef7 --- /dev/null +++ b/Source/HBIOS/cfg_MBC.asm @@ -0,0 +1,367 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MBC +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_HILO ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPCL_RAM .SET $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) +MPCL_ROM .SET $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) +; +RTCIO .SET $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET (4915200/8) ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 3 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $80 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $88 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .SET TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +CVDUMODE .SET CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] +CVDUMON .SET CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MBC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_MBC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +ESPCONENABLE .SET TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +; +PIOENABLE .SET TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $E8 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $EC ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .SET $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_MK4.asm b/Source/HBIOS/cfg_MK4.asm new file mode 100644 index 00000000..8f51dcaa --- /dev/null +++ b/Source/HBIOS/cfg_MK4.asm @@ -0,0 +1,364 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MK4 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Mark IV", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +; +Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +MK4_IDE .SET $80 ; MK4: IDE REGISTERS BASE ADR +MK4_XAR .SET $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR +MK4_SD .SET $89 ; MK4: SD CARD CONTROL REGISTER ADR +MK4_RTC .SET $8A ; MK4: RTC LATCH REGISTER ADR +; +RTCIO .SET MK4_RTC ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 6 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET TRUE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $18 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $80 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $C0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $C8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $D0 ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $D8 ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] +CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_DIDE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .SET TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_MK4 ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $80 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_DIDE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $20 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $28 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $28 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET FALSE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET FALSE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_DIDE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $30 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $38 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $38 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET FALSE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET FALSE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $14 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS +PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT +PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $E8 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $EC ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .SET $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_MON.asm b/Source/HBIOS/cfg_MON.asm new file mode 100644 index 00000000..885fcf07 --- /dev/null +++ b/Source/HBIOS/cfg_MON.asm @@ -0,0 +1,391 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: MON +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 4000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_MON ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6E ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_N8.asm b/Source/HBIOS/cfg_N8.asm new file mode 100644 index 00000000..ae3b6df9 --- /dev/null +++ b/Source/HBIOS/cfg_N8.asm @@ -0,0 +1,357 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: N8 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RetroBrew N8", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +; +Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +N8_PPI0 .SET $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR +N8_PPI1 .SET $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR +N8_RTC .SET $88 ; N8: RTC LATCH REGISTER ADR +N8_ACR .SET $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR +N8_RMAP .SET $96 ; N8: ROM PAGE REGISTER ADR +N8_DEFACR .SET $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) +; +RTCIO .SET N8_RTC ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET N8_PPI0 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET N8_PPI0 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 5 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET TRUE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $C0 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $C8 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $D0 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $D8 ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] +CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET N8_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET N8_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .SET $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_NABU.asm b/Source/HBIOS/cfg_NABU.asm new file mode 100644 index 00000000..01174339 --- /dev/null +++ b/Source/HBIOS/cfg_NABU.asm @@ -0,0 +1,396 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: NABU +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "NABU Personal Computer", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 3580000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6E ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_NABU ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $00 ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $48 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_NABU ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET TRUE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET TRUE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_NABU ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm new file mode 100644 index 00000000..b90567fb --- /dev/null +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -0,0 +1,391 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ180 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +RTCIO .SET $0C ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY +LCDBASE .SET $AA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm new file mode 100644 index 00000000..e9e6e629 --- /dev/null +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -0,0 +1,401 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ280 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 24000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +Z280_MEMLOWAIT .SET 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) +Z280_MEMHIWAIT .SET 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) +Z280_IOWAIT .SET 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z280_INTWAIT .SET 0 ; Z280: INT ACK WAIT STATUS (0-3) +Z280_TIMER .SET TRUE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +Z2UOSC .SET 1843200 ; Z2U: OSC FREQUENCY IN MHZ +Z2UOSCEXT .SET TRUE ; Z2U: USE EXTERNAL OSCILLATOR +Z2U0BASE .SET $10 ; Z2U 0: BASE I/O ADDRESS +Z2U0CFG .SET DEFSERCFG ; Z2U 0: SERIAL LINE CONFIG +Z2U0HFC .SET FALSE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL +; +ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET 7372800 ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET 7372800 ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z280 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_RCZ80.asm b/Source/HBIOS/cfg_RCZ80.asm new file mode 100644 index 00000000..56279490 --- /dev/null +++ b/Source/HBIOS/cfg_RCZ80.asm @@ -0,0 +1,396 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RCZ80 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ +INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6E ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_RPH.asm b/Source/HBIOS/cfg_RPH.asm new file mode 100644 index 00000000..41021e1b --- /dev/null +++ b/Source/HBIOS/cfg_RPH.asm @@ -0,0 +1,345 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: RPH +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Rhyophyre", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET TRUE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_RPH ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +; +Z180_BASE .SET $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +RPH_PPI0 .SET $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR +RPH_RTC .SET $84 ; RPH: RTC LATCH REGISTER ADR +RPH_ACR .SET $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR +RPH_DEFACR .SET $20 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) +; +RTCIO .SET RPH_RTC ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET RPH_PPI0 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET RPH_PPI0 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] +CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] +GDCENABLE .SET TRUE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +GDCMODE .SET GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH] +GDCMON .SET GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA] +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET RPH_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .SET $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_S100.asm b/Source/HBIOS/cfg_S100.asm new file mode 100644 index 00000000..fbffdab6 --- /dev/null +++ b/Source/HBIOS/cfg_S100.asm @@ -0,0 +1,381 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: S100 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_57600_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 1 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 2 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +RTCIO .SET $0C ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET TRUE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_SBC.asm b/Source/HBIOS/cfg_SBC.asm new file mode 100644 index 00000000..fc569260 --- /dev/null +++ b/Source/HBIOS/cfg_SBC.asm @@ -0,0 +1,346 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: SBC +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "RetroBrew SBC", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPCL_RAM .SET $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) +MPCL_ROM .SET $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) +; +RTCIO .SET $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $B0 ; CTC BASE I/O ADDRESS +CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET 614400 ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 7 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET TRUE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $80 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $18 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $C0 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $C8 ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $D0 ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $D8 ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $B0 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +VDUSIZ .SET V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +CVDUMODE .SET CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] +CVDUMON .SET CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VGASIZ .SET V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +RFCNT .SET 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $20 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET FALSE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET FALSE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $20 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $14 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +HDSKTRACE .SET 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO4BASE .SET $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIOZBASE .SET $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +UFBASE .SET $0C ; UF: REGISTERS BASE ADR +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_SCZ180.asm b/Source/HBIOS/cfg_SCZ180.asm new file mode 100644 index 00000000..38416754 --- /dev/null +++ b/Source/HBIOS/cfg_SCZ180.asm @@ -0,0 +1,391 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: SCZ180 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Small Computer", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +RAMBIAS .SET ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +Z180_BASE .SET $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS +Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 +Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) +Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) +Z180_TIMER .SET TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER +; +RTCIO .SET $0C ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET TRUE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET TRUE ; ENABLE LCD DISPLAY +LCDBASE .SET $AA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +ASCIINTS .SET TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +ASCISWAP .SET FALSE ; ASCI: SWAP CHANNELS +ASCIBOOT .SET 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) +ASCI0CFG .SET DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG +ASCI1CFG .SET DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $00 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $00 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET TRUE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +PRPSDENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT +PRPSDTRACE .SET 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PRPCONENABLE .SET TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $18 ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_una.asm b/Source/HBIOS/cfg_UNA.asm similarity index 92% rename from Source/HBIOS/cfg_una.asm rename to Source/HBIOS/cfg_UNA.asm index 94fb6e51..4fe90615 100644 --- a/Source/HBIOS/cfg_una.asm +++ b/Source/HBIOS/cfg_UNA.asm @@ -15,7 +15,7 @@ ; #INCLUDE "../UBIOS/ubios.inc" ; -;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] +;PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA] ; diff --git a/Source/HBIOS/cfg_Z80RETRO.asm b/Source/HBIOS/cfg_Z80RETRO.asm new file mode 100644 index 00000000..b2640ee3 --- /dev/null +++ b/Source/HBIOS/cfg_Z80RETRO.asm @@ -0,0 +1,312 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: Z80RETRO +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 14745600 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $60 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $61 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $62 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $63 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $64 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $40 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now) +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 0 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 1 ; TIMER CHANNEL (0-3) +CTCOSC .SET 7372800 ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $00 ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $FF ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_Z80R ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC/2 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC/2 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_Z80R ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC/2 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC/2 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS +PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT +PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_ZETA.asm b/Source/HBIOS/cfg_ZETA.asm new file mode 100644 index 00000000..e832496a --- /dev/null +++ b/Source/HBIOS/cfg_ZETA.asm @@ -0,0 +1,282 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Zeta", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPCL_RAM .SET $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) +MPCL_ROM .SET $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) +; +RTCIO .SET $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS +PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT +PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_ZETA2.asm b/Source/HBIOS/cfg_ZETA2.asm new file mode 100644 index 00000000..caaa9bbe --- /dev/null +++ b/Source/HBIOS/cfg_ZETA2.asm @@ -0,0 +1,293 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: ZETA2 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "Zeta 2", " [", CONFIG, "]" +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 8000000 ; CPU OSC FREQ IN MHZ +INTMODE .SET 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +DEFSERCFG .SET SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $70 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET TRUE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $20 ; CTC BASE I/O ADDRESS +CTCTIMER .SET TRUE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 0 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 1 ; TIMER CHANNEL (0-3) +CTCOSC .SET 921600 ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET RTCIO ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +LCDDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON LCD DISPLAY +GM7303ENABLE .SET FALSE ; ENABLES THE PROLOG 7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; +UARTENABLE .SET TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 1 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $68 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $FF ; UART 1: REGISTERS BASE ADR +UART1CFG .SET SER_300_8N1 ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $FF ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $FF ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $60 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +PPPBASE .SET $60 ; PPP: PPI REGISTERS BASE ADDRESS +PPPSDENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT +PPPSDTRACE .SET 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPPCONENABLE .SET TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +; +PPAENABLE .SET FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) +; +IMMENABLE .SET FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) +; +SYQENABLE .SET FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +PIOSBASE .SET $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_duo.asm b/Source/HBIOS/cfg_duo.asm deleted file mode 100644 index 9d4cfe8d..00000000 --- a/Source/HBIOS/cfg_duo.asm +++ /dev/null @@ -1,326 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR DUODYNE -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Duodyne", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_DUO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU FALSE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_UNSUP ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPGSEL_0 .EQU $50 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $51 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $52 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $53 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $54 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -RTCIO .EQU $94 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $60 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) -CTCOSC .EQU (7372800/8) ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $56 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $42 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $42 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU TRUE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $88 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU TRUE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $88 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 7372800 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU TRUE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $60 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU (7372800/4) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU 0 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU (7372800/4) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU 1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -CVDUMODE .EQU CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] -CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_DUO ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -; -FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_DUO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $88 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU TRUE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 1 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $4E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU TRUE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $FF ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU FALSE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -ESPCONENABLE .EQU TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -; -PIOENABLE .EQU TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $68 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $6C ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU TRUE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $48 ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -UFBASE .EQU $0C ; UF: REGISTERS BASE ADR -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_DUO ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] -; -AY38910ENABLE .EQU TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_DUO ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU TRUE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $40 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_DUO ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm deleted file mode 100644 index 912d9200..00000000 --- a/Source/HBIOS/cfg_dyno.asm +++ /dev/null @@ -1,305 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR DYNO -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Dyno", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -RTCIO .EQU $0C ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU TRUE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_DYNO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $4C ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_NONE ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_epitx.asm b/Source/HBIOS/cfg_epitx.asm deleted file mode 100644 index 00cf849f..00000000 --- a/Source/HBIOS/cfg_epitx.asm +++ /dev/null @@ -1,337 +0,0 @@ -; -;================================================================================================== -; ROMWBW 2.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.) -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "MiniITX" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_EPITX ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -; -Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -RTCIO .EQU $0C ; RTC LATCH REGISTER ADR - TODO -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPENABLE .EQU FALSE ; ENABLES FRONT PANEL SWITCHES -FPBASE .EQU $00 ; FRONT PANEL I/O PORT BASE ADDRESS -DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT -DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS -DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -; TODO - ADD PS/2 BITBANGER -VDAEMU_SERKBD .EQU $00 ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_EPFDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_EPITX ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|EPITX] -SDPPIBASE .EQU $40 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY -SDTRACE .EQU 2 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_heath.asm b/Source/HBIOS/cfg_heath.asm deleted file mode 100644 index 218bd52b..00000000 --- a/Source/HBIOS/cfg_heath.asm +++ /dev/null @@ -1,330 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80 -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_HEATH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) -CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT -ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) -ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR -ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ -ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER -ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) -ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR -ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ -ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER -ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_mbc.asm b/Source/HBIOS/cfg_mbc.asm deleted file mode 100644 index 81d37064..00000000 --- a/Source/HBIOS/cfg_mbc.asm +++ /dev/null @@ -1,313 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR MBC -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Nhyodyne", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_MBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_HILO ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_LOW ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_MBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) -MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) -; -RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) -CTCOSC .EQU (4915200/8) ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU TRUE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU TRUE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] -CVDUENABLE .EQU TRUE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -CVDUMODE .EQU CVDUMODE_MBC ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] -CVDUMON .EQU CVDUMON_CGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MBC ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_MBC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -ESPCONENABLE .EQU TRUE ; ESP: ENABLE ESP32 CONSOLE IO DRIVER VIDEO/KBD SUPPORT -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -; -PIOENABLE .EQU TRUE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_SPP ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $E8 ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_SPP ; PPA: DRIVER MODE: PPAMODE_[NONE|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_SPP ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_SPP ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -UFBASE .EQU $0C ; UF: REGISTERS BASE ADR -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_MBC ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU TRUE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_MBC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm deleted file mode 100644 index 275ef074..00000000 --- a/Source/HBIOS/cfg_mk4.asm +++ /dev/null @@ -1,309 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION FOR MARK IV -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Mark IV", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -; -Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -MK4_IDE .EQU $80 ; MK4: IDE REGISTERS BASE ADR -MK4_XAR .EQU $88 ; MK4: EXTERNAL ADDRESS REGISTER (XAR) ADR -MK4_SD .EQU $89 ; MK4: SD CARD CONTROL REGISTER ADR -MK4_RTC .EQU $8A ; MK4: RTC LATCH REGISTER ADR -; -RTCIO .EQU MK4_RTC ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] -CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_DIDE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) -; -IDEENABLE .EQU TRUE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_MK4 ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $80 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_DIDE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $20 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $28 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $28 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU FALSE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU FALSE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_DIDE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $30 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $38 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $38 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU FALSE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU FALSE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 2 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $14 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MK4 ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU TRUE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS -PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT -PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_NONE ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $E8 ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $EC ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -UFBASE .EQU $0C ; UF: REGISTERS BASE ADR -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_mon.asm b/Source/HBIOS/cfg_mon.asm deleted file mode 100644 index 5cc7f56f..00000000 --- a/Source/HBIOS/cfg_mon.asm +++ /dev/null @@ -1,335 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR MONSPUTER Z80 -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Monsputer", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_MON ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 4000000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_MON ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -; -RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) -CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT -ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) -ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR -ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ -ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER -ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) -ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR -ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ -ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER -ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm deleted file mode 100644 index 7590884b..00000000 --- a/Source/HBIOS/cfg_n8.asm +++ /dev/null @@ -1,302 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION FOR N8 -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "RetroBrew N8", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_N8 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -; -Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -N8_PPI0 .EQU $80 ; N8: FIRST PARALLEL PORT REGISTERS BASE ADR -N8_PPI1 .EQU $84 ; N8: SECOND PARALLEL PORT REGISTERS BASE ADR -N8_RTC .EQU $88 ; N8: RTC LATCH REGISTER ADR -N8_ACR .EQU $94 ; N8: AUXILLARY CONTROL REGISTER (ACR) ADR -N8_RMAP .EQU $96 ; N8: ROM PAGE REGISTER ADR -N8_DEFACR .EQU $1B ; N8: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) -; -RTCIO .EQU N8_RTC ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU N8_PPI0 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU N8_PPI0 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] -CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU N8_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU N8_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU N8_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_nabu.asm b/Source/HBIOS/cfg_nabu.asm deleted file mode 100644 index 9bb6c4f1..00000000 --- a/Source/HBIOS/cfg_nabu.asm +++ /dev/null @@ -1,340 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR NABU Z80 W/ OPTION BOARD -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "NABU Personal Computer", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_NABU ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 3580000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) -CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU FALSE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU TRUE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_NABU ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $00 ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU TRUE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT -ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) -ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR -ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ -ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER -ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) -ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR -ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ -ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER -ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU TRUE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_NABU80 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU TRUE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU TRUE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_NABU ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm deleted file mode 100644 index f5ae9229..00000000 --- a/Source/HBIOS/cfg_rcz180.asm +++ /dev/null @@ -1,341 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z180 CPU -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -RTCIO .EQU $0C ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPENABLE .EQU FALSE ; ENABLES FRONT PANEL SWITCHES -FPBASE .EQU $00 ; FRONT PANEL I/O PORT BASE ADDRESS -DIAGENABLE .EQU TRUE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT -DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS -DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm deleted file mode 100644 index 9e3af1dc..00000000 --- a/Source/HBIOS/cfg_rcz280.asm +++ /dev/null @@ -1,345 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z280 CPU -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_RCZ280 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z280 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 24000000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -Z280_MEMLOWAIT .EQU 0 ; Z280: LOW 8MB MEMORY WAIT STATES (0-3) -Z280_MEMHIWAIT .EQU 0 ; Z280: HIGH 8MB MEMORY WAIT STATES (0-3) -Z280_IOWAIT .EQU 1 ; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z280_INTWAIT .EQU 0 ; Z280: INT ACK WAIT STATUS (0-3) -Z280_TIMER .EQU TRUE ; Z280: ENABLE INTERNAL Z280 SYSTEM PERIODIC TIMER -; -RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -Z2UOSC .EQU 1843200 ; Z2U: OSC FREQUENCY IN MHZ -Z2UOSCEXT .EQU TRUE ; Z2U: USE EXTERNAL OSCILLATOR -Z2U0BASE .EQU $10 ; Z2U 0: BASE I/O ADDRESS -Z2U0CFG .EQU DEFSERCFG ; Z2U 0: SERIAL LINE CONFIG -Z2U0HFC .EQU FALSE ; Z2U 0: ENABLE HARDWARE FLOW CONTROL -; -ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT -ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) -ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR -ACIA0CLK .EQU 7372800 ; ACIA 0: OSC FREQ IN HZ -ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER -ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) -ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR -ACIA1CLK .EQU 7372800 ; ACIA 1: OSC FREQ IN HZ -ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER -ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z280 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm deleted file mode 100644 index c3eb0c93..00000000 --- a/Source/HBIOS/cfg_rcz80.asm +++ /dev/null @@ -1,340 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR RCBUS Z80 -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "RCBus", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 7372800 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -RTCIO .EQU $C0 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) -CTCOSC .EQU CPUOSC ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -SKZDIV .EQU DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -WDOGIO .EQU $6E ; WATCHDOG REGISTER ADR -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU TRUE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -ACIADEBUG .EQU FALSE ; ACIA: ENABLE DEBUG OUTPUT -ACIACNT .EQU 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) -ACIA0BASE .EQU $80 ; ACIA 0: REGISTERS BASE ADR -ACIA0CLK .EQU CPUOSC ; ACIA 0: OSC FREQ IN HZ -ACIA0DIV .EQU 1 ; ACIA 0: SERIAL CLOCK DIVIDER -ACIA0CFG .EQU DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) -ACIA1BASE .EQU $40 ; ACIA 1: REGISTERS BASE ADR -ACIA1CLK .EQU CPUOSC ; ACIA 1: OSC FREQ IN HZ -ACIA1DIV .EQU 1 ; ACIA 1: SERIAL CLOCK DIVIDER -ACIA1CFG .EQU DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_MT ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 1 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $88 ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU FALSE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $0C ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_rph.asm b/Source/HBIOS/cfg_rph.asm deleted file mode 100644 index b866b733..00000000 --- a/Source/HBIOS/cfg_rph.asm +++ /dev/null @@ -1,290 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION FOR RHYOPHYRE -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Rhyophyre", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_RPH ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU TRUE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_RPH ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU 0 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -; -Z180_BASE .EQU $40 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -RPH_PPI0 .EQU $88 ; RPH: FIRST PARALLEL PORT REGISTERS BASE ADR -RPH_RTC .EQU $84 ; RPH: RTC LATCH REGISTER ADR -RPH_ACR .EQU $80 ; RPH: AUXILLARY CONTROL REGISTER (ACR) ADR -RPH_DEFACR .EQU $20 ; RPH: AUX CTL REGISTER DEFAULT VALUE (QUIESCIENT STATE) -; -RTCIO .EQU RPH_RTC ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU RPH_PPI0 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] -CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] -GDCENABLE .EQU TRUE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -GDCMODE .EQU GDCMODE_RPH ; GDC: GDC MODE: GDCMODE_[NONE|ECB|RPH] -GDCMON .EQU GDCMON_EGA ; GDC: GDC MONITOR SETUP: GDCMON_[NONE|CGA|EGA] -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_N8 ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU RPH_PPI0 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_CSIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU RPH_PPI0 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU FALSE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU RPH_PPI0 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -FIFO_BASE .EQU $0C ; UF: REGISTERS BASE ADR -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_NONE ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_N8 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_s100.asm b/Source/HBIOS/cfg_s100.asm deleted file mode 100644 index 101d36d4..00000000 --- a/Source/HBIOS/cfg_s100.asm +++ /dev/null @@ -1,325 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR S100 Z180 -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "S100", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_S100 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_57600_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 1 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 2 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -RTCIO .EQU $0C ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU TRUE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm deleted file mode 100644 index b7d860c3..00000000 --- a/Source/HBIOS/cfg_sbc.asm +++ /dev/null @@ -1,291 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SBC -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "RetroBrew SBC", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) -MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) -; -RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $B0 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 2 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 3 ; TIMER CHANNEL (0-3) -CTCOSC .EQU 614400 ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU TRUE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU TRUE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU TRUE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_ZP ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $B0 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU (4915200/8) ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU (4915200/8) ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -VDUSIZ .EQU V80X25 ; VDU: DISPLAY FORMAT [V80X24|V80X25|V80X30] -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -CVDUMODE .EQU CVDUMODE_ECB ; CVDU: CVDU MODE: CVDUMODE_[NONE|ECB|MBC] -CVDUMON .EQU CVDUMON_EGA ; CVDU: CVDU MONITOR SETUP: CVDUMON_[NONE|CGA|EGA] -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_SCG ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VGASIZ .EQU V80X25 ; VGA: DISPLAY FORMAT [V80X25|V80X30|V80X43] -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -RFCNT .EQU 1 ; RF: NUMBER OF RAM FLOPPY UNITS (1-4) -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_DIO ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $20 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $20 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $28 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU FALSE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU FALSE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $20 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $14 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_JUHA ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -HDSKTRACE .EQU 1 ; HDSK: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO4BASE .EQU $90 ; PIO: PIO REGISTERS BASE ADR FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIOZBASE .EQU $88 ; PIO: PIO REGISTERS BASE ADR FOR ECB ZP BOARD -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -UFBASE .EQU $0C ; UF: REGISTERS BASE ADR -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_VGM ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_SCG ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_ECB ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm deleted file mode 100644 index 0a3919a9..00000000 --- a/Source/HBIOS/cfg_scz180.asm +++ /dev/null @@ -1,335 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SC Z180 VARIANTS (SC126, SC130, ETC.) -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Small Computer", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -RAMBIAS .EQU ROMSIZE ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS -Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 -Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) -Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) -Z180_TIMER .EQU TRUE ; Z180: ENABLE Z180 SYSTEM PERIODIC TIMER -; -RTCIO .EQU $0C ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $88 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU TRUE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) -LEDMODE .EQU LEDMODE_SC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKTRACE .EQU 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -KBDTRACE .EQU 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPKKBLOUT .EQU KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] -KBDKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -MKYKBLOUT .EQU KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -DUARTCNT .EQU 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) -DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP -DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG -DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG -DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP -DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG -DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG | SER_RTS ; UART: LINE CONFIG FOR UART PORTS -UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU TRUE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -ASCIINTS .EQU TRUE ; ASCI: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -ASCISWAP .EQU FALSE ; ASCI: SWAP CHANNELS -ASCIBOOT .EQU 0 ; ASCI: REBOOT ON RCV CHAR (0=DISABLED) -ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG -ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU 7372800 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU SER_115200_8N1 ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU 7372800 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU SER_115200_8N1 ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU 7372800 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU SER_115200_8N1 ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU 7372800 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU SER_115200_8N1 ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IDECNT .EQU 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH -IDE0MODE .EQU IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE0BASE .EQU $10 ; IDE 0: IO BASE ADDRESS -IDE0DATLO .EQU $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O -IDE0DATHI .EQU $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O -IDE0A8BIT .EQU TRUE ; IDE 0A (MASTER): 8 BIT XFER -IDE0B8BIT .EQU TRUE ; IDE 0B (MASTER): 8 BIT XFER -IDE1MODE .EQU IDEMODE_NONE ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE1BASE .EQU $00 ; IDE 1: IO BASE ADDRESS -IDE1DATLO .EQU $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O -IDE1DATHI .EQU $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O -IDE1A8BIT .EQU TRUE ; IDE 1A (MASTER): 8 BIT XFER -IDE1B8BIT .EQU TRUE ; IDE 1B (MASTER): 8 BIT XFER -IDE2MODE .EQU IDEMODE_NONE ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC] -IDE2BASE .EQU $00 ; IDE 2: IO BASE ADDRESS -IDE2DATLO .EQU $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O -IDE2DATHI .EQU $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O -IDE2A8BIT .EQU TRUE ; IDE 2A (MASTER): 8 BIT XFER -IDE2B8BIT .EQU TRUE ; IDE 2B (MASTER): 8 BIT XFER -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $20 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE1BASE .EQU $00 ; PPIDE 1: PPI REGISTERS BASE ADR -PPIDE1A8BIT .EQU FALSE ; PPIDE 1A (MASTER): 8 BIT XFER -PPIDE1B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -PPIDE2BASE .EQU $00 ; PPIDE 2: PPI REGISTERS BASE ADR -PPIDE2A8BIT .EQU FALSE ; PPIDE 2A (MASTER): 8 BIT XFER -PPIDE2B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_SC ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU TRUE ; CH: ENABLE CH375/376 USB SUPPORT -CHTRACE .EQU 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHUSBTRACE .EQU 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHSDTRACE .EQU 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -CHCNT .EQU 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) -CH0BASE .EQU $3E ; CH 0: BASE I/O ADDRESS -CH0USBENABLE .EQU TRUE ; CH 0: ENABLE USB DISK -CH0SDENABLE .EQU FALSE ; CH 0: ENABLE SD DISK -CH1BASE .EQU $3C ; CH 1: BASE I/O ADDRESS -CH1USBENABLE .EQU TRUE ; CH 1: ENABLE USB DISK -CH1SDENABLE .EQU FALSE ; CH 1: ENABLE SD DISK -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -PRPSDENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER SD CARD SUPPORT -PRPSDTRACE .EQU 1 ; PRP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PRPCONENABLE .EQU TRUE ; PRP: ENABLE PROPIO DRIVER VIDEO/KBD SUPPORT -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -PIOCNT .EQU 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -PIO0BASE .EQU $B8 ; PIO 0: REGISTERS BASE ADR -PIO1BASE .EQU $BC ; PIO 1: REGISTERS BASE ADR -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -LPTMODE .EQU LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] -LPTCNT .EQU 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) -LPTTRACE .EQU 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -LPT0BASE .EQU $18 ; LPT 0: REGISTERS BASE ADR -LPT1BASE .EQU $00 ; LPT 1: REGISTERS BASE ADR -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -PPACNT .EQU 1 ; PPA: NUMBER OF PPA DEVICES (1-2) -PPATRACE .EQU 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPAMODE .EQU PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] -PPA0BASE .EQU LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA -PPA1BASE .EQU LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -IMMCNT .EQU 1 ; IMM: NUMBER OF IMM DEVICES (1-2) -IMMTRACE .EQU 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -IMMMODE .EQU IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] -IMM0BASE .EQU LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM -IMM1BASE .EQU LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -SYQCNT .EQU 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) -SYQTRACE .EQU 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SYQMODE .EQU IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] -SYQ0BASE .EQU LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ -SYQ1BASE .EQU LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN: ENABLE SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AUDIOTRACE .EQU FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER -SN7CLK .EQU 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD -SNMODE .EQU SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM] -; -AY38910ENABLE .EQU FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER -AY_CLK .EQU 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD -AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] -; -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_Z180 ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_z80retro.asm b/Source/HBIOS/cfg_z80retro.asm deleted file mode 100644 index 73b38f04..00000000 --- a/Source/HBIOS/cfg_z80retro.asm +++ /dev/null @@ -1,252 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR SIMPLE Z80 RETRO -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Z80Retro", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_Z80RETRO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 14745600 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPGSEL_0 .EQU $60 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $61 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $62 ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $63 ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $64 ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $40 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU FALSE ; ENABLE CTC PERIODIC TIMER (too fast for RomWBW right now) -CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 0 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 1 ; TIMER CHANNEL (0-3) -CTCOSC .EQU 7372800 ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU $00 ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -; -DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU TRUE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -SIODEBUG .EQU FALSE ; SIO: ENABLE DEBUG OUTPUT -SIOBOOT .EQU 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) -SIOCNT .EQU 1 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP -SIOINTS .EQU TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 -SIO0MODE .EQU SIOMODE_Z80R ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO0BASE .EQU $80 ; SIO 0: REGISTERS BASE ADR -SIO0ACLK .EQU CPUOSC/2 ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0ACFG .EQU DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG -SIO0ACTCC .EQU -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO0BCLK .EQU CPUOSC/2 ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO0BCFG .EQU DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG -SIO0BCTCC .EQU -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1MODE .EQU SIOMODE_Z80R ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] -SIO1BASE .EQU $84 ; SIO 1: REGISTERS BASE ADR -SIO1ACLK .EQU CPUOSC/2 ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1ACFG .EQU DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG -SIO1ACTCC .EQU -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -SIO1BCLK .EQU CPUOSC/2 ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 -SIO1BCFG .EQU DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG -SIO1BCTCC .EQU -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU TRUE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_Z80R ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS -PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT -PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm deleted file mode 100644 index e35ea484..00000000 --- a/Source/HBIOS/cfg_zeta.asm +++ /dev/null @@ -1,222 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V1 -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Zeta", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_SBC ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPCL_RAM .EQU $78 ; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY) -MPCL_ROM .EQU $7C ; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY) -; -RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_RTC ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS -PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT -PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm deleted file mode 100644 index 3a7bc05c..00000000 --- a/Source/HBIOS/cfg_zeta2.asm +++ /dev/null @@ -1,233 +0,0 @@ -; -;================================================================================================== -; ROMWBW 3.X CONFIGURATION DEFAULTS FOR ZETA V2 -;================================================================================================== -; -; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM -; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD -; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY -; UNDER THIS DIRECTORY. -; -; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS -; FOR THE PLATFORM. -; -#DEFINE PLATFORM_NAME "Zeta 2", " [", CONFIG, "]" -; -#INCLUDE "hbios.inc" -; -PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|RCEZ80|SCZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|MON] -CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] -BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] -BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE -HBIOS_MUTEX .EQU FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) -USELZSA2 .EQU TRUE ; ENABLE FONT COMPRESSION -TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) -; -BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE -BOOT_DELAY .EQU 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT -AUTOCON .EQU TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT -; -CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO -CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW -CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ -INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) -DEFSERCFG .EQU SER_38400_8N1 | SER_RTS ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) -; -RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) -ROMSIZE .EQU 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) -APP_BNKS .EQU $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) -MEMMGR .EQU MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON] -MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) -MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) -MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) -MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) -MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) -; -RTCIO .EQU $70 ; RTC LATCH REGISTER ADR -; -KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT -KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS -; -CTCENABLE .EQU TRUE ; ENABLE ZILOG CTC SUPPORT -CTCDEBUG .EQU FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT -CTCBASE .EQU $20 ; CTC BASE I/O ADDRESS -CTCTIMER .EQU TRUE ; ENABLE CTC PERIODIC TIMER -CTCMODE .EQU CTCMODE_CTR ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] -CTCPRE .EQU 256 ; PRESCALE CONSTANT (1-256) -CTCPRECH .EQU 0 ; PRESCALE CHANNEL (0-3) -CTCTIMCH .EQU 1 ; TIMER CHANNEL (0-3) -CTCOSC .EQU 921600 ; CTC CLOCK FREQUENCY -; -PCFENABLE .EQU FALSE ; ENABLE PCF8584 I2C CONTROLLER -PCFBASE .EQU $F0 ; PCF8584 BASE I/O ADDRESS -; -EIPCENABLE .EQU FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION -; -SKZENABLE .EQU FALSE ; ENABLE SERGEY'S Z80-512K FEATURES -; -WDOGMODE .EQU WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] -; -FPLED_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL LEDS -FPLED_IO .EQU $00 ; FP: PORT ADDRESS FOR FP LEDS -FPLED_INV .EQU FALSE ; FP: LED BITS ARE INVERTED -FPLED_DSKACT .EQU TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS -FPSW_ENABLE .EQU FALSE ; FP: ENABLES FRONT PANEL SWITCHES -FPSW_IO .EQU $00 ; FP: PORT ADDRESS FOR FP SWITCHES -FPSW_INV .EQU FALSE ; FP: SWITCH BITS ARE INVERTED -; -DIAGLVL .EQU DL_CRITICAL ; ERROR LEVEL REPORTING -; -LEDENABLE .EQU FALSE ; ENABLES STATUS LED -LEDMODE .EQU LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] -LEDPORT .EQU RTCIO ; STATUS LED PORT ADDRESS -LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED -; -DSKYENABLE .EQU FALSE ; ENABLES DSKY FUNCTIONALITY -DSKYDSKACT .EQU TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY -ICMENABLE .EQU FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) -ICMPPIBASE .EQU $60 ; BASE I/O ADDRESS OF ICM PPI -PKDENABLE .EQU FALSE ; ENABLES DSKY NG PKD DRIVER (8259) -PKDPPIBASE .EQU $60 ; BASE I/O ADDRESS OF PKD PPI -PKDOSC .EQU 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) -H8PENABLE .EQU FALSE ; ENABLES HEATH H8 FRONT PANEL -; -BOOTCON .EQU 0 ; BOOT CONSOLE DEVICE -SECCON .EQU $FF ; SECONDARY CONSOLE DEVICE -CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP -VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] -VDAEMU_SERKBD .EQU $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD -ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MKYENABLE .EQU FALSE ; MSX 5255 PPI KEYBOARD COMPATIBLE DRIVER (REQUIRES TMS VDA DRIVER) -; -DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) -DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC|K80W] -DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) -; -DS1501RTCENABLE .EQU FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) -DS1501RTC_BASE .EQU $50 ; DS1501RTC: I/O BASE ADDRESS -; -BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) -BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS -; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) -; -RP5RTCENABLE .EQU FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) -; -HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT -SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) -; -DS7RTCENABLE .EQU FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) -DS7RTCMODE .EQU DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTC_[PCF] -; -DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) -; -UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) -UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ -UARTINTS .EQU FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 -UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS -UARTCASSPD .EQU SER_300_8N1 ; UART: ECB CASSETTE UART DEFAULT SPEED -UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA/DUO/NABU ONBOARD UART -UARTSBCFORCE .EQU FALSE ; UART: FORCE DETECTION OF SBC UART (FOR SIMH) -UARTAUX .EQU FALSE ; UART: AUTO-DETECT AUX UART -UARTCAS .EQU FALSE ; UART: AUTO-DETECT ECB CASSETTE UART -UARTMFP .EQU FALSE ; UART: AUTO-DETECT MF/PIC UART -UART4 .EQU FALSE ; UART: AUTO-DETECT 4UART UART -UARTRC .EQU FALSE ; UART: AUTO-DETECT RC UART -UARTDUAL .EQU FALSE ; UART: AUTO-DETECT DUAL UART -; -ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) -; -Z2UENABLE .EQU FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) -; -ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) -; -SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) -; -XIOCFG .EQU DEFSERCFG ; XIO: SERIAL LINE CONFIG -; -VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) -CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) -GDCENABLE .EQU FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) -TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) -TMSMODE .EQU TMSMODE_NONE ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MBC|MSX|MSX9958|MSXKBD|COLECO|DUO|NABU40|NABU80] -TMSTIMENABLE .EQU FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) -VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) -VRCENABLE .EQU FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) -SCONENABLE .EQU FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) -EFENABLE .EQU FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) -; -MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) -MDROM .EQU TRUE ; MD: ENABLE ROM DISK -MDRAM .EQU TRUE ; MD: ENABLE RAM DISK -MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -MDFFENABLE .EQU FALSE ; MD: ENABLE FLASH FILE SYSTEM -; -FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) -FDMODE .EQU FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] -FDCNT .EQU 1 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) -FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) -FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS -FD0TYPE .EQU FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -FD1TYPE .EQU FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] -; -RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER -; -IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) -; -PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) -PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPIDECNT .EQU 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP -PPIDE0BASE .EQU $60 ; PPIDE 0: PPI REGISTERS BASE ADR -PPIDE0A8BIT .EQU FALSE ; PPIDE 0A (MASTER): 8 BIT XFER -PPIDE0B8BIT .EQU FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER -; -SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) -SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|PIO|Z80R|USR] -SDPPIBASE .EQU $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE -SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY -SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE -SDMTSWAP .EQU FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 -; -CHENABLE .EQU FALSE ; CH: ENABLE CH375/376 USB SUPPORT -; -PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) -; -PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) -PPPBASE .EQU $60 ; PPP: PPI REGISTERS BASE ADDRESS -PPPSDENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER SD CARD SUPPORT -PPPSDTRACE .EQU 1 ; PPP: SD CARD TRACE LEVEL (0=NO,1=ERRORS,2=ALL) -PPPCONENABLE .EQU TRUE ; PPP: ENABLE PPP DRIVER VIDEO/KBD SUPPORT -; -ESPENABLE .EQU FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) -; -HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) -; -PIOENABLE .EQU FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) -; -LPTENABLE .EQU FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) -; -PPAENABLE .EQU FALSE ; PPA: ENABLE PPA DISK DRIVER (PPA.ASM) -; -IMMENABLE .EQU FALSE ; IMM: ENABLE IMM DISK DRIVER (IMM.ASM) -; -SYQENABLE .EQU FALSE ; SYQ: ENABLE IMM DISK DRIVER (SYQ.ASM) -; -PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD -PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) -PIO_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP -PIOSBASE .EQU $60 ; PIO: PIO REGISTERS BASE ADR FOR SBC PPI -; -UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) -; -SN76489ENABLE .EQU FALSE ; SN76489 SOUND DRIVER -SN76489CHNOUT .EQU SNCHAN_BOTH ; SN: CHANNEL OUTPUTS: SNCHAN_[BOTH|LEFT|RIGHT] -AY38910ENABLE .EQU FALSE ; AY: AY-3-8910 / YM2149 SOUND DRIVER -SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) -; -DMAENABLE .EQU FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) -DMABASE .EQU $E0 ; DMA: DMA BASE ADDRESS -DMAMODE .EQU DMAMODE_NONE ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) -; -YM2612ENABLE .EQU FALSE ; YM2612: ENABLE YM2612 DRIVER (MUTE STUB) -VGMBASE .EQU $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/ds5rtc.asm b/Source/HBIOS/ds5rtc.asm new file mode 100644 index 00000000..1c67d55b --- /dev/null +++ b/Source/HBIOS/ds5rtc.asm @@ -0,0 +1,566 @@ +; +;================================================================================================== +; MAXIM DS1305 RTC DRIVER +;================================================================================================== +; +; THE DS1305 USES AN SPI INTERFACE. THIS DRIVER CURRENTLY ASSUMES THE +; FPGA-BASED SPI INTERFACE IMPLEMENTED IN THE S100 FPGA Z80. +; +; TRICKLE CHARGING IS NOT CURRENTLY IMPLEMENTED SINCE THE S100 FPGA Z80 +; DOES NOT SUPPORT THE USER OF A SUPER CAPACITOR. +; +; REGISTER ADDRESSES (HEX / BCD): +; +; +---+-----+---------------+-------------------+------------------+----------------+ +; |ADR| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | RANGE | REGISTER | +; +---+-----+---------------+-------------------+------------------+----------------+ +; | 0 | 0 | 10-SECOND | 1-SECOND | 00-59 | SECONDS | +; +---+-----+-----+---------+-------------------+------------------+----------------+ +; | 1 | 0 | 10-MINUTE | 1-MINUTE | 00-59 | MINUTES | +; +---+-----+-----+---------+-------------------+------------------+----------------+ +; | 2 | 0 | 0 | 10-HOUR | 1-HOUR | 00-23 | HOURS | +; +---+-----+-----+----+----+-------------------+------------------+----------------+ +; | 3 | 0 | 0 | 0 | 0 | DAY OF WEEK | 01-07 | DAY OF WEEK | +; +---+-----+-----+----+----+----+--------------+------------------+----------------+ +; | 4 | 0 | 0 | 10-DATE | 1-DATE | 01-31 | DATE | +; +---+-----+-----+----+----+-------------------+------------------+----------------+ +; | 5 | 0 | 0 |10-MONTH | 1-MONTH | 01-12 | MONTH | +; +---+-----+-----+----+----+-------------------+------------------+----------------+ +; | 6 | 10-YEAR | 1-YEAR | 00-99 | YEAR | +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; --- ALARM 0 --- +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; | 7 | M | 10-SECOND | 1-SECOND | 00-59 | SECONDS ALARM | +; +---+-----+---------------+-------------------+------------------+----------------+ +; | 8 | M | 10-MINUTE | 1-MINUTE | 00-59 | MINUTES ALARM | +; +---+-----+-----+---------+-------------------+------------------+----------------+ +; | 9 | M | 0 | 10-HOUR | 1-HOUR | 00-23 | HOURS ALARM | +; +---+-----+-----+----+----+-------------------+------------------+----------------+ +; | A | M | 0 | 0 | 0 | DAY | 1-7 | DAY ALARM | +; +---+-----+-----+----+----+----+--------------+------------------+----------------+ +; --- ALARM 1 --- +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; | B | M | 10-SECOND | 1-SECOND | 00-59 | SECONDS ALARM | +; +---+-----+---------------+-------------------+------------------+----------------+ +; | C | M | 10-MINUTE | 1-MINUTE | 00-59 | MINUTES ALARM | +; +---+-----+-----+---------+-------------------+------------------+----------------+ +; | D | M | 0 | 10-HOUR | 1-HOUR | 00-23 | HOURS ALARM | +; +---+-----+-----+----+----+-------------------+------------------+----------------+ +; | E | M | 0 | 0 | 0 | DAY | 1-7 | DAY ALARM | +; +---+-----+-----+----+----+----+--------------+------------------+----------------+ +; +; +---+-----+-----+---------+-------------------+------------------+----------------+ +; | F |/EOSC| WP | 0 | 0 | 0 |INTC|AIE1|AIE0| | CONTROL REG | +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; |10 | 0 | 0 | 0 | 0 | 0 | 0 |IRQ1|IRQ0| | STATUS REG | +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; |11 | TRICKLE CHG ENABLE | DIODE |RESISTOR | | TRICKLE CHG REG| +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; |12-1F | RESERVED | | | +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; |20-7F | USER NVRAM | 00-FF | | +; +---+-----+-----+----+----+----+----+----+----+------------------+----------------+ +; +; 0 = SHOULD BE SET TO 0 FOR VALID TIME/CALENDAR RANGE. +; CLOCK CALENDAR DATA IS BCD. AUTOMATIC LEAP YEAR ADJUSTMENT. +; DAY-OF-WEEK CODED AS SUNDAY = 1 THROUGH SATURDAY = 7. +; +; CONSTANTS +; +DS5RTC_BASE .EQU $68 +DS5RTC_DATA .EQU DS5RTC_BASE + 0 +DS5RTC_SELECT .EQU DS5RTC_BASE + 2 ; WRITE +DS5RTC_STATUS .EQU DS5RTC_BASE + 2 ; READ +DS5RTC_RUN .EQU DS5RTC_BASE + 3 ; START READ/WRITE USING IN/OUT OPCODE +; +; IO PORTS +; +DS5NVM_BASE .EQU DS5RTC_BASE + $20 + +DS5RTC_REG_SEC .EQU $00 +DS5RTC_REG_MIN .EQU $01 +DS5RTC_REG_HOUR .EQU $02 +DS5RTC_REG_WEEKDAY .EQU $03 +DS5RTC_REG_DATE .EQU $04 +DS5RTC_REG_MONTH .EQU $05 +DS5RTC_REG_YEAR .EQU $06 +DS5RTC_REG_ALM0_SEC .EQU $07 +DS5RTC_REG_ALM0_MIN .EQU $08 +DS5RTC_REG_ALM0_HOUR .EQU $09 +DS5RTC_REG_ALM0_DAY .EQU $0A +DS5RTC_REG_ALM1_SEC .EQU $0B +DS5RTC_REG_ALM1_MIN .EQU $0C +DS5RTC_REG_ALM1_HOUR .EQU $0D +DS5RTC_REG_ALM1_DAY .EQU $0E +DS5RTC_REG_CONTROL .EQU $0F +DS5RTC_REG_STATUS .EQU $10 +DS5RTC_REG_TCHG .EQU $11 +DS5RTC_REG_NVM_BASE .EQU $20 +; +; VALUES FOR DIFFERENT BATTERY OR SUPERCAPACITOR CHARGE RATES +; +DS5RTC_TC1D2K .EQU %10100101 ; 1 DIODE 2K RESISTOR (DEFAULT) +DS5RTC_TC1D4K .EQU %10100110 ; 1 DIODE 4K RESISTOR +DS5RTC_TC1D8K .EQU %10100111 ; 1 DOIDE 8K RESISTOR +DS5RTC_TC2D2K .EQU %10101001 ; 2 DIODES 2K RESISTOR +DS5RTC_TC2D4K .EQU %10101010 ; 2 DIODES 4K RESISTOR +DS5RTC_TC2D8K .EQU %10101011 ; 2 DIODES 8K RESISTOR +; +; +; +DS5RTC_BUFSIZE .EQU 6 ; 6 BYTE BUFFER (YYMMDDHHMMSS) +; + DEVECHO "DS5RTC: RTCIO=" + DEVECHO DS5RTC_BASE + DEVECHO ", IO=" + DEVECHO DS5RTC_BASE + DEVECHO "\n" +; +; RTC DEVICE INITIALIZATION ENTRY +; +DS5RTC_INIT: + LD A,(RTC_DISPACT) ; RTC DISPATCHER ALREADY SET? + OR A ; SET FLAGS + RET NZ ; IF ALREADY ACTIVE, ABORT +; + CALL NEWLINE ; FORMATTING + PRTS("DS5RTC: IO=0x$") + LD A, DS5RTC_BASE + CALL PRTHEXBYTE +; + CALL DS5RTC_DETECT ; HARDWARE DETECTION + JR Z,DS5RTC_INIT1 ; IF ZERO, ALL GOOD + PRTS(" NOT PRESENT$") ; NOT ZERO, H/W NOT PRESENT + OR $FF ; SIGNAL FAILURE + RET ; BAIL OUT +; +DS5RTC_INIT1: + ; DISPLAY CURRENT TIME + CALL PC_SPACE ; FORMATTING + LD HL,DS5RTC_BUF ; USE INTERNAL BUFFER + CALL DS5RTC_RDCLK ; GET RAW RTC DATE/TIME + LD HL,DS5RTC_TIMBUF ; POINT TO HBIOS TIME BUF + CALL DS5RTC_CLK2TIM ; CONVERT TO HBIOS FMT + LD HL,DS5RTC_TIMBUF ; POINT TO HBIOS TIME BUF + CALL PRTDT ; PRINT FORMATTED DATE/TIME +; + ; ADD OURSELVES TO RTC DISPATCHER + LD BC,DS5RTC_DISPATCH + CALL RTC_SETDISP +; + XOR A + RET +; +; RTC DEVICE FUNCTION DISPATCH ENTRY +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; B: FUNCTION (IN) +; +DS5RTC_DISPATCH: + LD A, B ; Get requested function + AND $0F ; Isolate Sub-Function + JP Z, DS5RTC_GETTIM ; Get Time + DEC A + JP Z, DS5RTC_SETTIM ; Set Time + DEC A + JP Z, DS5RTC_GETBYT ; Get NVRAM Byte Value + DEC A + JP Z, DS5RTC_SETBYT ; Set NVRAM Byte Value + DEC A + JP Z, DS5RTC_GETBLK ; Get NVRAM Data Block Value + DEC A + JP Z, DS5RTC_SETBLK ; Set NVRAM Data Block Value + DEC A + JP Z, DS5RTC_GETALM ; Get Alarm + DEC A + JP Z, DS5RTC_SETALM ; Set Alarm +; +; RTC GET TIME +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; HL: DATE/TIME BUFFER (OUT) +; BUFFER FORMAT IS BCD: YYMMDDHHMMSS +; 24 HOUR TIME FORMAT IS ASSUMED +; +DS5RTC_GETTIM: + PUSH HL ; SAVE ADR OF OUTPUT BUF +; + ; READ THE CLOCK + LD HL,DS5RTC_BUF ; POINT TO CLOCK BUFFER + CALL DS5RTC_RDCLK ; READ THE CLOCK + LD HL,DS5RTC_TIMBUF ; POINT TO TIME BUFFER + CALL DS5RTC_CLK2TIM ; CONVERT CLOCK TO TIME +; + ; NOW COPY TO REAL DESTINATION (INTERBANK SAFE) + LD A,BID_BIOS ; COPY FROM BIOS BANK + LD (HB_SRCBNK),A ; SET IT + LD A,(HB_INVBNK) ; COPY TO CURRENT USER BANK + LD (HB_DSTBNK),A ; SET IT + LD HL,DS5RTC_TIMBUF ; SOURCE ADR + POP DE ; DEST ADR + LD BC,6 ; LENGTH IS 6 BYTES +#IF (INTMODE == 1) + DI +#ENDIF + CALL HB_BNKCPY ; COPY THE CLOCK DATA +#IF (INTMODE == 1) + EI +#ENDIF +; + ; CLEAN UP AND RETURN + XOR A ; SIGNAL SUCCESS + RET ; AND RETURN +; +; RTC SET TIME +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; HL: DATE/TIME BUFFER (IN) +; BUFFER FORMAT IS BCD: YYMMDDHHMMSS +; 24 HOUR TIME FORMAT IS ASSUMED +; +DS5RTC_SETTIM: + ; COPY INCOMING TIME DATA TO OUR TIME BUFFER + LD A,(HB_INVBNK) ; COPY FROM CURRENT USER BANK + LD (HB_SRCBNK),A ; SET IT + LD A,BID_BIOS ; COPY TO BIOS BANK + LD (HB_DSTBNK),A ; SET IT + LD DE,DS5RTC_TIMBUF ; DEST ADR + LD BC,6 ; LENGTH IS 6 BYTES +#IF (INTMODE == 1) + DI +#ENDIF + CALL HB_BNKCPY ; COPY THE CLOCK DATA +#IF (INTMODE == 1) + EI +#ENDIF +; + ; WRITE TO CLOCK + LD HL,DS5RTC_TIMBUF ; POINT TO TIME BUFFER + CALL DS5RTC_TIM2CLK ; CONVERT TO CLOCK FORMAT + LD HL,DS5RTC_BUF ; POINT TO CLOCK BUFFER + CALL DS5RTC_WRCLK ; WRITE TO THE CLOCK +; + ; CLEAN UP AND RETURN + XOR A ; SIGNAL SUCCESS + RET ; AND RETURN +; +; RTC GET NVRAM BYTE +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; C: INDEX (IN) +; E: VALUE (OUT) +; +DS5RTC_GETBYT: + LD A,C ; INDEX TO A + ADD A,$20 ; NVRAM STARTS AT REG $20 + LD C,A ; BACK TO REG C + CALL DS5RTC_GET ; DO IT + LD E,A ; MOVE RESULT TO E + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +; RTC SET NVRAM BYTE +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; C: INDEX (IN) +; E: VALUE (IN) +; +DS5RTC_SETBYT: + LD A,C ; INDEX TO A + ADD A,$20 ; NVRAM STARTS AT REG $20 + LD C,A ; BACK TO REG C + CALL DS5RTC_WPOFF ; DISABLE WRITE PROTECT + CALL DS5RTC_PUT ; DO IT + CALL DS5RTC_WPOFF ; ENABLE WRITE PROTECT + LD E,A ; MOVE RESULT TO E + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +; RTC GET BLOCK +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; HL: BUFFER ADDRESS (IN) +; +DS5RTC_GETBLK: + SYSCHKERR(ERR_NOTIMPL) + RET +; +; RTC GET BLOCK +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR +; HL: BUFFER ADDRESS (IN) +; +DS5RTC_SETBLK: + SYSCHKERR(ERR_NOTIMPL) + RET +; +; RTC GET ALARM +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERROR +; HL: DATE/TIME BUFFER ADDRESS (IN) +; BUFFER FORMAT IS BCD: YYMMDDHHMMSS +; 24 HOUR TIME FORMAT IS ASSUMED +; +DS5RTC_GETALM: + SYSCHKERR(ERR_NOTIMPL) + RET +; +; RTC SET ALARM +; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERROR +; HL: DATE/TIME BUFFER ADDRESS (IN) +; BUFFER FORMAT IS BCD: YYMMDDHHMMSS +; 24 HOUR TIME FORMAT IS ASSUMED +; +DS5RTC_SETALM: + SYSCHKERR(ERR_NOTIMPL) + RET +; +;================================================================================================== +; INTERNAL PROCEDURES +;================================================================================================== +; +; TURN ON WRITE PROTECT +; +DS5RTC_WPON: + PUSH AF + PUSH BC + LD A,%01000000 ; CONTROL REGISTER W/P ON VALUE + LD C,DS5RTC_REG_CONTROL ; CONTROL REGISTER ADR + CALL DS5RTC_PUT ; SET CONTROL REGISTER + POP BC + POP AF + RET +; +; TURN OFF WRITE PROTECT +; +DS5RTC_WPOFF: + PUSH AF + PUSH BC + XOR A ; CONTROL REGISTER W/P OFF VALUE + LD C,DS5RTC_REG_CONTROL ; CONTROL REGISTER ADR + CALL DS5RTC_PUT ; SET CONTROL REGISTER + POP BC + POP AF + RET +; +; DETECT RTC HARDWARE PRESENCE +; +DS5RTC_DETECT: + CALL DS5RTC_WPOFF ; DISABLE WRITE PROTECT +; + ; TEST AN NVRAM BYTE (NON-DESTRUCTIVE) + LD C,$7F ; LAST NVRAM BYTE + CALL DS5RTC_GET ; GET CURRENT VALUE + LD B,A ; SAVE IN B + XOR $FF ; FLIP ALL BITS + CALL DS5RTC_PUT ; SAVE TO RTC NVRAM + CALL DS5RTC_GET ; GET UPDATED VALUE + XOR $FF ; FLIP ALL BITS + CP B ; COMPARE W/ ORIGINAL READ + PUSH AF ; SAVE FLAGS + CALL DS5RTC_PUT ; RESAVE ORIGINAL VALUE +; + CALL DS5RTC_WPON ; RESTORE WRITE PROTECT + POP AF ; RESTORE FLAGS + RET ; ZF INDICATES PRESENCE +; +; READ RTC DATE/TIME INTO INTERNAL BUFFER +; +DS5RTC_RDCLK: + LD B,7 ; 7 BYTE DATE/TIME BUFFER + LD C,DS5RTC_REG_SEC ; START W/ SECONDS REGISTER + LD HL,DS5RTC_BUF ; USE INTERNAL BUFFER + CALL DS5RTC_GETBUF ; FILL THE BUFFER + XOR A ; SIGNAL SUCCESS + RET ; RETURN +; +; WRITE RTC DATE/TIME FROM INTERNAL BUFFER +; +DS5RTC_WRCLK: + CALL DS5RTC_WPOFF ; DISABLE WRITE PROTECT + LD B,7 ; 7 BYTE DATE/TIME BUFFER + LD C,DS5RTC_REG_SEC ; START W/ SECONDS REGISTER + LD HL,DS5RTC_BUF ; USE INTERNAL BUFFER + CALL DS5RTC_PUTBUF ; FILL THE BUFFER + CALL DS5RTC_WPON ; RESTORE WRITE PROTECT + XOR A ; SIGNAL SUCCESS + RET ; RETURN +; +; CONVERT DATA IN CLOCK BUFFER TO TIME BUFFER AT HL +; +DS5RTC_CLK2TIM: + LD A,(DS5RTC_YR) + LD (HL),A + INC HL + LD A,(DS5RTC_MON) + LD (HL),A + INC HL + LD A,(DS5RTC_DT) + LD (HL),A + INC HL + LD A,(DS5RTC_HR) + LD (HL),A + INC HL + LD A,(DS5RTC_MIN) + LD (HL),A + INC HL + LD A,(DS5RTC_SEC) + LD (HL),A + RET +; +; CONVERT DATA IN TIME BUFFER AT HL TO CLOCK BUFFER +; +DS5RTC_TIM2CLK: + PUSH HL + LD A,(HL) + LD (DS5RTC_YR),A + INC HL + LD A,(HL) + LD (DS5RTC_MON),A + INC HL + LD A,(HL) + LD (DS5RTC_DT),A + INC HL + LD A,(HL) + LD (DS5RTC_HR),A + INC HL + LD A,(HL) + LD (DS5RTC_MIN),A + INC HL + LD A,(HL) + LD (DS5RTC_SEC),A + POP HL + CALL TIMDOW + INC A ; CONVERT FROM 0-6 TO 1-7 + LD (DS5RTC_DAY),A + RET +; +; READ A BUFFER OF BYTES FROM THE RTC +; START RTC ADR IN C, COUNT IN B, BUF PTR IN HL +; +DS5RTC_GETBUF: + LD A,1 + OUT (DS5RTC_SELECT),A ; SELECT RTC + LD A,C ; ADDRESS TO A + OUT (DS5RTC_DATA),A ; SEND TO INTERFACE + OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR + CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION +DS5RTC_GETBUF1: + OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO READ DATA + CALL DS5RTC_WAITBSY ; WAIT FOR DATA + IN A,(DS5RTC_DATA) ; GET VALUE + LD (HL),A ; SAVE BYTE IN BUFFER + INC HL ; BUMP BUF PTR + DJNZ DS5RTC_GETBUF1 ; LOOP FOR REQUESTED BYTES + LD A,0 + OUT (DS5RTC_SELECT),A ; DESELECT DEVICE + RET +; +; WRITE A BUFFER OF BYTES TO THE RTC +; START RTC ADR IN C, COUNT IN B, BUF PTR IN HL +; +DS5RTC_PUTBUF: + LD A,1 + OUT (DS5RTC_SELECT),A ; SELECT RTC + LD A,C ; ADDRESS TO A + SET 7,A ; SET WRITE BIT + OUT (DS5RTC_DATA),A ; SEND TO INTERFACE + OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR + CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION +DS5RTC_PUTBUF1: + LD A,(HL) ; NEXT BYTE TO WRITE + INC HL ; BUMP BUF PTR + OUT (DS5RTC_DATA),A ; SEND TO INTERFACE + OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE BYTE + CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION + DJNZ DS5RTC_PUTBUF1 ; LOOP FOR REQUESTED BYTES + LD A,0 + OUT (DS5RTC_SELECT),A ; DESELECT DEVICE + RET +; +; GET A BYTE FROM THE RTC +; ADDRESS IN C, RETURN VALLUE IN A +; +DS5RTC_GET: + LD A,1 + OUT (DS5RTC_SELECT),A ; SELECT RTC + LD A,C ; ADDRESS TO A + OUT (DS5RTC_DATA),A ; SEND TO INTERFACE + OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR + CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION + OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO READ DATA + CALL DS5RTC_WAITBSY ; WAIT FOR DATA + IN A,(DS5RTC_DATA) ; GET VALUE + PUSH AF ; SAVE VALUE + LD A,0 + OUT (DS5RTC_SELECT),A ; DESELECT DEVICE + POP AF ; RESTORE VALUE + RET +; +; PUT A BYTE TO THE RTC +; ADDRESS IN C, VALUE IN A +; +DS5RTC_PUT: + PUSH AF ; SAVE VALUE TO PUT + LD A,1 + OUT (DS5RTC_SELECT),A ; SELECT RTC + LD A,C ; ADDRESS TO A + SET 7,A ; SET WRITE BIT + OUT (DS5RTC_DATA),A ; SEND TO INTERFACE + OUT (DS5RTC_RUN),A ; SPI TRANSACTION TO WRITE ADR + CALL DS5RTC_WAITBSY ; WAIT FOR COMPLETION + POP AF ; RECOVER VALUE TO PUT + OUT (DS5RTC_DATA),A ; VALUE TO OUTPUT + OUT (DS5RTC_RUN),A ; SPI TRANSACTOIN TO WRITE VALUE + CALL DS5RTC_WAITBSY ; WAIT FOR WRITE TO COMPLETE + LD A,0 + OUT (DS5RTC_SELECT),A ; DESELECT DEVICE + RET +; +; WAIT UNTIL SPI INTERFACE IS NO LONGER BUSY +; +DS5RTC_WAITBSY: + PUSH AF ; PRESERVE AF + PUSH BC ; PRESERVE BC +; + ; AFTER INITIATING A SPI TRANSACTION, IT MAY TAKE A WHILE + ; FOR THE BUSY STATUS TO BE REFLECTED. THE DELAYS BELOW + ; ENSURE ENOUGH TIME HAS ELAPSED. + CALL DELAY + CALL DELAY + CALL DELAY + CALL DELAY + CALL DELAY + CALL DELAY + CALL DELAY + CALL DELAY +; + ; SINCE THIS ROUTINE MAY BE USED TO DETECT AN RTC THAT DOES + ; NOT EXIST, WE PROTECT THE WAIT WITH A TIMEOUT LOOP TO + ; PREVENT A SYSTEM STALL. + LD B,0 +DS5RTC_WAITBSY1: + IN A,(DS5RTC_STATUS) ; GET STATUS BYTE + OR A ; SET FLAGS + JR Z,DS5RTC_WAITBSY2 ; IF ZERO, WE ARE DONE + DJNZ DS5RTC_WAITBSY1 ; TRY TILL COUNTER EXHAUSTED +DS5RTC_WAITBSY2: + POP BC ; RECOVER BC + POP AF ; RECOVER AF + RET +; +; DS5RTC_BUF IS USED FOR BURST READ/WRITE OF CLOCK DATA TO DS1305 +; FIELDS BELOW MATCH ORDER OF DS1305 FIELDS (BCD) +; +DS5RTC_BUF: +DS5RTC_SEC .DB 0 ; SECOND +DS5RTC_MIN .DB 0 ; MINUTE +DS5RTC_HR .DB 0 ; HOUR +DS5RTC_DAY .DB 0 ; DAY OF WEEK +DS5RTC_DT .DB 0 ; DATE +DS5RTC_MON .DB 0 ; MONTH +DS5RTC_YR .DB 0 ; YEAR +; +; DS5RTC_TIMBUF IS TEMP BUF USED TO STORE TIME TEMPORARILY TO DISPLAY +; IT. +; +DS5RTC_TIMBUF .FILL 6,0 ; 6 BYTES FOR GETTIM +; +; DS5RTC_TIMDEF IS DEFAULT TIME VALUE TO INITIALIZE CLOCK IF IT IS +; NOT RUNNING. +; +DS5RTC_TIMDEF: ; DEFAULT TIME VALUE TO INIT CLOCK + .DB $00,$01,$01 ; 2000-01-01 + .DB $00,$00,$00 ; 00:00:00 diff --git a/Source/HBIOS/dsrtc.asm b/Source/HBIOS/dsrtc.asm index f7e89631..ecce36ee 100644 --- a/Source/HBIOS/dsrtc.asm +++ b/Source/HBIOS/dsrtc.asm @@ -165,14 +165,6 @@ DSRTC_BUFSIZ .EQU 7 ; 7 BYTE BUFFER (YYMMDDHHMMSSWW) ; RTC DEVICE PRE-INITIALIZATION ENTRY ; DSRTC_PREINIT: -; - ;; SET RELEVANT BITS IN RTC LATCH SHADOW REGISTER - ;; TO THEIR QUIESENT STATE - ;LD A,(DSRTC_OPRVAL) ; GET CURRENT SHADOW REG VAL - ;AND ~DSRTC_MASK ; CLEAR OUR BITS - ;OR DSRTC_IDLE ; SET OUR IDLE BITS - ;LD (DSRTC_OPRVAL),A ; SAVE IT -; XOR A ; ZERO LD (DSRTC_STAT),A ; CLEAR STATUS CALL DSRTC_DETECT ; HARDWARE DETECTION diff --git a/Source/HBIOS/esp.asm b/Source/HBIOS/esp.asm index 5a76ffb7..e8820e1d 100644 --- a/Source/HBIOS/esp.asm +++ b/Source/HBIOS/esp.asm @@ -364,7 +364,8 @@ ESPCON_INIT: PUSH IY ; COPY CONFIG ENTRY PTR POP DE ; ... TO DE CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED - LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + ;;;LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + CALL CIO_SETCRT ; SET OURSELVES AS THE CRT DEVICE ; ; ANNOUNCE OURSLEVES ; diff --git a/Source/HBIOS/fd.asm b/Source/HBIOS/fd.asm index 8092fad0..467b79bd 100644 --- a/Source/HBIOS/fd.asm +++ b/Source/HBIOS/fd.asm @@ -894,11 +894,11 @@ FD_DETECT: IN_A_NN(FDC_MSR) ; ... AND REREAD THE STATUS ;CALL PC_SPACE ; *DEBUG* ;CALL PRTHEXBYTE ; *DEBUG* - +; FD_DETECT1: CP $80 ; WE EXPECT $80 - RET Z ; IF SO, ALL DONE - + JR Z,FD_DETECT2 ; IF SO, CONTINUE CHECKING +; ; WE HAVE SEEN AN FDC THAT NEEDS A SECOND READ TO GET ; DESIRED VALUE, SO TRY ONE MORE TIME CALL DLY32 ; WAIT A BIT @@ -906,7 +906,19 @@ FD_DETECT1: ;CALL PC_SPACE ; *DEBUG* ;CALL PRTHEXBYTE ; *DEBUG* CP $80 ; CHECK FOR CORRECT VALUE - RET ; RETURN WITH ZF ACCORDING TO RESULT + RET NZ ; RETURN IF FAILED WITH ZF RESET +; +FD_DETECT2: + ; AS A FINAL TEST, WE REREAD THE MSR USING A DIFFERENT + ; OPCODE. THIS SHOULD ELIMINATE ANY FALSE POSITIVES FROM + ; A FLOATING BUS. + CALL DLY32 ; WAIT A BIT + LD C,FDC_MSR ; POINT TO MSR PORT + IN A,(C) ; READ USING (C) FORM OF INPUT + ;CALL PC_SPACE ; *DEBUG* + ;CALL PRTHEXBYTE ; *DEBUG* + CP $80 ; CHECK FOR CORRECT VALUE + RET ; RETURN WITH ZF SET CORRECTLY ; ; UNIT INITIALIZATION ; diff --git a/Source/HBIOS/fv.asm b/Source/HBIOS/fv.asm new file mode 100644 index 00000000..57041386 --- /dev/null +++ b/Source/HBIOS/fv.asm @@ -0,0 +1,497 @@ +;====================================================================== +; VIDEO DRIVER FOR FPGA VGA +; http://s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm +; +; WRITTEN BY: WAYNE WARTHEN -- 9/2/2024 +;====================================================================== +; +; FPGA VGA EXPOSES A FRAME BUFFER STARTING AT $E000. +; PORT $08 CONTROLS ACCESS TO THE FRAME BUFFER. +; - WHEN $01, FRAME BUFFER APPEARS AT $E000 IN CPU ADDRESS SPACE +; - WHEN $00, FRAME BUFFER IS INACCESSIBLE BY CPU +; PORT $C0: SET/GET CURSOR COL +; PORT $C1: SET/GET CURSOR ROW +; PORT $C2: CONTROLS VGA OUTPUT +; BIT 0: BLUE +; BIT 1: GREEN +; BIT 2: RED +; BIT 3: UNUSED? +; BIT 4: CURSOR MODE +; BIT 5: CURSOR BLINK +; BIT 6: CURSOR ENABLE +; BIT 7: VGA SIGNAL OUTPUT ENABLE +; PORT $08: BUFFER SELECT, 1=SELECTED +; +; TODO: +; +;====================================================================== +; FPGA VGA DRIVER - CONSTANTS +;====================================================================== +; +FV_FBUF .EQU $E000 ; ADDRESS OF FRAME BUFFER +FV_BASE .EQU $C0 ; BASE I/O ADDRESS +FV_CCOL .EQU FV_BASE+0 ; CUR COL PORT +FV_CROW .EQU FV_BASE+1 ; CUR ROW PORT +FV_CTL .EQU FV_BASE+2 ; VGA CONTROL PORT +; +FV_BUFCTL .EQU $08 +; +FV_KBDDATA .EQU $03 +FV_KBDST .EQU $02 +; +FV_ROWS .EQU 40 +FV_COLS .EQU 80 +; +TERMENABLE .SET TRUE ; INCLUDE TERMINAL PSEUDODEVICE DRIVER +;;;KBDENABLE .SET TRUE ; INCLUDE KBD KEYBOARD SUPPORT +; + DEVECHO "FV: IO=" + DEVECHO FV_BASE + DEVECHO ", KBD MODE=FV" + DEVECHO ", KBD IO=" + DEVECHO FV_KBDDATA + DEVECHO "\n" +; +;====================================================================== +; FPGA VGA DRIVER - INITIALIZATION +;====================================================================== +; +FV_INIT: + LD IY,FV_IDAT ; POINTER TO INSTANCE DATA +; + CALL NEWLINE ; FORMATTING + PRTS("FV: IO=0x$") + LD A,FV_BASE + CALL PRTHEXBYTE + CALL FV_PROBE ; CHECK FOR HW PRESENCE + JR Z,FV_INIT1 ; CONTINUE IF HW PRESENT +; + ; HARDWARE NOT PRESENT + PRTS(" NOT PRESENT$") + OR $FF ; SIGNAL FAILURE + RET +; +FV_INIT1: + ; RECORD DRIVER ACTIVE + OR $FF + LD (FV_ACTIVE),A + ; DISPLAY CONSOLE DIMENSIONS + LD A,FV_COLS + CALL PC_SPACE + CALL PRTDECB + LD A,'X' + CALL COUT + LD A,FV_ROWS + CALL PRTDECB + PRTS(" TEXT$") + + ; HARDWARE INITIALIZATION + CALL FV_CRTINIT ; SETUP THE FPGA VGA CHIP REGISTERS + CALL FV_VDAINI ; INITIALIZE + ;CALL KBD_INIT ; INITIALIZE KEYBOARD DRIVER + + ; ADD OURSELVES TO VDA DISPATCH TABLE + LD BC,FV_FNTBL ; BC := FUNCTION TABLE ADDRESS + LD DE,FV_IDAT ; DE := FPGA VGA INSTANCE DATA PTR + CALL VDA_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED + + ; INITIALIZE EMULATION + LD C,A ; C := ASSIGNED VIDEO DEVICE NUM + LD DE,FV_FNTBL ; DE := FUNCTION TABLE ADDRESS + LD HL,FV_IDAT ; HL := FPGA VGA INSTANCE DATA PTR + CALL TERM_ATTACH ; DO IT + + XOR A ; SIGNAL SUCCESS + RET +; +;====================================================================== +; FPGA VGA DRIVER - VIDEO DISPLAY ADAPTER (VDA) FUNCTIONS +;====================================================================== +; +FV_FNTBL: + .DW FV_VDAINI + .DW FV_VDAQRY + .DW FV_VDARES + .DW FV_VDADEV + .DW FV_VDASCS + .DW FV_VDASCP + .DW FV_VDASAT + .DW FV_VDASCO + .DW FV_VDAWRC + .DW FV_VDAFIL + .DW FV_VDACPY + .DW FV_VDASCR + .DW FV_STAT + .DW FV_FLUSH + .DW FV_READ + .DW FV_VDARDC +#IF (($ - FV_FNTBL) != (VDA_FNCNT * 2)) + .ECHO "*** INVALID FV FUNCTION TABLE ***\n" + !!!!! +#ENDIF + +FV_VDAINI: + ; RESET VDA + CALL FV_VDARES ; RESET VDA + LD HL,0 ; ZERO + LD (FV_POS),HL ; ... TO POSITION + LD A,' ' ; BLANK THE SCREEN + LD DE,FV_ROWS*FV_COLS ; FILL ENTIRE BUFFER + CALL FV_FILL ; DO IT + LD DE,0 ; ROW = 0, COL = 0 + CALL FV_XY ; SEND CURSOR TO TOP LEFT + CALL FV_SHOWCUR ; NOW SHOW THE CURSOR + XOR A ; SIGNAL SUCCESS + RET + +FV_VDAQRY: + LD C,$00 ; MODE ZERO IS ALL WE KNOW + LD D,FV_ROWS ; ROWS + LD E,FV_COLS ; COLS + LD HL,0 ; EXTRACTION OF CURRENT BITMAP DATA NOT SUPPORTED + XOR A ; SIGNAL SUCCESS + RET + +FV_VDARES: + CALL FV_CRTINIT + XOR A ; SIGNAL SUCCESS + RET + +FV_VDADEV: + LD D,VDADEV_FV ; D := DEVICE TYPE + LD E,0 ; E := PHYSICAL UNIT IS ALWAYS ZERO + LD H,0 ; H := 0, DRIVER HAS NO MODES + LD L,FV_BASE ; L := BASE I/O ADDRESS + XOR A ; SIGNAL SUCCESS + RET + +FV_VDASCS: + SYSCHKERR(ERR_NOTIMPL) ; NOT IMPLEMENTED (YET) + RET + +FV_VDASCP: + CALL FV_XY ; SET CURSOR POSITION + XOR A ; SIGNAL SUCCESS + RET + +FV_VDASAT: + ; ATTRIBUTES NOT SUPPORTED BY HARDWARE + XOR A + RET + +FV_VDASCO: + ; CHARACTER COLOR NOT SUPPORT BY HARDWARE + XOR A ; SIGNAL SUCCESS + RET ; DONE + +FV_VDAWRC: + LD A,E ; CHARACTER TO WRITE GOES IN A + CALL FV_PUTCHAR ; PUT IT ON THE SCREEN + XOR A ; SIGNAL SUCCESS + RET + +FV_VDAFIL: + LD A,E ; FILL CHARACTER GOES IN A + EX DE,HL ; FILL LENGTH GOES IN DE + CALL FV_FILL ; DO THE FILL + XOR A ; SIGNAL SUCCESS + RET + +FV_VDACPY: + ; LENGTH IN HL, SOURCE ROW/COL IN DE, DEST IS FV_POS + ; BLKCPY USES: HL=SOURCE, DE=DEST, BC=COUNT + PUSH HL ; SAVE LENGTH + CALL FV_XY2IDX ; ROW/COL IN DE -> SOURCE ADR IN HL + POP BC ; RECOVER LENGTH IN BC + LD DE,(FV_POS) ; PUT DEST IN DE + JP FV_BLKCPY ; DO A BLOCK COPY + +FV_VDASCR: + LD A,E ; LOAD E INTO A + OR A ; SET FLAGS + RET Z ; IF ZERO, WE ARE DONE + PUSH DE ; SAVE E + JP M,FV_VDASCR1 ; E IS NEGATIVE, REVERSE SCROLL + CALL FV_SCROLL ; SCROLL FORWARD ONE LINE + POP DE ; RECOVER E + DEC E ; DECREMENT IT + JR FV_VDASCR ; LOOP +FV_VDASCR1: + CALL FV_RSCROLL ; SCROLL REVERSE ONE LINE + POP DE ; RECOVER E + INC E ; INCREMENT IT + JR FV_VDASCR ; LOOP + +FV_STAT: + IN A,(FV_KBDST) ; GET STATUS + AND $01 ; ISOLATE DATA WAITING BIT + JP Z,CIO_IDLE ; NO DATA, EXIT VIA IDLE PROCESS + RET + +FV_FLUSH: + XOR A ; SIGNAL SUCCESS + RET + +FV_READ: + CALL FV_STAT ; GET STATUS + JR Z,FV_READ ; LOOP TILL DATA READY + IN A,(FV_KBDDATA) ; GET BYTE + LD E,A ; PUT IN E FOR RETURN + XOR A ; SIGNAL SUCCESS + RET ; DONE + +;---------------------------------------------------------------------- +; READ VALUE AT CURRENT VDU BUFFER POSITION +; RETURN E = CHARACTER, B = COLOUR, C = ATTRIBUTES +;---------------------------------------------------------------------- + +FV_VDARDC: + CALL FV_GETCHAR ; GET THE CHARACTER AT CUR CUR POS + LD E,A ; PUT IN E + LD BC,0 ; COLOR AND ATTR NOT SUPPORTED + XOR A ; SIGNAL SUCCESS + RET +; +;====================================================================== +; FPGA VGA DRIVER - PRIVATE DRIVER FUNCTIONS +;====================================================================== +; +; +;---------------------------------------------------------------------- +; PROBE FOR FPGA VGA HARDWARE +;---------------------------------------------------------------------- +; +; ON RETURN, ZF SET INDICATES HARDWARE FOUND +; +FV_PROBE: + XOR A ; ASSUME H/W EXISTS + RET +; +;---------------------------------------------------------------------- +; CRTC DISPLAY CONTROLLER CHIP INITIALIZATION +;---------------------------------------------------------------------- +; +FV_CRTINIT: + LD A,%11001111 ; WHITE ON BLACK, CURSOR ON, ENABLE OUTPUT + OUT (FV_CTL),A ; WRITE TO CONTROL PORT + XOR A ; ZERO ACCUM + RET ; DONE +; +;---------------------------------------------------------------------- +; SET CURSOR POSITION TO ROW IN D AND COLUMN IN E +;---------------------------------------------------------------------- +; +FV_XY: + CALL FV_HIDECUR ; HIDE THE CURSOR + PUSH DE ; SAVE NEW POSITION FOR NOW + CALL FV_XY2IDX ; CONVERT ROW/COL TO BUF IDX + LD (FV_POS),HL ; SAVE THE RESULT (DISPLAY POSITION) + POP DE ; RECOVER INCOMING ROW/COL + LD A,D ; GET ROW + OUT (FV_CROW),A ; SET ROW REGISTER + LD A,E ; GET COL + INC A ; 1..79,0 (WHY???) + CP 80 ; COL 80? + JR NZ, FV_XY1 ; SKIP IF NOT + XOR A ; ELSE MAKE IT ZERO! +FV_XY1: + OUT (FV_CCOL),A ; SET COL REGISTER + JP FV_SHOWCUR ; SHOW THE CURSOR AND EXIT +; +;---------------------------------------------------------------------- +; CONVERT XY COORDINATES IN DE INTO LINEAR INDEX IN HL +; D=ROW, E=COL +;---------------------------------------------------------------------- +; +FV_XY2IDX: + LD A,E ; SAVE COLUMN NUMBER IN A + LD H,D ; SET H TO ROW NUMBER + LD E,FV_COLS ; SET E TO ROW LENGTH + CALL MULT8 ; MULTIPLY TO GET ROW OFFSET, H * E = HL, E=0, B=0 + LD E,A ; GET COLUMN BACK + ADD HL,DE ; ADD IT IN + RET ; RETURN +; +;---------------------------------------------------------------------- +; SHOW OR HIDE CURSOR +;---------------------------------------------------------------------- +; +FV_SHOWCUR: + LD A,%11001111 ; CONTROL PORT VALUE + ;;;LD A,%11111111 ; CONTROL PORT VALUE + OUT (FV_CTL),A ; SET REGISTER + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +FV_HIDECUR: + LD A,%11001111 ; CONTROL PORT VALUE + ;;;LD A,%11111111 ; CONTROL PORT VALUE + OUT (FV_CTL),A ; SET REGISTER + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +;---------------------------------------------------------------------- +; (DE)SELECT FRAME BUFFER +;---------------------------------------------------------------------- +; +FV_BUFSEL: + PUSH AF + LD A,$01 + OUT (FV_BUFCTL),A + POP AF + RET +; +FV_BUFDESEL: + PUSH AF + XOR A + OUT (FV_BUFCTL),A + POP AF + RET +; +;---------------------------------------------------------------------- +; WRITE VALUE IN A TO CURRENT VDU BUFFER POSITION, ADVANCE CURSOR +;---------------------------------------------------------------------- +; +FV_PUTCHAR: + ; WRITE CHAR AT CURRENT CURSOR POSITION. + PUSH AF ; SAVE INCOMING CHAR + CALL FV_HIDECUR ; HIDE CURSOR + CALL FV_BUFSEL ; SELECT FRAME BUFFER + POP AF + LD HL,(FV_POS) ; GET CUR BUF POSITION + LD DE,FV_FBUF ; START OF FRAME BUF + ADD HL,DE ; ADD IT IN + LD (HL),A ; PUT THE CHAR +; + ; SET NEW POSITION + LD HL,(FV_POS) ; GET POSITION + INC HL ; BUMP POSITION + LD (FV_POS),HL ; SAVE NEW POSITION +; + ; PUT CUROR IN PLACE + LD DE,FV_COLS ; COLS PER LINE + CALL DIV16 ; BC=ROW, HL=COL + LD D,C + LD E,L + CALL FV_XY + CALL FV_BUFDESEL ; DESELECT FRAME BUFFER + JP FV_SHOWCUR ; SHOW IT AND RETURN +; +;---------------------------------------------------------------------- +; GET CHAR VALUE TO A FROM CURRENT VDU BUFFER POSITION +;---------------------------------------------------------------------- +; +FV_GETCHAR: + XOR A + RET +; +;---------------------------------------------------------------------- +; FILL AREA IN BUFFER WITH SPECIFIED CHARACTER AND CURRENT COLOR/ATTRIBUTE +; STARTING AT THE CURRENT FRAME BUFFER POSITION +; A: FILL CHARACTER +; DE: NUMBER OF CHARACTERS TO FILL +;---------------------------------------------------------------------- +; +FV_FILL: + PUSH AF ; SAVE INCOMING FILL CHAR + CALL FV_HIDECUR ; HIDE CURSOR + CALL FV_BUFSEL ; SELECT BUFFER + LD HL,(FV_POS) ; CUR POS TO HL + LD BC,FV_FBUF ; ADR OF FRAME + ADD HL,BC ; ADD IT IN + POP AF + LD C,A ; FILL CHAR TO C +FV_FILL1: + LD A,D ; CHECK FILL + OR E ; ... COUNTER + JR Z,FV_FILL2 ; DONE IF ZERO + LD (HL),C ; FILL ONE CHAR + INC HL ; BUMP BUF PTR + DEC DE ; DEC FILL COUNTER + JR FV_FILL1 ; LOOP +; +FV_FILL2: + CALL FV_BUFDESEL ; DESELECT BUFFER + JP FV_SHOWCUR ; EXIT VIA SHOW CURSOR +; +;---------------------------------------------------------------------- +; SCROLL ENTIRE SCREEN FORWARD BY ONE LINE (CURSOR POSITION UNCHANGED) +;---------------------------------------------------------------------- +; +FV_SCROLL: + CALL FV_BUFSEL ; SELECT FRAME BUFFER +; + ; COPY "UP" ONE LINE + LD HL,FV_FBUF + FV_COLS ; FROM SECOND LINE + LD DE,FV_FBUF ; TO FIRST LINE + LD BC,+(FV_ROWS - 1) * FV_COLS ; ALL BUT ONE LINE + LDIR ; DO IT +; + ; FILL LAST LINE OF SCREEN + LD HL,FV_FBUF + ((FV_ROWS - 1) * FV_COLS) ; LAST LINE + LD A,' ' ; FILL CHAR + LD (HL),A ; COPY 1 CHAR + LD DE,FV_FBUF + ((FV_ROWS - 1) * FV_COLS) + 1 ; SECOND POS IN LAST LINE + LD BC,FV_COLS - 1 ; COLS PER LINE - 1 + LDIR ; FILL IT +; + CALL FV_BUFDESEL ; DESELECT FRAME BUFFER + RET ; DONE +; +;---------------------------------------------------------------------- +; REVERSE SCROLL ENTIRE SCREEN BY ONE LINE (CURSOR POSITION UNCHANGED) +;---------------------------------------------------------------------- +; +FV_RSCROLL: + CALL FV_BUFSEL ; SELECT FRAME BUFFER +; + ; COPY "DOWN" ONE LINE + LD HL,FV_FBUF + (FV_COLS * (FV_ROWS - 1)) - 1 ; FROM END OF SECOND TO LAST LINE + LD DE,FV_FBUF + (FV_COLS * FV_ROWS) - 1 ; TO END OF LAST LINE + LD BC,+(FV_ROWS - 1) * FV_COLS ; ALL BUT ONE LINE + LDDR ; DO IT IN REVERSE +; + ; FILL FIRST LINE OF SCREEN + LD HL,FV_FBUF ; FIRST LINE + LD A,' ' ; FILL CHAR + LD (HL),A ; COPY 1 CHAR + LD DE,FV_FBUF + 1 ; SECOND POS IN FIRST LINE + LD BC,FV_COLS - 1 ; COLS PER LINE - 1 + LDIR ; FILL IT +; + CALL FV_BUFDESEL ; DESELECT FRAME BUFFER + RET ; DONE +; +;---------------------------------------------------------------------- +; BLOCK COPY BC BYTES FROM HL TO DE +;---------------------------------------------------------------------- +; +FV_BLKCPY: + + CALL FV_BUFSEL ; SELECT FRAME BUFFER + PUSH BC ; SAVE LENGTH + LD BC,FV_FBUF ; FRAME BUFFER ADR + ADD HL,BC ; ADD TO SOURCE + EX DE,HL ; EXCHANGE + ADD HL,BC ; ADD TO DEST + EX DE,HL ; EXCHANGE + POP BC ; RECOVER LENGTH + LDIR ; LDIR DOES THE COPY + CALL FV_BUFDESEL ; DESELECT FRAME BUFFER + RET ; DONE +; +;================================================================================================== +; FPGA VGA DRIVER - DATA +;================================================================================================== +; +FV_POS .DW 0 ; CURRENT DISPLAY POSITION +FV_ACTIVE .DB FALSE ; FLAG FOR DRIVER ACTIVE +; +;================================================================================================== +; VGA DRIVER - INSTANCE DATA +;================================================================================================== +; +FV_IDAT: + .DB KBDMODE_FV ; FPGA VGA KEYBOARD CONTROLLER + .DB FV_KBDST + .DB FV_KBDDATA diff --git a/Source/HBIOS/gm7303.asm b/Source/HBIOS/gm7303.asm new file mode 100644 index 00000000..a0f7430e --- /dev/null +++ b/Source/HBIOS/gm7303.asm @@ -0,0 +1,316 @@ +; +;================================================================================================== +; HARDWARE SUPPORT FOR GENESS MODULES 7303 STD BUS KEYBOARD/GM7303 +; - INCORPORATES HITACHI HD44780 AS 2 X 16 DISPLAY AND 24 KEY HEX KEYPAD +;================================================================================================== +; +; Heavily derived from the lcd.asm driver, but forked because the 7303 card has keyboard +; functionality as well. Eventually will be used as a Z80/180 monitor tool +; +; The GM7303 supports an LCD display while the original has 2 DL1416 starburst displays. +;================================================================================================== +; +; CARD FUNCTIONS: (BASE_IO = 0x30) +; +; 20X2 LCD 0X30 OUTPUT (D0-D7) +; 0X31 OUTPUT (D0 - LCD E) +; (D1 - LCD R/W*) +; (D2 - LCD RS) +; S1 & S2 INPUT 0x30 INPUT (BIT 6,7) +; 8 OUTPUT LEDS 0x30 OUTPUT +; KEYBOARD 0X30 OUTPUT (COLUMN BIT 0-3) +; 0X30 INPUT (ROW BIT 0-5) +; +;=================================================================================================== +; +; Date Change +; 05Sep2024 Initial development - basic init functions +; 06Sep2024 Working - Cleaned out functions that wont be used - TODO - Implement keyboard +; +; +GM7303_DATA .EQU GM7303BASE + 0 ; WRITE +GM7303_CTRL .EQU GM7303BASE + 1 ; WRITE +GM7303_KYBD .EQU GM7303BASE + 0 ; READ/WRITE +; +GM7303_FUNC_CLEAR .EQU $01 ; CLEAR DISPLAY +GM7303_FUNC_HOME .EQU $02 ; HOME CURSOR & REMOVE ALL SHIFTING +GM7303_FUNC_ENTRY .EQU $04 ; SET CUR DIR AND DISPLAY SHIFT +GM7303_FUNC_DISP .EQU $08 ; DISP, CUR, BLINK ON/OFF +GM7303_FUNC_SHIFT .EQU $10 ; MOVE CUR / SHIFT DISP +GM7303_FUNC_SET .EQU $20 ; SET INTERFACE PARAMS +GM7303_FUNC_CGADR .EQU $40 ; SET CGRAM ADRESS +GM7303_FUNC_DDADR .EQU $80 ; SET DDRAM ADDRESS +; + DEVECHO "GM7303: IO=" + DEVECHO GM7303BASE + DEVECHO "\n" +; +; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION +; +GM7303_PREINIT: + +; TEST FOR PRESENCE... + CALL GM7303_DETECT ; PROBE FOR HARDWARE + LD A,(GM7303_PRESENT) ; GET PRESENCE FLAG + OR A ; SET FLAGS + RET Z ; BAIL OUT IF NOT PRESENT ; RESET GM7303 CONTROLLER, DELAYS ARE FIXED, + +; INITIALISE LCD + CALL GM7303_RESET ; RESET THE LCD + PUSH HL + LD HL,GM7303_INIT_TBL + LD D,04H ; 4 BYTES TO SEND +NEXT_INIT: + LD A,(HL) ; GET COMMAND + OUT (GM7303_DATA),A ; WRITE TO TO DISPLAY + CALL CMD_STROBE ; COMMAND STROBE + PUSH DE + LD DE,5000/16 ; WAIT >4MS, WE USE 5MS + CALL VDELAY ; DO IT + POP DE + INC HL + DEC D ; (D)=00 -> COMMAND + JR NZ,NEXT_INIT ; NO - DO NEXT INIT COMMAND + POP HL +; +; PUT SOMETHING ON THE DISPLAY + LD DE,GM7303_STR_BAN ; DISPLAY BANNER + CALL GM7303_OUTDS + +; SECOND LINE + LD HL,$0100 ; ROW 2, COL 0 + CALL GM7303_GOTORC + LD DE,GM7303_STR_CFG ; DISPLAY CONFIG + CALL GM7303_OUTDS + + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +; POST CONSOLE INITIALIZATION +; +GM7303_INIT: + CALL NEWLINE ; FORMATTING + PRTS("GM7303: IO=$") + LD A,GM7303BASE + CALL PRTHEXBYTE +; + LD A,(GM7303_PRESENT) ; GET PRESENCE FLAG + OR A ; SET FLAGS + JR Z,GM7303_INIT1 ; HANDLE NOT PRESENT + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +GM7303_INIT1: + PRTS(" NOT PRESENT$") + OR $FF + RET +; +; CALLED FROM HBIOS RIGHT BEFORE A DISK ACCESS +; HL: ADDRESS OF 32-BIT SECTOR NUMBER (LITTLE-ENDIAN) +; +; FORMAT: "Dsk99 R:12345678" +; 0123456789012345 +; +GM7303_DSKACT: + ; SAVE EVERYTHING + PUSH AF + PUSH BC + PUSH DE + PUSH HL +; + LD A,(GM7303_PRESENT) ; GET PRESENCE FLAG + OR A ; SET FLAGS + JR Z,GM7303_DSKACT_Z ; HANDLE NOT PRESENT +; + PUSH HL + LD HL,$0100 ; ROW 1, COL 0 + CALL GM7303_GOTORC ; SET DISPLAY ADDRESS + POP HL +; + LD DE,GM7303_STR_IO ; PREFIX + CALL GM7303_OUTDS ; SEND TO DISPLAY (COLS 0-5) + + LD A,(HB_DSKUNIT) ; GET DISK UNIT NUM + CALL GM7303_DSKACT_BYTE ; SEND TO DISPLAY (COLS 6-7) HEX??? +; + LD A,' ' ; SEPARATOR + CALL GM7303_OUTD ; SEND TO DISPLAY (COL 8) +; + LD A,(HB_DSKFUNC) ; ACTIVE DISK FUNCTION + CP BF_DIOWRITE ; WRITE? + LD A,'W' ; ASSUME WRITE + JR Z,GM7303_DSKACT0 ; GO AHEAD + LD A,'R' ; OTHERWISE READ +GM7303_DSKACT0: + CALL GM7303_OUTD ; SEND CHAR (COL 10) + + LD A,':' ; SEPARATOR + CALL GM7303_OUTD ; SEND TO DISPLAY (COL 11) +; + LD A,3 ; POINT TO + CALL ADDHLA ; END OF DWORD (MSB) + LD B,4 ; DO 4 BYTES +; +GM7303_DSKACT1: + LD A,(HL) ; GET BYTE + CALL GM7303_DSKACT_BYTE ; SEND TO DISPLAY (COLS 12-19) + DEC HL ; DEC PTR + DJNZ GM7303_DSKACT1 ; DO ALL 4 BYTES +; +GM7303_DSKACT_Z: + ; CLEAN UP AND GO AWAY + POP HL + POP DE + POP BC + POP AF + RET +;; +GM7303_DSKACT_BYTE: + PUSH AF ; SAVE BYTE + RRCA ; DO TOP NIBBLE FIRST + RRCA + RRCA + RRCA + CALL HEXCONV ; CONVERT NIBBLE TO ASCII + CALL GM7303_OUTD ; SEND TO DISPLAY + POP AF ; RECOVER CURRENT BYTE + CALL HEXCONV ; CONVERT NIBBLE TO ASCII + CALL GM7303_OUTD ; SEND TO DISPLAY + RET ; DONE + + +; DETECT PRESENCE OF GM7303 CONTROLLER +; WE CAN'T USE CONTROLLER RAM AS THE GM7303 DOES NOT SUPPORT LCD READS +; SIMPLY TEST FOR THE EXISTANCE OF BUS PULLDOWN AT THE SWITCH PORT +; +GM7303_DETECT: + IN A,(GM7303_DATA) ; GET VALUE OF DATA INPUTS + CP 00 ; GM7303 PULLS DATA TO GROUND + JR Z,GM7303_AVAILABLE +GM7303_MISSING: + LD A,00 + LD (GM7303_PRESENT),A + RET +GM7303_AVAILABLE: + LD A,$FF + LD (GM7303_PRESENT),A + RET +; +; DELAY ROUTINE +; +GM7303_DELAY: + PUSH AF + PUSH DE + LD DE,3 ; WAIT PERIOD + CALL VDELAY ; DO IT + POP DE + POP AF + RET + + + +CMD_STROBE: ; Send a command to the LCD + LD A,01H ; (A) = (X,X,X,X,X,RS,R/W*, E) + ; SET R/W* LINE low (BIT 1=0) + ; SET RS line LOW FOR COMMAND (BIT 2=0) + ; SET ENABLE LINE HIGH (BIT 0=1) + ; CARRY ON THROUGH THE STROBE ROUTINE +STROBE: + OR 01H ; SET ENABLE LINE HIGH (BIT 0=1) + OUT (GM7303_CTRL),A + CALL GM7303_DELAY + + XOR 01H ; SET ENABLE LINE LOW (BIT 0=0) + OUT (GM7303_CTRL),A + CALL GM7303_DELAY + RET ; EXIT + +GM7303_OUTD: +GM7303_DISPLAY: ; OUTPUT ASCII CHARACTER TO LCD DISPLAY + ; CHAR IN A + AND 07FH + OUT (GM7303_DATA),A ; OUTPUT TO THE DATA PORT + ; AND STROBE IT IN +DATA_STROBE: + LD A,04H ; SET R/W* LINE low (BIT 1=0) + ; SET RS line HIGH FOR DATA (BIT 2=1) + ; (A) = (X,X,X,X,X,RS,R/W*, E) + JP STROBE ; DO THE STROBE + ; RETURN THROUGH THE STROBE ROUTINE + +GM7303_COMMAND: ; OUTPUT COMMAND TO 7303 MODULE LCD + OUT (GM7303_DATA),A ; WRITE TO TO DISPLAY + JP CMD_STROBE ; COMMAND STROBE (STROBE ROUTING LETS US RETURN) + +; SEND DATA STRING +; DE=STRING ADDRESS, NULL TERMINATED +; +GM7303_OUTDS: + LD A,(DE) ; NEXT BYTE TO SEND +; LD A,045H ; NEXT BYTE TO SEND + OR A ; SET FLAGS + RET Z ; DONE WHEN NULL REACHED + INC DE ; BUMP POINTER + CALL GM7303_DISPLAY ; SEND IT + JR GM7303_OUTDS ; LOOP AS NEEDED +; +; GOTO ROW(H),COL(L) +; +GM7303_GOTORC: + PUSH HL ; SAVE INCOMING + LD A,H ; ROW # TO A + LD HL,GM7303_ROWS ; POINT TO ROWS TABLE + CALL ADDHLA ; INDEX TO ROW ENTRY + LD A,(HL) ; GET ROW START + POP HL ; RECOVER INCOMING + ADD A,L ; ADD COLUMN + ADD A,GM7303_FUNC_DDADR ; ADD SET DDRAM COMMAND + JR GM7303_COMMAND ; AND SEND IT +; + +; RESET LCD CONTROLLER MANUAL RESET METHOD +; +GM7303_RESET: + LD A,GM7303_FUNC_SET | %11000 ; 8 BIT INTERFACE, COMMAND MODE, 2 LINES + OUT (GM7303_DATA),A + LD A,01 ; SET ENABLE LINE HIGH (BIT 0=1) + OUT (GM7303_CTRL),A + LD DE,5000/16 ; WAIT >40MS, WE USE 50MS + CALL VDELAY ; DO IT + LD A,00 ; SET ENABLE LINE LOW (BIT 0=0) + OUT (GM7303_CTRL),A + + LD A,01 ; SET ENABLE LINE HIGH (BIT 0=1) + OUT (GM7303_CTRL),A + LD DE,500/16 ; WAIT >4MS, WE USE 5MS + CALL VDELAY ; DO IT + LD A,00 ; SET ENABLE LINE LOW (BIT 0=0) + OUT (GM7303_CTRL),A + + LD A,01 ; SET ENABLE LINE HIGH (BIT 0=1) + OUT (GM7303_CTRL),A + LD DE,500/16 ; WAIT >4MS, WE USE 5MS + CALL VDELAY ; DO IT + LD A,00 ; SET ENABLE LINE LOW (BIT 0=0) + OUT (GM7303_CTRL),A + RET + +; +; DATA STORAGE +; +GM7303_PRESENT .DB 0 ; NON-ZERO WHEN HARDWARE DETECTED +; +GM7303_ROWS .DB $00,$40 ; ROW START INDEX FOR 2 LINE DISPLAY +; +GM7303_INIT_TBL: ; TABLE OF INITIALISATION COMMANDS FOR THE LCD + .DB 38H ; 8 BIT OPERATION, 2 LINE DISPLAY, 8X5 FONT + .DB 0EH ; TURN ON DISPLAY, CURSOR AND BLINK + .DB 06H ; SET CURSOR MOVE FROM LEFT TO RIGHT + .DB 01H ; CLEAR DISPLAY +; +GM7303_STR_BAN .DB "RomWBW ", BIOSVER, 0 +GM7303_STR_CFG .DB "Build:", CONFIG, 0 +GM7303_STR_IO .DB "Dsk", 0 + + + diff --git a/Source/HBIOS/h8p.asm b/Source/HBIOS/h8p.asm index 234283f5..67e8aade 100644 --- a/Source/HBIOS/h8p.asm +++ b/Source/HBIOS/h8p.asm @@ -12,8 +12,31 @@ ; +--10--+ 80 ; ; - DEVECHO "H8P: IO=??" - ;DEVECHO 0 +H8PKEYNONE .EQU $FF ; NONE +H8PKEY0 .EQU $FE +H8PKEY1 .EQU $FC +H8PKEY2 .EQU $FA +H8PKEY3 .EQU $F8 +H8PKEY4 .EQU $F6 +H8PKEY5 .EQU $F4 +H8PKEY6 .EQU $F2 +H8PKEY7 .EQU $F0 +H8PKEY8 .EQU $EF +H8PKEY9 .EQU $CF +H8PKEYPLUS .EQU $AF ; PLUS +H8PKEYMINUS .EQU $8F ; MINUS +H8PKEYMUL .EQU $6F ; MULTIPLY +H8PKEYDIV .EQU $4F ; DIVIDE +H8PKEYNUM .EQU $2F ; NUMBER +H8PKEYDOT .EQU $0F ; DOT +; +H8P_TICCNT .EQU $FFEA ; TICCNT AT $FFEA IS COPIED DOWN TO $000B FOR HEATH COMPATIBILITY +H8P_SPEED .EQU $FFEC ; SPEED CONTROL VALUE IS STORED HERE +H8P_SPDIO .EQU $30 +H8FPIO .EQU $F0 +; + DEVECHO "H8P: IO=" + DEVECHO H8FPIO DEVECHO "\n" ; ;__H8P_PREINIT_______________________________________________________________________________________ @@ -24,144 +47,917 @@ ; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION ; H8P_PREINIT: - LD A,(DSKY_DISPACT) ; DSKY DISPATCHER ALREADY SET? - OR A ; SET FLAGS - RET NZ ; IF ALREADY ACTIVE, ABORT -; - ; REGISTER DRIVER WITH HBIOS - LD BC,H8P_DISPATCH - CALL DSKY_SETDISP + LD HL,H8P_INTR + CALL HB_ADDIM1 ; RET ; ;__H8P_INIT__________________________________________________________________________________________ ; -; DISPLAY DSKY INFO ON ROMWBW CONSOLE +; DISPLAY H8 FRONT PANEL INFO ON ROMWBW CONSOLE ;____________________________________________________________________________________________________ ; H8P_INIT: CALL NEWLINE ; FORMATTING - PRTS("H8P:$") ; DRIVER TAG + PRTS("H8FP:$") ; FORMATTING +; + PRTS(" IO=0x$") ; FORMATTING + LD A,H8FPIO ; GET BASE PORT + CALL PRTHEXBYTE ; PRINT BASE PORT ; RET ; DONE ; -; DSKY DEVICE FUNCTION DISPATCH ENTRY -; A: RESULT (OUT), 0=OK, Z=OK, NZ=ERR -; B: FUNCTION (IN) -; -H8P_DISPATCH: - LD A,B ; GET REQUESTED FUNCTION - AND $0F ; ISOLATE SUB-FUNCTION - JP Z,H8P_RESET ; RESET DSKY HARDWARE - DEC A - JP Z,H8P_STAT ; GET KEYPAD STATUS - DEC A - JP Z,H8P_GETKEY ; READ A KEY FROM THE KEYPAD - DEC A - JP Z,H8P_SHOWHEX ; DISPLAY A 32-BIT BINARY VALUE IN HEX - DEC A - JP Z,H8P_SHOWSEG ; DISPLAY SEGMENTS - DEC A - JP Z,H8P_KEYLEDS ; SET KEYPAD LEDS - DEC A - JP Z,H8P_STATLED ; SET STATUS LED - DEC A - JP Z,H8P_BEEP ; BEEP DSKY SPEAKER - DEC A - JP Z,H8P_DEVICE ; DEVICE INFO - SYSCHKERR(ERR_NOFUNC) - RET -; -; RESET DSKY -- CLEAR DISPLAY AND KEYPAD FIFO -; -H8P_RESET: - XOR A ; SIGNAL SUCCESS +; H8 FRONT PANEL INTERRUPT +; +H8P_INTR: + LD (H8P_BCVAL),BC + LD (H8P_DEVAL),DE + LD (H8P_HLVAL),HL + LD HL,(H8P_TICCNT) ; 2MS TIC COUNTER + INC HL + LD (H8P_TICCNT),HL + CALL H8P_TIMER ; UP TIMER + CALL H8P_STAT ; CHECK KEYPAD PRESS + CALL H8P_GETSEGIDX ; SEGMENT INDEX IN (C) + CALL H8P_HORN + OR C + OUT (H8FPIO),A ; CLEAR INTERRUPT AND SET LED IDX + LD C,A + LD A,(H8P_FPENA) + OR A + LD A,$FF + CALL NZ,H8P_GETSEGPAT + OUT (H8FPIO+1),A ; SET LED PATTERN +; + CALL H8P_KEYPAD + LD A,(H8P_STTIMER) + INC A + AND $1F ; UPDATE LEDS EVERY 32 TICKS + LD (H8P_STTIMER),A + CALL Z,H8P_HDLSTATE + LD A,(H8P_HBTICK) ; ROMWBW TIMER + INC A + LD (H8P_HBTICK),A + CP 10 + RET NZ + CALL HB_TICK + XOR A + LD (H8P_HBTICK),A + INC A ; INTERRUPT HANDLED + RET +; +; HANDLE FRONT PANEL SPEAKER SOUNDS +; +H8P_HORN: + LD HL,(H8P_HORNDUR) + LD A,H + OR L + LD A,$D0 ; HORN OFF + RET Z + DEC HL + LD (H8P_HORNDUR),HL + LD A,$50 ; HORN ON + RET +; +; HANDLE UP-TIME TIMER +; +H8P_TIMER: + LD HL,(H8P_ONESEC) + DEC HL + LD (H8P_ONESEC),HL + LD A,H + OR L + RET NZ + LD HL,(H8P_UPTIME) + INC HL + LD (H8P_UPTIME),HL + LD HL,500 + LD (H8P_ONESEC),HL + CALL H8P_TIMER1 + LD A,(H8P_STATE) + OR A + CALL Z,H8P_TIMER2 + RET +; ADVANCE DIGITS +H8P_TIMER1: + LD C,9 + LD HL,H8P_UPTDIG+8 + CALL H8P_ADVDIG + RET +; SHOW DIGITS +H8P_TIMER2: + LD DE,H8P_UPTDIG+8 + LD HL,H8P_SEGBUF+8 + LD C,9 +H8P_TIMER3: + PUSH BC + PUSH HL + LD A,C + CP 7 + JR Z,H8P_TIMER4 + CP 4 + JR Z,H8P_TIMER4 + JR H8P_TIMER5 +H8P_TIMER4: + LD A,$80 + JR H8P_TIMER6 +H8P_TIMER5: + LD HL,H8P_DIGMAP + LD A,(DE) + LD C,A + LD B,0 + ADD HL,BC + LD A,(HL) +H8P_TIMER6: + POP HL + LD (HL),A + DEC HL + DEC DE + POP BC + DEC C + JR NZ,H8P_TIMER3 + RET +H8P_ADVDIG: + LD A,(HL) ; 000.000.00X + INC A + LD (HL),A + CP 10 ; 0-9 + RET NZ + LD (HL),0 + DEC HL + LD A,(HL) ; 000.000.0X0 + INC A + LD (HL),A + CP 6 ; 0-5 + RET NZ + LD (HL),0 + DEC HL + DEC HL + LD A,(HL) ; 000.00X.000 + INC A + LD (HL),A + CP 10 ; 0-9 + RET NZ + LD (HL),0 + DEC HL + LD A,(HL) ; 000.0X0.000 + INC A + LD (HL),A + CP 6 ; 0-5 + RET NZ + LD (HL),0 + DEC HL + DEC HL + LD A,(HL) ; 00X.000.000 + INC A + LD (HL),A + CP 10 ; 0-9 + RET NZ + LD (HL),0 + DEC HL + LD A,(HL) ; 0X0.000.000 + INC A + LD (HL),A + CP 10 ; 0-9 + RET NZ + LD (HL),0 + DEC HL + LD A,(HL) ; X00.000.000 + INC A + LD (HL),A + CP 10 ; 0-9 + RET NZ + LD (HL),0 RET ; -; CHECK FOR KEY PRESS, SAVE RAW VALUE, RETURN STATUS +; CHECK FOR KEY PRESS, SAVE RAW VALUE ; H8P_STAT: - XOR A ; ZERO KEYS PENDING (FOR NOW) + IN A,(H8FPIO) + LD (H8P_KEYBUF),A RET ; -; WAIT FOR A DSKY KEYPRESS AND RETURN +; GET KEY AND RESET KEYBUF ; H8P_GETKEY: - ; PUT KEY VALUE IN REGISTER E - XOR A ; SIGNAL SUCCESS + LD A,(H8P_KEYBUF) RET ; -; DISPLAY HEX VALUE FROM DE:HL +H8P_KEYPAD: + CALL H8P_GETKEY + LD C,A + LD A,(H8P_LSTKEY) + CP C + RET Z + LD A,C + LD (H8P_LSTKEY),A + CP H8PKEYNONE + RET Z + LD HL,$04 + LD (H8P_HORNDUR),HL + CP H8PKEYDIV ; / KEY (ALTER) + JP Z,H8P_KEYPADALT + CP H8PKEYMUL ; * KEY (CANCEL) + JP Z,H8P_KEYPADCAN + CP H8PKEYNUM ; MEM KEY + JP Z,H8P_KEYPADMEM + CP H8PKEYDOT ; REG KEY + JP Z,H8P_KEYPADREG + CP H8PKEY9 + JP Z,H8P_KEYPAD9 + CP H8PKEY8 + JP Z,H8P_KEYPAD8 + CP H8PKEY7 + JP Z,H8P_KEYPAD7 + CP H8PKEY6 + JP Z,H8P_KEYPAD6 + CP H8PKEY5 + JP Z,H8P_KEYPAD5 + CP H8PKEY4 + JP Z,H8P_KEYPAD4 + CP H8PKEY3 + JP Z,H8P_KEYPAD3 + CP H8PKEY2 + JP Z,H8P_KEYPAD2 + CP H8PKEY1 + JP Z,H8P_KEYPAD1 + CP H8PKEY0 + JP Z,H8P_KEYPAD0 + CP H8PKEYPLUS + JP Z,H8P_KEYPADPLUS + CP H8PKEYMINUS + JP Z,H8P_KEYPADMINUS + RET +; RESET TIMER +H8P_KEYPADALT: + LD A,(H8P_FPENA) + OR A + RET Z + LD A,(H8P_STATE) + OR A + RET NZ + XOR A + LD C,9 + LD HL,H8P_UPTDIG +H8P_KEYPADALTL: + LD (HL),A + INC HL + DEC C + JR NZ,H8P_KEYPADALTL + RET +; ENABLE FRONT PANEL DISPLAY +H8P_KEYPADCAN: + LD A,(H8P_FPENA) + CPL + LD (H8P_FPENA),A + RET +; SET MEM STATE +H8P_KEYPADMEM: + LD A,2 + LD (H8P_STATE),A + LD (H8P_MEMENTER),A + XOR A + LD (H8P_MEMADRIDX),A + CALL H8P_UPDMEMLOC + RET +; SET REG STATE +H8P_KEYPADREG: + LD A,1 + LD (H8P_STATE),A + XOR A + LD (H8P_MEMENTER),A + RET +; NOTHING +H8P_KEYPAD9: +; RET +; TIMER +H8P_KEYPAD8: + LD A,(H8P_STATE) + CP 2 + RET Z + LD A,0 + LD (H8P_STATE),A + RET +; SPEED CONTROL +H8P_KEYPAD7: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + LD A,7 + JP Z,H8P_KEYPADDIG + LD A,3 + LD (H8P_STATE),A + RET +; PC (OUT) +H8P_KEYPAD6: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + LD A,6 + JP Z,H8P_KEYPADDIG + LD A,5 + LD (H8P_REGNUM),A + RET +; HL (IN) +H8P_KEYPAD5: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + LD A,5 + JP Z,H8P_KEYPADDIG + LD A,3 + LD (H8P_REGNUM),A + RET +; DE +H8P_KEYPAD4: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + LD A,4 + JP Z,H8P_KEYPADDIG + LD A,2 + LD (H8P_REGNUM),A + RET +; BC +H8P_KEYPAD3: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + LD A,3 + JP Z,H8P_KEYPADDIG + LD A,1 + LD (H8P_REGNUM),A + RET +; AF +H8P_KEYPAD2: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + LD A,2 + JP Z,H8P_KEYPADDIG + LD A,0 + LD (H8P_REGNUM),A + RET +; SP +H8P_KEYPAD1: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + LD A,1 + JP Z,H8P_KEYPADDIG + LD A,4 + LD (H8P_REGNUM),A + RET +; NOTHING +H8P_KEYPAD0: + LD A,(H8P_STATE) + CP 2 ; MEM MODE + JP NZ,H8P_KEYPAD8 + LD A,0 +; +H8P_KEYPADDIG: + LD C,A + LD A,(H8P_MEMENTER) + OR A + JR Z,H8P_KEYPADDIG1 + LD A,(H8P_MEMADRIDX) + OR A + CALL Z,H8P_SETDIG0 + DEC A + CALL Z,H8P_SETDIG1 + DEC A + CALL Z,H8P_SETDIG2 + DEC A + CALL Z,H8P_SETDIG3 + DEC A + CALL Z,H8P_SETDIG4 + DEC A + CALL Z,H8P_SETDIG5 + CALL H8P_UPDMEMLOC +; NEXT MEMORY ADR INDEX + LD A,(H8P_MEMADRIDX) + INC A + LD (H8P_MEMADRIDX),A + CP 6 + RET NZ + XOR A + LD (H8P_MEMADRIDX),A + RET +; CHECK FOR IN/OUT TO PORT +H8P_KEYPADDIG1: + LD A,C + CP 5 ; IN PORT + JR Z,H8P_KEYPADINP + CP 6 ; OUT PORT + JR Z,H8P_KEYPADOUT + RET +H8P_KEYPADINP: + LD BC,(H8P_MEMLOC) + IN A,(C) + LD B,A + LD (H8P_MEMLOC),BC + JP H8P_UPDMEMLOC +H8P_KEYPADOUT: + LD BC,(H8P_MEMLOC) + LD A,B + OUT (C),A + RET +H8P_UPDMEMLOC: + LD BC,H8P_MEMLOC + LD HL,H8P_SEGBUF + CALL H8P_FILLOCT + RET +; C=VAL +H8P_SETDIG0: + LD HL,(H8P_MEMLOC) + LD B,H + CALL H8P_SETOCTH + LD H,A + LD (H8P_MEMLOC),HL + LD A,$FF + RET +H8P_SETDIG1: + LD HL,(H8P_MEMLOC) + LD B,H + CALL H8P_SETOCTM + LD H,A + LD (H8P_MEMLOC),HL + LD A,$FF + RET +H8P_SETDIG2: + LD HL,(H8P_MEMLOC) + LD B,H + CALL H8P_SETOCTL + LD H,A + LD (H8P_MEMLOC),HL + LD A,$FF + RET +H8P_SETDIG3: + LD HL,(H8P_MEMLOC) + LD B,L + CALL H8P_SETOCTH + LD L,A + LD (H8P_MEMLOC),HL + LD A,$FF + RET +H8P_SETDIG4: + LD HL,(H8P_MEMLOC) + LD B,L + CALL H8P_SETOCTM + LD L,A + LD (H8P_MEMLOC),HL + LD A,$FF + RET +H8P_SETDIG5: + LD HL,(H8P_MEMLOC) + LD B,L + CALL H8P_SETOCTL + LD L,A + LD (H8P_MEMLOC),HL + XOR A + LD (H8P_MEMENTER),A + LD A,$FF + RET +H8P_SETDIGD: + LD A,(H8P_MEMVAL) + PUSH AF + CALL H8P_GETOCTH + LD (H8P_SEGBUF+6),A + POP AF + PUSH AF + CALL H8P_GETOCTM + LD (H8P_SEGBUF+7),A + POP AF + CALL H8P_GETOCTL + LD (H8P_SEGBUF+8),A + RET +; MEM/SPEED INCREASE +H8P_KEYPADPLUS: + LD A,(H8P_STATE) + CP 3 + JR Z,H8P_KEYPADPLUS3 + CP 2 + RET NZ + LD HL,(H8P_MEMLOC) + INC HL + LD (H8P_MEMLOC),HL + JP H8P_UPDMEMLOC +H8P_KEYPADPLUS3: + LD A,(H8P_SPEED) + OR A + RET Z + DEC A + ;;;LD (H8P_SPEED),A + ;;;OUT (H8P_SPDIO),A + ;;;RET + ; EXIT VIA HBIOS SPEED CHANGE, W/ L=NEW SPEED + JP H8P_SETSPD ; SEE HBIOS.ASM +; MEM/SPEED DECREASE +H8P_KEYPADMINUS: + LD A,(H8P_STATE) + CP 3 + JR Z,H8P_KEYPADMINUS3 + CP 2 + RET NZ + LD HL,(H8P_MEMLOC) + DEC HL + LD (H8P_MEMLOC),HL + JP H8P_UPDMEMLOC +H8P_KEYPADMINUS3: + LD A,(H8P_SPEED) + CP 3 + RET Z + INC A + ;;;LD (H8P_SPEED),A + ;;;OUT (H8P_SPDIO),A + ;;;RET + ; EXIT VIA HBIOS H8P SPEED CHANGE, W/ A=NEW SPEED + JP H8P_SETSPD ; SEE HBIOS.ASM +; +; HANDLE FRONT PANEL STATE +; +H8P_HDLSTATE: + LD A,(H8P_STATE) + OR A + RET Z ; UP-TIME TIMER + DEC A + JP Z,H8P_HDLREG ; SHOWING REGISTER VALUES + DEC A + JP Z,H8P_HDLMEM ; SHOWING MEMORY LOCATION VALUE + DEC A + JP Z,H8P_HDLSPD ; MODIFYING SPEED + RET ; -H8P_SHOWHEX: - LD BC,DSKY_HEXBUF ; POINT TO HEX BUFFER - CALL ST32 ; STORE 32-BIT BINARY THERE - LD HL,DSKY_HEXBUF ; FROM: BINARY VALUE (HL) - LD DE,DSKY_BUF ; TO: SEGMENT BUFFER (DE) - CALL DSKY_BIN2SEG ; CONVERT - LD HL,DSKY_BUF ; POINT TO SEGMENT BUFFER - ; AND FALL THRU TO DISPLAY IT +H8P_HDLREG: + LD A,(H8P_REGNUM) + LD HL,H8P_REGAF + OR A + JP Z,H8P_HDLREGAF + DEC A + LD HL,H8P_REGBC + JP Z,H8P_HDLREGBC + DEC A + LD HL,H8P_REGDE + JP Z,H8P_HDLREGDE + DEC A + LD HL,H8P_REGHL + JP Z,H8P_HDLREGHL + DEC A + LD HL,H8P_REGSP + JP Z,H8P_HDLREGSP + DEC A + LD HL,H8P_REGPC + JP Z,H8P_HDLREGPC + RET +H8P_HDLREGAF: + CALL H8P_UPDLEDS + LD HL,HBX_INTSTK + DEC HL + LD A,(HL) ; (HL)=AF LOW + LD (H8P_AFVAL),A + DEC HL + LD A,(HL) ; (HL)=AF HIGH + LD (H8P_AFVAL+1),A + LD BC,H8P_AFVAL + LD HL,H8P_SEGBUF + JP H8P_FILLOCT +H8P_HDLREGBC: + LD BC,H8P_BCVAL + CALL H8P_FILLOCT + JP H8P_UPDLEDS +H8P_HDLREGDE: + LD BC,H8P_DEVAL + CALL H8P_FILLOCT + JP H8P_UPDLEDS +H8P_HDLREGHL: + CALL H8P_UPDLEDS +; + ;;;LD HL,(HBX_INT_SP) + ;;;LD A,(HL) + ;;;LD (H8P_HLVAL),A + ;;;INC HL + ;;;LD A,(HL) + ;;;LD (H8P_HLVAL+1),A +; + LD A,(HB_CURBNK) ; GET PRE-INT BANK + LD D,A ; PUT IN D +; + ; HORRIBLE HACK TO MAKE PEEK RETURN TO OUR BANK!!! + PUSH AF ; SAVE ORIG HB_CURBNK + LD A,BID_BIOS ; MAKE IT OUR BANK + LD (HB_CURBNK),A ; OVERRIDE FOR PEEK +; + ; FOLLOW STACK TO GET PC, USE PEEK IN CASE STACK IN ALT BANK + LD HL,(HBX_INT_SP) ; PRE-INT SP HAS HL AT TOS + CALL HBX_PEEK ; GET LSB TO E + LD C,E ; PUT IN C + INC HL ; POINT TO MSB + CALL HBX_PEEK ; GET MSB TO E + LD B,E ; PUT IN B + LD (H8P_HLVAL),BC ; SAVE FOR DISPLAY +; + ; UNDO HACK!!! + POP AF ; RECOVER HB_CURBNK + LD (HB_CURBNK),A ; SAVE RESTORE IT +; + LD BC,H8P_HLVAL + LD HL,H8P_SEGBUF + JP H8P_FILLOCT +H8P_HDLREGSP: + CALL H8P_UPDLEDS + LD HL,(HBX_INT_SP) ; GET INT SAVED SP + INC HL ; BUMP TO VAL + INC HL ; ... OF SP + INC HL ; ... AT TIME + INC HL ; ... OF INTERRUPT + LD (H8P_SPVAL),HL ; SAVE FOR DISPLAY + LD BC,H8P_SPVAL + LD HL,H8P_SEGBUF + JP H8P_FILLOCT +H8P_HDLREGPC: + CALL H8P_UPDLEDS +; + ;;;LD HL,(HBX_INT_SP) ; (HL)=HL LOW + ;;;INC HL ; (HL)=HL HIGH + ;;;INC HL ; (HL)=PC LOW + ;;;LD A,(HL) + ;;;LD (H8P_PCVAL),A + ;;;INC HL ; (HL)=PC HIGH + ;;;LD A,(HL) + ;;;LD (H8P_PCVAL+1),A +; + LD A,(HB_CURBNK) ; GET PRE-INT BANK + LD D,A ; PUT IN D +; + ; HORRIBLE HACK TO MAKE PEEK RETURN TO OUR BANK!!! + PUSH AF ; SAVE ORIG HB_CURBNK + LD A,BID_BIOS ; MAKE IT OUR BANK + LD (HB_CURBNK),A ; OVERRIDE FOR PEEK +; + ; FOLLOW STACK TO GET PC, USE PEEK IN CASE STACK IN ALT BANK + LD HL,(HBX_INT_SP) ; PRE-INT SP + INC HL ; REMOVE 1 LEVEL TO + INC HL ; ... POINT TO PRE-INT PC + CALL HBX_PEEK ; GET LSB TO E + LD C,E ; PUT IN C + INC HL ; POINT TO MSB + CALL HBX_PEEK ; GET MSB TO E + LD B,E ; PUT IN B + LD (H8P_PCVAL),BC ; SAVE FOR DISPLAY +; + ; UNDO HACK!!! + POP AF ; RECOVER HB_CURBNK + LD (HB_CURBNK),A ; SAVE RESTORE IT +; + LD BC,H8P_PCVAL + LD HL,H8P_SEGBUF + JP H8P_FILLOCT +H8P_HDLMEM: + CALL H8P_SETDIGD + RET +H8P_HDLSPD: + LD HL,H8P_SPD16 + LD A,(H8P_SPEED) + OR A + JR Z,H8P_UPDLEDS + LD HL,H8P_SPD08 + DEC A + JR Z,H8P_UPDLEDS + LD HL,H8P_SPD04 + DEC A + JR Z,H8P_UPDLEDS + LD HL,H8P_SPD02 +H8P_UPDLEDS: + LD C,9 + LD DE,H8P_SEGBUF +H8P_UPDLEDS1: + LD A,(HL) + INC HL + LD (DE),A + INC DE + DEC C + JR NZ,H8P_UPDLEDS1 + RET ; -; DISPLAY BYTE VALUES POINTED TO BY DE. THE INCOMING BYTES ARE IN -; THE STANDARD ROMWBW SEGMENT ENCODING AND MUST BE TRANSLATED TO THE -; HEATH ENCODING (SEE ICM.ASM FOR EXAMPLE): +H8P_GETSEGIDX: + LD A,(H8P_SEGIDX) + DEC A + LD (H8P_SEGIDX),A + LD C,A + RET NZ + LD A,9 + LD (H8P_SEGIDX),A + LD C,A + RET ; +; A = SEG IDX ; -; From: To: -; +--01--+ +--02--+ -; 20 02 40 04 -; +--40--+ +--01--+ -; 10 04 20 08 -; +--08--+ 80 +--10--+ 80 +; +--02--+ +; 40 04 +; +--01--+ +; 20 08 +; +--10--+ 80 ; -H8P_SHOWSEG: - XOR A ; SIGNAL SUCCESS +H8P_GETSEGPAT: + LD A,C + AND $0F ; IDX=1 THRU 9 + DEC A + LD C,A + LD B,0 + LD HL,H8P_SEGBUF + ADD HL,BC + LD E,(HL) + LD A,(H8P_MEMENTER) + OR A + JR Z,H8P_GETSEGPATX + LD A,(H8P_MEMADRIDX) + CP C + JR NZ,H8P_GETSEGPATX + LD A,$80 + OR E + LD E,A +H8P_GETSEGPATX: + LD A,E + CPL RET -; -; UPDATE KEY LEDS (H8 HAS NONE) -; -H8P_KEYLEDS: - XOR A ; SIGNAL SUCCESS +; BC=MEMLOC, HL=LED BUFFER +H8P_FILLOCT: + PUSH HL + INC BC ; POINT TO HIGH BYTE + LD A,(BC) + CALL H8P_GETOCTH + LD (HL),A + INC HL + LD A,(BC) + CALL H8P_GETOCTM + LD (HL),A + INC HL + LD A,(BC) + CALL H8P_GETOCTL + LD (HL),A + INC HL + DEC BC ; POINT TO LOW BYTE + LD A,(BC) + CALL H8P_GETOCTH + LD (HL),A + INC HL + LD A,(BC) + CALL H8P_GETOCTM + LD (HL),A + INC HL + LD A,(BC) + CALL H8P_GETOCTL + LD (HL),A + POP HL RET -; -; SET STATUS LEDS BASED ON BITS IN E -; -H8P_STATLED: - XOR A ; SIGNAL SUCCESS +; HIGH OCTAL BITS +H8P_GETOCTH: + AND $C0 + RRA + RRA + RRA + RRA + RRA + RRA + JR H8P_GETOCTX +; MEDIUM OCTAL BITS +H8P_GETOCTM: + AND $38 + RRA + RRA + RRA + JR H8P_GETOCTX +; LOW OCTAL BITS +H8P_GETOCTL: + AND $07 +H8P_GETOCTX: + PUSH HL + LD E,A + LD D,0 + LD HL,H8P_DIGMAP + ADD HL,DE + LD A,(HL) ; VALUE CONVERTED TO LED SEGMENT PATTERN + POP HL + RET +; B=CURVAL, C=NEWVAL +H8P_SETOCTH: + LD A,C + AND $03 + RLA + RLA + RLA + RLA + RLA + RLA + LD C,A + LD A,B + AND $3F + OR C + RET +H8P_SETOCTM: + LD A,C + AND $07 + RLA + RLA + RLA + LD C,A + LD A,B + AND $C7 + OR C + RET +H8P_SETOCTL: + LD A,C + AND $07 + LD C,A + LD A,B + AND $F8 + OR C + CALL H8P_BEEP RET -; -; BEEP THE SPEAKER ON THE H8P ; H8P_BEEP: - POP BC - XOR A ; SIGNAL SUCCESS + PUSH HL + LD HL,16 + LD (H8P_HORNDUR),HL + POP HL RET ; ; DEVICE INFORMATION ; H8P_DEVICE: - LD D,DSKYDEV_H8P ; D := DEVICE TYPE +; LD D,DSKYDEV_H8P ; D := DEVICE TYPE LD E,0 ; E := PHYSICAL DEVICE NUMBER LD H,0 ; H := MODE - LD L,0 ; L := BASE I/O ADDRESS + LD L,H8FPIO ; L := BASE I/O ADDRESS XOR A ; SIGNAL SUCCESS RET ; -;_KEYMAP_TABLE_____________________________________________________________________________________________________________ -; -H8P_KEYMAP: ; *** NEEDS TO BE UPDATED *** - ; POS $00 $01 $02 $03 $04 $05 $06 $07 - ; KEY [0] [1] [2] [3] [4] [5] [6] [7] - .DB $0D, $04, $0C, $14, $03, $0B, $13, $02 -; - ; POS $08 $09 $0A $0B $0C $0D $0E $0F - ; KEY [8] [9] [A] [B] [C] [D] [E] [F] - .DB $0A, $12, $01, $09, $11, $00, $08, $10 +; DIGITS TO LED PATTERNS +; +--02--+ +; 40 04 +; +--01--+ +; 20 08 +; +--10--+ 80 ; - ; POS $10 $11 $12 $13 $14 $15 $16 $17 - ; KEY [FW] [BK] [CL] [EN] [DE] [EX] [GO] [BO] - .DB $05, $15, $1D, $1C, $1B, $1A, $19, $18 - - ; POS $18 $19 $1A $1B - ; KEY [F4] [F3] [F2] [F1] - .DB $23, $22, $21, $20 +H8P_DIGMAP: + ; 0 1 2 3 4 5 6 7 + .DB $7E, $0C, $37, $1F, $4D, $5B, $7B, $0E + ; 8 9 A B C D E F + .DB $7F, $5F, $6F, $79, $72, $3D, $73, $63 +; +H8P_REGNUM: + .DB 0 +H8P_REGAF: + .DB $00, $00, $00, $00, $00, $00, $00, $6F, $63 +H8P_REGBC: + .DB $00, $00, $00, $00, $00, $00, $00, $79, $72 +H8P_REGDE: + .DB $00, $00, $00, $00, $00, $00, $00, $3D, $73 +H8P_REGHL: + .DB $00, $00, $00, $00, $00, $00, $00, $6D, $70 +H8P_REGSP: + .DB $00, $00, $00, $00, $00, $00, $00, $5B, $67 +H8P_REGPC: + .DB $00, $00, $00, $00, $00, $00, $00, $67, $72 +H8P_SPD16: + .DB $00, $00, $00, $00, $0C, $7B, $5B, $67, $3D +H8P_SPD08: + .DB $00, $00, $00, $00, $00, $7F, $5B, $67, $3D +H8P_SPD04: + .DB $00, $00, $00, $00, $00, $4D, $5B, $67, $3D +H8P_SPD02: + .DB $00, $00, $00, $00, $00, $37, $5B, $67, $3D +H8P_MEMADRIDX: + .DB 0 +H8P_MEMENTER: + .DB 0 +H8P_SPVAL: + .DW 0 +H8P_AFVAL: + .DW 0 +H8P_BCVAL: + .DW 0 +H8P_DEVAL: + .DW 0 +H8P_HLVAL: + .DW 0 +H8P_PCVAL: + .DW 0 +; +H8P_STATE: + .DB 00 +H8P_STTIMER: + .DB 00 +H8P_FPENA: + .DB $FF +H8P_SEGIDX: + .DB 09 +H8P_HBTICK: + .DB 00 +H8P_KEYBUF: + .DB 00 +H8P_LSTKEY: + .DB 00 +H8P_SEGBUF: + .DB $FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF +H8P_HORNDUR: + .DW $0080 +H8P_ONESEC: + .DW 500 +H8P_UPTIME: + .DW 0 +H8P_UPTDIG: + .DB 0,0,0,0,0,0,0,0,0 diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm index 333c19cd..c53416ed 100644 --- a/Source/HBIOS/hbios.asm +++ b/Source/HBIOS/hbios.asm @@ -46,28 +46,29 @@ ; ; INCLUDE FILE NESTING: ; -; hbios.asm -; - std.asm -; - ver.inc -; - hbios.inc -; - build.inc -; - config/_.asm -; - cfg_.asm -; - [z180.inc|z280.inc] -; - [eipc.inc] -; - .asm -; - .asm -; - util.asm -; - time.asm -; - bcd.asm -; - decode.asm -; - encode.asm -; - [xio|mio].asm -; - unlzsa2s.asm +; - std.asm +; - ../ver.inc +; - build.inc +; - Config/_std.asm +; - cfg_.asm +; - cfg_MASTER.asm +; - hbios.inc +; - [z180.inc] +; - [z280.inc] +; - [eipc.inc] +; - util.asm +; - time.asm +; - bcd.asm +; - decode.asm +; - encode.asm +; - [xio.asm] +; - [mio.asm] +; - [unlzsa2s.asm] +; - .asm +; - .asm ; ; MEMORY LAYOUT: ; -; ; DESCRIPTION START LENGTH ; ----------------------------- ------- ------- ; Page Zero 0x0000 0x0100 @@ -97,7 +98,7 @@ ; D4 ~PSG_RES ~PSG_RES ~PSG_RES ROM_A19 ~PSG_RES ; D3 STATUS_LED STATUS_LED VDP_LED PSG_LED ROM_A18 PSG_LED ; D2 VDP_A14 VDP_A14 ROM_A17 VDP_LED -; D1 ~VDP_SYN ~VDP_SYN ROM_A16 +; D1 ~VDP_SYN ~VDP_SYN ROM_A16 ; D0 ~VDP_RES ~VDP_RES VDP_RES ROM_A15 VDP_RES ; ; PORT SCG:0x9C 0x94 VDP:0x92 PSG:0xA2 0x80 MEDIA:0xA6 @@ -164,7 +165,10 @@ SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT #IF (FPLED_ENABLE) #DEFINE FPLEDS(N) PUSH AF #DEFCONT \ LD A,N - #DEFCONT \ CALL FP_SETLEDS + #IF (FPLED_INV) + #DEFCONT \ XOR $FF ; INVERT BITS IF NEEDED + #ENDIF + #DEFCONT \ OUT (FPLED_IO),A #DEFCONT \ POP AF #ELSE #DEFINE FPLEDS(N) \; @@ -173,14 +177,14 @@ SUPCTS .EQU FALSE ; SUPPRESS CTS DURING HBIOS BOOT ; SET DIAGNOSTIC LEDS ; ; SCxxx: LED Port=0x0E, bit 2, inverted, dedicated port (LEDMODE_SC) -; SC7xx: LED Port=0x0E, bit 0, inverted, dedicated port (LEDMODE_STD) +; SC7xx/SC5xx: LED Port=0x0E, bit 0, inverted, dedicated port (LEDMODE_STD) ; TinyZ80: LED Port=0x6E, bit 0, inverted, dedicated port (LEDMODE_STD) ; Z80-512K: LED Port=0x6E, bit 0, inverted, dedicated port (LEDMODE_STD) ; MBC: LED Port=0x70, bits 1-0, normal, shared w/ RTC port (LEDMODE_RTC) ; DUO: LED Port=0x94, bits 1-0, normal, shared w/ RTC port (LEDMODE_RTC) ; S100: LED Port = $0E, bit 2, inverted, dedicated port (LEDMODE_SC) ; NABU: LED Port = $00, bits 5-3, normal, shared w/ control port (LEDMODE_NABU) -; +; #IF (LEDENABLE) #IF (LEDMODE == LEDMODE_STD) #DEFINE DIAG(N) PUSH AF @@ -637,7 +641,7 @@ HBX_ROM: #IF (PLATFORM == PLT_DUO) ADD A,64 ; ADD 64 x 32K - RAM STARTS FROM 2048K #ELSE - ADD A,16 ; ADD 16 x 32K - RAM STARTS FROM 512K + ADD A,ROMSIZE / 32 ; STARTING RAM BANK NUMBER OFFSET #ENDIF ; HBX_ROM: @@ -1032,7 +1036,8 @@ HBX_BNKCALL_ADR: ; HBX_PEEK: LD (HBX_PPSP),SP ; SAVE ORIGINAL STACK FRAME - LD SP,HBX_BUF_END ; BORROW HBX_BUF FOR TEMP STACK + ;;;LD SP,HBX_BUF_END ; BORROW HBX_BUF FOR TEMP STACK + LD SP,HBX_BUF_END - $20 ; BORROW HBX_BUF FOR TEMP STACK LD A,(HB_CURBNK) PUSH AF LD A,D @@ -1042,7 +1047,8 @@ HBX_PEEK: ; HBX_POKE: LD (HBX_PPSP),SP ; SAVE ORIGINAL STACK FRAME - LD SP,HBX_BUF_END ; BORROW HBX_BUF FOR TEMP STACK + ;;;LD SP,HBX_BUF_END ; BORROW HBX_BUF FOR TEMP STACK + LD SP,HBX_BUF_END - $20 ; BORROW HBX_BUF FOR TEMP STACK LD A,(HB_CURBNK) PUSH AF LD A,D @@ -1064,6 +1070,22 @@ HBX_PPSP .EQU $ - 2 ; #IF (MEMMGR != MM_Z280) ; +; HEATH FRONT PANEL WORK SPACE (4 BYTES) +; + #IF (H8PENABLE) +H8P_MEMLOC: + .DW 0 +H8P_MEMVAL: + .DB 0 +H8P_MEMCPY: + LD HL,(H8P_TICCNT) + LD ($000B),HL + LD HL,(H8P_MEMLOC) + LD A,(HL) + LD (H8P_MEMVAL),A + RET + #ENDIF +; HBX_INTSTKSIZ .EQU $FF00 - $ MEMECHO "HBIOS INT STACK space: " MEMECHO HBX_INTSTKSIZ @@ -1080,23 +1102,23 @@ HBX_INTSTK .EQU $ ; ; HBIOS INTERRUPT MODE 2 SLOT ASSIGNMENTS (SEE STD.ASM) ; -; # Z80/Z280 Z180 MBC DUO NABU -; --- -------------- -------------- -------------- -------------- -------------- -; 0 CTC0A INT1 -+ -+ -+ HCCARCV -+ -; 1 CTC0B INT2 | | | HCCASND | -; 2 CTC0C TIM0 | | IM2 | IM2 NABUKB | IM2 -; 3 CTC0D TIM1 | | INT | INT VDP | INT -; 4 UART0 DMA0 | Z180 UART0 | VEC UART0 | VEC OPTCRD0 | VEC -; 5 UART1 DMA1 | CPU UART1 | GEN UART1 | GEN OPTCRD1 | GEN -; 6 CSIO | | | OPTCRD2 | -; 7 SIO0 SER0 | -+ -+ OPTCRD3 -+ -; 8 SIO1 SER1 -+ SIO0 SIO0 -; 9 PIO0A PIO0A SIO1 SIO1 -; 10 PIO0B PIO0B PIO0A PIO0A -; 11 PIO1A PIO1A PIO0B PIO0B -; 12 PIO1B PIO1B CTC0A CTC0A -; 13 SIO0 CTC0B CTC0B -; 14 SIO1 CTC0C CTC0C +; # Z80/Z280 Z180 MBC DUO NABU +; --- -------------- -------------- -------------- -------------- -------------- +; 0 CTC0A INT1 -+ -+ -+ HCCARCV -+ +; 1 CTC0B INT2 | | | HCCASND | +; 2 CTC0C TIM0 | | IM2 | IM2 NABUKB | IM2 +; 3 CTC0D TIM1 | | INT | INT VDP | INT +; 4 UART0 DMA0 | Z180 UART0 | VEC UART0 | VEC OPTCRD0 | VEC +; 5 UART1 DMA1 | CPU UART1 | GEN UART1 | GEN OPTCRD1 | GEN +; 6 CSIO | | | OPTCRD2 | +; 7 SIO0 SER0 | -+ -+ OPTCRD3 -+ +; 8 SIO1 SER1 -+ SIO0 SIO0 +; 9 PIO0A PIO0A SIO1 SIO1 +; 10 PIO0B PIO0B PIO0A PIO0A +; 11 PIO1A PIO1A PIO0B PIO0B +; 12 PIO1B PIO1B CTC0A CTC0A +; 13 SIO0 CTC0B CTC0B +; 14 SIO1 CTC0C CTC0C ; 15 CTC0D CTC0D ; ; IVT MUST START AT PAGE BOUNDARY @@ -1207,6 +1229,10 @@ HBX_RETI: ; LD A,(HB_CURBNK) ; GET PRE-INT BANK CALL HBX_BNKSEL ; SELECT IT +; + #IF (H8PENABLE) + CALL H8P_MEMCPY + #ENDIF ; ; RESTORE STATE POP IY ; RESTORE IY @@ -1490,7 +1516,7 @@ BOOTWAIT: LD C,Z280_MSR ; MASTER STATUS REGISTER LD HL,$0000 ; SYS MODE, NO INTERRUPTS LDCTL (C),HL ; DO IT -; +; ; SET MAXIMUM I/O WAIT STATES FOR NOW LD C,Z280_BTCR ; BUS TIMING AND CONTROL REGISTER LD HL,$0033 ; 3 I/O WAIT STATES ADDED @@ -1659,6 +1685,14 @@ Z280_INITZ: OUT (EIPC_SCDP),A ; SET SYSTEM CONTROL DATA PORT (SCDP) #ENDIF ; +; HEATH BARE METAL INIT +; +#IF (PLATFORM == PLT_HEATH) + XOR A ; 16 MHZ OPERATION? + OUT (H8P_SPDIO),A ; IMPLEMENT IT + LD (H8P_SPEED),A ; UPDATE FP SHADOW +#ENDIF +; ;-------------------------------------------------------------------------------------------------- ; PLATFORM MEMORY MANAGEMENT INITIALIZATION ;-------------------------------------------------------------------------------------------------- @@ -1747,7 +1781,8 @@ ROMRESUME: #ELSE ; NORMAL ZETA 2 SYSTEM HAS FIXED 512K OF RAM. SETUP COMMON ; FOR TOP 32K OF THIS. - LD A,64 - 2 + ;LD A,64 - 2 + LD A,((ROMSIZE + RAMSIZE) / 16) - 2 #ENDIF ; EZ80_IO() @@ -1759,6 +1794,12 @@ ROMRESUME: LD A,1 EZ80_IO() OUT (MPGENA),A ; ENABLE MMU NOW +; + #IF (PLATFORM == PLT_FZ80) + ; REMOVE FPGA ROM MONITOR FROM THE CPU ADDRESS SPACE + LD A,%00000010 + OUT ($07),A + #ENDIF #ENDIF ; @@ -1771,7 +1812,7 @@ ROMRESUME: ; ; WE USE THE TWO BYTES IMMEDIATELY BELOW THE PROXY TO STORE A COUPLE ; VALUES TEMPORARILY BECAUSE WE MAY BE OPERATING IN ROM AT THIS POINT. -; (HBX_LOC - 1) = BATCOND, (HBX_LOC - 2) = APPBANK +; (HBX_LOC - 1) = BATCOND, (HBX_LOC - 2) = LOADBANK ; THERE IS NOTHING ON THE STACK AT THIS POINT SO, HERE, WE JUST RESET ; THE STACK TO HBX_LOC - 2. ; @@ -1793,7 +1834,7 @@ ROMRESUME: XOR A ; ZERO MEANS LOW BAT LD (HL),A ; FIRST RAM ACCESS INC A ; 1 MEANS BAT OK - LD (HL),A ; SECOND RAM ACCESS (BLOLCKED IF BATTERY ISSUE) + LD (HL),A ; SECOND RAM ACCESS (BLOCKED IF BATTERY ISSUE) ; ; INSTALL PROXY IN UPPER MEMORY ; @@ -1895,23 +1936,23 @@ S100MON_SKIP: ; MBC BANK SELECT MASK SETUP ;-------------------------------------------------------------------------------------------------- ; -; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS. THE COMMON RAM BANK IS +; THE MBC RAM BOARD CAN CONTAIN 1 OR 2 RAM CHIPS. THE COMMON RAM BANK IS ; FIXED BY HARDWARE TO BE THE TOP 32K OF THE *FIRST* RAM CHIP. WHEN THERE -; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN -; THE MIDDLE OF PHYSICAL RAM. HBIOS REQUIRES THAT THE COMMON RAM BANK BE -; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM. THIS IS REQUIRED SO THAT -; THE RAM DISK BANKS CAN BE SEQUENTIAL. TO WORK AROUND THIS, WE USE AN -; XOR MASK THAT IS APPLIED DURING BANK SELECT. THIS MASK WILL FLIP THE -; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO -; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE +; ARE 2 RAM CHIPS INSTALLED, THE HARDWARE WILL THUS PLACE THE COMMON RAM IN +; THE MIDDLE OF PHYSICAL RAM. HBIOS REQUIRES THAT THE COMMON RAM BANK BE +; MAPPED TO THE VERY LAST 32K OF PHYSICAL RAM. THIS IS REQUIRED SO THAT +; THE RAM DISK BANKS CAN BE SEQUENTIAL. TO WORK AROUND THIS, WE USE AN +; XOR MASK THAT IS APPLIED DURING BANK SELECT. THIS MASK WILL FLIP THE +; HIGH ORDER BANK SELECT BIT (WHEN 2 RAM CHIPS ARE USED) SO THAT THE TWO +; RAM CHIPS WIND UP "REVERSED" AND THE FIXED COMMON BANK WINDS UP AT THE ; END OF THE RAM BANKS. THE MASK IS SETUP HERE BASED ON THE NUMBER OF RAM ; CHIPS AND THEIR SIZE. NOTE THAT THE NUMBER OF RAM CHIPS IS INFERRED BY ; THE TOTAL RAM SIZE. A SINGLE CHIP WILL BE EITHER 128K OR 512K. IF THE ; TOTAL RAM SIZE OF THE SYSTEM IS 256K OR 1M, THEN THERE MUST BE TWO CH -; IPS. THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK +; IPS. THE RESULTING BANK SELECT MASK IS INSERTED INTO THE MBC BANK ; SELECT ROUTINE. -; -#IF (MEMMGR == MM_MBC) +; +#IF (MEMMGR == MM_MBC) ; ; ALTHOUGH DYNAMIC SYSTEM RAM SIZING IS NOT POSSIBLE FOR MBC ; (SEE COMMENTS ABOVE), WE ARE STILL DOING THE MASK SETUP @@ -1945,6 +1986,7 @@ MBC_SINGLE: ; COPY OURSELVES TO HBIOS BANK IN RAM ; LD A,(HB_CURBNK) ; GET CURRENT BANK ID + LD (HBX_LOC - 2),A ; SAVE THE LOAD BANK ; ; CHECK TO SEE IF WE ARE ALREADY RUNNING IN THE HBIOS RAM ; BANK AND SKIP THE COPY IF SO (DON'T COPY OVER OURSELVES). @@ -1952,7 +1994,7 @@ MBC_SINGLE: ; FULL RESTART OF A SYSTEM USING THE EXISTING HBIOS COPY. ; NOTE THAT THIS TEST WORKS BECAUSE BID_BIOS == BID_BOOT ; IN THESE SCENARIOS. - CP BID_BIOS ; SAVE AS BIOS BANK? + CP BID_BIOS ; SAME AS BIOS BANK? JR Z,HB_START1 ; IF SO, SKIP ; LD (HB_SRCBNK),A ; CURRENT BANK IS SOURCE @@ -2009,11 +2051,96 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK LD A,H ; GET FIRST BYTE PUSHED LD (HB_BATCOND),A ; ... AND SAVE AS BAT COND ; -; IF APPBOOT, WE NEED TO FIX UP A FEW THINGS IN PAGE ZERO -; ;;; SHOULD THIS BE DONE FOR AN HBIOS RESTART IN PLACE??? +#IF FALSE +; +; POPULATE THE CRITICAL RAM BANK NUMBERS. +; +; ASSUME THAT CB_RAMBANKS IS THE NUMBER OF 32K RAM BANKS THAT HAS BEEN SET EITHER +; AT ASSEMBLY TIME OR BY PROBING THE ACTUAL AVAILABLE MEMORY (NOT IMPLEMENTED YET). +; + LD A,(CB_RAMBANKS) ; CALCULATE TOP RAMBANK + ADD A,BID_RAM0 ; AS FIRST RAMBANK + + DEC A ; #RAMBANKS - 1 +; + LD HL,CB_BIDCOM + LD B,4 +CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM + INC HL ; POPULATE CB_BIDUSR + DEC A ; POPULATE CB_BIDBIOS + DJNZ CB_IDS ; POPULATE CB_BIDAUX +; + LD A,(CB_BIDUSR) + LD (HB_SRCBNK),A ; POPULATE HB_SRCBNK + LD (HB_DSTBNK),A ; POPULATE HB_DSTBNK +; + LD A,BID_RAM0 ; POPULATE CB_BIDRAMD0 ; START RAMBANK + LD (HL),A + INC HL +; + LD A,(CB_RAMBANKS) ; POPULATE CB_BIDRAMDN ; END RAMBANK + DEC A + SUB TOT_RAM_RB + LD (HL),A +; +#ENDIF +; +;-------------------------------------------------------------------------------------------------- +; INTERRUPT MANAGEMENT SETUP +;-------------------------------------------------------------------------------------------------- +; +; SETUP INTERRUPT VECTOR TABLE ADDRESS(ES) AND TRANSITION TO +; OPERATING INTERRUPT MODE. NOTE THAT INTERRUPTS REMAIN +; DISABLED AT THIS POINT. +; +#IF (CPUFAM != CPU_EZ80) +#IF ((INTMODE == 2) | ((INTMODE == 1) & (CPUFAM == CPU_Z180))) + ; SETUP Z80 IVT AND INT MODE 2 + LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS + LD I,A ; ... AND PLACE IT IN I REGISTER + + #IF (CPUFAM == CPU_Z180) + ; SETUP Z180 IVT + XOR A ; SETUP LO BYTE OF IVT ADDRESS + OUT0 (Z180_IL),A ; ... AND PLACE IN Z180 IL REGISTER + #ENDIF + + #IF (INTMODE == 2) + IM 2 ; SWITCH TO INT MODE 2 + #ENDIF +#ENDIF +; +#IF (MEMMGR == MM_Z280) + ; NOW POINT TO RAM COPY OF Z280 INT/TRAP TABLE + ; HL IS TOP 16 BITS OF PHYSICAL ADDRESS OF IVT + ; IVT *MUST* BE ON A 4K BOUNDARY + LD C,Z280_VPR + LD HL,0 + (((PBANK(BID_BIOS) << 15) + Z280_IVT) >> 8) + LDCTL (C),HL +#ENDIF +; +#IF (INTMODE == 3) +; + ; SETUP Z280 INT A FOR VECTORED INTERRUPTS + LD HL,%0010000000000000 + LD C,Z280_ISR + LDCTL (C),HL +; + ; TRANSITION TO INTERRUPT MODE 3 + IM 3 +; +#ENDIF +#ENDIF +; +;-------------------------------------------------------------------------------------------------- +; APPLICATION BOOT INITIALIZATION +;-------------------------------------------------------------------------------------------------- +; +; IF APPBOOT, WE NEED TO FIX UP A FEW THINGS IN PAGE ZERO AND +; COPY THE PAYLOAD CONTAINING ROMLDR, MONITOR, AND ZSDOS TO AUX BANK. ; #IFDEF APPBOOT ; + ;;; SHOULD THIS BE DONE FOR AN HBIOS RESTART IN PLACE??? ; MAKE SURE RST 08 VECTOR IS RIGHT LD A,$C3 LD ($0008),A @@ -2037,40 +2164,37 @@ HB_START1: ; BNKCALL ARRIVES HERE, BUT NOW RUNNING IN RAM BANK INC HL LD (HL),$4D #ENDIF -#ENDIF -; -#IF FALSE -; -; POPULATE THE CRITICAL RAM BANK NUMBERS. -; -; ASSUME THAT CB_RAMBANKS IS THE NUMBER OF 32K RAM BANKS THAT HAS BEEN SET EITHER -; AT ASSEMBLY TIME OR BY PROBING THE ACTUAL AVAILABLE MEMORY (NOT IMPLEMENTED YET). ; - LD A,(CB_RAMBANKS) ; CALCULATE TOP RAMBANK - ADD A,BID_RAM0 ; AS FIRST RAMBANK + - DEC A ; #RAMBANKS - 1 + ; CHECK TO SEE IF THIS IS AN IN-PLACE RESTART. IF SO, + ; WE NEED TO SKIP THE COPY OF THE CONCATENATED OS IMAGES BELOW. + LD A,(HB_RAMFLAG) ; GET THE FLAG + OR A ; TEST IT + JR NZ,HB_START2 ; IF SET, SKIP + DEC A ; SET FLAG + LD (HB_RAMFLAG),A ; SAVE IT ; - LD HL,CB_BIDCOM - LD B,4 -CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM - INC HL ; POPULATE CB_BIDUSR - DEC A ; POPULATE CB_BIDBIOS - DJNZ CB_IDS ; POPULATE CB_BIDAUX + ; FOR AN APPLICATION BOOT, WE ALSO COPY THE CONCATENATED OS + ; IMAGES TO THE AUX BANK WHERE WE WILL JUMP TO ROMLDR LATER. + LD A,(HB_CURBNK) ; GET CURRENT BANK ID + LD (HB_SRCBNK),A ; SETUP SOURCE BANK + LD A,BID_AUX ; DEST BANK IS AUX BANK + LD (HB_DSTBNK),A ; SETUP DESTINATION BANK + LD HL,HB_END ; COPY FROM END OF HBIOS + LD DE,0 ; TO START OF TARGET BANK + LD BC,$8000 ; COPY ENTIRE 32KB BANK + CALL HBX_BNKCPY ; ELSE NORMAL BANK COPY + JR HB_START2 ; CONTINUE ; - LD A,(CB_BIDUSR) - LD (HB_SRCBNK),A ; POPULATE HB_SRCBNK - LD (HB_DSTBNK),A ; POPULATE HB_DSTBNK +;;; RELOCATE THIS DATA FIELD +HB_RAMFLAG .DB $00 ; - LD A,BID_RAM0 ; POPULATE CB_BIDRAMD0 ; START RAMBANK - LD (HL),A - INC HL +#ENDIF ; - LD A,(CB_RAMBANKS) ; POPULATE CB_BIDRAMDN ; END RAMBANK - DEC A - SUB TOT_RAM_RB - LD (HL),A +HB_START2: ; -#ENDIF +;-------------------------------------------------------------------------------------------------- +; GENERAL HBIOS INITIALIZATION +;-------------------------------------------------------------------------------------------------- ; ; CLEAR DISPATCH TABLE ENTRIES ; @@ -2082,6 +2206,11 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM LD (RTC_DISPACT),A ; RTC DEVICE LD (DSKY_DISPACT),A ; DSKY DEVICE ; +; INITIALIZE SOME HCB ENTRIES +; + OR $FF ; $FF TO ACCUM + LD (CB_CRTDEV),A ; RESET CRT DEVICE +; ; CLEAR INTERRUPT VECTOR TABLES ; ; THIS IS REALLY ONLY REQUIRED ON A RESTART, BUT IT DOESN'T HURT TO @@ -2097,12 +2226,12 @@ CB_IDS: LD (HL),A ; POPULATE CB_BIDCOM LD (HB_IM1CNT),A ; ... TO CLEAR IM1 VECTOR CNT LD HL,HB_IM1INT ; POINTER TO START OF IM1 IVT LD (HB_IM1PTR),HL ; ... TO CLEAR IM1 PTR - + LD HL,HB_TICK LD (VEC_TICK + 1),HL LD HL,HB_SECOND LD (VEC_SECOND + 1),HL - + JR HB_CLRIVT_Z ; DONE, JUMP OVER SUBROUTINE ; HB_CLRIVT: @@ -2221,9 +2350,6 @@ HB_CPU1: #IF (PKDENABLE) CALL PKD_PREINIT #ENDIF - #IF (H8PENABLE) - CALL H8P_PREINIT - #ENDIF ; ; ANNOUNCE OURSELVES ON DSKY LD HL,MSG_HBVER + 5 @@ -2241,6 +2367,15 @@ HB_CPU1: LD B,BF_DSKYSHOWSEG CALL DSKY_DISPATCH #ENDIF +#IF (LCDENABLE) + CALL LCD_PREINIT +#ENDIF +#IF (H8PENABLE) + CALL H8P_PREINIT +#ENDIF +#IF (GM7303ENABLE) + CALL GM7303_PREINIT +#ENDIF ; FPLEDS(DIAG_05) ; @@ -2319,7 +2454,7 @@ HB_CPU2: ; ADJUST HL TO REFLECT HALF SPEED OPERATION SRL H ; ADJUST HL ASSUMING RR L ; HALF SPEED OPERATION -; +; #IF (Z180_CLKDIV >= 1) LD A,(HB_CPUTYPE) ; GET CPU TYPE CP 2 ; Z8S180 REV K OR BETTER? @@ -2438,55 +2573,6 @@ HB_CPU3: CALL DELAY_INIT ; .. SPEED COMPENSATED DELAY ; ;-------------------------------------------------------------------------------------------------- -; INTERRUPT MANAGEMENT SETUP -;-------------------------------------------------------------------------------------------------- -; -; SETUP INTERRUPT VECTOR TABLE ADDRESS(ES) AND TRANSITION TO -; OPERATING INTERRUPT MODE. NOTE THAT INTERRUPTS REMAIN -; DISABLED AT THIS POINT. -; -#IF (CPUFAM != CPU_EZ80) -#IF ((INTMODE == 2) | ((INTMODE == 1) & (CPUFAM == CPU_Z180))) - ; SETUP Z80 IVT AND INT MODE 2 - LD A,HBX_IVT >> 8 ; SETUP HI BYTE OF IVT ADDRESS - LD I,A ; ... AND PLACE IT IN I REGISTER - - #IF (CPUFAM == CPU_Z180) - ; SETUP Z180 IVT - XOR A ; SETUP LO BYTE OF IVT ADDRESS - OUT0 (Z180_IL),A ; ... AND PLACE IN Z180 IL REGISTER - #ENDIF - - #IF (INTMODE == 2) - IM 2 ; SWITCH TO INT MODE 2 - #ENDIF -#ENDIF -#ENDIF -; -#IF (MEMMGR == MM_Z280) - ; NOW POINT TO RAM COPY OF Z280 INT/TRAP TABLE - ; HL IS TOP 16 BITS OF PHYSICAL ADDRESS OF IVT - ; IVT *MUST* BE ON A 4K BOUNDARY - LD C,Z280_VPR - LD HL,0 + (((PBANK(BID_BIOS) << 15) + Z280_IVT) >> 8) - LDCTL (C),HL -#ENDIF -; -#IF (CPUFAM != CPU_EZ80) -#IF (INTMODE == 3) -; - ; SETUP Z280 INT A FOR VECTORED INTERRUPTS - LD HL,%0010000000000000 - LD C,Z280_ISR - LDCTL (C),HL -; - ; TRANSITION TO INTERRUPT MODE 3 - IM 3 -; -#ENDIF -#ENDIF -; -;-------------------------------------------------------------------------------------------------- ; SYSTEM TIMER INITIALIZATION ;-------------------------------------------------------------------------------------------------- ; @@ -3368,6 +3454,28 @@ HB_WDZ: JR NZ,INITSYS3 ; NOT SET, BYPASS CONSOLE SWITCH #ENDIF ; + #IF (PLATFORM == PLT_FZ80) + ; IOBYTE: XXXXXVVC + ; 00- FORCE ONBOARD VGA/PS2 KBD (FV) + ; --1 FORCE PROPELLER CONSOLE (SCON) + ; 110 NORMAL USB SERIAL BOOT + ; + ; WE ASSUME THAT THE ONBOARD VGA (FV) IS ALWAYS DETECTED AND + ; WILL BE THE CURRENT CRTDEV. SCON IS ASSUMED TO BE THE + ; DEVICE AT CRTDEV + 1. THESE ARE REASONABLE ASSUMPTIONS + ; UNLESS THE DRIVER DETECTION OR DRIVER ORDER IS CHANGED. + IN A,($36) ; GET IO BYTE + AND %00000110 ; ISOLATE BITS + JR Z,HB_CRTACT ; FORCE ONBOARD CRT + IN A,($36) ; GET IO BYTE + AND %00000001 ; ISOLATE BIT + JR Z,INITSYS3 ; NORMAL USB SERIAL BOOT + LD A,(CB_CRTDEV) ; GET CRT DEV + INC A ; SWITCH FROM FV -> SCON + LD (CB_CRTDEV),A ; SAVE IT AND DO CONSOLE SWITCH + #ENDIF +; +HB_CRTACT: LD A,(CB_CRTDEV) ; GET CRT DISPLAY DEVICE LD (HB_NEWCON),A ; AND QUEUE TO SWITCH ; @@ -3429,7 +3537,7 @@ HB_FP2: LD B,A ; MOVE TO B LD A,SECCON ; GET SEC CONSOLE SETTING CP $FF ; $FF MEANS USE INCREMENT - JR NZ,HB_FP3 ; BYPASS IF NOT $FF + JR NZ,HB_FP3 ; BYPASS IF NOT $FF ; ; INCREMENT CONSOLE UNIT LD A,(HB_NEWCON) ; GET NEW CONSOLE UNIT @@ -3597,11 +3705,12 @@ DBG_NOTE: ; #ENDIF ; -; DIAGNOSTIC ROUTINE TO PLAY A BEEP -; -#IFDEF TESTING - CALL SND_BEEP -#ENDIF + ; MAKE A LITTLE NOISE... + LD B,BF_SNDBEEP ; HBIOS BEEP FUNCTION + LD C,0 ; SOUND UNIT 0 + LD A,(SND_CNT) ; GET SOUND UNIT COUNT + OR A ; CHECK FOR ZERO + CALL NZ,HB_DISPATCH ; DO IT IF WE HAVE A SOUND UNIT ; ;-------------------------------------------------------------------------------------------------- ; TRANSITION TO USER LAND @@ -3678,6 +3787,9 @@ HB_INITRLEN .EQU (($ - HB_INIT_REC) / 2) ; HB_PCINITTBL: ; +#IF (SSERENABLE) + .DW SSER_PREINIT +#ENDIF #IF (ASCIENABLE) .DW ASCI_PREINIT #ENDIF @@ -3699,15 +3811,6 @@ HB_PCINITTBL: #IF (ACIAENABLE) .DW ACIA_PREINIT #ENDIF -#IF (PIOENABLE) - .DW PIO_PREINIT -#ENDIF -#IF LPTENABLE) - .DW LPT_PREINIT -#ENDIF -#IF (PIO_4P | PIO_ZP) - .DW PIO_PREINIT -#ENDIF #IF (UFENABLE) .DW UF_PREINIT #ENDIF @@ -3715,6 +3818,12 @@ HB_PCINITTBL: .DW TMS_PREINIT #ENDIF .DW TERM_PREINIT ; ALWAYS DO THIS ONE +#IF (PIOENABLE) + .DW PIO_PREINIT +#ENDIF +#IF (PIO_4P | PIO_ZP) + .DW PIO_PREINIT +#ENDIF ; HB_PCINITTBLLEN .EQU (($ - HB_PCINITTBL) / 2) ; @@ -3740,9 +3849,15 @@ HB_INITTBL: #IF (PKDENABLE) .DW PKD_INIT #ENDIF - #IF (H8PENABLE) +#ENDIF +#IF (LCDENABLE) + .DW LCD_INIT +#ENDIF +#IF (H8PENABLE) .DW H8P_INIT - #ENDIF +#ENDIF +#IF (GM7303ENABLE) + .DW GM7303_INIT #ENDIF #IF (PLATFORM == PLT_NABU) .DW NABU_INIT @@ -3759,6 +3874,9 @@ HB_INITTBL: #IF (SPKENABLE) .DW SP_INIT ; AUDIBLE INDICATOR OF BOOT START #ENDIF +#IF (SSERENABLE) + .DW SSER_INIT +#ENDIF #IF (ASCIENABLE) .DW ASCI_INIT #ENDIF @@ -3780,15 +3898,6 @@ HB_INITTBL: #IF (ACIAENABLE) .DW ACIA_INIT #ENDIF -#IF (PIOENABLE) - .DW PIO_INIT -#ENDIF -#IF (LPTENABLE) - .DW LPT_INIT -#ENDIF -#IF (PIO_4P | PIO_ZP) - .DW PIO_INIT -#ENDIF #IF (UFENABLE) .DW UF_INIT #ENDIF @@ -3810,6 +3919,9 @@ HB_INITTBL: #IF (DS7RTCENABLE) .DW DS7RTC_INIT #ENDIF +#IF (DS5RTCENABLE) + .DW DS5RTC_INIT +#ENDIF #IF (RP5RTCENABLE) .DW RP5RTC_INIT #ENDIF @@ -3841,6 +3953,27 @@ HB_INITTBL: #IF (VRCENABLE) .DW VRC_INIT #ENDIF +#IF (FVENABLE) + .DW FV_INIT +#ENDIF +#IF (SCONENABLE) + .DW SCON_INIT +#ENDIF +#IF (LPTENABLE) + .DW LPT_INIT +#ENDIF +#IF (PIOENABLE) + .DW PIO_INIT +#ENDIF +#IF (PIO_4P | PIO_ZP) + .DW PIO_INIT +#ENDIF +#IF (PRPENABLE) + .DW PRP_INIT +#ENDIF +#IF (PPPENABLE) + .DW PPP_INIT +#ENDIF #IF (DMAENABLE) .DW DMA_INIT #ENDIF @@ -3874,15 +4007,6 @@ HB_INITTBL: #IF (SYQENABLE) .DW SYQ_INIT #ENDIF -#IF (PRPENABLE) - .DW PRP_INIT -#ENDIF -#IF (PPPENABLE) - .DW PPP_INIT -#ENDIF -#IF (SCONENABLE) - .DW SCON_INIT -#ENDIF #IF (CHENABLE) .DW CH_INIT #ENDIF @@ -3950,7 +4074,7 @@ HB_DISPATCH1: JP C,DSKY_DISPATCH CP BF_VDA + $10 ; $40-$4F: VIDEO DISPLAY ADAPTER JP C,VDA_DISPATCH - CP BF_SND + $08 ; $50-$58: SOUND DRIVERS + CP BF_SND + $10 ; $50-$5F: SOUND DRIVERS JP C,SND_DISPATCH CP BF_SYS ; SKIP TO BF_SYS VALUE AT $F0 JR C,HB_DISPERR ; ERROR IF LESS THAN BF_SYS @@ -4016,6 +4140,24 @@ CIO_SIZ .EQU CIO_MAX * 4 ; EACH ENTRY IS 4 BYTES CIO_CNT .DB 0 ; ENTRY COUNT PREFIX CIO_TBL .FILL CIO_SIZ,0 ; SPACE FOR ENTRIES ; +; CRT TYPE CHAR DEVICES CALL THIS TO REGISTER THAT THEY WANT TO BE THE +; DEFAULT CRT DEVICE. THIS ROUTINE WILL SET CB_CRTDEV WHEN CALLED THE +; FIRST TIME. SUBSEQUENT CALLS ARE IGNORED. THIS ENSURES THAT THE +; *FIRST* CRT DEVICE WINS. +; +CIO_SETCRT: + PUSH AF ; SAVE INCOMING CRT DEV NUM + LD A,(CB_CRTDEV) ; GET CURRENT CRT DEV NUM + INC A ; $FF -> $00 + JR NZ,CIO_SETCRT_Z ; IF ALREADY SET, LEAVE IT ALONE + POP AF ; RESTORE AF + LD (CB_CRTDEV),A ; SAVE CRT DEV NUM + RET ; AND DONE +; +CIO_SETCRT_Z: + POP AF ; RESTORE AF + RET ; AND DONE +; ;-------------------------------------------------------------------------------------------------- ; DISK I/O DEVICE FUNCTION DISPATCHER ;-------------------------------------------------------------------------------------------------- @@ -4338,10 +4480,20 @@ HB_DSKFUNC .DB 0 ; CURRENT DISK FUNCTION ; HL: ADDRESS OF 32-BIT SECTOR NUMBER (LITTLE-ENDIAN) ; ALL REGISTERS PERSERVED ; +HB_DSKACT: +#IF (LCDENABLE) + #IF (LCDDSKACT) + CALL LCD_DSKACT + #ENDIF +#ENDIF +#IF (GM7303ENABLE) + #IF (GM7303DSKACT) + CALL GM7303_DSKACT + #ENDIF +#ENDIF #IF (DSKYENABLE) #IF (DSKYDSKACT) ; -HB_DSKACT: ; SAVE EVERYTHING PUSH AF PUSH BC @@ -4386,7 +4538,7 @@ HB_DSKACT2: POP DE POP BC POP AF - RET ; DONE + JR HB_DSKACT_Z ; DONE ; ; THIS IS THE CHS VARIANT OF THE ABOVE. THIS IS USED BY CHS ORIENTED ; DISK DRIVERS (BASICALLY JUST FLOPPY). @@ -4411,6 +4563,9 @@ HB_DSKACTCHS: #ENDIF #ENDIF ; +HB_DSKACT_Z: + RET +; ;-------------------------------------------------------------------------------------------------- ; REAL TIME CLOCK DEVICE DISPATCHER ;-------------------------------------------------------------------------------------------------- @@ -4548,7 +4703,7 @@ SND_ADDENT: ; WORD DRIVER FUNCTION TABLE ADDRESS ; WORD UNIT SPECIFIC DATA (TYPICALLY A DEVICE INSTANCE DATA ADDRESS) ; -SND_FNCNT .EQU 8 ; NUMBER OF SND FUNCS (FOR RANGE CHECK) +SND_FNCNT .EQU 9 ; NUMBER OF SND FUNCS (FOR RANGE CHECK) SND_MAX .EQU 5 ; UP TO 5 UNITS SND_SIZ .EQU SND_MAX * 4 ; EACH ENTRY IS 4 BYTES ; @@ -4561,47 +4716,48 @@ SND_TBL .FILL SND_SIZ,0 ; SPACE FOR ENTRIES ; SPEAKER BEEP ROUTINE ;-------------------------------------------------------------------------------------------------- ; -;;; RELOCATE -; -; ROUTINE TO BEEP THE DEFAULT SOUND UNIT -; NEED TO CHECK FOR EXISTENCE OF SOUND UNIT +; ROUTINE TO BEEP A SOUND UNIT +; THE SOUND DRIVERS CAN DEFER THEIR BEEP FUNCTION TO THIS FUNCTION +; ON ENTRY, B = SOUND UNIT ; WHICH CHANNEL SHOULD BE USED? IS THERE A GOOD DEFAULT CHANNEL? ; SND_BEEP: - ; CHECK FOR AT LEAST 1 SOUND DEVICE - LD A,(SND_CNT) ; GET SOUND UNIT COUNT - OR A ; CHECK FOR ZERO - RET Z ; BAIL OUT IF NO SOUND UNITS - - ; PLAY A BEEP ON SOUND DEVICE UNIT 0 + ; RESET THE SOUND DEVICE TO START LD B,$50 ; SOUND RESET FUNCTION - LD C,0 ; SOUND UNIT NUMBER - CALL SND_DISPATCH ; DO IT + CALL SND_BEEP_DISP ; DO IT +; + ; SET VOLUME TO MAX LD B,$51 ; VOLUME - LD C,0 ; SOUND UNIT NUMBER LD L,$FF ; MAX - CALL SND_DISPATCH ; DO IT + CALL SND_BEEP_DISP ; DO IT +; + ; SET NOTE TO PLAY LD B,$53 ; SELECT NOTE - LD C,0 ; SOUND UNIT NUMBER - ;LD HL,0 ; A0# LD HL,244 ; B5 (CLOSE TO 1 KHZ) - CALL SND_DISPATCH ; DO IT - ;LD B,$56 ; DURATION - ;LD C,0 ; SOUND UNIT NUMBER - ;LD HL,500 ; 1/2 SECOND - ;CALL SND_DISPATCH ; DO IT + CALL SND_BEEP_DISP ; DO IT +; + ; START PLAYING THE SOUND LD B,$54 ; PLAY SOUND - LD C,0 ; SOUND UNIT NUMBER LD D,0 ; CHANNEL 0 - CALL SND_DISPATCH ; DO IT - LD DE,15625 ; PLAY FOR 1/4 SECOND + CALL SND_BEEP_DISP ; DO IT +; + ; WAIT A BIT FOR SOUND TO PLAY + LD DE,23436 ; PLAY FOR 1/3 SECOND CALL VDELAY ; WAIT WHILE TONE IS PLAYED - ;CALL LDELAY ; LET SOUND PLAY 1/2 SECOND +; LD B,$50 ; SOUND RESET FUNCTION - LD C,0 ; SOUND UNIT NUMBER - CALL SND_DISPATCH ; DO IT + CALL SND_BEEP_DISP ; DO IT +; + XOR A ; SIGNAL SUCCESS RET ; DONE ; +SND_BEEP_DISP: + ; CALL SOUND DISPATCHER PRESERVING BC ACROSS CALL + PUSH BC + CALL SND_DISPATCH + POP BC + RET +; ;-------------------------------------------------------------------------------------------------- ; SYSTEM FUNCTION DISPATCHER ;-------------------------------------------------------------------------------------------------- @@ -5199,9 +5355,9 @@ SYS_GETCPUSPD: ; #IF (((PLATFORM == PLT_SBC) | (PLATFORM == PLT_MBC)) & (CPUSPDCAP==SPD_HILO)) LD A,(HB_RTCVAL) -#IF (PLATFORM == PLT_SBC) + #IF (PLATFORM == PLT_SBC) XOR %00001000 ; SBC SPEED BIT IS INVERTED -#ENDIF + #ENDIF BIT 3,A LD L,0 ; ASSUME HALF SPEED JR Z,SYS_GETCPUSPD1 @@ -5213,6 +5369,16 @@ SYS_GETCPUSPD1: RET #ENDIF ; +#IF (PLATFORM == PLT_HEATH) + LD A,(H8P_SPEED) ; GET HEATH SPEED BITS SHADOW + XOR $03 ; CONVERT TO HBIOS VALUE + LD L,A ; PUT IN L FOR RETURN + LD DE,$FFFF ; UNKNOWN WAIT STATES +; + XOR A + RET +#ENDIF +; #IF (CPUFAM == CPU_Z180) LD HL,0 ; INIT CPU SPEED TO HALF LD A,(HB_CPUTYPE) ; LOAD CPUTYPE @@ -5371,7 +5537,7 @@ SYS_SETSECS: ; ; SET SYSTEM CPU SPEED ATTRIBUTES ; ON ENTRY: -; L: CLOCK MULT (0:HALF, 1:FULL, 2: DOUBLE) +; L: CLOCK MULT (0:HALF, 1:FULL, 2: DOUBLE, 3: QUAD) ; D: MEMORY WAIT STATES ; E: I/O WAIT STATES ; @@ -5437,6 +5603,50 @@ SYS_SETCPUSPD3: RET #ENDIF ; +#IF (PLATFORM == PLT_HEATH) + ; PORT $30: + ; 0=16MHZ, 1=8MHZ, 2=4MHZ, 3=2MHZ + LD A,L ; REQUESTED SPEED TO ACCUM + XOR $03 ; CONVERT TO HEATH BITS + AND $03 ; ONLY 2 LS BITS +; +H8P_SETSPD: ; INVOKED BY H8P.ASM WHEN SPEED CHANGED VIA FRONT PANEL + OUT (H8P_SPDIO),A ; DO IT + LD (H8P_SPEED),A ; UPDATE FP SHADOW +; + ; UPDATE CPUKHZ/CPMHZ + LD HL,(HB_CPUOSC) ; START WITH OSC VALUE IN KHZ + LD B,A ; USE BITS FOR LOOP COUNT + OR A ; CHECK FOR ZERO + JR Z,SYS_SETCPUSPD2 ; IF SO, SKIP ADJUSTMENT LOOP +SYS_SETCPUSPD1: + SRL H ; DIVIDE + RR L ; ... BY TWO + DJNZ SYS_SETCPUSPD1 ; LOOP AS NEEDED +; +SYS_SETCPUSPD2: +; +; HL SHOULD NOW HAVE FINAL CPU RUNNING SPEED IN KHZ. +; UPDATE CB_CPUMHZ/CB_CPUKHZ WITH THIS VALUE. +; + LD (CB_CPUKHZ),HL ; UPDATE CPUKHZ + LD DE,1000 ; SET UP TO DIV BY 1000 FOR MHZ + CALL DIV16 ; BC=CPU MHZ, HL=REMAINDER + LD DE,500 ; SET UP TO ROUND UP + XOR A ; IF WITHIN 500 KHZ + SBC HL,DE ; REMAINDER - 500 + CCF ; COMPLEMENT CF + ADC A,C ; C -> A; ADD CF FOR ROUNDING + LD (CB_CPUMHZ),A ; SAVE IT +; + ; REINIT DELAY ROUTINE + LD A,(CB_CPUMHZ) ; CPU SPEED TO ACCUM AND INIT + CALL DELAY_INIT ; .. SPEED COMPENSATED DELAY +; + XOR A ; SIGNAL SUCCESS + RET +#ENDIF +; #IF (CPUFAM == CPU_Z180) ; VERIFY THAT REQUESTED SETTINGS ARE ALLOWED BY HARDWARE LD A,L ; GET SPEED REQUESTED @@ -6658,7 +6868,7 @@ Z280_PRIVINST: ;;;HB_DI ; DO THE DI XOR A ; NO INTERRUPTS LD (HB_MSRSAV),A ; UPDATE SAVED MSR LSB - + INC HL ; BUMP PAST IT JR Z280_PRIVINSTX ; @@ -7102,7 +7312,7 @@ RS_IMAGE: RS_START: LD A,(HB_CURBNK) ; GET CURRENT BANK PUSH AF ; SAVE IT - + LD C,0 ; RUNNING BANK COUNT LD HL,$7FFF ; BYTE TEST ADDRESS LD IX,RS_ARY ; ORIG BYTE STORAGE ARRAY PTR @@ -7134,7 +7344,7 @@ RS_LOOP1: LD (HL),A OR A ; ZERO? JR Z,RS_NEXT ; SKIP STORED VALUE CHECK - + ; VERIFY ALL STORED VALUES LD B,C ; INIT LOOP COUNTER LD E,0 ; INIT BANK ID @@ -7151,7 +7361,7 @@ RS_LOOP3: RS_NEXT: INC C ; ADD 1 TO RAM BANK COUNT JR RS_LOOP1 ; AND LOOP TILL DONE -; +; RS_DONE: LD E,C ; FINAL BANK COUNT TO E LD A,C @@ -7274,7 +7484,6 @@ FP_SETLEDS1: POP HL ; RESTORE HL RET ; DONE ; -; #ENDIF ; #IF (FPSW_ENABLE) @@ -7510,7 +7719,7 @@ PS_PRTDT: LD A,00001111B CALL PRTIDXMSK CALL PS_PAD18 ; PAD TO 18 SPACES - RET + RET ; ; PRINT DISK CAPACITY (UNIT IN C, ATTRIBUTE IN E) ; @@ -7956,6 +8165,8 @@ PS_SDLPT .TEXT "LPT$" PS_SDESPCON .TEXT "ESPCON$" PS_SDESPSER .TEXT "ESPSER$" PS_SDSCON .TEXT "SCON$" +PS_SDEF .TEXT "EF$" +PS_SDSSER .TEXT "SSER$" ; ; CHARACTER SUB TYPE STRINGS ; @@ -7980,6 +8191,8 @@ PS_VDGDC .TEXT "GDC$" PS_VDTMS .TEXT "TMS$" PS_VDVGA .TEXT "VGA$" PS_VDVRC .TEXT "VRC$" +PS_VDEF .TEXT "EF$" +PS_VDFV .TEXT "FV$" ; ; VIDEO TYPE STRINGS ; @@ -8027,15 +8240,33 @@ SIZ_PKD .EQU $ - ORG_PKD MEMECHO SIZ_PKD MEMECHO " bytes.\n" #ENDIF +#ENDIF ; - #IF (H8PENABLE) +#IF (LCDENABLE) +ORG_LCD .EQU $ + #INCLUDE "lcd.asm" +SIZ_LCD .EQU $ - ORG_LCD + MEMECHO "LCD occupies " + MEMECHO SIZ_LCD + MEMECHO " bytes.\n" +#ENDIF +; +#IF (GM7303ENABLE) +ORG_GM7303 .EQU $ + #INCLUDE "gm7303.asm" +SIZ_GM7303 .EQU $ - ORG_GM7303 + MEMECHO "GM7303 occupies " + MEMECHO SIZ_GM7303 + MEMECHO " bytes.\n" +#ENDIF +; +#IF (H8PENABLE) ORG_H8P .EQU $ #INCLUDE "h8p.asm" SIZ_H8P .EQU $ - ORG_H8P MEMECHO "H8P occupies " MEMECHO SIZ_H8P MEMECHO " bytes.\n" - #ENDIF #ENDIF ; #IF (PLATFORM == PLT_NABU) @@ -8092,12 +8323,12 @@ SIZ_PCF .EQU $ - ORG_PCF MEMECHO " bytes.\n" #ENDIF ; -#IF (DS7RTCENABLE) -ORG_DS7RTC .EQU $ - #INCLUDE "ds7rtc.asm" -SIZ_DS7RTC .EQU $ - ORG_DS7RTC - MEMECHO "DS7RTC occupies " - MEMECHO SIZ_DS7RTC +#IF (DS5RTCENABLE) +ORG_DS5RTC .EQU $ + #INCLUDE "ds5rtc.asm" +SIZ_DS5RTC .EQU $ - ORG_DS5RTC + MEMECHO "DS5RTC occupies " + MEMECHO SIZ_DS5RTC MEMECHO " bytes.\n" #ENDIF ; @@ -8119,6 +8350,15 @@ SIZ_RP5RTC .EQU $ - ORG_RP5RTC MEMECHO " bytes.\n" #ENDIF ; +#IF (SSERENABLE) +ORG_SSER .EQU $ + #INCLUDE "sser.asm" +SIZ_SSER .EQU $ - ORG_SSER + MEMECHO "SSER occupies " + MEMECHO SIZ_SSER + MEMECHO " bytes.\n" +#ENDIF +; #IF (ASCIENABLE) ORG_ASCI .EQU $ #INCLUDE "asci.asm" @@ -8272,6 +8512,15 @@ SIZ_VRC .EQU $ - ORG_VRC MEMECHO " bytes.\n" #ENDIF ; +#IF (FVENABLE) +ORG_FV .EQU $ + #INCLUDE "fv.asm" +SIZ_FV .EQU $ - ORG_FV + MEMECHO "FV occupies " + MEMECHO SIZ_FV + MEMECHO " bytes.\n" +#ENDIF +; #IF (DMAENABLE) ORG_DMA .EQU $ #INCLUDE "dma.asm" @@ -8644,7 +8893,7 @@ HB_TICKS .FILL 4,0 ; 32 BIT TICK COUNTER HB_SECTCK .DB TICKFREQ ; TICK COUNTER FOR FRACTIONAL SECONDS HB_SECS .FILL 4,0 ; 32 BIT SECONDS COUNTER ; -HB_CPUTYPE .DB 0 ; 0=Z80, 1=80180, 2=SL1960, 3=ASCI BRG +HB_CPUTYPE .DB 0 ; 0=Z80, 1=Z180, 2=Z180-K, 3=Z180-N, 4=Z280 HB_CPUOSC .DW CPUOSC ; ACTUAL CPU HARDWARE OSC FREQ IN KHZ ; HB_BATCOND .DB 0 ; BATTERY CONDITION (0=LOW, 1=OK) @@ -8719,30 +8968,41 @@ HB_APPBOOTERR: STR_APPBOOTERR .DB "\r\n\r\n*** App Boot is only possible on running RomWBW system!\r\n\r\n$" ; HB_APPBOOT1: + ; APPBOOT REQUIRES THAT THE COMMON BANK IS NOT CHANGED BY + ; THE NEW CONFIG. TEST FOR THIS AND DIAGNOSE IF SO. + LD A,(HCB_BIDCOM) ; RUNNING COMMON BANK ID + + LD B,BF_SYSGET ; HBIOS SYSGET + LD C,BF_SYSGET_BNKINFO ; BANK INFORMATION + RST 08 ; D = BIOS BANK ID + LD B,BF_SYSPEEK ; HBIOS FUNC: PEEK + LD HL,HCB_LOC + HCB_BIDCOM ; COMMON BANK ID + RST 08 ; E = COMMON BANK ID + LD A,E ; PUT IN A + CP BID_COM ; COMPARE TO NEW CONFIG + JR Z,HB_APPBOOT2 ; IF SAME, CONTINUE +; + ; DIAGNOSE COMMON BANK ID MISMATCH + LD DE,STR_COMBANKERR ; POINT TO ERROR MESSAGE + LD C,9 ; BDOS FUNC 9: WRITE STR + CALL $0005 ; DO IT + OR $FF ; SIGNAL ERROR + RET ; AND RETURN +; +STR_COMBANKERR .DB "\r\n\r\n*** Common Bank Mismatch!\r\n\r\n$" +; +HB_APPBOOT2: ; ANNOUNCE THE APPLICATION BOOT LD DE,STR_APPBOOT ; POINT TO MESSAGE LD C,9 ; BDOS FUNC 9: WRITE STR CALL $0005 ; DO IT - JR HB_APPBOOT2 ; AND CONTINUE + CALL LDELAY ; SERIAL PORT FLUSH TIME + JR HB_APPBOOT3 ; AND CONTINUE ; STR_APPBOOT .DB "\r\n\r\n*** Launching RomWBW HBIOS v", BIOSVER, ", ", TIMESTAMP, " for" .DB "\r\n\r\n ", PLATFORM_NAME, "$" ; -HB_APPBOOT2: - ; FOR AN APPLICATION BOOT, WE ALSO COPY THE CONCATENATED OS - ; IMAGES TO THE AUX BANK WHERE WE WILL JUMP TO ROMLDR LATER. - ; THE AUX BANK WILL BE DESTROYED IF CP/M 3 IS LOADED. WE DON'T - ; LIVE IN A PERFECT WORLD. - LD B,BF_SYSSETCPY ; HBIOS FUNC: SETUP BANK COPY - LD D,BID_AUX ; D = DEST BANK = AUX BANK - LD A,(HB_CURBNK) ; E = SRC BANK = CUR BANK - LD E,A ; USE AS SOURCE - LD HL,$8000 ; HL = COPY LEN = ENTIRE BANK - RST 08 ; DO IT - LD B,BF_SYSBNKCPY ; HBIOS FUNC: PERFORM BANK COPY - LD HL,HB_END ; COPY FROM END OF HBIOS - LD DE,0 ; TO START OF TARGET BANK - RST 08 ; DO IT +HB_APPBOOT3: ; #IF (MEMMGR == MM_Z280) ; WE NEED TO SWITCH FROM USER MODE TO SYSTEM MODE, BUT CONTINUE @@ -8750,7 +9010,6 @@ HB_APPBOOT2: ; ; FIRST, OVERLAY PROXY CODE WITH FRESH CODE SO WE CAN USE THE ; PROXY ROUTINES SAFELY. - LD A,(HB_CURBNK) ; GET CURBNK LD DE,HBX_LOC ; RUNNING LOCATION LD HL,HBX_IMG ; LOCATION IN IMAGE @@ -8766,7 +9025,7 @@ HB_APPBOOT2: LDIR ; ; THEN SYSCALL IT. NOTE THAT THE ROUTINE CALLED DOES NOT - ; (RET)URN, IT JUMPS TO CONTINUE SO THAT THE SYSCALL DOES + ; (RET)URN, IT JUMPS TO HB_RESTART SO THAT THE SYSCALL DOES ; NOT RETURN TO USER MODE. SC HBX_BUF ; SYSCALL ROUTINE ; @@ -8921,7 +9180,7 @@ SLACK .EQU BNKTOP - $ !!! ; FORCE AN ASSEMBLY ERROR #ENDIF ; -;;;#IF (SLACK < (1024 * 3)) +;;;#IF (SLACK < (1024 * 3)) ;;; .ECHO "*** ERROR: Low HEAP space!!!\n" ;;; !!! ; FORCE AN ASSEMBLY ERROR ;;;#ENDIF diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc index 8949f3fc..2c6448e3 100644 --- a/Source/HBIOS/hbios.inc +++ b/Source/HBIOS/hbios.inc @@ -74,6 +74,7 @@ BF_SNDPLAY .EQU BF_SND + 4 ; INITIATE THE REQUESTED SOUND COMMAND BF_SNDQUERY .EQU BF_SND + 5 ; E IS SUBFUNCTION BF_SNDDURATION .EQU BF_SND + 6 ; REQUEST DURATION HL MILLISECONDS BF_SNDDEVICE .EQU BF_SND + 7 ; SOUND DEVICE INFO REQUEST +BF_SNDBEEP .EQU BF_SND + 8 ; PLAY A BEEP SOUND ON DEVICE ; ; BF_SNDQUERY SUBCOMMANDS BF_SNDQ_STATUS .EQU 0 @@ -136,6 +137,7 @@ CIO_CONSOLE .EQU $80 ; CIO UNIT NUM FOR CUR CON ; ; PRIMARY HARDWARE PLATFORMS ; +PLT_NONE .EQU 0 ; UNDEFINED PLATFORM PLT_SBC .EQU 1 ; SBC ECB Z80 SBC PLT_ZETA .EQU 2 ; ZETA Z80 SBC PLT_ZETA2 .EQU 3 ; ZETA Z80 V2 SBC @@ -156,9 +158,10 @@ PLT_DUO .EQU 17 ; DUODYNE Z80 SYSTEM PLT_HEATH .EQU 18 ; HEATHKIT H8 Z80 SYSTEM PLT_EPITX .EQU 19 ; Z180 MINI-ITX PLT_MON .EQU 20 ; MONSPUTER -PLT_STDZ180 .EQU 21 ; GENESIS Z180 SYSTEM +PLT_GMZ180 .EQU 21 ; GENESIS Z180 SYSTEM PLT_NABU .EQU 22 ; NABU PERSONAL COMPUTER -PLT_RCEZ80 .EQU 23 ; RCBUS W/ eZ80 +PLT_FZ80 .EQU 23 ; S100 FPGA Z80 +PLT_RCEZ80 .EQU 24 ; RCBUS W/ eZ80 ; ; HBIOS GLOBAL ERROR RETURN VALUES ; @@ -324,7 +327,8 @@ CIODEV_ESPCON .EQU $0C CIODEV_ESPSER .EQU $0D CIODEV_SCON .EQU $0E CIODEV_EF .EQU $0F -CIODEV_EZ80UART .EQU $10 +CIODEV_SSER .EQU $10 +CIODEV_EZ80UART .EQU $11 ; ; SUB TYPES OF CHAR DEVICES ; @@ -359,7 +363,8 @@ RTCDEV_SIMH .EQU $02 ; SIMH RTCDEV_INT .EQU $03 ; PERIODIC INT TIMER RTCDEV_DS7 .EQU $04 ; DS1307 (I2C) RTCDEV_RP5 .EQU $05 ; RP5C01 -RTCDEV_EZ80 .EQU $06 ; EZ80 ON-CHIP RTC +RTCDEV_DS5 .EQU $06 ; DS1305 (SPI) +RTCDEV_EZ80 .EQU $07 ; EZ80 ON-CHIP RTC ; ; DSKY DEVICE IDS ; @@ -376,6 +381,7 @@ VDADEV_TMS .EQU $03 ; N8 ONBOARD VDA SUBSYSTEM - TMS 9918 VDADEV_VGA .EQU $04 ; ECB VGA3 - HITACHI HD6445 VDADEV_VRC .EQU $05 ; VGARC VDADEV_EF .EQU $06 ; EF9345 +VDADEV_FV .EQU $07 ; S100 FPGA VGA ; ; SOUND DEVICE IDS ; diff --git a/Source/HBIOS/hdsk.asm b/Source/HBIOS/hdsk.asm index 6dfc426f..af357564 100644 --- a/Source/HBIOS/hdsk.asm +++ b/Source/HBIOS/hdsk.asm @@ -239,13 +239,13 @@ HDSK_RW0: XOR A ; A = 0 LD (HDSK_RC),A ; CLEAR RETURN CODE ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,HDSK_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; ; CONVERT LBA HHHH:LLLL (4 BYTES) ; TO HDSK TRACK/SECTOR TTTT:SS (3 BYTES) diff --git a/Source/HBIOS/ide.asm b/Source/HBIOS/ide.asm index 57ec4749..8056a120 100644 --- a/Source/HBIOS/ide.asm +++ b/Source/HBIOS/ide.asm @@ -18,6 +18,7 @@ ; MK4 $80 N/A N/A ; RC $10 N/A N/A ; SMB $E0 N/A N/A +; GIDE $20 $20 $28 - Genesis IDE controller - Note Read Hi Low - Write - Low High ; ; +-----------------------------------------------------------------------+ ; | CONTROL BLOCK REGISTERS | @@ -224,6 +225,9 @@ IDE_DEV0M: ; DEVICE 0, MASTER #IF (IDE0MODE == IDEMODE_DIDE) DEVECHO "DIDE" #ENDIF + #IF (IDE0MODE == IDEMODE_GIDE) + DEVECHO "GIDE" + #ENDIF #IF (IDE0MODE == IDEMODE_MK4) DEVECHO "MK4" #ENDIF @@ -259,6 +263,9 @@ IDE_DEV0S: ; DEVICE 0, SLAVE #IF (IDE0MODE == IDEMODE_DIDE) DEVECHO "DIDE" #ENDIF + #IF (IDE0MODE == IDEMODE_GIDE) + DEVECHO "GIDE" + #ENDIF #IF (IDE0MODE == IDEMODE_MK4) DEVECHO "MK4" #ENDIF @@ -297,6 +304,9 @@ IDE_DEV1M: ; DEVICE 1, MASTER #IF (IDE1MODE == IDEMODE_DIDE) DEVECHO "DIDE" #ENDIF + #IF (IDE1MODE == IDEMODE_GIDE) + DEVECHO "GIDE" + #ENDIF #IF (IDE1MODE == IDEMODE_MK4) DEVECHO "MK4" #ENDIF @@ -332,6 +342,9 @@ IDE_DEV1S: ; DEVICE 1, SLAVE #IF (IDE1MODE == IDEMODE_DIDE) DEVECHO "DIDE" #ENDIF + #IF (IDE1MODE == IDEMODE_GIDE) + DEVECHO "GIDE" + #ENDIF #IF (IDE1MODE == IDEMODE_MK4) DEVECHO "MK4" #ENDIF @@ -370,6 +383,9 @@ IDE_DEV2M: ; DEVICE 2, MASTER #IF (IDE2MODE == IDEMODE_DIDE) DEVECHO "DIDE" #ENDIF + #IF (IDE2MODE == IDEMODE_GIDE) + DEVECHO "GIDE" + #ENDIF #IF (IDE2MODE == IDEMODE_MK4) DEVECHO "MK4" #ENDIF @@ -405,6 +421,9 @@ IDE_DEV2S: ; DEVICE 2, SLAVE #IF (IDE2MODE == IDEMODE_DIDE) DEVECHO "DIDE" #ENDIF + #IF (IDE2MODE == IDEMODE_GIDE) + DEVECHO "GIDE" + #ENDIF #IF (IDE2MODE == IDEMODE_MK4) DEVECHO "MK4" #ENDIF @@ -435,7 +454,8 @@ IDE_DEV2S: ; DEVICE 2, SLAVE ; PICO TO WAIT FOR THE PICO DEVICE TO INITIALIZE. ; IDE_TOSLOW .EQU 200 ; SLOW TIMEOUT IS 20 SECS -IDE_TONORM .EQU 5 ; NORMAL TIMEOUT IS 0.5 SECS +;IDE_TONORM .EQU 5 ; NORMAL TIMEOUT IS 0.5 SECS +IDE_TONORM .EQU 200 ; NORMAL TIMEOUT IS 0.5 SECS IDE_TOPICO .EQU 50 ; RC2014 SD PICO (5 SECONDS) ; ;============================================================================= @@ -490,6 +510,9 @@ IDE_INIT2: LD DE,IDE_STR_MODE_RC ; MODE LABEL CP IDEMODE_RC ; TEST FOR MODE JR Z,IDE_INIT2A ; IF SO, DISPLAY IT + LD DE,IDE_STR_MODE_GIDE ; MODE LABEL + CP IDEMODE_GIDE ; TEST FOR MODE + JR Z,IDE_INIT2A ; IF SO, DISPLAY IT JR IDE_INIT4 ; NO MODE? BYPASS ENTRY IDE_INIT2A: CALL WRITESTR ; DISPLAY MODE @@ -919,13 +942,13 @@ IDE_PKT_RDSEC: #ENDIF ; SETUP LBA ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,IDE_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; ; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN LD HL,IDE_PKTCMD_RW10+3 ; START OF LBA FIELD IN CDB (MSB) @@ -988,13 +1011,13 @@ IDE_PKT_WRSEC: #ENDIF ; SETUP LBA ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,IDE_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; ; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN LD HL,IDE_PKTCMD_RW10+3 ; START OF LBA FIELD IN CDB (MSB) @@ -1020,13 +1043,13 @@ IDE_PKT_WRSEC: ; IDE_SETADDR: ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,IDE_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER ; IDE_REG_LBA3 HAS ALREADY BEEN SET ; HSTLBA2-0 --> IDE_REG_LBA2-0 @@ -1254,12 +1277,19 @@ IDE_GET16: RET ; IDE_GET16A: +#IF (IDE0MODE == IDEMODE_GIDE) ; GENESIS BOARD IS REVERSED + LD C,E ; PORT FOR MSB + INI ; GET IT, SAVE IT, AND DEC B + LD C,D ; PORT FOR LSB + INI ; GET IT, SAVE IT, AND DEC B +#ELSE LD C,D ; PORT FOR LSB EZ80_IO INI ; GET IT, SAVE IT, AND DEC B LD C,E ; PORT FOR MSB EZ80_IO INI ; GET IT, SAVE IT, AND DEC B +#ENDIF DEC A JR NZ,IDE_GET16A ; LOOP TILL COUNTER EXHAUSTED RET @@ -1323,6 +1353,12 @@ IDE_PUT16: RET ; IDE_PUT16A: +#IF (IDE0MODE == IDEMODE_GIDE) ; GENESIS BOARD IS REVERSED + LD C,E ; PORT FOR MSB + OUTI ; PUT IT AND DEC B + LD C,D ; PORT FOR LSB + OUTI ; PUT IT AND DEC B +#ELSE LD C,D ; PORT FOR LSB EZ80_IO OUTI ; PUT IT AND DEC B @@ -1330,6 +1366,7 @@ IDE_PUT16A: EZ80_IO OUTI ; PUT IT AND DEC B DEC A +#ENDIF JR NZ,IDE_PUT16A ; LOOP TILL COUNTER EXHAUSTED RET ; @@ -1999,6 +2036,16 @@ IDE_OUT: EX (SP),HL ; GET PARM POINTER PUSH BC PUSH AF +; +#IF (IDE0MODE == IDEMODE_GIDE) ; SET TOP BYTE TO 0 FOR GENESIS BOARD + LD A,(HL) + LD C,(IY+IDE_DATAHI) + ADD A,C + LD C,A + LD A,0 + OUT (C),A +#ENDIF +; LD A,(HL) INC HL LD C,(IY+IDE_IOBASE) @@ -2200,6 +2247,7 @@ IDE_STR_MODE_DIO .TEXT "DIO$" IDE_STR_MODE_DIDE .TEXT "DIDE$" IDE_STR_MODE_MK4 .TEXT "MK4$" IDE_STR_MODE_RC .TEXT "RC$" +IDE_STR_MODE_GIDE .TEXT "GIDE$" ; IDE_STR_TYPEATA .TEXT " ATA$" IDE_STR_TYPEATAPI .TEXT " ATAPI$" diff --git a/Source/HBIOS/imm.asm b/Source/HBIOS/imm.asm index 237c6ed4..5999e79f 100644 --- a/Source/HBIOS/imm.asm +++ b/Source/HBIOS/imm.asm @@ -343,13 +343,13 @@ IMM_IO: ; LD (IMM_DSKBUF),HL ; SAVE DISK BUFFER ADDRESS ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,IMM_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; ; SETUP LBA ; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN diff --git a/Source/HBIOS/lcd.asm b/Source/HBIOS/lcd.asm new file mode 100644 index 00000000..90e9ec3b --- /dev/null +++ b/Source/HBIOS/lcd.asm @@ -0,0 +1,392 @@ +; +;================================================================================================== +; HARDWARE SUPPORT FOR HITACHI HD44780 OR EQUIVALENT +;================================================================================================== +; +; CURRENTLY ASSUMES A 20X4 DISPLAY +; +; TYPICAL PORTS USED ON RCBUS ECOSYSTEM: +; +; PRIMARY ALT +; FUNCTION $DA $AA +; DATA $DB $AB +; +LCD_FUNC .EQU LCDBASE + 0 ; WRITE +LCD_STAT .EQU LCDBASE + 0 ; READ +LCD_DATA .EQU LCDBASE + 1 ; READ/WRITE +; +LCD_FUNC_CLEAR .EQU $01 ; CLEAR DISPLAY +LCD_FUNC_HOME .EQU $02 ; HOME CURSOR & REMOVE ALL SHIFTING +LCD_FUNC_ENTRY .EQU $04 ; SET CUR DIR AND DISPLAY SHIFT +LCD_FUNC_DISP .EQU $08 ; DISP, CUR, BLINK ON/OFF +LCD_FUNC_SHIFT .EQU $10 ; MOVE CUR / SHIFT DISP +LCD_FUNC_SET .EQU $20 ; SET INTERFACE PARAMS +LCD_FUNC_CGADR .EQU $40 ; SET CGRAM ADRESS +LCD_FUNC_DDADR .EQU $80 ; SET DDRAM ADDRESS +; + DEVECHO "LCD: IO=" + DEVECHO LCDBASE + DEVECHO "\n" +; +; HARDWARE RESET PRIOR TO ROMWBW CONSOLE INITIALIZATION +; +LCD_PREINIT: +; + ; RESET LCD CONTROLLER, DELAYS ARE FIXED, BUSY FLAG + ; CANNOT BE USED YET, CONTROLLER MAY NOT EXIST! + LD A,LCD_FUNC_SET | %11000 + OUT (LCD_FUNC),A + LD DE,50000/16 ; WAIT >40MS, WE USE 50MS + CALL VDELAY ; DO IT + LD A,LCD_FUNC_SET | %11000 + OUT (LCD_FUNC),A + LD DE,5000/16 ; WAIT >4.1MS, WE USE 5MS + CALL VDELAY ; DO IT + LD A,LCD_FUNC_SET | %11000 + OUT (LCD_FUNC),A + LD DE,5000/16 ; WAIT >4.1MS, WE USE 5MS + CALL VDELAY ; DO IT +; + ; TEST FOR PRESENCE... + CALL LCD_DETECT ; PROBE FOR HARDWARE + LD A,(LCD_PRESENT) ; GET PRESENCE FLAG + OR A ; SET FLAGS + RET Z ; BAIL OUT IF NOT PRESENT +; + ; WE CAN NOW DO NORMAL I/O W/ BUSY FLAG + LD DE,LCD_INIT_SEQ ; INIT SEQUENCE + CALL LCD_OUTFS ; SEND IT +; + ; PUT SOMETHING ON THE DISPLAY + LD DE,LCD_STR_BAN + CALL LCD_OUTDS +; + ; SECOND LINE + ; CPU TYPE + LD HL,$0100 ; ROW 2, COL 0 + CALL LCD_GOTORC + LD HL,LCD_CPU + LD A,(HB_CPUTYPE) ; GET CPU TYPE + RRCA ; WORD OFFSET + CALL ADDHLA ; ADD OFFSET + LD E,(HL) ; GET LSB + INC HL ; BUMP + LD D,(HL) ; GET MSB + CALL LCD_OUTDS + LD DE,LCD_STR_XPU + CALL LCD_OUTDS +; + ; "12.345 MHz" RIGHT JUSTIFIED + LD HL,$010A ; ROW 2, COL 10 + CALL LCD_GOTORC + LD HL,(CB_CPUKHZ) + PUSH HL + LD BC,10000 ; 10 MHZ + SBC HL,BC ; SUBTRACT + JR NC,LCD_PREINIT1 + LD A,' ' ; EXTRA PAD + CALL LCD_OUTD +LCD_PREINIT1: + POP HL + CALL LCD_PRTD3M ; PRINT AS DECIMAL WITH 3 DIGIT MANTISSA + LD DE,LCD_STR_MHZ + CALL LCD_OUTDS +; + ; THIRD LINE + LD HL,$0200 ; ROW 2, COL 0 + CALL LCD_GOTORC + LD DE,LCD_STR_CFG + CALL LCD_OUTDS +; + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +; POST CONSOLE INITIALIZATION +; +LCD_INIT: + CALL NEWLINE ; FORMATTING + PRTS("LCD: IO=$") + LD A,LCDBASE + CALL PRTHEXBYTE +; + LD A,(LCD_PRESENT) ; GET PRESENCE FLAG + OR A ; SET FLAGS + JR Z,LCD_INIT1 ; HANDLE NOT PRESENT + XOR A ; SIGNAL SUCCESS + RET ; DONE +; +LCD_INIT1: + PRTS(" NOT PRESENT$") + OR $FF + RET +; +; CALLED FROM HBIOS RIGHT BEFORE A DISK ACCESS +; HL: ADDRESS OF 32-BIT SECTOR NUMBER (LITTLE-ENDIAN) +; +; FORMAT: "Disk #99 R:12345678" +; 01234567890123456789 +; +LCD_DSKACT: + ; SAVE EVERYTHING + PUSH AF + PUSH BC + PUSH DE + PUSH HL +; + LD A,(LCD_PRESENT) ; GET PRESENCE FLAG + OR A ; SET FLAGS + JR Z,LCD_DSKACT_Z ; HANDLE NOT PRESENT +; + PUSH HL + LD HL,$0300 ; ROW 3, COL 0 + CALL LCD_GOTORC ; SET DISPLAY ADDRESS + POP HL +; + LD DE,LCD_STR_IO ; PREFIX + CALL LCD_OUTDS ; SEND TO DISPLAY (COLS 0-5) +; + LD A,(HB_DSKUNIT) ; GET DISK UNIT NUM + CALL LCD_DSKACT_BYTE ; SEND TO DISPLAY (COLS 6-7) HEX??? +; + LD A,' ' ; SEPARATOR + CALL LCD_OUTD ; SEND TO DISPLAY (COL 8) + CALL LCD_OUTD ; SEND TO DISPLAY (COL 9) +; + LD A,(HB_DSKFUNC) ; ACTIVE DISK FUNCTION + CP BF_DIOWRITE ; WRITE? + LD A,'W' ; ASSUME WRITE + JR Z,LCD_DSKACT0 ; GO AHEAD + LD A,'R' ; OTHERWISE READ +LCD_DSKACT0: + CALL LCD_OUTD ; SEND CHAR (COL 10) +; + LD A,':' ; SEPARATOR + CALL LCD_OUTD ; SEND TO DISPLAY (COL 11) +; + LD A,3 ; POINT TO + CALL ADDHLA ; END OF DWORD (MSB) + LD B,4 ; DO 4 BYTES +; +LCD_DSKACT1: + LD A,(HL) ; GET BYTE + CALL LCD_DSKACT_BYTE ; SEND TO DISPLAY (COLS 12-19) + DEC HL ; DEC PTR + DJNZ LCD_DSKACT1 ; DO ALL 4 BYTES +; +LCD_DSKACT_Z: + ; CLEAN UP AND GO AWAY + POP HL + POP DE + POP BC + POP AF + RET +; +LCD_DSKACT_BYTE: + PUSH AF ; SAVE BYTE + RRCA ; DO TOP NIBBLE FIRST + RRCA + RRCA + RRCA + CALL HEXCONV ; CONVERT NIBBLE TO ASCII + CALL LCD_OUTD ; SEND TO DISPLAY + POP AF ; RECOVER CURRENT BYTE + CALL HEXCONV ; CONVERT NIBBLE TO ASCII + CALL LCD_OUTD ; SEND TO DISPLAY + RET ; DONE +; +; DETECT PRESENCE OF LCD CONTROLLER BY WRITING AND READING BACK +; TEST VALUES IN THE CONTROLLER RAM. +; WE DO NOT USE THE NORMAL READ/WRITE ROUTINES BECAUSE WE DO +; NOT WANT TO STALL WAITING ON THE BUSY FLAG IF THE CONTROLLER +; IS NOT PRESENT +; +LCD_DETECT: + ; FIRST PASS W/ TEST VALUE $AA + LD C,$AA + CALL LCD_DETECT_PASS + JR NZ,LCD_DETECT1 +; + ; SECOND PASS W/ TEST VALUE $55 + LD C,$55 + CALL LCD_DETECT_PASS + JR NZ,LCD_DETECT1 +; + ; LCD PRESENT + OR $FF + JR LCD_DETECT_Z +; +LCD_DETECT1: + ; LCD NOT PRESENT + XOR A + JR LCD_DETECT_Z +; +LCD_DETECT_Z: + LD (LCD_PRESENT),A + RET +; +; WRITE AND READBACK VALUE IN C TO THE FIRST BYTE OF DDRAM +; RETURN WITH COMPARE RESULT +; +LCD_DETECT_PASS: + CALL LCD_DELAY ; WAIT + LD A,LCD_FUNC_DDADR + OUT (LCD_FUNC),A ; POINT TO FIRST BYTE + CALL LCD_DELAY ; WAIT + LD A,C ; TEST VALUE + OUT (LCD_DATA),A ; WRITE IT + CALL LCD_DELAY ; WAIT + LD A,LCD_FUNC_DDADR + OUT (LCD_FUNC),A ; POINT TO FIRST BYTE + CALL LCD_DELAY + IN A,(LCD_DATA) ; GET VALUE + CP C ; AS WRITTEN? + RET +; +; DELAY USED DURING DETECT, >37US +; +LCD_DELAY: + CALL DELAY ; 16US + CALL DELAY ; 16US + JP DELAY ; 16US, TOTAL 48US +; +; SEND FUNCTION CODE IN A +; +LCD_OUTF: + PUSH AF ; SAVE CODE +LCD_OUTF1: + IN A,(LCD_STAT) ; GET STATUS + AND $80 ; ISOLATE BUSY FLAG + JR NZ,LCD_OUTF1 ; LOOP TILL NOT BUSY + POP AF ; RECOVER CODE + OUT (LCD_FUNC),A ; SEND IT + RET ; DONE +; +; SEND FUNCTION STRING +; DE=STRING ADDRESS, NULL TERMINATED +; +LCD_OUTFS: + LD A,(DE) ; NEXT BYTE TO SEND + OR A ; SET FLAGS + RET Z ; DONE WHEN NULL REACHED + INC DE ; BUMP POINTER + CALL LCD_OUTF ; SEND IT + JR LCD_OUTFS ; LOOP AS NEEDED +; +; SEND DATA BYTE IN A +; +LCD_OUTD: + PUSH AF ; SAVE BYTE +LCD_OUTD1: + IN A,(LCD_STAT) ; GET STATUS + AND $80 ; ISOLATE BUSY FLAG + JR NZ,LCD_OUTD1 ; LOOP TILL NOT BUSY + POP AF ; RECOVER BYTE + OUT (LCD_DATA),A ; SEND IT + RET ; DONE +; +; SEND DATA STRING +; DE=STRING ADDRESS, NULL TERMINATED +; +LCD_OUTDS: + LD A,(DE) ; NEXT BYTE TO SEND + OR A ; SET FLAGS + RET Z ; DONE WHEN NULL REACHED + INC DE ; BUMP POINTER + CALL LCD_OUTD ; SEND IT + JR LCD_OUTDS ; LOOP AS NEEDED +; +; GET DATA BYTE INTO A +; +LCD_IND: + IN A,(LCD_STAT) ; GET STATUS + AND $80 ; ISOLATE BUSY FLAG + JR NZ,LCD_IND ; LOOP TILL NOT BUSY + POP AF ; RECOVER BYTE + IN A,(LCD_DATA) ; GET IT + RET ; DONE +; +; GOTO ROW(H),COL(L) +; +LCD_GOTORC: + PUSH HL ; SAVE INCOMING + LD A,H ; ROW # TO A + LD HL,LCD_ROWS ; POINT TO ROWS TABLE + CALL ADDHLA ; INDEX TO ROW ENTRY + LD A,(HL) ; GET RWO START + POP HL ; RECOVER INCOMING + ADD A,L ; ADD COLUMN + ADD A,LCD_FUNC_DDADR ; APPLY FUNCTION BIT + JR LCD_OUTF ; AND SEND IT +; +; PRINT VALUE OF HL AS THOUSANDTHS, IE. 0.000 +; +LCD_PRTD3M: + PUSH BC + PUSH DE + PUSH HL + LD E,'0' + LD BC,-10000 + CALL LCD_PRTD3M1 + LD E,0 + LD BC,-1000 + CALL LCD_PRTD3M1 + LD A,'.' + CALL LCD_OUTD + LD BC,-100 + CALL LCD_PRTD3M1 + LD C,-10 + CALL LCD_PRTD3M1 + LD C,-1 + CALL LCD_PRTD3M1 + POP HL + POP DE + POP BC + RET +LCD_PRTD3M1: + LD A,'0' - 1 +LCD_PRTD3M2: + INC A + ADD HL,BC + JR C,LCD_PRTD3M2 + SBC HL,BC + CP E + JR Z,LCD_PRTD3M3 + LD E,0 + CALL LCD_OUTD +LCD_PRTD3M3: + RET +; +; DATA STORAGE +; +LCD_PRESENT .DB 0 ; NON-ZERO WHEN HARDWARE DETECTED +; +LCD_ROWS .DB $00,$40,$14,$54 ; ROW START INDEX +; +LCD_INIT_SEQ: + .DB LCD_FUNC_SET | %11000 ; FUNCTION SET, 2 LINES, 5X8 FONT + .DB LCD_FUNC_DISP ; DISPLAY OFF + .DB LCD_FUNC_CLEAR ; CLEAR DISPLAY, HOME CURSOR + .DB LCD_FUNC_ENTRY | $02 ; INCREMENT, NO SHIFT + .DB LCD_FUNC_DISP | $04 ; DISPLAY ON, NO CURSOR, NO BLINK + .DB $00 ; TERMINATOR +; +LCD_STR_BAN .DB "RomWBW v", BIOSVER, 0 +LCD_STR_CFG .DB "Build: ", CONFIG, 0 +LCD_STR_IO .DB "Disk #", 0 +LCD_STR_XPU .DB " CPU",0 +LCD_STR_SPD .DB "12.345",0 +LCD_STR_MHZ .DB " MHz",0 +; +LCD_CPU .DW LCD_CPU_Z80 + .DW LCD_CPU_Z180 + .DW LCD_CPU_Z180K + .DW LCD_CPU_Z180N + .DW LCD_CPU_Z280 +; +LCD_CPU_Z80 .DB "Z80",0 +LCD_CPU_Z180 .DB "Z180",0 +LCD_CPU_Z180K .DB "Z180-K",0 +LCD_CPU_Z180N .DB "Z180-N",0 +LCD_CPU_Z280 .DB "Z280",0 + + diff --git a/Source/HBIOS/lpt.asm b/Source/HBIOS/lpt.asm index 917a5a38..7e680296 100644 --- a/Source/HBIOS/lpt.asm +++ b/Source/HBIOS/lpt.asm @@ -50,7 +50,7 @@ ; ; D7 D6 D5 D4 D3 D2 D1 D0 ; +-------+-------+-------+-------+-------+-------+-------+-------+ -; | | | | /ERR | SEL | POUT | BUSY | /ACK | +; | | | | /ERR | SEL | POUT | BUSY | /ACK | ; +-------+-------+-------+-------+-------+-------+-------+-------+ ; ; PORT 2 (OUTPUT): @@ -62,40 +62,60 @@ ; ;================================================================================================== ; -; PRE-CONSOLE INITIALIZATION - DETECT AND INIT HARDWARE +; S100 STYLE INTERFACE: +; - S100 FPGA Z80 ; -LPT_PREINIT: +; BASE I/O PORT (OUTPUT): ; -; SETUP THE DISPATCH TABLE ENTRIES -; NOTE: INTS WILL BE DISABLED WHEN PREINIT IS CALLED AND THEY MUST -; REMAIN DISABLED. +; D7 D6 D5 D4 D3 D2 D1 D0 +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; | PD7 | PD6 | PD5 | PD4 | PD3 | PD2 | PD1 | PD0 | +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; +; STATUS PORT (INPUT, BASE I/O - 1): +; +; D7 D6 D5 D4 D3 D2 D1 D0 +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; | | | | | | | BUSY | /ACK | +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; +; CONTROL PORT (OUTPUT, BASE I/O - 1): +; +; D7 D6 D5 D4 D3 D2 D1 D0 +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; | | | | | | | | /STB | +; +-------+-------+-------+-------+-------+-------+-------+-------+ +; +;================================================================================================== ; +LPT_INIT: LD B,LPT_CFGCNT ; LOOP CONTROL XOR A ; ZERO TO ACCUM LD (LPT_DEV),A ; CURRENT DEVICE NUMBER LD IY,LPT_CFG ; POINT TO START OF CFG TABLE -LPT_PREINIT0: +LPT_INIT0: PUSH BC ; SAVE LOOP CONTROL CALL LPT_INITUNIT ; HAND OFF TO UNIT INIT CODE POP BC ; RESTORE LOOP CONTROL ; LD A,(IY+1) ; GET THE LPT TYPE DETECTED OR A ; SET FLAGS - JR Z,LPT_PREINIT2 ; SKIP IT IF NOTHING FOUND + JR Z,LPT_INIT2 ; SKIP IT IF NOTHING FOUND ; PUSH BC ; SAVE LOOP CONTROL PUSH IY ; CFG ENTRY ADDRESS POP DE ; ... TO DE LD BC,LPT_FNTBL ; BC := FUNCTION TABLE ADDRESS CALL NZ,CIO_ADDENT ; ADD ENTRY IF LPT FOUND, BC:DE + CALL LPT_PRTCFG ; PRINT IF NOT ZERO POP BC ; RESTORE LOOP CONTROL ; -LPT_PREINIT2: +LPT_INIT2: LD DE,LPT_CFGSIZ ; SIZE OF CFG ENTRY ADD IY,DE ; BUMP IY TO NEXT ENTRY - DJNZ LPT_PREINIT0 ; LOOP UNTIL DONE + DJNZ LPT_INIT0 ; LOOP UNTIL DONE ; -LPT_PREINIT3: +LPT_INIT3: XOR A ; SIGNAL SUCCESS RET ; AND RETURN ; @@ -119,24 +139,6 @@ LPT_INITUNIT: ; THE INITDEV ENTRY POINT THAT DOES NOT ENABLE/DISABLE INTS! JP LPT_INITDEVX ; IMPLEMENT IT AND RETURN ; -; -; -LPT_INIT: - LD B,LPT_CFGCNT ; COUNT OF POSSIBLE LPT UNITS - LD IY,LPT_CFG ; POINT TO START OF CFG TABLE -LPT_INIT1: - PUSH BC ; SAVE LOOP CONTROL - LD A,(IY+1) ; GET LPT TYPE - OR A ; SET FLAGS - CALL NZ,LPT_PRTCFG ; PRINT IF NOT ZERO - POP BC ; RESTORE LOOP CONTROL - LD DE,LPT_CFGSIZ ; SIZE OF CFG ENTRY - ADD IY,DE ; BUMP IY TO NEXT ENTRY - DJNZ LPT_INIT1 ; LOOP TILL DONE -; - XOR A ; SIGNAL SUCCESS - RET ; DONE -; ; DRIVER FUNCTION TABLE ; LPT_FNTBL: @@ -173,8 +175,16 @@ LPT_OUT: #IF (LPTMODE == LPTMODE_MG014) LD A,%00000100 ; SELECT & STROBE, LED OFF #ENDIF +#IF (LPTMODE == LPTMODE_S100) + LD A,%00000000 ; STROBE +#ENDIF +#IF ((LPTMODE == LPTMODE_SPP) | (LPTMODE == LPTMODE_MG014)) INC C ; PUT CONTROL PORT IN C INC C +#ENDIF +#IF (LPTMODE == LPTMODE_S100) + DEC C ; PUT CONTROL PORT IN C +#ENDIF OUT (C),A ; OUTPUT DATA TO PORT CALL DELAY #IF (LPTMODE == LPTMODE_SPP) @@ -182,6 +192,9 @@ LPT_OUT: #ENDIF #IF (LPTMODE == LPTMODE_MG014) LD A,%00000101 ; SELECT, LED OFF +#ENDIF +#IF (LPTMODE == LPTMODE_S100) + LD A,%11111111 ; STROBE #ENDIF OUT (C),A ; OUTPUT DATA TO PORT CALL DELAY @@ -199,7 +212,12 @@ LPT_IST: ; LPT_OST: LD C,(IY+3) ; BASE PORT +#IF ((LPTMODE == LPTMODE_SPP) | (LPTMODE == LPTMODE_MG014)) INC C ; SELECT STATUS PORT +#ENDIF +#IF (LPTMODE == LPTMODE_S100) + DEC C ; SELECT STATUS PORT +#ENDIF IN A,(C) ; GET STATUS INFO #IF (LPTMODE == LPTMODE_SPP) AND %10000000 ; ISOLATE /BUSY @@ -256,6 +274,14 @@ LPT_INITDEVX: RET ; RETURN #ENDIF ; +#IF (LPTMODE == LPTMODE_S100) + LD C,(IY+3) ; BASE PORT + DEC C ; DEC TO CONTROL PORT + LD A,$FF ; INIT VALUE + OUT (C),A ; DO IT + RET ; RETURN +#ENDIF +; ; ; LPT_QUERY: @@ -361,6 +387,13 @@ LPT_DETECT1: RET ; DONE #ENDIF ; +#IF (LPTMODE == LPTMODE_S100) +LPT_DETECT: + ; PORT ALWAYS EXISTS ON FPGA + LD A,LPTMODE_S100 ; RETURN CHIP TYPE + RET ; DONE +#ENDIF +; ; ; LPT_PRTCFG: @@ -400,10 +433,12 @@ LPT_TYPE_MAP: .DW LPT_STR_NONE .DW LPT_STR_SPP .DW LPT_STR_MG014 + .DW LPT_STR_S100 ; LPT_STR_NONE .DB "$" LPT_STR_SPP .DB "SPP$" LPT_STR_MG014 .DB "MG014$" +LPT_STR_S100 .DB "S100$" ; ; WORKING VARIABLES ; @@ -427,6 +462,9 @@ LPT0_CFG: #ENDIF #IF (LPTMODE == LPTMODE_MG014) DEVECHO "MG014" + #ENDIF + #IF (LPTMODE == LPTMODE_S100) + DEVECHO "S100" #ENDIF DEVECHO ", IO=" DEVECHO LPT0BASE @@ -450,6 +488,9 @@ LPT1_CFG: #ENDIF #IF (LPTMODE == LPTMODE_MG014) DEVECHO "MG014" + #ENDIF + #IF (LPTMODE == LPTMODE_S100) + DEVECHO "S100" #ENDIF DEVECHO ", IO=" DEVECHO LPT1BASE diff --git a/Source/HBIOS/md.asm b/Source/HBIOS/md.asm index 0d8b3378..e7e7fcea 100644 --- a/Source/HBIOS/md.asm +++ b/Source/HBIOS/md.asm @@ -64,6 +64,8 @@ MD_DEVCNT .EQU ($ - MD_CFGTBL) / MD_CFGSIZ ; ; ; + + MD_INIT: #IF (MDFFENABLE) CALL MD_FINIT ; PROBE FLASH CAPABILITY @@ -301,13 +303,13 @@ MD_RW: MD_RW1: PUSH BC ; SAVE COUNTERS ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,MD_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; LD HL,(MD_RWFNADR) ; GET PENDING IO FUNCTION ADDRESS #IF (MDFFENABLE) diff --git a/Source/HBIOS/ppa.asm b/Source/HBIOS/ppa.asm index 0b6da099..a30aa08a 100644 --- a/Source/HBIOS/ppa.asm +++ b/Source/HBIOS/ppa.asm @@ -339,13 +339,13 @@ PPA_IO: ; LD (PPA_DSKBUF),HL ; SAVE DISK BUFFER ADDRESS ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,PPA_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; ; SETUP LBA ; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN diff --git a/Source/HBIOS/ppide.asm b/Source/HBIOS/ppide.asm index 246b74da..7ab1cdbc 100644 --- a/Source/HBIOS/ppide.asm +++ b/Source/HBIOS/ppide.asm @@ -351,7 +351,8 @@ PPIDE_DEV2S: ; DEVICE 2, SLAVE ; BASED ON REAL WORLD EXPERIENCE. ; PPIDE_TOSLOW .EQU 200 ; SLOW TIMEOUT IS 20 SECS -PPIDE_TONORM .EQU 5 ; NORMAL TIMEOUT IS 0.5 SECS +;PPIDE_TONORM .EQU 5 ; NORMAL TIMEOUT IS 0.5 SECS +PPIDE_TONORM .EQU 200 ; NORMAL TIMEOUT IS 0.5 SECS ; ;============================================================================= ; INITIALIZATION ENTRY POINT @@ -832,13 +833,13 @@ PPIDE_PKT_RDSEC: #ENDIF ; SETUP LBA ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,PPIDE_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; ; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN LD HL,PPIDE_PKTCMD_RW10+3 ; START OF LBA FIELD IN CDB (MSB) @@ -901,13 +902,13 @@ PPIDE_PKT_WRSEC: #ENDIF ; SETUP LBA ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,PPIDE_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; ; 3 BYTES, LITTLE ENDIAN -> BIG ENDIAN LD HL,PPIDE_PKTCMD_RW10+3 ; START OF LBA FIELD IN CDB (MSB) @@ -933,13 +934,13 @@ PPIDE_PKT_WRSEC: ; PPIDE_SETADDR: ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,PPIDE_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER ; IDE_REG_LBA3 HAS ALREADY BEEN SET ; HSTLBA2-0 --> IDE_REG_LBA2-0 @@ -1536,6 +1537,13 @@ PPIDE_PROBE: ; WAIT FOR THE DEVICE TO BE READY. THIS WAIT IS MANDATORY BECAUSE ; SOME (IF NOT ALL) DEVICES WILL NOT PERSIST REGISTER VALUES UNTIL ; THE DRIVE IS READY. +; + ; FIRST, WRITE A $7F VALUE TO THE PPIDE STATUS REGISTER. IF + ; AN IDE DEVICE EXISTS, THIS WILL DO NO HARM. IF NOT, THIS + ; WILL HELP AVOID A FALSE POSITIVE (STALL). + LD A,$7F + CALL PPIDE_OUT + .DB PPIDE_REG_DATA ; CALL PPIDE_IN .DB PPIDE_REG_STAT diff --git a/Source/HBIOS/ppp.asm b/Source/HBIOS/ppp.asm index 9b1c1301..a4afb9e5 100644 --- a/Source/HBIOS/ppp.asm +++ b/Source/HBIOS/ppp.asm @@ -276,7 +276,8 @@ PPPCON_INIT: LD E,CIODEV_PPPCON ; DEVICE TYPE LD BC,PPPCON_FNTBL ; BC := FUNCTION TABLE ADDRESS CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED - LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + ;;;LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + CALL CIO_SETCRT ; SET OURSELVES AS THE CRT DEVICE ; XOR A RET @@ -948,11 +949,11 @@ PPPSD_SENDBLK: LD A,PPPSD_LBA ; OFFSET OF LBA CALL LDHLIYA ; HL := IY + A, REG A TRASHED -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF LD B,4 PPPSD_SENDBLK1: LD A,(HL) diff --git a/Source/HBIOS/prp.asm b/Source/HBIOS/prp.asm index 6cc98ff2..f00557ed 100644 --- a/Source/HBIOS/prp.asm +++ b/Source/HBIOS/prp.asm @@ -150,7 +150,8 @@ PRPCON_INIT: LD E,CIODEV_PRPCON ; DEVICE TYPE LD BC,PRPCON_FNTBL ; BC := FUNCTION TABLE ADDRESS CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED - LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + ;;;LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + CALL CIO_SETCRT ; SET OURSELVES AS THE CRT DEVICE ; XOR A ; SIGNAL SUCCESS RET @@ -882,11 +883,11 @@ PRPSD_SETBLK: LD B,4 ; 4 BYTES LD A,PRPSD_LBA ; OFFSET OF LBA CALL LDHLIYA ; HL := IY + A, REG A TRASHED -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF OTIR RET ; diff --git a/Source/HBIOS/rf.asm b/Source/HBIOS/rf.asm index cd804074..6d80fc81 100644 --- a/Source/HBIOS/rf.asm +++ b/Source/HBIOS/rf.asm @@ -333,13 +333,13 @@ RF_SETIO: ; RF_SETADR: ; -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) LD A,RF_LBA CALL LDHLIYA CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF ; LD A,(RF_IO) ; OUTPUT THE LOGICAL BLOCK OR RF_AL ; ADDRESS TO THE diff --git a/Source/HBIOS/romldr.asm b/Source/HBIOS/romldr.asm index 0c20695f..e6745893 100644 --- a/Source/HBIOS/romldr.asm +++ b/Source/HBIOS/romldr.asm @@ -2415,8 +2415,8 @@ ra_ent .equ 12 ; ; Note: The loadable ROM images are placed in ROM banks BID_IMG0 and ; BID_IMG1. However, RomWBW supports a mechanism to load a complete -; new system dynamically as a runnable application (see appboot and -; imgboot in hbios.asm). In this case, the contents of BID_IMG0 will +; new system dynamically as a runnable application (see appboot +; in hbios.asm). In this case, the contents of BID_IMG0 will ; be pre-loaded into the currently executing ram bank thereby allowing ; those images to be dynamically loaded as well. To support this ; concept, a pseudo-bank called bid_cur is used to specify the images @@ -2436,14 +2436,13 @@ ra_entsiz .equ $ - ra_tbl ra_ent(str_smon, 'S', $FF, bid_cur , $8000, $8000, $0001, s100mon) #endif #endif -ra_ent(str_zsys, 'Z', KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT) ra_ent(str_cpm22, 'C', KY_BK, BID_IMG0, CPM_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT) +ra_ent(str_zsys, 'Z', KY_FW, BID_IMG0, ZSYS_IMGLOC, CPM_LOC, CPM_SIZ, CPM_ENT) #if (BIOS == BIOS_WBW) -ra_ent(str_fth, 'F', KY_EX, BID_IMG1, FTH_IMGLOC, FTH_LOC, FTH_SIZ, FTH_LOC) ra_ent(str_bas, 'B', KY_DE, BID_IMG1, BAS_IMGLOC, BAS_LOC, BAS_SIZ, BAS_LOC) ra_ent(str_tbas, 'T', KY_EN, BID_IMG1, TBC_IMGLOC, TBC_LOC, TBC_SIZ, TBC_LOC) +ra_ent(str_fth, 'F', KY_EX, BID_IMG1, FTH_IMGLOC, FTH_LOC, FTH_SIZ, FTH_LOC) ra_ent(str_play, 'P', $FF, BID_IMG1, GAM_IMGLOC, GAM_LOC, GAM_SIZ, GAM_LOC) -ra_ent(str_egg, 'E'+$80, $FF, BID_IMG1, EGG_IMGLOC, EGG_LOC, EGG_SIZ, EGG_LOC) ra_ent(str_net, 'N', $FF, BID_IMG1, NET_IMGLOC, NET_LOC, NET_SIZ, NET_LOC) ra_ent(str_upd, 'X', $FF, BID_IMG1, UPD_IMGLOC, UPD_LOC, UPD_SIZ, UPD_LOC) ra_ent(str_user, 'U', $FF, BID_IMG1, USR_IMGLOC, USR_LOC, USR_SIZ, USR_LOC) @@ -2451,6 +2450,7 @@ ra_ent(str_user, 'U', $FF, BID_IMG1, USR_IMGLOC, USR_LOC, USR_SIZ, USR_LO #if (DSKYENABLE) ra_ent(str_dsky, 'Y'+$80, KY_GO, BID_IMG0, MON_IMGLOC, MON_LOC, MON_SIZ, MON_DSKY) #endif +ra_ent(str_egg, 'E'+$80, $FF, BID_IMG1, EGG_IMGLOC, EGG_LOC, EGG_SIZ, EGG_LOC) .dw 0 ; table terminator ; ra_tbl_app: diff --git a/Source/HBIOS/scon.asm b/Source/HBIOS/scon.asm index 1d3b4a5d..9d8452de 100644 --- a/Source/HBIOS/scon.asm +++ b/Source/HBIOS/scon.asm @@ -5,7 +5,7 @@ ; ; TODO: ; -SCON_IOBASE .EQU $00 +SCON_IOBASE .EQU $0000 ; NOTE: 16-BIT I/O ; SCON_STATUS .EQU SCON_IOBASE SCON_DATA .EQU SCON_IOBASE + 1 @@ -25,6 +25,9 @@ SCON_ROWS .EQU 40 SCON_INIT: CALL NEWLINE PRTS("SCON:$") + PRTS(" IO=0x$") ; FORMATTING + LD A,SCON_IOBASE + CALL PRTHEXBYTE ; ; DISPLAY CONSOLE DIMENSIONS CALL PC_SPACE @@ -43,7 +46,8 @@ SCON_INIT: LD E,CIODEV_SCON ; DEVICE TYPE LD BC,SCON_FNTBL ; BC := FUNCTION TABLE ADDRESS CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED - LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + ;;;LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + CALL CIO_SETCRT ; SET OURSELVES AS THE CRT DEVICE ; XOR A ; SIGNAL SUCCESS RET @@ -67,14 +71,18 @@ SCON_FNTBL: SCON_IN: CALL SCON_IST ; CHECK FOR CHAR PENDING JR Z,SCON_IN ; WAIT FOR IT IF NECESSARY - IN0 A,(SCON_DATA) ; READ THE CHAR FROM PROPIO + ;IN0 A,(SCON_DATA) ; READ THE CHAR FROM PROPIO + LD BC,SCON_DATA ; DATA PORT (16 BIT I/O) + IN A,(C) ; READ THE CHAR FROM PROPIO LD E,A RET ; ; ; SCON_IST: - IN0 A,(SCON_STATUS) ; READ LINE STATUS REGISTER + ;IN0 A,(SCON_STATUS) ; READ LINE STATUS REGISTER + LD BC,SCON_STATUS ; STATUS PORT (16-BIT I/O) + IN A,(C) ; READ LINE STATUS REGISTER AND SCON_KBDRDY ; ISOLATE KBDRDY JP Z,CIO_IDLE ; RETURN VIA IDLE PROCESSING OR $FF ; SET A=$FF TO SIGNAL READY @@ -86,13 +94,17 @@ SCON_OUT: CALL SCON_OST ; CHECK FOR OUTPUT READY JR Z,SCON_OUT ; WAIT IF NECESSARY LD A,E ; RECOVER THE CHAR TO WRITE - OUT0 (SCON_DATA),A ; WRITE THE CHAR TO PROPIO + ;OUT0 (SCON_DATA),A ; WRITE THE CHAR TO PROPIO + LD BC,SCON_DATA ; DATA PORT (16 BIT I/O) + OUT (C),A ; WRITE THE CHAR TO PROPIO RET ; ; ; SCON_OST: - IN0 A,(SCON_STATUS) ; READ LINE STATUS REGISTER + ;IN0 A,(SCON_STATUS) ; READ LINE STATUS REGISTER + LD BC,SCON_STATUS ; STATUS PORT (16-BIT I/O) + IN A,(C) ; READ LINE STATUS REGISTER AND SCON_DSPRDY ; ISOLATE DSPRDY JP Z,CIO_IDLE ; RETURN VIA IDLE PROCESSING OR $FF ; SET A=$FF TO SIGNAL READY diff --git a/Source/HBIOS/sd.asm b/Source/HBIOS/sd.asm index aa77ef6e..3873e36e 100644 --- a/Source/HBIOS/sd.asm +++ b/Source/HBIOS/sd.asm @@ -125,8 +125,8 @@ SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION SD_OPRDEF .EQU %00000001 ; QUIESCENT STATE SD_OPRMSK .EQU %10000111 ; MASK FOR BITS WE OWN IN RTC LATCH PORT SD_INPREG .EQU RTCIO ; INPUT REGISTER IS RTC -SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT -SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK +SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT +SD_CLK .EQU %00000010 ; RTC:1 IS CLOCK SD_DI .EQU %00000001 ; RTC:0 IS DATA IN (CARD <- CPU) SD_DO .EQU %10000000 ; RTC:7 IS DATA OUT (CARD -> CPU) SD_IOBASE .EQU SD_OPRREG ; IOBASE @@ -242,7 +242,21 @@ SD_TRDR .EQU Z180_TRDR SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU TRUE ; INVERT CS DEVECHO "SC" +RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE +#ENDIF ; +#IF (SDMODE == SDMODE_GM) ; GM +SD_DEVMAX .EQU 2 ; NUMBER OF PHYSICAL UNITS (SOCKETS) +SD_OPRREG .EQU RTCIO ; USES RTC LATCHES FOR OPERATION +SD_OPRDEF .EQU %00000100 ; QUIESCENT STATE (/CS1 & /CS2 DEASSERTED) +SD_OPRMSK .EQU %00000100 ; MASK FOR BITS WE OWN IN RTC LATCH PORT +SD_CS0 .EQU %00000100 ; RTC:2 IS SELECT FOR PRIMARY SPI CARD +SD_CS1 .EQU %00000000 ; RTC:3 IS SELECT FOR SECONDARY SPI CARD +SD_CNTR .EQU Z180_CNTR +SD_TRDR .EQU Z180_TRDR +SD_IOBASE .EQU SD_OPRREG ; IOBASE +SD_INVCS .EQU TRUE ; INVERT CS + DEVECHO "GM" RTCDEF .SET RTCDEF | SD_OPRDEF ; SET DEFAULT IN HBIOS MAINLINE #ENDIF ; @@ -372,10 +386,10 @@ SD_CS0 .EQU %00000100 ; SELECT SD_DI .EQU %00000001 ; DATA IN (CARD <- CPU) MOSI SD_DO .EQU %00000001 ; DATA OUT (CARD -> CPU) MISO SD_CINIT .EQU FALSE ; INITIALIZE OUTPUT PORT -SD_INVCS .EQU FALSE ; INVERT CS +SD_INVCS .EQU TRUE ; INVERT CS DEVECHO "Z80R" #ENDIF - +; ; FOR NOW WE JUST HOOK UP ONE UNIT. THERE ARE EIGHT PORTS FOR DIFFERENT ; THINGS BUT THIS WILL GET US GOING #IF (SDMODE == SDMODE_EPITX) ; Z180 ITX - CSIO, 82C55 for CS @@ -389,6 +403,39 @@ SD_IOBASE .EQU SD_OPRREG ; IOBASE SD_INVCS .EQU FALSE ; INVERT CS DEVECHO "EPITX" #ENDIF +; +; S100 FPGA Z80 SPI-BASED SD CARD +; +; BASE PORT: $6C +; BASE + 0: DATA IN/OUT +; BASE + 1: SPI CLOCK SPEED (0=LOW 4KHZ, 1=HIGH 10MHZ) +; BASE + 2: SELECT (W), STATUS (R) +; BASE + 3: START READ (IN OPCODE), START WRITE (OUT OPCODE), ANY VALUE +; +; STATUS BITS: +; 7: BUSY (1=BUSY) +; 0: PRIMARY DEVICE SELECT STATUS (1=SELECTED) +; 1: SECONDARY DEVICE SELECT STATUS (1=SELECTED) +; +; SELECT BITS (INVERTED!!!): +; 0: PRIMARY DEVICE, USE VALUE ~$01 +; 1: SECONDARY DEVICE, USE VALUE ~$02 +; +#IF (SDMODE == SDMODE_FZ80) ; S100 FPGA Z80 +SD_IOBASE .EQU $6C ; IOBASE +SD_DATA .EQU SD_IOBASE + 0 ; DATA IN/OUT PORT +SD_CLKSEL .EQU SD_IOBASE + 1 ; CLOCK SPEED SELECT PORT +SD_SELSTAT .EQU SD_IOBASE + 2 ; DEVICE SELECT PORT (W) / STATUS (R) +SD_ACTION .EQU SD_IOBASE + 3 ; INITIATE R/W ACTION VIA IN/OUT +; +SD_DEVMAX .EQU 2 ; NUMBER OF PHYSICAL UNITS (SOCKETS) +SD_OPRREG .EQU SD_SELSTAT ; SELECT/STATUS PORT +SD_OPRDEF .EQU $FF ; QUIESCENT STATE +SD_CS0 .EQU %00000001 ; PRIMARY DEVICE SELECT BIT +SD_CS1 .EQU %00000010 ; SECONDARY DEVICE SELECT BIT +SD_INVCS .EQU TRUE ; INVERT CS + DEVECHO "FZ80" +#ENDIF ; DEVECHO ", IO=" DEVECHO SD_IOBASE @@ -413,6 +460,7 @@ SD_CMD_READ_SNGL_BLK .EQU $40 + 17 ; $51, CMD17 -> R1 SD_CMD_WRITE_BLOCK .EQU $40 + 24 ; $58, CMD24 -> R1 SD_CMD_APP_CMD .EQU $40 + 55 ; $77, CMD55 -> R1 SD_CMD_READ_OCR .EQU $40 + 58 ; $7A, CMD58 -> R3 +SD_CMD_CRC_ON_OFF .EQU $40 + 59 ; $7B, CMD59 -> R1 ; ; SD CARD APPLICATION COMMANDS (PRECEDED BY APP_CMD COMMAND) ; @@ -574,7 +622,7 @@ SD_INIT: CALL PRTHEXBYTE #ENDIF ; -#IF (SDMODE == SDMODE_SC) +#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM)) PRTS(" MODE=SC$") #IF (SDCSIOFAST) PRTS(" FAST$") @@ -640,6 +688,13 @@ SD_INIT: LD A,SD_TRDR CALL PRTHEXBYTE #ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + PRTS(" MODE=FZ80$") + PRTS(" IO=0x$") + LD A,SD_IOBASE + CALL PRTHEXBYTE +#ENDIF ; CALL SD_PROBE ; CHECK FOR HARDWARE JR Z,SD_INIT00 ; CONTINUE IF PRESENT @@ -901,19 +956,12 @@ SD_IO: OR A ; SET FLAGS RET Z ; ZERO SECTOR I/O, RETURN W/ E=0 & A=0 ; -#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) - ; CONSIDER CAPTURING CURRENT CNTR VALUE HERE AND USE IT - ; IN SD_CSIO_DEF - ; SET CSIO FOR HIGH SPEED OPERATION - CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING - CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT - XOR A ; ZERO MEANS MAX SPEED - OUT0 (SD_CNTR),A ; NOW SET CSIO PORT + CALL SD_SPD_FAST +; ; HOOK RETURN TO RESTORE CSIO TO DEFAULT SPEED - LD HL,SD_CSIO_DEF ; ROUTE RETURN + LD HL,SD_SPD_STD ; ROUTE RETURN PUSH HL ; ... THRU CSIO RESTORE -#ENDIF ; #IF (SDTRACE == 1) LD HL,SD_PRTERR ; SET UP SD_PRTERR @@ -1005,6 +1053,9 @@ SD_MEDIA: JR NZ,SD_MEDIA1 ; ERROR ACTIVE, GO RIGHT TO RESET ; ; USE SEND_CSD TO CHECK CARD + ;;;LD A,'C' ;;; + ;;;CALL COUT ;;; + CALL SD_SPD_FAST ; GO FAST FOR COMPATIBILITY CALL SD_SELUNIT ; SET CUR UNIT LD A,SD_CMD_SEND_CSD ; SEND_CSD CALL SD_INITCMD ; SETUP COMMAND BUFFER @@ -1017,9 +1068,14 @@ SD_MEDIA: JR Z,SD_MEDIA2 ; IF SUCCESS, BYPASS RESET ; SD_MEDIA1: + ;;;LD A,'R' ;;; + ;;;CALL COUT ;;; CALL SD_RESET ; RESET CARD ; SD_MEDIA2: + ;;;LD A,'D' ;;; + ;;;CALL COUT ;;; + CALL SD_SPD_STD ; BACK TO STD SPEED LD A,(IY+SD_STAT) ; GET STATUS OR A ; SET FLAGS LD D,0 ; NO MEDIA CHANGE DETECTED @@ -1032,7 +1088,6 @@ SD_MEDIA2: ; ; ; -; SD_SEEK: BIT 7,D ; CHECK FOR LBA FLAG CALL Z,HB_CHS2LBA ; CLEAR MEANS CHS, CONVERT TO LBA @@ -1080,9 +1135,7 @@ SD_INITCARD: CALL SD_CHKCD ; CHECK CARD DETECT JP Z,SD_NOMEDIA ; Z=NO MEDIA, HANDLE IF SO ; -#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) - CALL SD_CSIO_DEF ; ENSURE CSIO AT DEFAULT SPEED -#ENDIF + CALL SD_SPD_SLOW ; SET SLOW SPEED FOR INIT ; ; WAKE UP THE CARD, KEEP DIN HI (ASSERTED) AND /CS HI (DEASSERTED) LD B,$10 ; MIN 74 CLOCKS REQUIRED, WE USE 128 ($10 * 8) @@ -1093,8 +1146,8 @@ SD_INITCARD1: POP BC ; RESTORE LOOP CONTROL DJNZ SD_INITCARD1 ; LOOP AS NEEDED ; - ; MAKE SURE WE FINISH SENDING -#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM) | (SDMODE == SDMODE_EPITX)) + ; MAKE SURE CSIO IS DONE SENDING DATA CALL SD_WAITTX ; WAIT FOR TE TO CLEAR CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT #ENDIF @@ -1189,9 +1242,28 @@ SD_INITCARD4: CALL SD_INITCMD ; SETUP COMMAND BUFFER CALL SD_EXECCMD ; EXECUTE COMMAND RET NZ ; ABORT ON ERROR - ; CMD58 WORKED, GET OCR DATA AND SET CARD TYPE - CALL SD_GET ; BITS 31-24 + ; CMD58 WORKED, GET OCR DATA + LD B,4 ; 4 BYTES OF OCR + LD HL,SD_BUF ; PUT IN OUR PRIVATE BUFFER +SD_INITCARD4B: + PUSH BC ; SAVE LOOP CONTROL + CALL SD_GET ; GET NEXT BYTE + POP BC ; RESTORE LOOP CONTROL + LD (HL),A ; SAVE IT + INC HL ; BUMP BUF PTR + DJNZ SD_INITCARD4B ; LOOP AS NEEDED CALL SD_DONE ; FINISH THE TRANSACTION +; +#IF (SDTRACE >= 3) + ; IF TRACING, DUMP THE OCR CONTENTS + CALL SD_PRTPREFIX + LD DE,SD_STR_OCR + CALL WRITESTR + LD DE,SD_BUF + LD A,4 + CALL PRTHEXBUF +#ENDIF + LD A,(SD_BUF) ; FIRST BYTE OF BUF (BITS 31-24 OF OCR) AND $40 ; ISOLATE BIT 30 (CCS) LD C,SD_TYPESDSC ; ASSUME V1 CARD JR Z,SD_INITCARD5 ; IF BIT NOT SET, THIS IS SDSC CARD @@ -1254,7 +1326,7 @@ SD_INITCARD5: ; HIGH SPEED CSIO OPERATION IS NOW SET AT THE START OF SD_IO ; -;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) +;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM)) ; ; PER SPEC, THE CARD SHOULD NOW BE ABLE TO HANDLE FULL SPEED OPERATION ; ; SO, FOR CSIO OPERATION, WE SET CSIO TO MAXIMUM SPEED ; CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING @@ -1439,11 +1511,11 @@ SD_SETADDR: PUSH AF ; SAVE IT LD A,SD_LBA ; OFFSET OF LBA VALUE CALL LDHLIYA ; HL := IY + A, REG A TRASHED -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF CALL LD32 ; LOAD IT TO DE:HL, AF IS TRASHED POP AF ; GET CARD TYPE BACK CP SD_TYPESDHC ; IS IT V2 OR BETTER? @@ -1486,8 +1558,10 @@ SD_GOIDLE: ; SD_GOIDLE1: ; SEEMS TO HELP SOME CARDS? - ;CALL SD_SELECT ; ASSERT CS - ;CALL SD_DONE ; SEND 8 CLOCKS AND DEASSERT CS + ;;; DEBUG + CALL SD_SELECT ; ASSERT CS + CALL SD_DONE ; SEND 8 CLOCKS AND DEASSERT CS + ;;; DEBUG ; SMALL DELAY HERE HELPS SOME CARDS ;;LD DE,300 ; 16US * 300 = ~5MS @@ -1699,8 +1773,11 @@ SD_GETDATA3: LD A,D OR E JR NZ,SD_GETDATA3 ; LOOP FOR ALL BYTES + ;;;CALL PC_SPACE CALL SD_GET ; DISCARD CRC BYTE 1 + ;;;CALL PRTHEXBYTE CALL SD_GET ; DISCARD CRC BYTE 2 + ;;;CALL PRTHEXBYTE #ENDIF XOR A ; RESULT IS ZERO SD_GETDATA4: @@ -1811,6 +1888,11 @@ SD_DONE: PUSH AF LD A,$FF CALL SD_PUT +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) + ; MAKE SURE CSIO IS DONE SENDING DATA + CALL SD_WAITTX ; WAIT FOR TE TO CLEAR + CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT +#ENDIF CALL SD_DESELECT POP AF RET @@ -1830,14 +1912,14 @@ SD_SETUP: OUT (SD_PPIX),A #ENDIF ; -#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) ; CSIO SETUP FOR Z180 CSIO ; LD A,2 ; DIV 80, 225KHZ @ 18MHZ CLK LD A,6 ; DIV 1280, 14KHZ @ 18MHZ CLK OUT0 (SD_CNTR),A #ENDIF ; -#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC)) +#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM)) LD A,(HB_RTCVAL) LD (SD_OPRVAL),A OUT (SD_OPRREG),A @@ -1884,6 +1966,15 @@ SD_SETUP: LD (SD_OPRVAL),A OUT (SD_OPRREG),A #ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + LD A,SD_OPRDEF ; DEFAULT SELECT VALUE + LD (SD_OPRVAL),A ; PUT IN SHADOW + OUT (SD_OPRREG),A ; WRITE TO PORT + XOR A ; LOW SPEED OPERATION + LD (SD_CLKSEL),A ; DO IT + CALL SD_DESELECT ; MAKE SURE CARD(S) ARE NOT SELECTED +#ENDIF ; XOR A RET @@ -1927,11 +2018,11 @@ SD_CHKWP: ; SD_SELECT: ; ; FINISH SENDING BEFORE ASSERTING CS! -;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) +;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM)) ; CALL SD_WAITTX ;#ENDIF ; -#IF ((SDMODE == SDMODE_SC) | SDMODE == SDMODE_MT)) +#IF ((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_MT) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) LD A,(IY+SD_DEV) ; GET CURRENT DEVICE OR A ; SET FLAGS LD A,(SD_OPRVAL) ; GET CURRENT OPRVAL BACK @@ -1949,21 +2040,21 @@ SD_SELECT1: OR SD_CS1 #ENDIF #ELSE -#IF (SDMODE == SDMODE_EPITX) + #IF (SDMODE == SDMODE_EPITX) LD A,(SD_OPRVAL) AND $F8 OR SD_CS0 ; WILL DO 1-7 LATER -#ELSE + #ELSE LD A,(SD_OPRVAL) ; GET CURRENT OPRVAL BACK OR SD_CS0 -#ENDIF + #ENDIF #ENDIF ; SD_SELECT2: ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS -;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC)) +;#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM)) #IF (SD_INVCS) - #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1)) + #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1)) XOR SD_CS0 | SD_CS1 #ELSE XOR SD_CS0 @@ -1972,7 +2063,7 @@ SD_SELECT2: LD (SD_OPRVAL),A OUT (SD_OPRREG),A ;; -;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC)) +;#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_GM)) ; CALL DLY32 ; DELAY FOR FINAL BIT ;#ENDIF ; @@ -1981,7 +2072,7 @@ SD_SELECT2: ; DESELECT CARD ; SD_DESELECT: -#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) ; DON'T REMOVE CS UNTIL WE ARE DONE SENDING! CALL SD_WAITTX ; WAIT FOR TE TO CLEAR ; @@ -1994,20 +2085,24 @@ SD_DESELECT: ; TRACES. CALL DLY32 ; DELAY FOR FINAL BIT #ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + ;;;CALL SD_WAITBSY +#ENDIF ; LD A,(SD_OPRVAL) -#IF (((SDMODE == SDMODE_SC) | (SDMODE_MT)) & (SD_DEVCNT > 1)) +#IF (((SDMODE == SDMODE_SC) | (SDMODE_MT) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1)) AND ~(SD_CS0 | SD_CS1) #ELSE -#if (SDMODE == SDMODE_EPITX) +#IF (SDMODE == SDMODE_EPITX) OR 7 ; CHAN 7 IS USED FOR DESELECTS #ELSE AND ~SD_CS0 #ENDIF #ENDIF ; ADJUST BIT(S) FOR INTERFACES USING INVERTED CS BITS -#IF ((SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_PIO) | (SDMODE == SDMODE_Z80R)) - #IF ((SDMODE == SDMODE_SC) & (SD_DEVCNT > 1)) +#IF (SD_INVCS) + #IF (((SDMODE == SDMODE_SC) | (SDMODE == SDMODE_FZ80) | (SDMODE == SDMODE_GM)) & (SD_DEVCNT > 1)) XOR SD_CS0 | SD_CS1 #ELSE XOR SD_CS0 @@ -2017,7 +2112,7 @@ SD_DESELECT: OUT (SD_OPRREG),A RET ; -#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) ; ; CSIO WAIT FOR TRANSMIT READY (TX REGISTER EMPTY) ; @@ -2037,24 +2132,38 @@ SD_WAITRX: ; #ENDIF ; +#IF (SDMODE == SDMODE_FZ80) +; +; WAIT WHILE FPGA SPI INTERFACE IS BUSY SENDING OR RECEIVING +; +SD_WAITBSY: + PUSH AF +SD_WAITBSY1: + IN A,(SD_SELSTAT) + BIT 7,A + JR NZ,SD_WAITBSY1 + POP AF + RET +#ENDIF +; ; SEND ONE BYTE ; SD_PUT: ; #IF (SDMODE == SDMODE_MT) OUT (SD_WRTR),A -#ELSE +#ENDIF ; - #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) CALL MIRROR ; MSB<-->LSB MIRROR BITS, RESULT IN C CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING OUT0 (SD_TRDR),C ; PUT BYTE IN BUFFER IN0 A,(SD_CNTR) SET 4,A ; SET TRANSMIT ENABLE OUT0 (SD_CNTR),A - #ELSE - - #IF (SDMODE == SDMODE_Z80R) +#ENDIF +; +#IF (SDMODE == SDMODE_Z80R) ; USE C - THE CALLING CODE FOR COMMAND SEND FAILS TO SAVE HL/DE ; WHILST THE OTHER PATHS DO ? LD C,A @@ -2090,8 +2199,9 @@ SD_PUT: RLA OUT (SD_IOREG),A OUT (SD_IOCLK),A - #ELSE - +#ENDIF +; +#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO)) #IF (SDMODE == SDMODE_UART) XOR $FF ; DI IS INVERTED ON UART #ENDIF @@ -2110,8 +2220,15 @@ SD_PUT1: DJNZ SD_PUT1 ; REPEAT FOR ALL 8 BITS LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE OUT (SD_OPRREG),A ; LEAVE WITH CLOCK LOW - #ENDIF - #ENDIF +#ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + ;;;CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY + OUT (SD_DATA),A ; POST THE VALUE + OUT (SD_ACTION),A ; INITIATE THE WRITE + ;;;CALL PC_SPACE ; *DEBUG* + ;;;CALL PC_GT ; *DEBUG* + ;;;CALL PRTHEXBYTE ; *DEBUG* #ENDIF RET ; DONE ; @@ -2122,8 +2239,9 @@ SD_GET: ; #IF (SDMODE == SDMODE_MT) IN A,(SD_RDTR) -#ELSE - #IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +#ENDIF +; +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING IN0 A,(SD_CNTR) ; GET CSIO STATUS SET 5,A ; START RECEIVER @@ -2132,8 +2250,9 @@ SD_GET: IN0 A,(SD_TRDR) ; GET RECEIVED BYTE CALL MIRROR ; MSB<-->LSB MIRROR BITS LD A,C ; KEEP RESULT - #ELSE - #IF (SDMODE == SDMODE_Z80R) +#ENDIF +; +#IF (SDMODE == SDMODE_Z80R) ; MUST PRESERVE HL,DE PUSH DE LD A,1 @@ -2180,46 +2299,68 @@ SD_GET: RL E LD A,E POP DE - #ELSE +#ENDIF +; +#IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_N8) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_UART) | (SDMODE == SDMODE_DSD) | (SDMODE == SDMODE_USR) | (SDMODE == SDMODE_PIO)) LD B,8 ; RECEIVE 8 BITS (LOOP 8 TIMES) LD A,(SD_OPRVAL) ; LOAD CURRENT OPR VALUE SD_GET1: XOR SD_CLK ; TOGGLE CLOCK OUT (SD_OPRREG),A ; UPDATE CLOCK IN A,(SD_INPREG) ; READ THE DATA WHILE CLOCK IS ACTIVE - #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO)) + #IF ((SDMODE == SDMODE_JUHA) | (SDMODE == SDMODE_PPI) | (SDMODE == SDMODE_PIO)) RLA ; ROTATE INP:7 INTO CF - #ENDIF - #IF (SDMODE == SDMODE_N8) + #ENDIF + #IF (SDMODE == SDMODE_N8) RLA ; ROTATE INP:6 INTO CF RLA ; " - #ENDIF - #IF (SDMODE == SDMODE_UART) + #ENDIF + #IF (SDMODE == SDMODE_UART) RLA ; ROTATE INP:5 INTO CF RLA ; " RLA ; " - #ENDIF - #IF (SDMODE == SDMODE_DSD) + #ENDIF + #IF (SDMODE == SDMODE_DSD) RRA ; ROTATE INP:0 INTO CF - #ENDIF + #ENDIF RL C ; ROTATE CF INTO C:0 LD A,(SD_OPRVAL) ; BACK TO INITIAL VALUES (TOGGLE CLOCK) OUT (SD_OPRREG),A ; DO IT DJNZ SD_GET1 ; REPEAT FOR ALL 8 BITS LD A,C ; GET BYTE RECEIVED INTO A - #IF (SDMODE == SDMODE_UART) + #IF (SDMODE == SDMODE_UART) XOR $FF ; DO IS INVERTED ON UART - #ENDIF - #ENDIF #ENDIF +#ENDIF +; +#IF (SDMODE == SDMODE_FZ80) + ;;;CALL SD_WAITBSY ; WAIT FOR PENDING ACTIVITY + IN A,(SD_ACTION) ; INITIATE READ + ;;;CALL SD_WAITBSY ; WAIT FOR DONE + IN A,(SD_DATA) ; GET THE VALUE +#ENDIF + RET +; +; SET STANDARD SPEED (RESTORE SPI INTERFACE TO DEFAULTS) +; +SD_SPD_STD: +; +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) + ; SET CSIO FOR DEFAULT OPERATION + PUSH AF ; PRESERVE AF + CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING + CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT + LD A,Z180_CNTR_DEF ; DIV 1280, 14KHZ @ 18MHZ CLK + OUT0 (SD_CNTR),A ; DO IT + POP AF ; RESTORE AF #ENDIF RET ; -; SET CSIO TO DEFAULT SPEED +; SET SLOW SPEED ; -#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) +SD_SPD_SLOW: ; -SD_CSIO_DEF: +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) ; SET CSIO FOR DEFAULT OPERATION PUSH AF ; PRESERVE AF CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING @@ -2227,9 +2368,23 @@ SD_CSIO_DEF: LD A,Z180_CNTR_DEF ; DIV 1280, 14KHZ @ 18MHZ CLK OUT0 (SD_CNTR),A ; DO IT POP AF ; RESTORE AF +#ENDIF RET ; +; SET FAST SPEED +; +SD_SPD_FAST: +; +#IF ((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) + ; SET CSIO FOR HIGH SPEED OPERATION + PUSH AF ; PRESERVE AF + CALL SD_WAITTX ; MAKE SURE WE ARE DONE SENDING + CALL DLY32 ; WAIT A BIT MORE FOR FINAL BIT + XOR A ; 0 IS HIGHEST CLOCK SPEED + OUT0 (SD_CNTR),A ; DO IT + POP AF ; RESTORE AF #ENDIF + RET ; ; ;============================================================================= @@ -2419,6 +2574,7 @@ SD_STR_TOK .TEXT " TOK=$" SD_STR_CSD .TEXT " CSD =$" SD_STR_CID .TEXT " CID =$" SD_STR_SCR .TEXT " SCR =$" +SD_STR_OCR .TEXT " OCR =$" SD_STR_SDTYPE .TEXT " SD CARD TYPE ID=$" ; SD_STR_STOK .TEXT "OK$" @@ -2470,7 +2626,7 @@ SD_DSKBUF .DW 0 ; ADR OF ACTIVE DISK BUFFER ; MSB<-->LSB MIRROR BITS IN A, RESULT IN C ; MIRROR: -#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST) +#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) & SDCSIOFAST) ; FASTEST BUT USES MOST CODE SPACE LD BC,MIRTAB ; 256 BYTE MIRROR TABLE ADD A,C ; ADD OFFSET @@ -2503,7 +2659,7 @@ MIRROR2: ; ; LOOKUP TABLE TO MIRROR BITS IN A BYTE ; -#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX)) & SDCSIOFAST) +#IF (((SDMODE == SDMODE_CSIO) | (SDMODE == SDMODE_MK4) | (SDMODE == SDMODE_SC) | (SDMODE == SDMODE_EPITX) | (SDMODE == SDMODE_GM)) & SDCSIOFAST) MIRTAB .DB 00H, 80H, 40H, 0C0H, 20H, 0A0H, 60H, 0E0H, 10H, 90H, 50H, 0D0H, 30H, 0B0H, 70H, 0F0H .DB 08H, 88H, 48H, 0C8H, 28H, 0A8H, 68H, 0E8H, 18H, 98H, 58H, 0D8H, 38H, 0B8H, 78H, 0F8H diff --git a/Source/HBIOS/sn76489.asm b/Source/HBIOS/sn76489.asm index b356f91c..8a41fe7d 100644 --- a/Source/HBIOS/sn76489.asm +++ b/Source/HBIOS/sn76489.asm @@ -4,7 +4,7 @@ ; WRITTEN BY: DEAN NETHERTON ;====================================================================== ; -; SN76489 PSG CHIP NEEDS AN INPUT CLOCK FREQUENCY OF +; SN74489 PSG CHIP NEEDS AN INPUT CLOCK FREQUENCY OF ; NO MORE THAN 4 MHZ. THE CLOSEST THING THERE IS TO A STANDARD ; IS THE MSX FREQ OF 3.579545 MHZ. ; @@ -37,20 +37,6 @@ SN76489_PORT_RIGHT .EQU $BF ; PORTS FOR ACCESSING THE SN76489 CHIP (RIGHT) DEVECHO "RC" #ENDIF ; - -SN76489_PORT16_LEFT .EQU (IO_SEGMENT*256) + SN76489_PORT_LEFT -SN76489_PORT16_RIGHT .EQU (IO_SEGMENT*256) + SN76489_PORT_RIGHT - -#IF (CPUFAM == CPU_EZ80) -; The eZ80 configuration must have sufficient bus cycles configured for this driver -; to work. See the entries: (EZ80_WSMD_TYP and EZ80_IO_CYCLES, EZ80_IO_WS, EZ80_IO_MIN_NS) -; -; For CPU @ ~18Mhz, the eZ80 must have at least 4 Bus Cycles for I/O operations -; For CPU @ ~24Mhz, the eZ80 must have at least 5 Bus Cycles for I/O operations - -SN76489_IO_DELAY .EQU 5 ; 200us DELAY BETWEEN CHANNEL WRITES - -#ENDIF DEVECHO ", IO_LEFT=" DEVECHO SN76489_PORT_LEFT DEVECHO ", IO_RIGHT=" @@ -63,10 +49,6 @@ SN7_IDAT .EQU 0 SN7_TONECNT .EQU 3 ; COUNT NUMBER OF TONE CHANNELS SN7_NOISECNT .EQU 1 ; COUNT NUMBER OF NOISE CHANNELS SN7_CHCNT .EQU SN7_TONECNT + SN7_NOISECNT -CHANNEL_0_SILENT .EQU $9F -CHANNEL_1_SILENT .EQU $BF -CHANNEL_2_SILENT .EQU $DF -CHANNEL_3_SILENT .EQU $FF ; #INCLUDE "audio.inc" ; @@ -92,64 +74,67 @@ SN76489_INIT: LD A, SN76489_PORT_RIGHT CALL PRTHEXBYTE - CALL SN7_VOLUME_OFF + CALL SN7_RESET XOR A ; SIGNAL SUCCESS RET - +; ;====================================================================== -; SN76489 DRIVER - SOUND ADAPTER (SND) FUNCTIONS +; INITIALIZE DEVICE ;====================================================================== ; -SN7_RESET: - AUDTRACE(SNT_INIT) - CALL SN7_VOLUME_OFF - XOR A ; SIGNAL SUCCESS - RET - -SN7_VOLUME_OFF: - AUDTRACE(SNT_VOLOFF) - - +SN7_INIT: +; #IFDEF SBCV2004 LD A,(HB_RTCVAL) OR %00001000 ; SBC-V2-004+ CHANGE OUT (RTCIO),A ; TO HALF CLOCK SPEED #ENDIF - - LD A, CHANNEL_0_SILENT - LD BC, SN76489_PORT16_LEFT - EZ80_THROTTLE_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER) - OUT (C), A - LD BC, SN76489_PORT16_RIGHT - OUT (C), A - - LD A, CHANNEL_1_SILENT - LD BC, SN76489_PORT16_LEFT - EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER) - OUT (C), A - LD BC, SN76489_PORT16_RIGHT - OUT (C), A - - LD A, CHANNEL_2_SILENT - LD BC, SN76489_PORT16_LEFT - EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER) - OUT (C), A - LD BC, SN76489_PORT16_RIGHT - OUT (C), A - - LD A, CHANNEL_3_SILENT - LD BC, SN76489_PORT16_LEFT - EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER) - OUT (C), A - LD BC, SN76489_PORT16_RIGHT - OUT (C), A - +; + LD HL,SN7_REG_INIT ; POINT TO REG INIT TBL + LD B,SN7_REG_CNT ; BYTES IN TABLE +SN7_INIT1 + LD A,(HL) + INC HL ; BUMP FOR NEXT TIME + OUT (SN76489_PORT_LEFT), A ; WRITE LEFT PORT + OUT (SN76489_PORT_RIGHT), A ; WRITE RIGHT PORT + DJNZ SN7_INIT1 ; LOOP TILL DONE +; #IFDEF SBCV2004 LD A,(HB_RTCVAL) AND %11110111 ; SBC-V2-004+ CHANGE TO OUT (RTCIO),A ; NORMAL CLOCK SPEED #ENDIF - +; + RET +; +SN7_REG_INIT: + .DB $80,$00 ; TONE 1 FREQ (2 BYTES) + .DB $9F ; TONE 1 ATTENTUATION + .DB $A0,$00 ; TONE 2 FREQ (2 BYTES) + .DB $BF ; TONE 2 ATTENTUATION + .DB $C0,$00 ; TONE 3 FREQ (2 BYTES) + .DB $DF ; TONE 3 ATTENTUATION + .DB $E0 ; NOISE CONTROL + .DB $FF ; NOISE ATTENTUATION +SN7_REG_CNT .EQU $ - SN7_REG_INIT +; +;====================================================================== +; SN76489 DRIVER - SOUND ADAPTER (SND) FUNCTIONS +;====================================================================== +; +SN7_RESET: + AUDTRACE(SNT_INIT) +; + CALL SN7_INIT ; HARDWARE INIT +; + ; RESET DEFAULTS IN CASE OF AN IN-PLACE HBIOS RESTART + LD HL,0 + LD (SN7_PENDING_PERIOD),HL + LD (SN7_PENDING_DURATION),HL + XOR A + LD (SN7_PENDING_VOLUME),A +; + XOR A RET ; BIT MAPPING @@ -200,12 +185,9 @@ SN7_PLAY: AUDTRACE_D AUDTRACE_CR - EZ80_THROTTLE_START(SN76489_IO_DELAY, SN7_DELAY_COUNTER) - LD A, (SN7_PENDING_PERIOD + 1) CP $FF JR Z, SN7_PLAY1 ; PERIOD IS TOO LARGE, UNABLE TO PLAY - CALL SN7_APPLY_VOL CALL SN7_APPLY_PRD @@ -310,15 +292,8 @@ SN7_APPLY_VOL: ; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS POP AF #ENDIF - LD BC, SN76489_PORT16_LEFT - EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER) -#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT)) - OUT (C), A -#ENDIF -#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_RIGHT)) - LD BC, SN76489_PORT16_RIGHT - OUT (C), A -#ENDIF + OUT (SN76489_PORT_LEFT), A + OUT (SN76489_PORT_RIGHT), A #IFDEF SBCV2004 LD A,(HB_RTCVAL) @@ -331,7 +306,6 @@ SN7_APPLY_VOL: ; APPLY VOLUME TO BOTH LEFT AND RIGHT CHANNELS RET SN7_APPLY_PRD: - PUSH DE PUSH BC PUSH AF @@ -363,15 +337,8 @@ SN7_APPLY_PRD: POP AF #ENDIF - LD BC, SN76489_PORT16_LEFT - EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER) -#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT)) - OUT (C), A -#ENDIF -#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_RIGHT)) - LD BC, SN76489_PORT16_RIGHT - OUT (C), A -#ENDIF + OUT (SN76489_PORT_LEFT), A + OUT (SN76489_PORT_RIGHT), A #IFDEF SBCV2004 LD A,(HB_RTCVAL) @@ -407,15 +374,8 @@ SN7_APPLY_PRD: POP AF #ENDIF - LD BC, SN76489_PORT16_LEFT - EZ80_THROTTLE_WAIT(SN76489_IO_DELAY, SN7_DELAY_COUNTER) -#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_LEFT)) - OUT (C), A -#ENDIF -#IF ((SN76489CHNOUT == SNCHAN_BOTH) | (SN76489CHNOUT == SNCHAN_RIGHT)) - LD BC, SN76489_PORT16_RIGHT - OUT (C), A -#ENDIF + OUT (SN76489_PORT_LEFT), A + OUT (SN76489_PORT_RIGHT), A #IFDEF SBCV2004 LD A,(HB_RTCVAL) @@ -442,6 +402,9 @@ SN7_DEVICE: XOR A RET +SN7_BEEP: + JP SND_BEEP ; DEFER TO GENERIC CODE IN HBIOS + SN7_FNTBL: .DW SN7_RESET .DW SN7_VOLUME @@ -451,23 +414,16 @@ SN7_FNTBL: .DW SN7_QUERY .DW SN7_DURATION .DW SN7_DEVICE + .DW SN7_BEEP ; #IF (($ - SN7_FNTBL) != (SND_FNCNT * 2)) .ECHO "*** INVALID SND FUNCTION TABLE ***\n" !!!!! #ENDIF -SN7_PENDING_PERIOD - .DW 0 ; PENDING PERIOD (10 BITS) -SN7_PENDING_VOLUME - .DB 0 ; PENDING VOL (8 BITS -> DOWNCONVERTED TO 4 BITS AND INVERTED) -SN7_PENDING_DURATION - .DW 0 ; PENDING DURATION (16 BITS) - -#IF (CPUFAM == CPU_EZ80) -SN7_DELAY_COUNTER: - .DW 0 -#ENDIF +SN7_PENDING_PERIOD .DW 0 ; PENDING PERIOD (10 BITS) +SN7_PENDING_VOLUME .DB 0 ; PENDING VOL (8 BITS -> DOWNCONVERTED TO 4 BITS AND INVERTED) +SN7_PENDING_DURATION .DW 0 ; PENDING DURATION (16 BITS) STR_MESSAGELT .DB "\r\nSN76489: LEFT IO=0x$" STR_MESSAGERT .DB ", RIGHT IO=0x$" diff --git a/Source/HBIOS/spk.asm b/Source/HBIOS/spk.asm index 23ab2079..3ceb148c 100644 --- a/Source/HBIOS/spk.asm +++ b/Source/HBIOS/spk.asm @@ -13,14 +13,15 @@ ; DRIVER FUNCTION TABLE AND INSTANCE DATA ; SP_FNTBL: - .DW SP_STUB ; SP_RESET - .DW SP_STUB ; SP_VOLUME + .DW SP_RESET + .DW SP_VOLUME .DW SP_PERIOD .DW SP_NOTE .DW SP_PLAY .DW SP_QUERY .DW SP_DURATION .DW SP_DEVICE + .DW SP_BEEP ; #IF (($ - SP_FNTBL) != (SND_FNCNT * 2)) .ECHO "*** INVALID SND FUNCTION TABLE ***\n" @@ -37,8 +38,8 @@ SP_RTCIOMSK .EQU 00000100B ; FOR OTHER DRIVERS, THE PERIOD VALUE FOR THE TONE IS STORED AT PENDING_PERIOD ; FOR THE SPK DRIVER THE ADDRESS IN THE TONE TABLE IS STORED IN PENDING_PERIOD ; -SP_PENDING_PERIOD .DW SP_NOTE_C8 ; PENDING PERIOD (16 BITS) -SP_PENDING_VOLUME .DB $FF ; PENDING VOL (8 BITS) +SP_PENDING_PERIOD .DW 0 ; PENDING PERIOD (16 BITS) +SP_PENDING_VOLUME .DB 0 ; PENDING VOL (8 BITS) SP_PENDING_DURATION .DW 0 ; PENDING DURATION (16 BITS) SP_TBLRDY .DB 0 ; IF != 0, NOTE TABLE IS READY ; @@ -60,17 +61,9 @@ SP_INIT: PRTS("SPK: IO=0x$") LD A,RTCIO CALL PRTHEXBYTE -; - ; RESET DEFAULTS IN CASE OF AN IN-PLACE HBIOS RESTART - LD HL,SP_NOTE_C8 - LD (SP_PENDING_PERIOD),HL - LD A,$FF - LD (SP_PENDING_VOLUME),A - XOR A - LD (SP_PENDING_DURATION),A -; +; CALL SP_SETTBL ; SETUP TONE TABLE - CALL SP_PLAY ; PLAY DEFAULT NOTE + CALL SP_RESET ; RESET PARAMETERS ; XOR A RET @@ -79,17 +72,24 @@ SP_INIT: ; SOUND DRIVER FUNCTION - RESET ;====================================================================== ; -;SP_RESET: -; XOR A ; SUCCESSFULL RESET -; RET +SP_RESET: + ; RESET DEFAULTS IN CASE OF AN IN-PLACE HBIOS RESTART + LD HL,0 + LD (SP_PENDING_PERIOD),HL ; SET TONE PERIOD TO ZERO + LD (SP_PENDING_DURATION),HL; SET DURATION TO ZERO + XOR A ; SIGNAL SUCCESS + LD (SP_PENDING_VOLUME),A ; SET VOLUME TO ZERO +; + XOR A ; SUCCESSFULL RESET + RET ; ;====================================================================== ; SOUND DRIVER FUNCTION - VOLUME ;====================================================================== ; -;SP_VOLUME: -; XOR A ; SIGNAL SUCCESS -; RET +SP_VOLUME: + XOR A ; SIGNAL SUCCESS + RET ; ;====================================================================== ; SOUND DRIVER FUNCTION - PERIOD @@ -97,7 +97,6 @@ SP_INIT: ; SP_PERIOD: LD (SP_PENDING_PERIOD), HL ; SAVE AND RETURN SUCCESSFUL -SP_STUB: XOR A RET ; @@ -362,16 +361,40 @@ SP_DEVICE: RET ; ;====================================================================== +; SOUND DRIVER FUNCTION - BEEP +;====================================================================== +; +SP_BEEP: + LD HL,SP_NOTE_B5 ; B5 (CLOSE TO 1 KHZ) + LD (SP_PENDING_PERIOD),HL + ;LD A,$FF + ;LD (SP_PENDING_VOLUME),A + ;XOR A + ;LD (SP_PENDING_DURATION),A +; + CALL SP_PLAY ; PLAY DEFAULT NOTE + CALL SP_RESET ; RESET DRIVER +; + XOR A + RET +; +;====================================================================== ; ; STANDARD ONE SECOND TONE TABLES AT 1MHZ. ; FOR SP_BEEPER ROUTINE, FIRST WORD LOADED INTO DE, SECOND INTO HL +; THE PARAMETER TO SP_TONESET IS (FREQ * 100) +; DE: FREQUENCY IN HZ +; HL: T-STATES PER HALF-CYCL E / 4 AT 1 MHZ CPU SPEED +; EX. MIDDLE C IS 261.63 HZ, 523.26 HALF CYCLES PER SECOND +; 1,000,000 / 523.26 / 4 = 477 +; OR ALTERNATIVELY 12,500,000 / 26163 = 477 ; ;====================================================================== ; #DEFINE SP_TONESET(SP_FREQ) .DW SP_FREQ/100, 12500000/SP_FREQ ; SP_TUNTBL: - SP_TONESET(1635) ; C0 + SP_TONESET(1635) ; C0 ; DE=16, HL=7645 SP_TONESET(1732) ; C SP_TONESET(1835) ; D0 SP_TONESET(1945) ; D @@ -419,7 +442,7 @@ SP_TUNTBL: SP_TONESET(22000) ; A3 SP_TONESET(23308) ; A SP_TONESET(24694) ; B3 - SP_TONESET(26163) ; C4 + SP_TONESET(26163) ; C4 ; DE=261, HL=477 SP_TONESET(27718) ; C SP_TONESET(29366) ; D4 SP_TONESET(31113) ; D @@ -442,6 +465,7 @@ SP_TUNTBL: SP_TONESET(83061) ; G SP_TONESET(88000) ; A5 SP_TONESET(93233) ; A +SP_NOTE_B5: SP_TONESET(98777) ; B5 SP_TONESET(104650) ; C6 SP_TONESET(110873) ; C @@ -467,7 +491,6 @@ SP_TUNTBL: SP_TONESET(352000) ; A7 SP_TONESET(372931) ; A SP_TONESET(395107) ; B7 -SP_NOTE_C8: SP_TONESET(418601) ; C8 SP_TONESET(443492) ; C SP_TONESET(469863) ; D8 @@ -479,7 +502,7 @@ SP_NOTE_C8: SP_TONESET(664488) ; G SP_TONESET(704000) ; A8 SP_TONESET(745862) ; A - SP_TONESET(790213) ; B8 + SP_TONESET(790213) ; B8 ; DE=7902, HL=15 ; SP_NOTCNT .EQU ($-SP_TUNTBL) / 4 ; diff --git a/Source/HBIOS/sser.asm b/Source/HBIOS/sser.asm new file mode 100644 index 00000000..726b83e7 --- /dev/null +++ b/Source/HBIOS/sser.asm @@ -0,0 +1,116 @@ +; +;================================================================================================== +; SIMPLE SERIAL DRIVER +;================================================================================================== +; +; TODO: +; + DEVECHO "SSER: IO=" + DEVECHO SSERSTATUS + DEVECHO "\n" +; +; +; +SSER_PREINIT: +; +; ADD OURSELVES TO CIO DISPATCH TABLE +; + LD D,0 ; PHYSICAL UNIT IS ZERO + LD E,CIODEV_SSER ; DEVICE TYPE + LD BC,SSER_FNTBL ; BC := FUNCTION TABLE ADDRESS + CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED +; + XOR A + RET +; +; +; +SSER_INIT: + CALL NEWLINE + PRTS("SSER:$") + PRTS(" IO=0x$") ; FORMATTING + LD A,SSERSTATUS + CALL PRTHEXBYTE +; + XOR A ; SIGNAL SUCCESS + RET +; +; DRIVER FUNCTION TABLE +; +SSER_FNTBL: + .DW SSER_IN + .DW SSER_OUT + .DW SSER_IST + .DW SSER_OST + .DW SSER_INITDEV + .DW SSER_QUERY + .DW SSER_DEVICE +#IF (($ - SSER_FNTBL) != (CIO_FNCNT * 2)) + .ECHO "*** INVALID SSER FUNCTION TABLE ***\n" +#ENDIF +; +; +; +SSER_IN: + CALL SSER_IST ; CHECK FOR CHAR PENDING + JR Z,SSER_IN ; WAIT FOR IT IF NECESSARY + IN A,(SSERDATA) ; READ THE CHAR + LD E,A + RET +; +; +; +SSER_IST: + IN A,(SSERSTATUS) ; READ LINE STATUS REGISTER +#IF (SSERIINV) + CPL +#ENDIF + AND SSERIRDY ; ISOLATE DATA READY + JP Z,CIO_IDLE ; RETURN VIA IDLE PROCESSING + OR $FF ; SET A=$FF TO SIGNAL READY + RET ; RETURN +; +; +; +SSER_OUT: + CALL SSER_OST ; CHECK FOR OUTPUT READY + JR Z,SSER_OUT ; WAIT IF NECESSARY + LD A,E ; RECOVER THE CHAR TO WRITE + OUT (SSERDATA),A ; WRITE THE CHAR + RET +; +; +; +SSER_OST: + IN A,(SSERSTATUS) ; READ LINE STATUS REGISTER +#IF (SSEROINV) + CPL +#ENDIF + AND SSERORDY ; ISOLATE OUTPUT RDY + JP Z,CIO_IDLE ; RETURN VIA IDLE PROCESSING + OR $FF ; SET A=$FF TO SIGNAL READY + RET ; RETURN +; +; +; +SSER_INITDEV: + SYSCHKERR(ERR_NOTIMPL) + RET +; +; +; +SSER_QUERY: + LD DE,SSERCFG + XOR A + RET +; +; +; +SSER_DEVICE: + LD D,CIODEV_SSER ; D := DEVICE TYPE + LD E,0 ; E := DEVICE NUM, ALWAYS 0 + LD C,$00 ; C := DEVICE TYPE, 0x00 IS RS-232 + LD H,0 ; H := 0, DRIVER HAS NO MODES + LD L,SSERSTATUS ; L := BASE I/O ADDRESS + XOR A ; SIGNAL SUCCESS + RET diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 87eccfb9..dc3935e0 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -22,8 +22,10 @@ ; 18. HEATH Les Bird's Heath Z80 Board ; 19. EPITX Alan Cox' Mini-ITX System ; 20. MON Jacques Pelletier's Monsputer -; 21. STDZ180 Genesis Z180 System +; 21. GMZ180 Doug Jacksons' Genesis Z180 System ; 22. NABU NABU w/ Les Bird's RomWBW Option Board +; 23. FZ80 S100 Computers FPGA Z80 +; ; ; INCLUDE BUILD VERSION ; @@ -193,6 +195,7 @@ IDEMODE_DIO .EQU 1 ; DISKIO V1 IDEMODE_DIDE .EQU 2 ; DUAL IDE IDEMODE_MK4 .EQU 3 ; MARK IV ONBOARD IDE (8 BIT ONLY) IDEMODE_RC .EQU 4 ; RCBUS CF MODULE (8 BIT ONLY) +IDEMODE_GIDE .EQU 5 ; GENESIS MODULES STD BUS IDE CONTROLLER ; ; PPIDE MODE SELECTIONS ; @@ -221,6 +224,8 @@ SDMODE_USR .EQU 10 ; USER DEFINED (in sd.asm) (NOT COMPLETE) SDMODE_PIO .EQU 11 ; Z80 PIO bitbang SDMODE_Z80R .EQU 12 ; Z80 Retro SDMODE_EPITX .EQU 13 ; Mini ITX Z180 +SDMODE_FZ80 .EQU 14 ; S100 FPGA Z80 +SDMODE_GM .EQU 15 ; Genesis SD Driver ; ; AY SOUND CHIP MODE SELECTIONS ; @@ -253,14 +258,13 @@ SNCHAN_RIGHT .EQU 2 ; RIGHT CHANNEL ONLY TMSMODE_NONE .EQU 0 TMSMODE_SCG .EQU 1 ; SCG ECB BOARD TMSMODE_N8 .EQU 2 ; N8 BUILT-IN VIDEO -TMSMODE_MSX .EQU 3 ; MSX PORT MAPPING -TMSMODE_MSX9958 .EQU 4 ; MSX PORTS, V9958 CHIP -TMSMODE_MSXKBD .EQU 5 ; MSX PORTS + PS2 KEYBOARD +TMSMODE_MSX .EQU 3 ; STD MSX PORTS +TMSMODE_MSXKBD .EQU 4 ; STD MSX PORTS + PS2 KEYBOARD +TMSMODE_MSXMKY .EQU 5 ; STD MSX PORTS + MSX KEYBAORD TMSMODE_MBC .EQU 6 ; MBC V9938/58 VIDEO BOARD TMSMODE_COLECO .EQU 7 ; COLECOVISION PORT MAPPING TMSMODE_DUO .EQU 8 ; DUODYNE PORT MAPPING -TMSMODE_NABU40 .EQU 9 ; NABU V9918 + NABU KBD -TMSMODE_NABU80 .EQU 10 ; NABU V9958 + NABU KBD +TMSMODE_NABU .EQU 9 ; NABU ; ; CVDU VIDEO MODE SELECTIONS ; @@ -285,6 +289,7 @@ GDCMODE_RPH .EQU 2 ; RPH GDC LPTMODE_NONE .EQU 0 ; NONE LPTMODE_SPP .EQU 1 ; IBM PC STANDARD PAR PORT (SPP) LPTMODE_MG014 .EQU 2 ; RCBUS MG014 STYLE INTERFACE +LPTMODE_S100 .EQU 3 ; S100 Z80 FPGA BUILT-IN PRINTER PORT ; ; PPA DRIVER MODE SELECTIONS ; @@ -326,6 +331,7 @@ DMAMODE_VDG .EQU 7 ; VELESOFT DATAGEAR KBDMODE_NONE .EQU 0 KBDMODE_PS2 .EQU 1 ; PS/2 KEYBOARD CONTROLLER KBDMODE_VRC .EQU 2 ; VGARC KEYBOARD CONTROLLER +KBDMODE_FV .EQU 3 ; FPGA VGA KEYBOARD CONTROLLER ; ; SERIAL DEVICE CONFIGURATION CONSTANTS ; @@ -495,7 +501,9 @@ TERMENABLE .EQU FALSE ; TERM PSEUDO DEVICE, WILL AUTO-ENABLE IF A VDA IS ENABLE ; KBDENABLE .EQU FALSE ; PS/2 KEYBOARD DRIVER PPKENABLE .EQU FALSE ; PPK KEYBOARD DRIVER +MKYENABLE .EQU FALSE ; MSX KEYBOARD DRIVER NABUKBENABLE .EQU FALSE ; NABU KEYBOARD DRIVER +FVKBDENABLE .EQU FALSE ; FPGA KEYBOARD DRIVER ; ; VIDEO MODES ; diff --git a/Source/HBIOS/syq.asm b/Source/HBIOS/syq.asm index a913ddf7..c107e4ea 100644 --- a/Source/HBIOS/syq.asm +++ b/Source/HBIOS/syq.asm @@ -417,11 +417,11 @@ SYQ_IO: LD (SYQ_DSKBUF),HL ; SAVE DISK BUFFER ADDRESS LD A,SYQ_LBA ; LBA OFFSET IN CONFIG CALL LDHLIYA ; POINT TO LBA DWORD -#IF (DSKYENABLE) - #IF (DSKYDSKACT) +;;;#IF (DSKYENABLE) +;;; #IF (DSKYDSKACT) CALL HB_DSKACT ; SHOW ACTIVITY - #ENDIF -#ENDIF +;;; #ENDIF +;;;#ENDIF CALL LD32 ; SET DE:HL TO LBA ; CALL SYQ_CMDSETUP ; SETUP ATA COMMAND BUF diff --git a/Source/HBIOS/term.asm b/Source/HBIOS/term.asm index 1325cff2..6f193013 100644 --- a/Source/HBIOS/term.asm +++ b/Source/HBIOS/term.asm @@ -76,7 +76,8 @@ TERM_ATTACH: PUSH HL ; COPY VDA INSTANCE DATA PTR POP DE ; ... TO DE CALL CIO_ADDENT ; ADD ENTRY, A := UNIT ASSIGNED - LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + ;;;LD (HCB + HCB_CRTDEV),A ; SET OURSELVES AS THE CRT DEVICE + CALL CIO_SETCRT ; SET OURSELVES AS THE CRT DEVICE ; ; INCREMENT DEVICE COUNT LD HL,TERM_DEVCNT ; POINT TO DEVICE COUNT diff --git a/Source/HBIOS/tms.asm b/Source/HBIOS/tms.asm index d8116d14..0dd2fc33 100644 --- a/Source/HBIOS/tms.asm +++ b/Source/HBIOS/tms.asm @@ -1,5 +1,5 @@ ;====================================================================== -; TM9918 AND V9958 VDU DRIVER +; TMS9918, V9938/58 VDU DRIVER ; ; WRITTEN BY: DOUGLAS GOODALL ; UPDATED BY: WAYNE WARTHEN -- 4/7/2013 @@ -43,32 +43,21 @@ TMSCTRL1: .EQU 1 ; CONTROL BITS TMSINTEN: .EQU 5 ; INTERRUPT ENABLE BIT ; - DEVECHO "TMS: MODE=" -; -#IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958)) -TMS_DATREG .EQU $98 ; READ/WRITE DATA -TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL +TMSKBD_NONE .EQU 0 +TMSKBD_KBD .EQU 1 +TMSKBD_PPK .EQU 2 +TMSKBD_MKY .EQU 3 +TMSKBD_NABU .EQU 4 ; - #IF (TMSMODE == TMSMODE_MSX) - DEVECHO "MSX" - #ENDIF - #IF (TMSMODE == TMSMODE_MSX9958) - DEVECHO "MSX9958" - #ENDIF -#ENDIF +TMSKBD .EQU TMSKBD_NONE ; ASSUME NONE ; -#IF (TMSMODE == TMSMODE_COLECO) -TMS_DATREG .EQU $BE ; READ/WRITE DATA -TMS_CMDREG .EQU $BF ; READ STATUS / WRITE REG SEL - DEVECHO "COLECO" -#ENDIF + DEVECHO "TMS: MODE=" ; -#IF (TMSMODE == TMSMODE_MSXKBD) +#IF (TMSMODE == TMSMODE_SCG) TMS_DATREG .EQU $98 ; READ/WRITE DATA TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL -TMS_KBDDATA .EQU $E0 ; KBD CTLR DATA PORT -TMS_KBDST .EQU $E1 ; KBD CTLR STATUS/CMD PORT - DEVECHO "MSXKBD" +TMS_ACR .EQU $9C ; AUX CONTROL REGISTER + DEVECHO "SCG" #ENDIF ; #IF (TMSMODE == TMSMODE_N8) @@ -78,14 +67,29 @@ TMS_PPIA .EQU $84 ; PPI PORT A TMS_PPIB .EQU $85 ; PPI PORT B TMS_PPIC .EQU $86 ; PPI PORT C TMS_PPIX .EQU $87 ; PPI CONTROL PORT +TMSKBD .SET TMSKBD_PPK ; PPK KEYBOARD DEVECHO "N8" #ENDIF ; -#IF (TMSMODE == TMSMODE_SCG) +#IF (TMSMODE == TMSMODE_MSX) TMS_DATREG .EQU $98 ; READ/WRITE DATA TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL -TMS_ACR .EQU $9C ; AUX CONTROL REGISTER - DEVECHO "SCG" +#ENDIF +; +#IF (TMSMODE == TMSMODE_MSXKBD) +TMS_DATREG .EQU $98 ; READ/WRITE DATA +TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL +TMS_KBDDATA .EQU $60 ; KBD CTLR DATA PORT +TMS_KBDST .EQU $64 ; KBD CTLR STATUS/CMD PORT +TMSKBD .SET TMSKBD_KBD ; PS2 KEYBOARD + DEVECHO "MSXKBD" +#ENDIF +; +#IF (TMSMODE == TMSMODE_MSXMKY) +TMS_DATREG .EQU $98 ; READ/WRITE DATA +TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL +TMSKBD .SET TMSKBD_MKY ; MSX KEYBOARD + DEVECHO "MSXMKY" #ENDIF ; #IF (TMSMODE == TMSMODE_MBC) @@ -94,40 +98,38 @@ TMS_CMDREG .EQU $99 ; READ STATUS / WRITE REG SEL TMS_ACR .EQU $9C ; AUX CONTROL REGISTER TMS_KBDDATA .EQU $E2 ; KBD CTLR DATA PORT TMS_KBDST .EQU $E3 ; KBD CTLR STATUS/CMD PORT +TMSKBD .SET TMSKBD_KBD ; PS2 KEYBOARD DEVECHO "MBC" #ENDIF - +; +#IF (TMSMODE == TMSMODE_COLECO) +TMS_DATREG .EQU $BE ; READ/WRITE DATA +TMS_CMDREG .EQU $BF ; READ STATUS / WRITE REG SEL + DEVECHO "COLECO" +#ENDIF +; #IF (TMSMODE == TMSMODE_DUO) TMS_DATREG .EQU $A0 ; READ/WRITE DATA TMS_CMDREG .EQU $A1 ; READ STATUS / WRITE REG SEL TMS_ACR .EQU $A6 ; AUX CONTROL REGISTER TMS_KBDDATA .EQU $4C ; KBD CTLR DATA PORT TMS_KBDST .EQU $4D ; KBD CTLR STATUS/CMD PORT +TMSKBD .SET TMSKBD_KBD ; PS2 KEYBOARD DEVECHO "DUO" #ENDIF ; -#IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80)) +#IF (TMSMODE == TMSMODE_NABU) TMS_DATREG .EQU $A0 ; READ/WRITE DATA TMS_CMDREG .EQU $A1 ; READ STATUS / WRITE REG SEL -; - #IF (TMSMODE == TMSMODE_NABU40) - DEVECHO "NABU-40" - #ENDIF - #IF (TMSMODE == TMSMODE_NABU80) - DEVECHO "NABU-80" - #ENDIF +TMSKBD .SET TMSKBD_NABU ; NABU KEYBOARD #ENDIF ; DEVECHO ", IO=" DEVECHO TMS_DATREG -#IF (TMSTIMENABLE & (INTMODE > 0)) - DEVECHO ", INTERRUPTS ENABLED" -#ENDIF - DEVECHO "\n" ; TMS_ROWS .EQU 24 ; -#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80)) +#IF (TMS80COLS) TMS_FNTVADDR .EQU $1000 ; VRAM ADDRESS OF FONT DATA TMS_FNTSIZE .EQU 8*256 ; ### JLC Mod for JBL compatibility ### = 8x8 Font 256 Chars TMS_CHRVADDR .EQU $0000 ; VRAM ADDRESS OF CHAR SCREEN DATA (NEW CONSTANT) = REG2 * $400 @@ -140,24 +142,48 @@ TMS_FNTSIZE .EQU 8*256 ; ### JLC Mod for JBL compatibility ### = 8x8 Font 256 C TMS_CHRVADDR .EQU $3800 ; VRAM ADDRESS OF CHAR SCREEN DATA (NEW CONSTANT) = REG2 * $400 TMS_COLS .EQU 40 #ENDIF +; + DEVECHO ", SCREEN=" + DEVECHO TMS_COLS + DEVECHO "X" + DEVECHO TMS_ROWS ; #DEFINE USEFONT8X8 #DEFINE TMS_FONT FONT8X8 ; TERMENABLE .SET TRUE ; INCLUDE TERMINAL PSEUDODEVICE DRIVER ; -#IF (TMSMODE == TMSMODE_N8) + DEVECHO ", KEYBOARD=" +; +#IF (TMSKBD == TMSKBD_NONE) + DEVECHO "NONE" +#ENDIF +; +#IF (TMSKBD == TMSKBD_PPK) PPKENABLE .SET TRUE ; INCLUDE PPK KEYBOARD SUPPORT + DEVECHO "PPK" #ENDIF ; -#IF ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO)) -KBDENABLE .SET TRUE ; INCLUDE KBD KEYBOARD SUPPORT +#IF (TMSKBD == TMSKBD_KBD) +KBDENABLE .SET TRUE ; INCLUDE PS2 KEYBOARD SUPPORT + DEVECHO "KBD" #ENDIF ; -#IF ((TMSMODE == TMSMODE_NABU40) |(TMSMODE == TMSMODE_NABU80)) +#IF (TMSKBD == TMSKBD_MKY) +MKYENABLE .SET TRUE ; INCLUDE MSX KEYBOARD SUPPORT + DEVECHO "MKY" +#ENDIF +; +#IF (TMSKBD == TMSKBD_NABU) NABUKBENABLE .SET TRUE ; INCLUDE NABU KEYBOARD SUPPORT + DEVECHO "NABU" #ENDIF ; +#IF (TMSTIMENABLE & (INTMODE > 0)) + DEVECHO ", INTERRUPTS ENABLED" +#ENDIF + DEVECHO "\n" +; ; TMS_IODELAY IS USED TO ADD RECOVERY TIME TO TMS9918/V9958 ACCESSES ; IF YOU SEE SCREEN CORRUPTION, ADJUST THIS!!! ; @@ -166,8 +192,8 @@ NABUKBENABLE .SET TRUE ; INCLUDE NABU KEYBOARD SUPPORT #DEFINE TMS_IODELAY EX (SP),HL \ EX (SP),HL ; 38 W/S ;#DEFINE TMS_IODELAY NOP \ NOP \ NOP \ NOP \ NOP ; 20 W/S ### JLC Mod for Clock/2 (9 MHz) ### #ELSE - ; BELOW WAS TUNED FOR SBC AT 8MHZ - #IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80)) + ; BELOW WAS TUNED FOR Z80 AT 8MHZ + #IF (TMS80COLS) #DEFINE TMS_IODELAY NOP \ NOP \ NOP \ NOP \ NOP \ NOP \ NOP ; V9958 NEEDS AT WORST CASE, APPROX 4us (28T) DELAY BETWEEN I/O (WHEN IN TEXT MODE) #ELSE #DEFINE TMS_IODELAY NOP \ NOP ; 8 W/S @@ -212,32 +238,29 @@ TMS_INIT: #IF (TMSMODE == TMSMODE_SCG) PRTS("SCG$") #ENDIF -#IF (TMSMODE == TMSMODE_MBC) - PRTS("MBC$") -#ENDIF -#IF (TMSMODE == TMSMODE_DUO) - PRTS("DUO$") -#ENDIF #IF (TMSMODE == TMSMODE_N8) PRTS("N8$") #ENDIF #IF (TMSMODE == TMSMODE_MSX) PRTS("MSX$") #ENDIF -#IF (TMSMODE == TMSMODE_COLECO) - PRTS("COLECO$") -#ENDIF #IF (TMSMODE == TMSMODE_MSXKBD) PRTS("MSXKBD$") #ENDIF -#IF (TMSMODE == TMSMODE_MSX9958) - PRTS("MSXV9958$") +#IF (TMSMODE == TMSMODE_MSXMKY) + PRTS("MSXMKY$") +#ENDIF +#IF (TMSMODE == TMSMODE_MBC) + PRTS("MBC$") +#ENDIF +#IF (TMSMODE == TMSMODE_COLECO) + PRTS("COLECO$") #ENDIF -#IF (TMSMODE == TMSMODE_NABU40) - PRTS("NABU-40$") +#IF (TMSMODE == TMSMODE_DUO) + PRTS("DUO$") #ENDIF -#IF (TMSMODE == TMSMODE_NABU80) - PRTS("NABU-80$") +#IF (TMSMODE == TMSMODE_NABU) + PRTS("NABU$") #ENDIF ; PRTS(" IO=0x$") @@ -256,19 +279,27 @@ TMS_INIT1: PRTS(" INTERRUPT ENABLED$") #ENDIF + CALL PC_SPACE + LD A,TMS_COLS + CALL PRTDEC8 + LD A,'X' + CALL COUT + LD A,TMS_ROWS + CALL PRTDEC8 +; CALL TMS_CRTINIT ; SETUP THE TMS CHIP REGISTERS CALL TMS_LOADFONT ; LOAD FONT DATA FROM ROM TO TMS STRORAGE CALL TMS_CLEAR ; CLEAR SCREEN, HOME CURSOR -#IF (PPKENABLE) +#IF (TMSKBD == TMSKBD_PPK) CALL PPK_INIT ; INITIALIZE PPI KEYBOARD DRIVER #ENDIF -#IF (KBDENABLE) +#IF (TMSKBD == TMSKBD_KBD) CALL KBD_INIT ; INITIALIZE 8242 KEYBOARD DRIVER #ENDIF -#IF (MKYENABLE) +#IF (TMSKBD == TMSKBD_MKY) CALL MKY_INIT ; INITIALIZE MKY KEYBOARD DRIVER #ENDIF -#IF (NABUKBENABLE) +#IF (TMSKBD == TMSKBD_NABU) CALL NABUKB_INIT ; INITIALIZE NABU KEYBOARD DRIVER #ENDIF @@ -291,7 +322,7 @@ TMS_INIT1: LD C, TMSCTRL1 CALL TMS_SET ; - #IF ((TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80)) + #IF (TMSMODE == TMSMODE_NABU) ; ENABLE VDP INTERRUPTS ON NABU INTERRUPT CONTROLLER LD A,14 ; PSG R14 (PORT A DATA) OUT (NABU_RSEL),A ; SELECT IT @@ -334,30 +365,30 @@ TMS_FNTBL: .DW TMS_VDAFIL .DW TMS_VDACPY .DW TMS_VDASCR -#IF (PPKENABLE) +#IF (TMSKBD == TMSKBD_NONE) + .DW TMS_STAT + .DW TMS_FLUSH + .DW TMS_READ +#ENDIF +#IF (TMSKBD == TMSKBD_PPK) .DW PPK_STAT .DW PPK_FLUSH .DW PPK_READ #ENDIF -#IF (KBDENABLE) +#IF (TMSKBD == TMSKBD_KBD) .DW KBD_STAT .DW KBD_FLUSH .DW KBD_READ #ENDIF -#IF (MKYENABLE) +#IF (TMSKBD == TMSKBD_MKY) .DW MKY_STAT .DW MKY_FLUSH .DW MKY_READ #ENDIF -#IF (NABUKBENABLE) +#IF (TMSKBD == TMSKBD_NABU) .DW NABUKB_STAT .DW NABUKB_FLUSH .DW NABUKB_READ -#ENDIF -#IF ((!PPKENABLE) & (!KBDENABLE) & (!NABUKBENABLE) & (!MKYENABLE)) - .DW TMS_STAT - .DW TMS_FLUSH - .DW TMS_READ #ENDIF .DW TMS_VDARDC #IF (($ - TMS_FNTBL) != (VDA_FNCNT * 2)) @@ -575,8 +606,8 @@ TMS_SET: ;---------------------------------------------------------------------- ; TMS_WR: -#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80)) - ; CLEAR R#14 FOR V9958 +#IF (TMS80COLS) + ; CLEAR R#14 FOR V9958 HB_DI XOR A EZ80_IO @@ -684,7 +715,7 @@ TMS_CRTINIT2: DJNZ TMS_CRTINIT2 ; LOOP ; ; ENABLE WAIT SIGNAL IF 9938/58 -#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80)) +#IF (TMS80COLS) LD C,25 ; REGISTER 25 LD A,%00000100 ; ONLY WTE BIT SET CALL TMS_SET ; DO IT @@ -1109,6 +1140,11 @@ TMS_TSTINT: RET TMS_INTHNDL: + +#IF (TMSKBD == TMSKBD_MKY) + CALL MKY_INT +#ENDIF + CALL HB_TIMINT ; RETURN NZ - HANDLED OR $FF RET @@ -1131,21 +1167,21 @@ TMS_COLOR_TBL .DB $01,$08,$02,$0A,$04,$06,$0C,$0F,$0E,$09,$03,$0B,$05,$0D,$07,$0 ;================================================================================================== ; TMS_IDAT: -#IF ((TMSMODE == TMSMODE_N8)) +#IF ((TMSKBD == TMSKBD_NONE) | (TMSKBD == TMSKBD_MKY) | (TMSKBD == TMSKBD_NABU)) + .FILL 4,0 ; DUMMY KEYBOARD CONFIG DATA +#ENDIF +#IF (TMSKBD == TMSKBD_PPK) .DB TMS_PPIA ; PPI PORT A .DB TMS_PPIB ; PPI PORT B .DB TMS_PPIC ; PPI PORT C .DB TMS_PPIX ; PPI CONTROL PORT #ENDIF -#IF ((TMSMODE == TMSMODE_MSXKBD) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO)) +#IF (TMSKBD == TMSKBD_KBD) .DB KBDMODE_PS2 ; PS/2 8242 KEYBOARD CONTROLLER .DB TMS_KBDST ; 8242 CMD/STATUS PORT .DB TMS_KBDDATA ; 8242 DATA PORT .DB 0 ; FILLER #ENDIF -#IF ((TMSMODE == TMSMODE_MSX) | (TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_SCG) | (TMSMODE == TMSMODE_COLECO) | (TMSMODE == TMSMODE_NABU40) | (TMSMODE == TMSMODE_NABU80)) - .FILL 4,0 ; DUMMY KEYBOARD CONFIG DATA -#ENDIF ; .DB TMS_DATREG .DB TMS_CMDREG @@ -1192,11 +1228,11 @@ TMS_IDAT: ; 5S Fifth sprite (not displayed) detected. Value in FS* is valid. ; INT Set at each screen update, used for interrupts. ; -#IF ((TMSMODE == TMSMODE_MSX9958) | (TMSMODE == TMSMODE_MBC) | (TMSMODE == TMSMODE_DUO) | (TMSMODE == TMSMODE_NABU80)) +#IF (TMS80COLS) ; ; NOTE: YAMAHA 9938/58 DOCUMENTATION SAYS R3 IS SAME AS 9918 (ADR >> 10), ; BUT THIS SEEMS TO BE WRONG AND CORRECTLY DOCUMENTED AT -; https://www.msx.org/wiki/Screen_Modes_Description#SCREEN_0_in_80-column_.28Text_mode_2.29 +; https://www.msx.org/wiki/Screen_Modes_Description#SCREEN_0_in_80-column_.28Text_mode_2.29 ; BITS 1-0 SHOULD BE 1. BITS 8-2 SHOULD BE (ADR >> 8). ; ; ### JLC Mod diff --git a/Source/HBIOS/uart.asm b/Source/HBIOS/uart.asm index bedf4487..205a291e 100644 --- a/Source/HBIOS/uart.asm +++ b/Source/HBIOS/uart.asm @@ -17,6 +17,21 @@ ; F E D C B A 9 8 7 6 5 4 3 2 1 0 ; -- MCR -- -- LCR -- ; +; STANDARD UART BASE I/O ADDRESSES: +; - ECB SBC Z80 $68 +; - ECB CASSETTE $80 +; - ECB 4UART $C0,$C8,$D0,$D8 +; - ECB MFPIC $18 +; - ZETA $68 +; - DUODYNE Z80 $58 +; - DUODYNE SELFHOST $A8 +; - DUODYNE MULTI IO $70,$78 +; - NHYODYNE Z80 $68 +; - NHYODYNE DUART $80,$88 +; - RCBUS EPSER $A0,$A8 +; - RCBUS DUAL RS232 $80,$88 +; - EPITX $A0,$A8 +; - NABU $48 ; UART_DEBUG .EQU FALSE ; @@ -54,27 +69,6 @@ UART_FIFOACT .EQU 6 ; FIFO ACTIVE BIT UART_AFCACT .EQU 5 ; AUTO FLOW CONTROL ACTIVE BIT UART_CTSBAD .EQU 4 ; CTS STALL DETECTED ; -#IF (PLATFORM == PLT_DUO) -UARTSBASE .EQU $58 -UARTDBASE .EQU $70 -#ENDIF -; -#IF (PLATFORM == PLT_NABU) -UARTSBASE .EQU $48 -UARTDBASE .EQU $80 -#ENDIF -; -#IF ((PLATFORM != PLT_DUO) & (PLATFORM != PLT_NABU)) -UARTSBASE .EQU $68 -UARTDBASE .EQU $80 -#ENDIF -; -UARTABASE .EQU $A8 -UARTCBASE .EQU $80 -UARTMBASE .EQU $18 -UART4BASE .EQU $C0 -UARTRBASE .EQU $A0 -; #IF (UARTINTS) ; #IF ((INTMODE == 2) | (INTMODE == 3)) @@ -92,17 +86,17 @@ UART1_IVT .EQU IVT(INT_UART1) ; ; UART_PREINIT: -#IF (UART4) +#IF (UART4UART) ; ; INIT UART4 BOARD CONFIG REGISTER (NO HARM IF IT IS NOT THERE) ; LD A,$80 ; SELECT 7.3728MHZ OSC & LOCK CONFIG REGISTER - OUT (UART4BASE+$0F),A ; DO IT + OUT (UART4UARTBASE+$0F),A ; DO IT #ENDIF ; ; SETUP THE DISPATCH TABLE ENTRIES ; - LD B,UART_CNT ; LOOP CONTROL + LD B,UARTCNT ; LOOP CONTROL LD C,0 ; PHYSICAL UNIT INDEX XOR A ; ZERO TO ACCUM LD (UART_DEV),A ; CURRENT DEVICE NUMBER @@ -203,7 +197,7 @@ UART_INITUNIT1: ; ; UART_INIT: - LD B,UART_CNT ; COUNT OF POSSIBLE UART UNITS + LD B,UARTCNT ; COUNT OF POSSIBLE UART UNITS LD C,0 ; INDEX INTO UART CONFIG TABLE UART_INIT1: PUSH BC ; SAVE LOOP CONTROL @@ -249,14 +243,14 @@ UART_INIT2: UART_INT: ; - #IF (UARTSBC) - LD IY,UART_CFG_SBC + #IF (UARTCNT >= 1) + LD IY,UART0_CFG CALL UART_INTRCV RET NZ #ENDIF ; - #IF (UARTCAS) - LD IY,UART_CFG_CAS + #IF (UARTCNT >= 2) + LD IY,UART1_CFG CALL UART_INTRCV RET NZ #ENDIF @@ -265,15 +259,15 @@ UART_INT: ; #IF ((INTMODE == 2) | (INTMODE == 3)) ; - #IF (UARTSBC) -UART_INTSBC: - LD IY,UART_CFG_SBC + #IF (UARTCNT >= 1) +UART_INT0: + LD IY,UART0_CFG JR UART_INTRCV #ENDIF ; - #IF (UARTCAS) -UART_INTCAS: - LD IY,UART_CFG_CAS + #IF (UARTCNT >= 2) +UART_INT1: + LD IY,UART1_CFG JR UART_INTRCV #ENDIF ; @@ -837,16 +831,6 @@ UART_CHIP2: ; PICK BETWEEN 16550A/C JR UART_CHIP_16550C ; IS SET, SO 16550C ; UART_CHIP_NONE: -; -#IF (UARTSBCFORCE) - ; SIMH DOES NOT EMULATE A UART WELL ENOUGH TO BE DETECTED, SO - ; THIS BIT OF CODE CAN BE ENABLED TO FORCE THE PRIMARY SBC - ; UART TO BE HANDLED AS AN 8250. - LD A,(IY+2) ; BASE IO PORT - CP UARTSBASE ; IS THIS PRIMARY SBC PORT? - JR Z,UART_CHIP_8250 ; SPECIAL CASE FOR PRIMARY UART! -#ENDIF -; LD A,UART_NONE ; NO UART DETECTED AT THIS PORT RET ; @@ -1028,199 +1012,153 @@ UART_DEV .DB 0 ; DEVICE NUM USED DURING INIT ; UART PORT TABLE ; UART_CFG: -#IF (UARTSBC) -UART_CFG_SBC: - ; SBC/ZETA ONBOARD SERIAL PORT - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTSBASE ; IO PORT BASE (RBR, THR) - .DB UARTSBASE + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW UARTSBC_RCVBUF ; POINTER TO RCV BUFFER STRUCT -; - DEVECHO "UART: MODE=SBC, IO=" - DEVECHO UARTSBASE +; +#IF (UARTCNT >= 1) +UART0_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) ; +0 + .DB 0 ; UART TYPE (SET DURING INIT) ; +1 + .DB UART0BASE ; IO PORT BASE (RBR, THR) ; +2 + .DB UART0BASE + UART_LSR ; LINE STATUS PORT (LSR) ; +3 + .DW UART0CFG ; LINE CONFIGURATION ; +4 + .DW UART0_RCVBUF ; POINTER TO RCV BUFFER STRUCT ; +6 +; + DEVECHO "UART: IO=" + DEVECHO UART0BASE #IF ((UARTINTS) & (INTMODE > 0)) DEVECHO ", INTERRUPTS ENABLED" #ENDIF DEVECHO "\n" #ENDIF -#IF (UARTAUX) -UART_CFG_AUX: - ; AUX SERIAL PORT - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTABASE ; IO PORT BASE (RBR, THR) - .DB UARTABASE + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; NO INT HANDLER -; - DEVECHO "UART: MODE=AUX, IO=" - DEVECHO UARTABASE - DEVECHO "\n" -#ENDIF -#IF (UARTCAS) -UART_CFG_CAS: - ; CASSETTE INTERFACE SERIAL PORT - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTCBASE ; IO PORT BASE (RBR, THR) - .DB UARTCBASE + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCASSPD ; LINE CONFIGURATION - .DW UARTCAS_RCVBUF ; POINTER TO RCV BUFFER STRUCT -; - DEVECHO "UART: MODE=CAS, IO=" - DEVECHO UARTCBASE +; +#IF (UARTCNT >= 2) +UART1_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; UART TYPE (SET DURING INIT) + .DB UART1BASE ; IO PORT BASE (RBR, THR) + .DB UART1BASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UART1CFG ; LINE CONFIGURATION + .DW UART1_RCVBUF ; POINTER TO RCV BUFFER STRUCT +; + DEVECHO "UART: IO=" + DEVECHO UART1BASE #IF ((UARTINTS) & (INTMODE > 0)) DEVECHO ", INTERRUPTS ENABLED" #ENDIF DEVECHO "\n" #ENDIF -#IF (UARTMFP) -UART_CFG_MFP: - ; MF/PIC SERIAL PORT - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTMBASE ; IO PORT BASE (RBR, THR) - .DB UARTMBASE + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=MFP, IO=" - DEVECHO UARTSBASE +; +#IF (UARTCNT >= 3) +UART2_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; UART TYPE (SET DURING INIT) + .DB UART2BASE ; IO PORT BASE (RBR, THR) + .DB UART2BASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UART2CFG ; LINE CONFIGURATION + .DW 0 ; POINTER TO RCV BUFFER STRUCT +; + DEVECHO "UART: IO=" + DEVECHO UART2BASE DEVECHO "\n" #ENDIF -#IF (UART4) - ; 4UART SERIAL PORT A - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UART4BASE+0 ; IO PORT BASE (RBR, THR) - .DB UART4BASE+0 + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=4UART, IO=" - DEVECHO UART4BASE+0 - DEVECHO "\n" ; - ; 4UART SERIAL PORT B - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UART4BASE+8 ; IO PORT BASE (RBR, THR) - .DB UART4BASE+8 + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=4UART, IO=" - DEVECHO UART4BASE+8 +#IF (UARTCNT >= 4) +UART3_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; UART TYPE (SET DURING INIT) + .DB UART3BASE ; IO PORT BASE (RBR, THR) + .DB UART3BASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UART3CFG ; LINE CONFIGURATION + .DW 0 ; POINTER TO RCV BUFFER STRUCT +; + DEVECHO "UART: IO=" + DEVECHO UART3BASE DEVECHO "\n" +#ENDIF ; - ; 4UART SERIAL PORT C - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UART4BASE+16 ; IO PORT BASE (RBR, THR) - .DB UART4BASE+16 + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=4UART, IO=" - DEVECHO UART4BASE+16 +#IF (UARTCNT >= 5) +UART4_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; UART TYPE (SET DURING INIT) + .DB UART4BASE ; IO PORT BASE (RBR, THR) + .DB UART4BASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UART4CFG ; LINE CONFIGURATION + .DW 0 ; POINTER TO RCV BUFFER STRUCT +; + DEVECHO "UART: IO=" + DEVECHO UART4BASE DEVECHO "\n" +#ENDIF ; - ; 4UART SERIAL PORT D - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UART4BASE+24 ; IO PORT BASE (RBR, THR) - .DB UART4BASE+24 + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=4UART, IO=" - DEVECHO UART4BASE+24 +#IF (UARTCNT >= 6) +UART5_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; UART TYPE (SET DURING INIT) + .DB UART5BASE ; IO PORT BASE (RBR, THR) + .DB UART5BASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UART5CFG ; LINE CONFIGURATION + .DW 0 ; POINTER TO RCV BUFFER STRUCT +; + DEVECHO "UART: IO=" + DEVECHO UART5BASE DEVECHO "\n" #ENDIF -#IF (UARTRC) - ; UARTRC SERIAL PORT A - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTRBASE ; IO PORT BASE (RBR, THR) - .DB UARTRBASE + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=RC, IO=" - DEVECHO UARTRBASE+0 - DEVECHO "\n" ; - ; UARTRC SERIAL PORT B - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTRBASE+8 ; IO PORT BASE (RBR, THR) - .DB UARTRBASE+8 + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=RC, IO=" - DEVECHO UARTRBASE+8 +#IF (UARTCNT >= 7) +UART6_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; UART TYPE (SET DURING INIT) + .DB UART6BASE ; IO PORT BASE (RBR, THR) + .DB UART6BASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UART6CFG ; LINE CONFIGURATION + .DW 0 ; POINTER TO RCV BUFFER STRUCT +; + DEVECHO "UART: IO=" + DEVECHO UART6BASE DEVECHO "\n" -; #ENDIF -#IF (UARTDUAL) - ; DUAL UART CHANNEL A - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTDBASE+8 ; IO PORT BASE (RBR, THR) - .DB UARTDBASE+8 + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER - ; DUAL UART CHANNEL B - .DB 0 ; DEVICE NUMBER (UPDATED DURING INIT) - .DB 0 ; UART TYPE - .DB UARTDBASE ; IO PORT BASE (RBR, THR) - .DB UARTDBASE + UART_LSR ; LINE STATUS PORT (LSR) - .DW UARTCFG ; LINE CONFIGURATION - .DW 0 ; SHOULD NEVER NEED INT HANDLER -; - DEVECHO "UART: MODE=DUAL, IO=" - DEVECHO UARTDBASE+8 - DEVECHO "\n" ; - DEVECHO "UART: MODE=DUAL, IO=" - DEVECHO UARTDBASE+0 +#IF (UARTCNT >= 8) +UART7_CFG: + .DB 0 ; DEVICE NUMBER (SET DURING INIT) + .DB 0 ; UART TYPE (SET DURING INIT) + .DB UART7BASE ; IO PORT BASE (RBR, THR) + .DB UART7BASE + UART_LSR ; LINE STATUS PORT (LSR) + .DW UART7CFG ; LINE CONFIGURATION + .DW 0 ; POINTER TO RCV BUFFER STRUCT +; + DEVECHO "UART: IO=" + DEVECHO UART7BASE DEVECHO "\n" -; #ENDIF ; -UART_CNT .EQU ($ - UART_CFG) / 8 -; #IF ((!UARTINTS) | (INTMODE == 0)) ; -UARTSBC_RCVBUF .EQU 0 -UARTCAS_RCVBUF .EQU 0 +UART0_RCVBUF .EQU 0 +UART1_RCVBUF .EQU 0 ; #ELSE ; ; UART SBC RECEIVE BUFFER ; - #IF (UARTSBC) + #IF (UARTCNT >= 1) ; -UARTSBC_RCVBUF: -UARTSBC_CNT .DB 0 ; CHARACTERS IN RING BUFFER -UARTSBC_HD .DW UARTSBC_BUF ; BUFFER HEAD POINTER -UARTSBC_TL .DW UARTSBC_BUF ; BUFFER TAIL POINTER -UARTSBC_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER +UART0_RCVBUF: +UART0_CNT .DB 0 ; CHARACTERS IN RING BUFFER +UART0_HD .DW UART0_BUF ; BUFFER HEAD POINTER +UART0_TL .DW UART0_BUF ; BUFFER TAIL POINTER +UART0_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER ; #ENDIF ; ; UART CASSETTE RECEIVE BUFFER ; - #IF (UARTCAS) + #IF (UARTCNT >= 2) ; -UARTCAS_RCVBUF: -UARTCAS_CNT .DB 0 ; CHARACTERS IN RING BUFFER -UARTCAS_HD .DW UARTCAS_BUF ; BUFFER HEAD POINTER -UARTCAS_TL .DW UARTCAS_BUF ; BUFFER TAIL POINTER -UARTCAS_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER +UART1_RCVBUF: +UART1_CNT .DB 0 ; CHARACTERS IN RING BUFFER +UART1_HD .DW UART1_BUF ; BUFFER HEAD POINTER +UART1_TL .DW UART1_BUF ; BUFFER TAIL POINTER +UART1_BUF .FILL UART_BUFSZ,0 ; RECEIVE RING BUFFER ; #ENDIF ; diff --git a/Source/HBIOS/usrrom.asm b/Source/HBIOS/usrrom.asm index 67f24c7b..146d4937 100644 --- a/Source/HBIOS/usrrom.asm +++ b/Source/HBIOS/usrrom.asm @@ -21,6 +21,13 @@ ; HBIOS WARM RESET FUNCTION AS DEMONSTRATED BELOW. ; - THE APPLICATION MAY MAKE HBIOS FUNCTION CALLS WITHOUT RESTRICTION, ; BUT CANNOT USE ANY OS (CP/M) FUNCTIONS BECAUSE NO OS IS LOADED. +; - THE APPLICATION MAY NOT CHANGE THE INTERRUPT MODE (WHICH IS DEFINED +; IN THE ROM CONFIGURATION). THE SYSTEM'S INTERRUPT +; MODE CAN BE QUERIED BY AN HBIOS API CALL IF DESIRED. +; - THE APPLICATION MAY TEMPORARILY DISABLE INTERRUPTS BY BRACKETING +; SECTIONS OF CODE WITH DI/EI AS NEEDED. IF INTERRUPTS ARE +; TEMPORARILY DISABLED, THEY SHOULD NOT SHOULD NOT +; BE LEFT DISABLED ACROSS HBIOS API CALLS. ; ; INCLUDE STD.ASM WHICH DEFINES SOME KEY EQUATES USED BELOW. MOST ; IMPORTANT ARE USR_LOC, USR_SIZ, AND USR_END. IT ALSO DEFINES EQUATES @@ -33,8 +40,8 @@ CR .EQU 0DH LF .EQU 0AH ; -ROWS .EQU 008H ; NUMBER OF PIXEL ROWS PER CHARACTER -COLS .EQU 008H ; NUMBER OF PIXEL COLUMNS PER CHARACTER +ROWS .EQU 8 ; NUMBER OF PIXEL ROWS PER CHARACTER +COLS .EQU 8 ; NUMBER OF PIXEL COLUMNS PER CHARACTER ; ; APPLICATION WILL WILL BE LOADED AT USR_LOC. THEREFORE, THE CODE ; MUST "ORG" AT THIS ADDRESS. TO CHANGE THE LOAD LOCATION OF THIS @@ -145,10 +152,10 @@ CIN: PUSH BC ; DATA SECTION ; BANNER: - .DB 006H; THE NUMBER OF CHARACTERS IN THE BANNER + .DB 6 ; THE NUMBER OF CHARACTERS IN THE BANNER ; #IF FALSE - ; UPPER CASE LOGO + ; UPPER CASE LOGO ("ROMWBW") .DB %01111100, %00011100, %01000001, %01000001, %01111100, %01000001 .DB %01000010, %00100010, %01100011, %01000001, %01000010, %01000001 .DB %01000001, %01000001, %01010101, %01000001, %01000001, %01000001 @@ -160,7 +167,7 @@ BANNER: #ENDIF ; #IF TRUE - ; UPPER AND LOWER CASE LOGO + ; UPPER AND LOWER CASE LOGO ("RomWBW") .DB %00000000, %00000000, %00000000, %00000000, %00000000, %00000000 .DB %01111000, %00000000, %00000000, %01000100, %01111000, %01000100 .DB %01000100, %00000000, %00000000, %01000100, %01000100, %01000100 diff --git a/Source/HBIOS/ym2612.asm b/Source/HBIOS/ym2612.asm index a4818364..018729d6 100644 --- a/Source/HBIOS/ym2612.asm +++ b/Source/HBIOS/ym2612.asm @@ -55,6 +55,7 @@ YM_FNTBL: .DW YM_RESET .DW YM_QUERY .DW YM_DURATION .DW YM_DEVICE + .DW YM_BEEP ; #IF (($ - YM_FNTBL) != (SND_FNCNT * 2)) .ECHO "*** INVALID SND FUNCTION TABLE ***\n" @@ -197,6 +198,13 @@ YM_DEVICE: LD D,SNDDEV_YM2612 ; D := DEVICE TYPE RET ; ;------------------------------------------------------------------------------ +; Sound driver function - BEEP +;------------------------------------------------------------------------------ +; +YM_BEEP: + JP SND_BEEP ; DEFER TO GENERIC CODE IN HBIOS +; +;------------------------------------------------------------------------------ ; Sound driver function - RESET ; Initialize device. Set volume off. Reset volume and tone variables. ;------------------------------------------------------------------------------ diff --git a/Source/Images/Build.cmd b/Source/Images/Build.cmd index c19abf07..44a7d334 100644 --- a/Source/Images/Build.cmd +++ b/Source/Images/Build.cmd @@ -24,7 +24,6 @@ call BuildDisk.cmd fortran hd wbw_fd144 || exit /b call BuildDisk.cmd games hd wbw_fd144 || exit /b call BuildDisk.cmd cowgol hd wbw_fd144 || exit /b - echo. echo Building Hard Disk Images (512 directory entry format)... echo. @@ -45,6 +44,8 @@ call BuildDisk.cmd bascomp hd wbw_hd512 || exit /b call BuildDisk.cmd fortran hd wbw_hd512 || exit /b call BuildDisk.cmd games hd wbw_hd512 || exit /b call BuildDisk.cmd cowgol hd wbw_hd512 || exit /b +call BuildDisk.cmd msxroms1 hd wbw_hd512 || exit /b +call BuildDisk.cmd msxroms2 hd wbw_hd512 || exit /b echo. echo Building Combo Disk (512 directory entry format) Image... @@ -69,6 +70,8 @@ call BuildDisk.cmd bascomp hd wbw_hd1k || exit /b call BuildDisk.cmd fortran hd wbw_hd1k || exit /b call BuildDisk.cmd games hd wbw_hd1k || exit /b call BuildDisk.cmd cowgol hd wbw_hd1k || exit /b +call BuildDisk.cmd msxroms1 hd wbw_hd1k || exit /b +call BuildDisk.cmd msxroms2 hd wbw_hd1k || exit /b if exist ..\BPBIOS\bp*.rel call BuildDisk.cmd bp hd wbw_hd1k ..\zsdos\zsys_wbw.sys || exit /b diff --git a/Source/Images/BuildMSX.cmd b/Source/Images/BuildMSX.cmd new file mode 100644 index 00000000..a6dfb9d6 --- /dev/null +++ b/Source/Images/BuildMSX.cmd @@ -0,0 +1,10 @@ +@echo off +setlocal + +echo. +echo Building MSX Hard Disk Combo Image (1024 directory entry format)... +echo. + +copy hd1k_prefix.dat ..\..\Binary\ || exit /b + +copy /b hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_msxroms1.img + ..\..\Binary\hd1k_msxroms2.img ..\..\Binary\hd1k_msxcombo.img || exit /b diff --git a/Source/Images/Common/Z3/u14/UMAP18.CFG b/Source/Images/Common/Z3/u14/UMAP18.CFG new file mode 100644 index 00000000..72b87e1d Binary files /dev/null and b/Source/Images/Common/Z3/u14/UMAP18.CFG differ diff --git a/Source/Images/Common/Z3/u15/UMAP.COM b/Source/Images/Common/Z3/u15/UMAP.COM new file mode 100644 index 00000000..84516a68 Binary files /dev/null and b/Source/Images/Common/Z3/u15/UMAP.COM differ diff --git a/Source/Images/Makefile b/Source/Images/Makefile index 45425599..7a546de9 100644 --- a/Source/Images/Makefile +++ b/Source/Images/Makefile @@ -13,13 +13,15 @@ HD512IMGS = hd512_cpm22.img hd512_zsdos.img hd512_nzcom.img \ HD512XIMGS = hd512_z80asm.img hd512_aztecc.img hd512_hitechc.img \ hd512_bascomp.img hd512_fortran.img hd512_games.img \ hd512_tpascal.img hd512_dos65.img hd512_qpm.img \ - hd512_cowgol.img hd512_blank.img + hd512_cowgol.img hd512_msxroms1.img hd512_msxroms2.img \ + hd512_blank.img HD1KIMGS = hd1k_cpm22.img hd1k_zsdos.img hd1k_nzcom.img \ hd1k_cpm3.img hd1k_zpm3.img hd1k_ws4.img HD1KXIMGS = hd1k_z80asm.img hd1k_aztecc.img hd1k_hitechc.img \ hd1k_bascomp.img hd1k_fortran.img hd1k_games.img \ hd1k_tpascal.img hd1k_qpm.img \ - hd1k_cowgol.img hd1k_blank.img + hd1k_cowgol.img hd1k_msxroms1.img hd1k_msxroms2.img \ + hd1k_blank.img HD1KXIMGS += hd1k_bp.img HD512PREFIX = diff --git a/Source/Images/d_bp/u0/support.txt b/Source/Images/d_bp/u0/support.txt index db70c39d..ad0035ba 100644 --- a/Source/Images/d_bp/u0/support.txt +++ b/Source/Images/d_bp/u0/support.txt @@ -2,16 +2,16 @@ This library contains a number of support files, programs and scripts needed to bring up a fully functioning BPBIOS Zsystem. These programs and files are used and/or loaded by the startup scripts. -Some of the support files are startup ZEX scripts, some are Z3+ segment files, -others are Date and Time stamp drivers, some are command line editors and -history shells others are needed to initialize the RAMDRIVE as well as help files. +Some of the support files are startup ZEX scripts, some are Z3+ segment files, +others are Date and Time stamp drivers, some are command line editors and +history shells others are needed to initialize the RAMDRIVE as well as help files. -The following table shows which files are needed to support each of the ten -BPBIOS variants (BP33, BP33BNK, BP34, BP34BNK & BBP41BNK). +The following table shows which files are needed to support each of the ten +BPBIOS variants (BP33, BP33BNK, BP34, BP34BNK & BBP41BNK). Variant Name BP33 BP33BNK BP34 BP34BNK BP41BNK ================================================================ -bpbio.ndr X X X +bpbio.ndr X X X bpbioz33.ndr X X BPCNFG.COM X X X X X EASE.COM X X @@ -20,18 +20,18 @@ fcp-4.zrl X X fcp-4t.zrl X X X RELOG X X X X X HELPLSH.COM X X X -IF.COM X X X X +IF.COM X X X X jetldr.com X X X X X LDTIMEC.COM X X X LSH.COM X X X LSHF.COM* X X X LSHF.VAR* X X X -myterm.z3t X X X X X -nzdec23d.z3t X X X X X +myterm.z3t X X X X X +nzdec23d.z3t X X X X X PUTDS.COM X X X X X RAMFILES.TXT X X X X X RCOPY.COM X X X X X -rcp-16h.zrl X X X X +rcp-16h.zrl X X X X SAVE.COM X X X X Z33.ZEX X X ZEX.COM X X X X X @@ -43,14 +43,14 @@ ZST.ZEX X X Instructions: The support files are "crunched" and stored in the library file -SUPPORT.LBR. Place SUPPORT.LBR on the RAMDRIVE using for example +SUPPORT.LBR. Place SUPPORT.LBR on the RAMDRIVE using for example XModem. Use LBREXT with the /U option to extract and uncrunch the -files. First extract ZEX.COM while logged onto the A: drive with the +files. First extract ZEX.COM while logged onto the A: drive with the following command: B0:LBREXT SUPPORT C0:ZEX.C?M /U Next place all the .COM files on C15: by typing: B0:LBREXT SUPPORT C15:*.C?M /U -The remaining files should be placed on C0:. +The remaining files should be placed on C0:. B0:LBREXT SUPPORT C0:*.Z?X /U B0:LBREXT SUPPORT C0:*.Z?L /U B0:LBREXT SUPPORT C0:*.N?R /U @@ -59,14 +59,14 @@ The remaining files should be placed on C0:. B0:LBREXT SUPPORT C0:*.H?P /U Note in all BPBIOS variants that A: is the RAMDRIVE, B: is -the ROMDRIVE and C: is the system drive. Hard drive slices occupy C: +the ROMDRIVE and C: is the system drive. Hard drive slices occupy C: through N: and floppy drives are O: & P:. A short desciption of each of the support files follows: bpbioz33.ndr - Named Directory Table for Z33 bpbio.ndr - Named Directory Table for Z34 & Z41 BPCNFG.COM - BPBIOS configuration program -EASE.COM - Command line editor & history shell for Z33* +EASE.COM - Command line editor & history shell for Z33* EASE.HLP - Help file for EASE fcp-4.zrl - Z33 Flow Control Processor (handles IF, ELSE etc) fcp-4t.zrl - Z34 & Z41 Flow Control Processor (IF is transient) @@ -80,7 +80,7 @@ LSHF.COM - LSH with a fixed length History file (runs faster) LSHF.VAR - History file for LSHF myterm.z3t - Terminal Capabilities file (defines ESC sequences etc) NZDEC23D.Z3T - VT100 Terminal Capabilities File. -PUTDS.COM - Installs date stamping for RAM drive. +PUTDS.COM - Prepare disk for DateStamper date/time stamping. RAMFILES.TXT - List of frequently used command (edit to suit) RCOPY.COM - Copies files listed in RAMFILES.TXT to RAMDRIVE rcp-16h.zrl - Zsystem Resident Command Processor @@ -92,4 +92,4 @@ ZSCFG2.COM - Configures ZSDOS 2 ZSTF.ZEX - Automatically executed Startup script for BP41BNK ZST.ZEX - Automatically executed Startup script for BP34* -Note that clock & datestamping drivers are builtin to Z41. \ No newline at end of file +Note that clock & datestamping drivers are builtin to Z41. diff --git a/Source/Images/d_msxroms1/ReadMe.txt b/Source/Images/d_msxroms1/ReadMe.txt new file mode 100644 index 00000000..d0ef09ea --- /dev/null +++ b/Source/Images/d_msxroms1/ReadMe.txt @@ -0,0 +1,19 @@ +===== MSX ROMs Disk for RomWBW ===== + +This is disk 1 of 2 of the collection of MSX ROMs as provided by Les +Bird (ROM filenames A-K). These ROMs are "run" by using the +appropriate variant of Les' MSX8 ROM loader. You can download the +loader binaries from https://github.com/lesbird/MSX8. You will need +appropriate hardware to run the loader. + +Please review the file ROMLIST.TXT for information on the current +operational status of the ROM and it's long file name/description. + +This disk (RomWBW slice) is not automatically included with the +RomWBW "combo" disk images. You can simply add it to a combo +image by appending it to the end. After booting your system, +you can use the ASSIGN command to map the slice to a drive letter. +Refer to the RomWBW User Guide for more information on this +process. + +-- WBW 11:15 AM 8/21/2024 diff --git a/Source/Images/d_msxroms1/u0/10YAR000.ROM b/Source/Images/d_msxroms1/u0/10YAR000.ROM new file mode 100644 index 00000000..ae5d7b06 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/10YAR000.ROM differ diff --git a/Source/Images/d_msxroms1/u0/3DGOL002.ROM b/Source/Images/d_msxroms1/u0/3DGOL002.ROM new file mode 100644 index 00000000..77a5ece1 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/3DGOL002.ROM differ diff --git a/Source/Images/d_msxroms1/u0/3DGOL003.ROM b/Source/Images/d_msxroms1/u0/3DGOL003.ROM new file mode 100644 index 00000000..4e56857f Binary files /dev/null and b/Source/Images/d_msxroms1/u0/3DGOL003.ROM differ diff --git a/Source/Images/d_msxroms1/u0/3DTEN004.ROM b/Source/Images/d_msxroms1/u0/3DTEN004.ROM new file mode 100644 index 00000000..fd9f8b31 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/3DTEN004.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ACTMA007.ROM b/Source/Images/d_msxroms1/u0/ACTMA007.ROM new file mode 100644 index 00000000..fa7c104d Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ACTMA007.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ADVEN008.ROM b/Source/Images/d_msxroms1/u0/ADVEN008.ROM new file mode 100644 index 00000000..1fb34dad Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ADVEN008.ROM differ diff --git a/Source/Images/d_msxroms1/u0/AEJAP005.ROM b/Source/Images/d_msxroms1/u0/AEJAP005.ROM new file mode 100644 index 00000000..b80324ce Binary files /dev/null and b/Source/Images/d_msxroms1/u0/AEJAP005.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ALBAT009.ROM b/Source/Images/d_msxroms1/u0/ALBAT009.ROM new file mode 100644 index 00000000..a35ac521 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ALBAT009.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ALCAZ010.ROM b/Source/Images/d_msxroms1/u0/ALCAZ010.ROM new file mode 100644 index 00000000..cba2d123 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ALCAZ010.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ALIBA011.ROM b/Source/Images/d_msxroms1/u0/ALIBA011.ROM new file mode 100644 index 00000000..2c11cae4 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ALIBA011.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ALIEN012.ROM b/Source/Images/d_msxroms1/u0/ALIEN012.ROM new file mode 100644 index 00000000..ecf6367d Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ALIEN012.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ALPHA014.ROM b/Source/Images/d_msxroms1/u0/ALPHA014.ROM new file mode 100644 index 00000000..5439aa19 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ALPHA014.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ALPHA015.ROM b/Source/Images/d_msxroms1/u0/ALPHA015.ROM new file mode 100644 index 00000000..3313446e Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ALPHA015.ROM differ diff --git a/Source/Images/d_msxroms1/u0/AMERI016.ROM b/Source/Images/d_msxroms1/u0/AMERI016.ROM new file mode 100644 index 00000000..39f9dbfd Binary files /dev/null and b/Source/Images/d_msxroms1/u0/AMERI016.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ANAZA017.ROM b/Source/Images/d_msxroms1/u0/ANAZA017.ROM new file mode 100644 index 00000000..ea6fd222 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ANAZA017.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ANGEL018.ROM b/Source/Images/d_msxroms1/u0/ANGEL018.ROM new file mode 100644 index 00000000..89881a99 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ANGEL018.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ANTAR020.ROM b/Source/Images/d_msxroms1/u0/ANTAR020.ROM new file mode 100644 index 00000000..422b9501 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ANTAR020.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ANTAR021.ROM b/Source/Images/d_msxroms1/u0/ANTAR021.ROM new file mode 100644 index 00000000..445a8f0f Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ANTAR021.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ANTYJ022.ROM b/Source/Images/d_msxroms1/u0/ANTYJ022.ROM new file mode 100644 index 00000000..a67c0d76 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ANTYJ022.ROM differ diff --git a/Source/Images/d_msxroms1/u0/AQUAP023.ROM b/Source/Images/d_msxroms1/u0/AQUAP023.ROM new file mode 100644 index 00000000..e6da508b Binary files /dev/null and b/Source/Images/d_msxroms1/u0/AQUAP023.ROM differ diff --git a/Source/Images/d_msxroms1/u0/AQUAT024.ROM b/Source/Images/d_msxroms1/u0/AQUAT024.ROM new file mode 100644 index 00000000..a0c6b2e7 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/AQUAT024.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ARAMO025.ROM b/Source/Images/d_msxroms1/u0/ARAMO025.ROM new file mode 100644 index 00000000..bfbfdce6 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ARAMO025.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ARKAN026.ROM b/Source/Images/d_msxroms1/u0/ARKAN026.ROM new file mode 100644 index 00000000..bc365bea Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ARKAN026.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ATHLE027.ROM b/Source/Images/d_msxroms1/u0/ATHLE027.ROM new file mode 100644 index 00000000..b7b1aa69 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ATHLE027.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ATHLE028.ROM b/Source/Images/d_msxroms1/u0/ATHLE028.ROM new file mode 100644 index 00000000..e60aa84a Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ATHLE028.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ATHLE029.ROM b/Source/Images/d_msxroms1/u0/ATHLE029.ROM new file mode 100644 index 00000000..0cdc3cff Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ATHLE029.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ATTAC030.ROM b/Source/Images/d_msxroms1/u0/ATTAC030.ROM new file mode 100644 index 00000000..c8e9d720 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ATTAC030.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BACKG032.ROM b/Source/Images/d_msxroms1/u0/BACKG032.ROM new file mode 100644 index 00000000..e66f0da2 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BACKG032.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BACKG034.ROM b/Source/Images/d_msxroms1/u0/BACKG034.ROM new file mode 100644 index 00000000..365128d4 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BACKG034.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BACKT033.ROM b/Source/Images/d_msxroms1/u0/BACKT033.ROM new file mode 100644 index 00000000..d2f30d91 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BACKT033.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BALAN035.ROM b/Source/Images/d_msxroms1/u0/BALAN035.ROM new file mode 100644 index 00000000..476266cf Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BALAN035.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BANAN036.ROM b/Source/Images/d_msxroms1/u0/BANAN036.ROM new file mode 100644 index 00000000..17e1c319 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BANAN036.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BANKP037.ROM b/Source/Images/d_msxroms1/u0/BANKP037.ROM new file mode 100644 index 00000000..b3579e3d Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BANKP037.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BASIC038.ROM b/Source/Images/d_msxroms1/u0/BASIC038.ROM new file mode 100644 index 00000000..731ef712 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BASIC038.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BASIC039.ROM b/Source/Images/d_msxroms1/u0/BASIC039.ROM new file mode 100644 index 00000000..5d0904e8 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BASIC039.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BATTE041.ROM b/Source/Images/d_msxroms1/u0/BATTE041.ROM new file mode 100644 index 00000000..5e32105d Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BATTE041.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BATTL042.ROM b/Source/Images/d_msxroms1/u0/BATTL042.ROM new file mode 100644 index 00000000..5a6022d3 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BATTL042.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BATTL043.ROM b/Source/Images/d_msxroms1/u0/BATTL043.ROM new file mode 100644 index 00000000..6e3346f1 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BATTL043.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BCSQU031.ROM b/Source/Images/d_msxroms1/u0/BCSQU031.ROM new file mode 100644 index 00000000..3df3ea51 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BCSQU031.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BEACH044.ROM b/Source/Images/d_msxroms1/u0/BEACH044.ROM new file mode 100644 index 00000000..ceea3df9 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BEACH044.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BEAMR045.ROM b/Source/Images/d_msxroms1/u0/BEAMR045.ROM new file mode 100644 index 00000000..d81d7e67 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BEAMR045.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BECKY046.ROM b/Source/Images/d_msxroms1/u0/BECKY046.ROM new file mode 100644 index 00000000..d6a6a304 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BECKY046.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BEEFL047.ROM b/Source/Images/d_msxroms1/u0/BEEFL047.ROM new file mode 100644 index 00000000..5ff6ae68 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BEEFL047.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BIFAM048.ROM b/Source/Images/d_msxroms1/u0/BIFAM048.ROM new file mode 100644 index 00000000..5d47a3c9 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BIFAM048.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BINAR049.ROM b/Source/Images/d_msxroms1/u0/BINAR049.ROM new file mode 100644 index 00000000..91af7e5d Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BINAR049.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BLACK051.ROM b/Source/Images/d_msxroms1/u0/BLACK051.ROM new file mode 100644 index 00000000..37b421bb Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BLACK051.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BLAGG052.ROM b/Source/Images/d_msxroms1/u0/BLAGG052.ROM new file mode 100644 index 00000000..6162bac0 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BLAGG052.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BLOCK053.ROM b/Source/Images/d_msxroms1/u0/BLOCK053.ROM new file mode 100644 index 00000000..b37356a4 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BLOCK053.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BLOCK054.ROM b/Source/Images/d_msxroms1/u0/BLOCK054.ROM new file mode 100644 index 00000000..f9141e13 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BLOCK054.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOGGY055.ROM b/Source/Images/d_msxroms1/u0/BOGGY055.ROM new file mode 100644 index 00000000..4d0f7c62 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOGGY055.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOING056.ROM b/Source/Images/d_msxroms1/u0/BOING056.ROM new file mode 100644 index 00000000..b6693c08 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOING056.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOKOS057.ROM b/Source/Images/d_msxroms1/u0/BOKOS057.ROM new file mode 100644 index 00000000..d1ccf715 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOKOS057.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOMBE059.ROM b/Source/Images/d_msxroms1/u0/BOMBE059.ROM new file mode 100644 index 00000000..5947632c Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOMBE059.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOMBE060.ROM b/Source/Images/d_msxroms1/u0/BOMBE060.ROM new file mode 100644 index 00000000..87008bdf Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOMBE060.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOOGI061.ROM b/Source/Images/d_msxroms1/u0/BOOGI061.ROM new file mode 100644 index 00000000..2ff616f2 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOOGI061.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOOME062.ROM b/Source/Images/d_msxroms1/u0/BOOME062.ROM new file mode 100644 index 00000000..8fae0aaa Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOOME062.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOSCO064.ROM b/Source/Images/d_msxroms1/u0/BOSCO064.ROM new file mode 100644 index 00000000..ea6e5005 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOSCO064.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOUKE065.ROM b/Source/Images/d_msxroms1/u0/BOUKE065.ROM new file mode 100644 index 00000000..d362a293 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOUKE065.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOULD066.ROM b/Source/Images/d_msxroms1/u0/BOULD066.ROM new file mode 100644 index 00000000..6412c3eb Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOULD066.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BOUNC067.ROM b/Source/Images/d_msxroms1/u0/BOUNC067.ROM new file mode 100644 index 00000000..9bb57080 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BOUNC067.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BRAIN068.ROM b/Source/Images/d_msxroms1/u0/BRAIN068.ROM new file mode 100644 index 00000000..1b62f7a5 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BRAIN068.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BREAK070.ROM b/Source/Images/d_msxroms1/u0/BREAK070.ROM new file mode 100644 index 00000000..65874352 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BREAK070.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BROTH071.ROM b/Source/Images/d_msxroms1/u0/BROTH071.ROM new file mode 100644 index 00000000..a96bce8e Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BROTH071.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BRUCE072.ROM b/Source/Images/d_msxroms1/u0/BRUCE072.ROM new file mode 100644 index 00000000..b1205bbb Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BRUCE072.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BUBBL073.ROM b/Source/Images/d_msxroms1/u0/BUBBL073.ROM new file mode 100644 index 00000000..a85441fc Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BUBBL073.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BURGE074.ROM b/Source/Images/d_msxroms1/u0/BURGE074.ROM new file mode 100644 index 00000000..ddc34299 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/BURGE074.ROM differ diff --git a/Source/Images/d_msxroms1/u0/BURUT075.ROM b/Source/Images/d_msxroms1/u0/BURUT075.ROM new file mode 100644 index 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b/Source/Images/d_msxroms1/u0/HYPER258.ROM new file mode 100644 index 00000000..368b8b42 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/HYPER258.ROM differ diff --git a/Source/Images/d_msxroms1/u0/HYPER259.ROM b/Source/Images/d_msxroms1/u0/HYPER259.ROM new file mode 100644 index 00000000..093755f0 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/HYPER259.ROM differ diff --git a/Source/Images/d_msxroms1/u0/HYPER260.ROM b/Source/Images/d_msxroms1/u0/HYPER260.ROM new file mode 100644 index 00000000..ab1bbe5c Binary files /dev/null and b/Source/Images/d_msxroms1/u0/HYPER260.ROM differ diff --git a/Source/Images/d_msxroms1/u0/HYPER261.ROM b/Source/Images/d_msxroms1/u0/HYPER261.ROM new file mode 100644 index 00000000..65da8d52 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/HYPER261.ROM differ diff --git a/Source/Images/d_msxroms1/u0/HYPER262.ROM b/Source/Images/d_msxroms1/u0/HYPER262.ROM new file mode 100644 index 00000000..78d8f534 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/HYPER262.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ICEWO263.ROM b/Source/Images/d_msxroms1/u0/ICEWO263.ROM new file mode 100644 index 00000000..68fe5f72 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ICEWO263.ROM differ diff --git a/Source/Images/d_msxroms1/u0/IGANI264.ROM b/Source/Images/d_msxroms1/u0/IGANI264.ROM new file mode 100644 index 00000000..d2277337 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/IGANI264.ROM differ diff --git a/Source/Images/d_msxroms1/u0/IGANI265.ROM b/Source/Images/d_msxroms1/u0/IGANI265.ROM new file mode 100644 index 00000000..eebeb05b Binary files /dev/null and b/Source/Images/d_msxroms1/u0/IGANI265.ROM differ diff --git a/Source/Images/d_msxroms1/u0/INDIA266.ROM b/Source/Images/d_msxroms1/u0/INDIA266.ROM new file mode 100644 index 00000000..525f89e9 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/INDIA266.ROM differ diff --git a/Source/Images/d_msxroms1/u0/IRIEG267.ROM b/Source/Images/d_msxroms1/u0/IRIEG267.ROM new file mode 100644 index 00000000..7ffb5bcc Binary files /dev/null and b/Source/Images/d_msxroms1/u0/IRIEG267.ROM differ diff --git a/Source/Images/d_msxroms1/u0/IRIEG268.ROM b/Source/Images/d_msxroms1/u0/IRIEG268.ROM new file mode 100644 index 00000000..c0908747 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/IRIEG268.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ISSUN269.ROM b/Source/Images/d_msxroms1/u0/ISSUN269.ROM new file mode 100644 index 00000000..801705f1 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/ISSUN269.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JANKA272.ROM b/Source/Images/d_msxroms1/u0/JANKA272.ROM new file mode 100644 index 00000000..488fa29a Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JANKA272.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JETSE273.ROM b/Source/Images/d_msxroms1/u0/JETSE273.ROM new file mode 100644 index 00000000..97c5d428 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JETSE273.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JIGSA274.ROM b/Source/Images/d_msxroms1/u0/JIGSA274.ROM new file mode 100644 index 00000000..295991b7 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JIGSA274.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JISSE275.ROM b/Source/Images/d_msxroms1/u0/JISSE275.ROM new file mode 100644 index 00000000..5528d199 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JISSE275.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JPWIN270.ROM b/Source/Images/d_msxroms1/u0/JPWIN270.ROM new file mode 100644 index 00000000..04e7657d Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JPWIN270.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JUMPC277.ROM b/Source/Images/d_msxroms1/u0/JUMPC277.ROM new file mode 100644 index 00000000..1d745007 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JUMPC277.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JUMPI279.ROM b/Source/Images/d_msxroms1/u0/JUMPI279.ROM new file mode 100644 index 00000000..9b76cda9 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JUMPI279.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JUMPJ276.ROM b/Source/Images/d_msxroms1/u0/JUMPJ276.ROM new file mode 100644 index 00000000..484aee0d Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JUMPJ276.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JUMPL278.ROM b/Source/Images/d_msxroms1/u0/JUMPL278.ROM new file mode 100644 index 00000000..56358488 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JUMPL278.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JUNOF280.ROM b/Source/Images/d_msxroms1/u0/JUNOF280.ROM new file mode 100644 index 00000000..728a51da Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JUNOF280.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JYANF281.ROM b/Source/Images/d_msxroms1/u0/JYANF281.ROM new file mode 100644 index 00000000..4cdd3a98 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JYANF281.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JYANK282.ROM b/Source/Images/d_msxroms1/u0/JYANK282.ROM new file mode 100644 index 00000000..312e435a Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JYANK282.ROM differ diff --git a/Source/Images/d_msxroms1/u0/JYANY283.ROM b/Source/Images/d_msxroms1/u0/JYANY283.ROM new file mode 100644 index 00000000..a38ec42f Binary files /dev/null and b/Source/Images/d_msxroms1/u0/JYANY283.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KAGEN284.ROM b/Source/Images/d_msxroms1/u0/KAGEN284.ROM new file mode 100644 index 00000000..ff101dab Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KAGEN284.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KARAM285.ROM b/Source/Images/d_msxroms1/u0/KARAM285.ROM new file mode 100644 index 00000000..aab310b5 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KARAM285.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KEYST287.ROM b/Source/Images/d_msxroms1/u0/KEYST287.ROM new file mode 100644 index 00000000..2ff1820a Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KEYST287.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KICKI288.ROM b/Source/Images/d_msxroms1/u0/KICKI288.ROM new file mode 100644 index 00000000..11e28f0b Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KICKI288.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KINAS289.ROM b/Source/Images/d_msxroms1/u0/KINAS289.ROM new file mode 100644 index 00000000..8d9bf8f7 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KINAS289.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KINGB290.ROM b/Source/Images/d_msxroms1/u0/KINGB290.ROM new file mode 100644 index 00000000..48799c65 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KINGB290.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KINGS292.ROM b/Source/Images/d_msxroms1/u0/KINGS292.ROM new file mode 100644 index 00000000..052e59c5 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KINGS292.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KINNI294.ROM b/Source/Images/d_msxroms1/u0/KINNI294.ROM new file mode 100644 index 00000000..6d9e0e93 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KINNI294.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KNIGH295.ROM b/Source/Images/d_msxroms1/u0/KNIGH295.ROM new file mode 100644 index 00000000..586382fc Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KNIGH295.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KNIGH296.ROM b/Source/Images/d_msxroms1/u0/KNIGH296.ROM new file mode 100644 index 00000000..553593b8 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KNIGH296.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM300.ROM b/Source/Images/d_msxroms1/u0/KONAM300.ROM new file mode 100644 index 00000000..a3c28167 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM300.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM301.ROM b/Source/Images/d_msxroms1/u0/KONAM301.ROM new file mode 100644 index 00000000..508cb9c2 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM301.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM302.ROM b/Source/Images/d_msxroms1/u0/KONAM302.ROM new file mode 100644 index 00000000..a5b250f1 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM302.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM303.ROM b/Source/Images/d_msxroms1/u0/KONAM303.ROM new file mode 100644 index 00000000..8910179b Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM303.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM304.ROM b/Source/Images/d_msxroms1/u0/KONAM304.ROM new file mode 100644 index 00000000..425119fa Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM304.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM305.ROM b/Source/Images/d_msxroms1/u0/KONAM305.ROM new file mode 100644 index 00000000..f2ddc197 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM305.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM306.ROM b/Source/Images/d_msxroms1/u0/KONAM306.ROM new file mode 100644 index 00000000..fba79319 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM306.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM307.ROM b/Source/Images/d_msxroms1/u0/KONAM307.ROM new file mode 100644 index 00000000..bc6feec3 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM307.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONAM308.ROM b/Source/Images/d_msxroms1/u0/KONAM308.ROM new file mode 100644 index 00000000..8b7d9319 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONAM308.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KONEK309.ROM b/Source/Images/d_msxroms1/u0/KONEK309.ROM new file mode 100644 index 00000000..f450a0e1 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KONEK309.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KUNGF310.ROM b/Source/Images/d_msxroms1/u0/KUNGF310.ROM new file mode 100644 index 00000000..a6f186a6 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KUNGF310.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KUNGF311.ROM b/Source/Images/d_msxroms1/u0/KUNGF311.ROM new file mode 100644 index 00000000..c77d1051 Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KUNGF311.ROM differ diff --git a/Source/Images/d_msxroms1/u0/KUNGF312.ROM b/Source/Images/d_msxroms1/u0/KUNGF312.ROM new file mode 100644 index 00000000..ba6ff72e Binary files /dev/null and b/Source/Images/d_msxroms1/u0/KUNGF312.ROM differ diff --git a/Source/Images/d_msxroms1/u0/ROMLIST.TXT b/Source/Images/d_msxroms1/u0/ROMLIST.TXT new file mode 100644 index 00000000..9bbaed80 --- /dev/null +++ b/Source/Images/d_msxroms1/u0/ROMLIST.TXT @@ -0,0 +1,495 @@ +379 LOADING GAMES OUT OF 481 ROMS + +Some require keyboard support and/or 2 joystick buttons. They are marked with a '?' in the list below +Some require the patcher (MSX8P.COM). They are marked with a 'P' in the list below +Some don't work at all. They are marked with a 'N' in the list below + +Y = (271) WORKS +YP= ( 55) USE MSX8P (PATCHER VERSION NEEDED DUE TO DIRECT VDP/PSG WRITES INSTEAD OF GOING THROUGH THE BIOS) +? = ( 53) RUNS BUT NOT PLAYABLE - POSSIBLY REQUIRES TWO BUTTON JOYSTICK OR UNSUPPORTED KEYBOARD CONTROLS +N = DOES NOT WORK + +STAT SHORT NAME LONG NAME (481 ROMS) +==== ============ ============================================ + Y 10YAR000.ROM 10-Yard Fight (Japan).rom + N0 3DGOL002.ROM 3-D Golf Simulation (Japan) (High Speed).rom + N0 3DGOL003.ROM 3-D Golf Simulation (Japan).rom + N0 3DTEN004.ROM 3D Tennis (Japan).rom + Y ACTMA007.ROM Actman (Japan).rom + Y ADVEN008.ROM Adven' Chuta! (Japan).rom + Y AEJAP005.ROM A.E. (Japan).rom + Y? ALBAT009.ROM Albatros (Japan).rom + NP8 ALCAZ010.ROM Alcazar - The Forgotten Fortress (Japan).rom + YP ALIBA011.ROM Alibaba and 40 Thieves (Japan).rom + YP ALIEN012.ROM Alien 8 (Japan).rom + YP? ALPHA014.ROM Alpha Roid (Japan).rom + YP ALPHA015.ROM Alpha Squadron (Japan).rom + Y AMERI016.ROM American Truck (Japan).rom + YP ANAZA017.ROM Anaza - Kaleidoscope Special (Japan).rom + Y? ANGEL018.ROM Angelo (Japan).rom + Y ANTAR020.ROM Antarctic Adventure (Europe).rom + YP ANTAR021.ROM Antarctic Adventure (Japan).rom + YP ANTYJ022.ROM Anty (Japan).rom + Y AQUAP023.ROM Aqua Polis SOS (Japan).rom + N4 AQUAT024.ROM Aquattack (Japan).rom + Y ARAMO025.ROM Aramo (Japan).rom + YP ARKAN026.ROM Arkanoid (Japan).rom + Y ATHLE027.ROM Athletic Ball (Japan).rom + N ATHLE028.ROM Athletic Land (Japan) (Beta).rom + YP ATHLE029.ROM Athletic Land (Japan).rom + Y ATTAC030.ROM Attack Four Volley Ball (Japan).rom + N4 BACKG032.ROM Back Gammon (Japan).rom + Y BACKG034.ROM Backgammon (Europe).rom + Y BACKT033.ROM Back to the Future (Japan).rom + YP BALAN035.ROM Balance (Japan).rom + Y BANAN036.ROM Banana (Japan).rom + Y BANKP037.ROM Bank Panic (Japan).rom + N5 BASIC038.ROM Basic Lessons 1 (Japan).rom + N BASIC039.ROM Basic Lessons 2 (Japan).rom + N4 BATTE041.ROM Batten Tanuki no Daibouken (Japan) (v1.03).rom + Y BATTL042.ROM Battle Cross (Japan).rom + Y BATTL043.ROM Battleship Clapton II (Japan).rom + Y BCSQU031.ROM B.C.'s Quest (Japan).rom + Y BEACH044.ROM Beach-Head (Europe).rom + N0 BEAMR045.ROM Beam Rider (Japan).rom + Y BECKY046.ROM Becky (Japan).rom + Y BEEFL047.ROM Bee & Flower (Japan).rom + Y BIFAM048.ROM Bifamu (Japan).rom + Y BINAR049.ROM Binary Land (Japan).rom + Y BLACK051.ROM Black Onyx, The (Japan).rom + Y? BLAGG052.ROM Blagger MSX (Europe) (Converted From Tape).rom + YP BLOCK053.ROM Block Hole (Korea) (Unl).rom + Y BLOCK054.ROM Blockade Runner (Japan).rom + Y BOGGY055.ROM Boggy '84 (Japan).rom + Y BOING056.ROM Boing Boing (Spain).rom + N8 BOKOS057.ROM Bokosuka Wars (Japan).rom + Y BOMBE059.ROM Bomber Man (Japan).rom + Y BOMBE060.ROM Bomber Man Special (Japan).rom + Y BOOGI061.ROM Boogie Woogi Jungle (Japan).rom + Y? BOOME062.ROM Boomerang (Japan).rom + Y BOSCO064.ROM Bosconian (Japan).rom + Y BOUKE065.ROM Bouken Roman - Dota (Japan).rom + Y BOULD066.ROM Boulder Dash (Japan).rom + Y BOUNC067.ROM Bouncing Block (Spain).rom + N0 BRAIN068.ROM Brain, The (Japan).rom + N0 BREAK070.ROM Break Out (Japan).rom + Y BROTH071.ROM Brother Adventure (Korea) (Unl).rom + Y BRUCE072.ROM Bruce Lee (Japan).rom + YP BUBBL073.ROM Bubble Bobble (Korea) (Unl).rom + N0 BURGE074.ROM Burgertime (Japan).rom + Y BURUT075.ROM Buru To Marty Kikiippatsu - Inspecteur Z (Japan).rom + Y BUTAM076.ROM Butam Pants (Japan).rom + Y CABBA078.ROM Cabbage Patch Kids (Japan).rom + YP? CANDO079.ROM Candoo Ninja (Japan).rom + Y CANNO080.ROM Cannon Ball (Japan).rom + Y CANNO081.ROM Cannon Fighter (Japan).rom + Y CAPTA082.ROM Captain Chef (Japan).rom + Y CARFI083.ROM Car Fighter (Japan).rom + YP CARJA084.ROM Car Jamboree (Japan).rom + Y CARRA085.ROM Car-Race (Japan).rom + Y CASIO086.ROM Casio Daishogai Keiba (Japan).rom + Y CASIO087.ROM Casio Pachinko-U.F.O. (Japan).rom + Y CASIO088.ROM Casio Ski Command (Japan).rom + Y CASIO089.ROM Casio Worldopen (Japan).rom + Y CASTL090.ROM Castle Excellent (Japan).rom + Y CASTL091.ROM Castle, The (Japan).rom + Y CHACK092.ROM Chack'n Pop (Japan).rom + Y CHALL093.ROM Challenge Derby (Japan).rom + Y CHAMP094.ROM Champion Boxing (Japan).rom + Y? CHAMP095.ROM Champion Ice Hockey (Japan).rom + Y CHAMP096.ROM Champion Kendou (Japan).rom + Y CHAMP097.ROM Champion Pro Wrestling (Japan).rom + Y CHAMP098.ROM Champion Soccer (Japan).rom + Y CHAMP099.ROM Championship Lode Runner (Japan).rom + Y? CHECK100.ROM Checkers in Tantan Tanuki (Japan).rom + NP4 CHESS101.ROM Chess (Japan).rom + NP4 CHESS102.ROM Chess Game, The (Europe).rom + Y CHOPL103.ROM Choplifter (Japan).rom + YP CHORO104.ROM Choro Q (Japan).rom + N4 CHUGA105.ROM Chugaku Hisshu Eibunpo 1 (Japan).rom + Y CIRCU106.ROM Circus Charlie (Japan).rom + Y CITYC107.ROM City Connection (Japan).rom + YP COAST108.ROM Coaster Race (Japan).rom + Y COLOR109.ROM Color Ball (Japan).rom + N0 COLUM110.ROM Columns (Japan).rom + Y COMEC112.ROM Comecocos (Spain).rom + YP COMEO111.ROM Come On! Picot (Japan).rom + N0 COMET113.ROM Comet Tail (Japan).rom + Y COMIC114.ROM Comic Bakery (Japan).rom + YP COMPU115.ROM Computer Billiards (Japan).rom + NP4 COMPU116.ROM Computer Nyuumon - Computer Lessons (Japan).rom + NP5 COMPU117.ROM Computer Othello (Japan).rom + YP COMPU118.ROM Computer Pachinko (Japan).rom + Y CONDO119.ROM Con-Dori (Japan).rom + N8 COSMO121.ROM Cosmo (Japan).rom + Y COSMO122.ROM Cosmo-Explorer (Japan).rom + N0 COURA123.ROM Courageous Perseus (Japan).rom + N0 CRAZY125.ROM Crazy Bullet (Japan).rom + Y CRAZY126.ROM Crazy Cars (Europe).rom + N0 CRAZY127.ROM Crazy Train (Japan).rom + Y CRUSA129.ROM Crusader (Japan).rom + N4 CSOJA077.ROM C-So! (Japan).rom + N4 DAIDA131.ROM Daidasso (Japan).rom + Y DAMBU133.ROM Dam Busters, The (Japan).rom + N0 DANGE134.ROM Danger X4 (Japan).rom + Y DAVID135.ROM David II (Japan).rom + Y DDAYJ130.ROM D-Day (Japan).rom + N0 DECAT137.ROM Decathlon (Japan).rom + N0 DEMON140.ROM Demon Crystal, The (Japan).rom + Y DEVIL142.ROM Devil's Heaven (Japan).rom + Y DIGDU143.ROM Dig Dug (Japan).rom + YP DIPDI145.ROM Dip Dip (Spain).rom + Y DOKID146.ROM Doki Doki Penguin Land (Japan).rom + Y DOORD147.ROM Doordoor (Japan).rom + N4 DOROD148.ROM Dorodon (Japan).rom + YP DOUBL149.ROM Double Dragon (Korea) (Unl).rom + Y? DRCOP150.ROM Dr. Copy (Japan).rom + Y DRAGO151.ROM Dragon Attack (Japan).rom + Y DRAGO154.ROM Dragon Slayer (Japan).rom + YP DRAIN158.ROM Drainer (Japan).rom + Y DRUAG159.ROM Druaga no Tou (Japan).rom + Y? DUNGE161.ROM Dungeon Master (Japan).rom + Y DUNKS162.ROM Dunk Shot (Japan).rom + NF EAGLE164.ROM Eagle Fighter (Japan).rom + N4 EGGER165.ROM Eggerland Mystery (Japan).rom + Y ELEVA166.ROM Elevator Action (Japan).rom + Y? ERIKA167.ROM Erika (Japan).rom + Y EXAIN168.ROM Exa Innova (Japan).rom + N0 EXCHA169.ROM Exchanger (Japan).rom + Y EXERI170.ROM Exerion (Japan).rom + Y EXERI171.ROM Exerion II - Zorni (Japan).rom + YP EXOID172.ROM Exoide-Z (Japan).rom + Y EXOID173.ROM Exoide-Z Area 5 (Japan).rom + N8 F16FI175.ROM F16 Fighting Falcon (Japan).rom + Y FAIRY177.ROM Fairy (Japan).rom + YP FATET176.ROM Fa Tetris (Korea) (Unl).rom + Y FATHO183.ROM Fathom (Japan).rom + Y FINAL184.ROM Final Justice (Japan).rom + Y FINAL185.ROM Final Mahjong (Japan).rom + Y FIRER187.ROM Fire Rescue (Japan).rom + Y FLAPP188.ROM Flappy (Japan).rom + Y FLAPP189.ROM Flappy - Limited 85 (Japan).rom + YP? FLASH190.ROM Flash Point (Korea) (Unl).rom + Y FLASH191.ROM Flash Splash (Japan).rom + Y FLICK192.ROM Flicky (Japan).rom + Y FLICS193.ROM Flics, Les (France).rom + Y FLIPP196.ROM Flipper Slipper (Japan).rom + Y FORMA197.ROM Formation Z (Japan).rom + YP FROGG198.ROM Frogger (Japan).rom + Y FRONT199.ROM Front Line (Japan).rom + Y FRUIT200.ROM Fruit Search (Japan).rom + Y FUNKY201.ROM Funky Mouse (Japan).rom + N8 FUTBO202.ROM Futbol (Spain).rom + Y FUUNT203.ROM Fuun Takeshijyou (Japan).rom + Y GALAG204.ROM Galaga (Japan).rom + Y GALAX205.ROM Galaxian (Japan).rom + N0 GAMEL208.ROM Game Land (Japan).rom + Y? GAMEM209.ROM Game Master (Europe).rom + Y? GAMEM210.ROM Game Master (Japan).rom + N0 GANGM213.ROM Gang Master (Japan).rom + YP GHOST216.ROM Ghostbusters (Europe).rom + Y? GLIDE217.ROM Glider (Japan).rom + Y GOKIB218.ROM Gokiburi Daisakusen - Bug Bomb (Japan).rom + N0 GOLFG219.ROM Golf Game (Japan).rom + YP? GOMOK221.ROM Gomok Narabe - Omo Go (Japan).rom + Y GOONI222.ROM Goonies, The (Japan).rom + Y GPWOR223.ROM GP World (Japan).rom + N9 GREEN224.ROM Green Beret (Europe).rom + Y GROGS225.ROM Grog's Revenge (Japan).rom + Y GUARD226.ROM Guardic (Japan).rom + Y GULKA227.ROM Gulkave (Japan).rom + YP GUNFR228.ROM Gun Fright (Japan).rom + Y GUNJI229.ROM Gunjin Shougi Mars (Japan).rom + YP GYROD230.ROM Gyrodine (Japan).rom + N0 HEROJ231.ROM H.E.R.O. (Japan).rom + Y HADES232.ROM Hades no Monsho (Japan).rom + Y HAFAN233.ROM Hafanuda Koi Koi - Gostop Godori (Japan).rom + YP HANAF235.ROM Hanafuta (Japan).rom + Y HANGO236.ROM Hang-On (Japan).rom + Y HARAP237.ROM Harapeko Pakkun (Japan).rom + Y HAUNT240.ROM Haunted Boynight (Japan).rom + Y HEAVY241.ROM Heavy Boxing (Japan).rom + Y HEIST242.ROM Heist, The (Japan).rom + Y HELIT243.ROM Helitank (Japan).rom + Y HIGHW244.ROM High Way Star (Japan).rom + Y HIGHW245.ROM High Way Star (Korea).rom + YP? HISYA246.ROM Hisya (Japan).rom + Y HITSU247.ROM Hitsuji Yai - Preety Sheep (Japan).rom + Y HOLEI248.ROM Hole in One (Japan).rom + Y? HOLEI249.ROM Hole in One Professional (Japan).rom + Y HONKB250.ROM Honkball (Japan).rom + YP HOPPE251.ROM Hopper (Europe).rom + Y? HUDSO252.ROM Hudson 3D Golf (Japan).rom + Y HUSTL253.ROM Hustle! Chumy (Japan).rom + Y HYDLI254.ROM Hydlide (Japan).rom + Y HYPER257.ROM Hyper Olympic 1 (Japan).rom + Y HYPER258.ROM Hyper Olympic 2 (Japan).rom + Y? HYPER259.ROM Hyper Rally (Japan).rom + Y HYPER260.ROM Hyper Sports 1 (Japan).rom + Y HYPER261.ROM Hyper Sports 2 (Japan).rom + N4 HYPER262.ROM Hyper Sports 3 (Japan).rom + Y ICEWO263.ROM Ice World (Japan).rom + Y IGANI264.ROM Iga Ninpouten - Small Ninja (Japan).rom + Y IGANI265.ROM Iga Ninpouten 2 - Small Ninja 2 (Japan).rom + Y INDIA266.ROM Indian no Bouken (Japan).rom + N0 IRIEG267.ROM Iriegas (Japan).rom + Y IRIEG268.ROM Iriegas - Theseus (Japan).rom + Y ISSUN269.ROM Issunhoushi No Donnamondai (Japan).rom + Y JPWIN270.ROM J.P. Winkle (Japan).rom + Y JANKA272.ROM Janka (Japan).rom + Y JETSE273.ROM Jet Set Willy (Japan).rom + Y JIGSA274.ROM Jigsaw Set (Japan).rom + Y JISSE275.ROM Jissen - 4-nin Mahjong (Japan).rom + Y JUMPJ276.ROM Jump (Japan).rom + Y JUMPC277.ROM Jump Coaster (Japan).rom + YP JUMPL278.ROM Jump Land (Japan).rom + Y JUMPI279.ROM Jumping Rabbit (Japan).rom + N0 JUNOF280.ROM Juno First (Japan).rom + Y JYANF281.ROM Jyan Friend (Japan).rom + Y JYANK282.ROM Jyankyo (Japan).rom + Y JYANY283.ROM Jyanyuu (Japan).rom + N4 KAGEN284.ROM Kage no Densetsu - Legend of Kage, The (Japan).rom + N0 KARAM285.ROM Karamaru (Japan).rom + N0 KEYST287.ROM Keystone Kapers (Japan).rom + YP KICKI288.ROM Kick It (Japan).rom + Y KINAS289.ROM Kinasai (Japan) (Unl).rom + Y KINGB290.ROM King & Balloon (Japan).rom + Y KINGS292.ROM King's Valley (Japan, Europe).rom + Y KINNI294.ROM Kinnikuman - Muscle Man (Japan).rom + YP KNIGH295.ROM Knight Lore (Japan).rom + Y KNIGH296.ROM Knightmare - Majou Densetsu (Japan).rom + Y KONAM300.ROM Konami's Baseball (Japan).rom + Y KONAM301.ROM Konami's Billiards (Europe).rom + Y KONAM302.ROM Konami's Boxing (Japan).rom + N4 KONAM303.ROM Konami's Football (Europe).rom + N4 KONAM304.ROM Konami's Golf (Japan).rom + Y? KONAM305.ROM Konami's Mahjong (Japan).rom + Y? KONAM306.ROM Konami's Ping-Pong (Japan).rom + N4 KONAM307.ROM Konami's Soccer (Japan).rom + Y KONAM308.ROM Konami's Tennis (Japan).rom + Y KONEK309.ROM Koneko no Daibouken - Catboy (Japan).rom + Y KUNGF310.ROM Kung Fu Acho (Japan).rom + Y KUNGF311.ROM Kung Fu Master (Japan).rom + Y KUNGF312.ROM Kung Fu Taigun (Japan).rom + N0 LADDE313.ROM Ladder Building (Japan).rom + YP LAPTI314.ROM Laptick 2 (Japan).rom + Y LEMAN315.ROM Le Mans 2 (Europe).rom + N8 LEONA317.ROM Leonard (Spain).rom + Y LODER319.ROM Lode Runner (Japan).rom + Y LODER320.ROM Lode Runner II (Japan).rom + N0 LORDO321.ROM Lord Over (Japan).rom + N3 LOTLO322.ROM Lot Lot (Japan).rom + Y LUNAR323.ROM Lunar Ball (Japan).rom + N7 MACAT325.ROM Mac Attack (Europe).rom + Y MACHI326.ROM Machinegun Joe vs The Mafia (Japan).rom + Y MACRO327.ROM Macross (Japan).rom + Y MAGIC328.ROM Magical Kid Wiz (Japan).rom + Y MAGIC329.ROM Magical Tree (Japan).rom + Y MANES331.ROM Manes (Japan).rom + Y MAPPY332.ROM Mappy (Japan).rom + N0 MARIN334.ROM Marine Battle (Japan).rom + YP? MARSI335.ROM Mars II (Japan).rom + Y? MASTE337.ROM Master Chess (Europe).rom + Y MEGAL338.ROM Megalopolis SOS (Japan).rom + Y? MIDNI340.ROM Midnight Brothers (Japan).rom + Y? MIDNI341.ROM Midnight Building (Japan).rom + Y? MIDWA342.ROM Midway (Japan).rom + Y? MILCA343.ROM Mil Caras (Spain).rom + Y MINIG344.ROM Mini Golf (Japan).rom + Y MOAIN347.ROM Moai no Hibou (Japan).rom + Y MOBIL348.ROM Mobile Planet Suthirus - Approach from the Westgate (Japan).rom + Y MOBIL349.ROM Mobile-Suit Gundam - Last Shooting (Japan).rom + YP MOKAR350.ROM Mokarimakka (Japan).rom + N0 MOLEJ351.ROM Mole (Japan).rom + Y? MOLEM352.ROM Mole Mole 2 (Japan).rom + YP? MONKE353.ROM Monkey Academy (Japan).rom + Y MONST354.ROM Monster's Fair (Japan).rom + N0 MOONL355.ROM Moon Landing (Japan).rom + Y MOONP356.ROM Moon Patrol (Japan).rom + Y MOONS357.ROM Moonsweeper (Japan).rom + N4 MOPIR358.ROM Mopiranger (Japan).rom + NC MORIT359.ROM Morita Kazuo no Othello (Japan).rom + YP? MOUSE360.ROM Mouser (Japan).rom + Y MRCHI361.ROM Mr. Chin (Japan).rom + Y? MRDOJ362.ROM Mr. Do (Japan).rom + Y MRDOS364.ROM Mr. Do's Wild Ride (Japan).rom + Y MRDOV363.ROM Mr. Do vs Unicorns (Japan).rom + N0 MSX21365.ROM MSX 21 (Japan).rom + Y MSXBA366.ROM MSX Baseball (Japan).rom + Y MSXBA367.ROM MSX Baseball II National (Japan).rom + N0 MSXDE368.ROM MSX Derby (Japan).rom + Y MSXRU369.ROM MSX Rugby (Japan).rom + Y MSXSO370.ROM MSX Soccer (Japan).rom + N0 NAUSI372.ROM Nausicaa (Japan).rom + Y NESSE378.ROM Nessen Koushiyen (Japan).rom + YP NIGHT379.ROM Night Shade (Japan).rom + Y NINJA380.ROM Ninja Jajamaru-kun (Japan).rom + YP NINJA381.ROM Ninja Princess (Japan).rom + Y NINJA382.ROM Ninjakun (Japan).rom + Y NINJA383.ROM Ninjakun Majou (Japan).rom + Y NINJY384.ROM Ninjya Kage (Japan).rom + Y? NYANN386.ROM Nyan Nyan Pro Wrestling (Japan).rom + Y NYORO387.ROM Nyorols (Japan).rom + Y OILSW389.ROM Oil's Well (Japan).rom + Y? OKAMI390.ROM Okami no Su (Japan).rom + Y OMACF388.ROM O'Mac Farmer (Japan).rom + Y OTHEL391.ROM Othello (Japan).rom + Y OYOID392.ROM Oyoide Tango (Japan).rom + Y PACHI394.ROM Pachi Com (Japan).rom + Y PACMA393.ROM Pac-Man (Japan).rom + Y PAIPA395.ROM Pai Panic (Japan).rom + N0 PAIRS396.ROM Pairs (Japan).rom + Y PANTH397.ROM Panther (Japan).rom + N0 PASSB399.ROM Pass Ball (Japan).rom + YP? PASTF400.ROM Pastfinder (Japan).rom + Y? PAYLO401.ROM Pay Load (Japan).rom + Y PEETA402.ROM Peetan (Japan).rom + Y PEGAS403.ROM Pegasus (Japan).rom + Y PENGU405.ROM Penguin-kun Wars (Japan).rom + YP? PICOP406.ROM Pico Pico (Japan).rom + Y PICTU407.ROM Picture Puzzle (Japan).rom + Y? PILLB408.ROM Pillbox (Japan).rom + Y? PINEA410.ROM Pine Applin (Japan).rom + YP? PINGB411.ROM Pingball Maker (Japan).rom + YP PINKY412.ROM Pinky Chase (Japan).rom + Y PIPIJ413.ROM Pipi (Japan).rom + Y PIPPO414.ROM Pippols (Japan).rom + YP PITFA415.ROM Pitfall II - Lost Caverns (Japan).rom + NP8 PITFA416.ROM Pitfall! (Japan).rom + Y PLAYB417.ROM Play Ball (Japan).rom + N4 POINY418.ROM Poiny X Senryosakusen - Operation Thanksgiving (Japan).rom + Y POLIC419.ROM Police Story, The (Japan).rom + YP POOYA420.ROM Pooyan (Japan).rom + Y POPPA421.ROM Poppaq the Fish (Japan).rom + N4 PROFE423.ROM Professional Baseball (Japan).rom + YP? PROFE424.ROM Professional Mahjong (Japan).rom + Y PROTE425.ROM Protector, The (Japan).rom + Y PUZZL427.ROM Puzzle Panic (Japan).rom + Y PYRAM428.ROM Pyramid Warp (Japan).rom + Y QBERT429.ROM Q-bert (Japan).rom + Y QUEEN430.ROM Queen's Golf (Japan).rom + Y RAIDO432.ROM Raid on Bungeling Bay (Japan).rom + Y RALLY433.ROM Rally-X (Japan).rom + YP? RAMBO434.ROM Rambo (Japan).rom + YP? REALT435.ROM Real Tennis (Japan).rom + Y REDZO436.ROM Red Zone (Japan).rom + N0 RENJU438.ROM Renju & Ojama Dogs (Japan).rom + Y RISEO439.ROM Rise Out from Dungeons (Japan).rom + N0 RIVER440.ROM River Raid (Japan).rom + Y ROADF441.ROM Road Fighter (Japan).rom + Y ROBOF443.ROM Robofrog (Japan).rom + NP8 ROCKN444.ROM Rock'n Bolt (Japan).rom + Y ROGER445.ROM Roger Rubbish (Europe).rom + Y? ROLLE446.ROM Roller Ball (Japan).rom + N0 ROTOR447.ROM Rotors (Japan).rom + YP SASAJ450.ROM Sasa (Japan).rom + Y? SAURU451.ROM Saurus Land (Japan).rom + Y SCARL452.ROM Scarlet 7 - The Mightiest Women (Japan).rom + Y SCION453.ROM Scion (Japan).rom + N0 SCOPE454.ROM Scope On - Fight in Space (Japan).rom + Y SCRAM455.ROM Scramble Eggs (Japan).rom + Y SEAHU456.ROM Sea Hunter (Europe).rom + Y SENJY458.ROM Senjyo (Japan).rom + N4 SEWER459.ROM Sewer Sam (Japan).rom + Y SHOUG460.ROM Shougi (Japan).rom + N4 SHOUG461.ROM Shougi 2 (Japan).rom + N0 SHOUG462.ROM Shougi Game (Japan).rom + Y SHOUG463.ROM Shougi Meijin (Japan).rom + Y SHOUG464.ROM Shougi Sinan 1 (Japan).rom + YP SHOUT465.ROM Shout Match (Japan).rom + YP SINBA466.ROM Sinbad (Japan).rom + YP SKOOT467.ROM Skooter (Japan).rom + Y SKYGA468.ROM Sky Galdo (Japan).rom + Y SKYJA469.ROM Sky Jaguar (Japan).rom + N8 SLAPS470.ROM Slapshot (Spain).rom + Y SNAKE471.ROM Snake It (Europe).rom + Y SOUKO473.ROM Soukoban (Japan).rom + Y SPACE474.ROM Space Camp (Japan).rom + Y SPACE475.ROM Space Invaders (Japan).rom + Y SPACE476.ROM Space Maze Attack (Japan).rom + Y SPACE477.ROM Space Trouble (Japan).rom + Y SPACE478.ROM Space Walk (Europe).rom + N0 SPARK479.ROM Sparkie (Japan).rom + Y SPELU480.ROM Spelunker (Japan).rom + N8 SPIDE481.ROM Spider, The (Japan).rom + Y SQUAR483.ROM Square Dancer (Japan).rom + Y SQUIS484.ROM Squish'em (Japan).rom + Y STARB485.ROM Star Blazer (Japan).rom + N0 STARC486.ROM Star Command (Japan).rom + Y STARF487.ROM Star Force (Japan).rom + Y STARS488.ROM Star Soldier (Japan).rom + Y? START489.ROM Star Trap (Japan).rom + Y? STARS490.ROM Starship Simulator (Japan).rom + Y STEPU491.ROM Step Up (Japan).rom + N8 STEPP492.ROM Stepper (Japan).rom + Y STONE493.ROM Stone of Wisdom, The (Japan).rom + N4 STRAN494.ROM Strange Loop (Japan).rom + Y SUPAR495.ROM Suparobo (Japan).rom + N0 SUPER496.ROM Super Billiards (Japan).rom + YP? SUPER499.ROM Super Boy I (Korea) (Unl).rom + YP? SUPER500.ROM Super Boy II (Korea) (Unl).rom + YP SUPER501.ROM Super Bubble Bobble (Korea) (Unl).rom + NP4 SUPER502.ROM Super Cobra (Japan).rom + YP SUPER503.ROM Super Columns (Japan).rom + YP SUPER504.ROM Super Cross Force (Europe).rom + Y SUPER505.ROM Super Drinker (Japan).rom + YP SUPER506.ROM Super Golf (Japan).rom + NP8 SUPER508.ROM Super Pachinko (Japan).rom + Y SUPER510.ROM Super Snake (Japan).rom + Y SUPER511.ROM Super Soccer (Japan).rom + Y SUPER512.ROM Super Tennis (Japan).rom + NP4 SUPER513.ROM Super Tripper (Spain).rom + YP SWEET514.ROM Sweet Acorn (Japan).rom + N4 SWING515.ROM Swing (Japan).rom + Y TANKB517.ROM Tank Battalion (Japan).rom + Y TATIC518.ROM Tatica (Japan).rom + Y TAWAR519.ROM Tawara-kun (Japan).rom + Y TEARO520.ROM Tear of Nile (Japan).rom + NP8 TELEB521.ROM Telebunnie (Japan).rom + Y TENSA522.ROM Tensai Rabbian Daifunsen (Japan).rom + Y? TENSI523.ROM Tensidachino Gogo (Japan).rom + YP TENSI524.ROM Tension (Spain).rom + NP8 TETRA525.ROM Tetra Horror (Japan).rom + Y TETRI526.ROM Tetris (Korea) (Unl).rom + NP8 TETSU527.ROM Tetsuman (Japan).rom + Y THEXD528.ROM Thexder (Japan).rom + Y? THUND529.ROM Thunder Ball (Japan).rom + N6 THUND530.ROM Thunderbolt (Japan).rom + YP TIMEP531.ROM Time Pilot (Japan).rom + YP TOPPL534.ROM Topple Zip (Japan).rom + Y TOPRO533.ROM Top Roller! (Japan).rom + Y TRACK535.ROM Track & Field 1 (Europe).rom + Y TRACK536.ROM Track & Field 2 (Europe).rom + Y TRAFF537.ROM Traffic (Japan).rom + N0 TRIAL538.ROM Trial Ski (Japan).rom + Y TRICK539.ROM Trick Boy (Japan).rom + YP TRITO540.ROM Tritorn (Japan).rom + N0 TRUMP541.ROM Trumpaid (Japan).rom + N8 TURBO543.ROM Turboat (Japan).rom + Y TWINB544.ROM Twin Bee (Japan).rom + YP TWINH545.ROM Twin Hammer (Europe).rom + Y TZRGR546.ROM TZR - Grand Prix Rider (Japan).rom + Y ULTRA547.ROM Ultraman (Japan).rom + YP? VENUS549.ROM Venus Fire (Japan).rom + NP4 VIDEO550.ROM Video Hustler (Japan).rom + Y VOLGU551.ROM Volguard (Japan).rom + Y WARPW552.ROM Warp & Warp (Japan).rom + YP WARRO553.ROM Warroid (Japan).rom + Y? WATER554.ROM Water Driver (Japan).rom + Y WONDE556.ROM Wonder Boy (Japan).rom + NP4 WRANG557.ROM Wrangler (Spain).rom + NP4 WRECK558.ROM Wreck, The (Europe).rom + YP XYXOL559.ROM Xyxolog (Japan).rom + N8 YABYU560.ROM Yab Yum (Netherlands).rom + Y YELLO561.ROM Yellow Submarine (Japan).rom + Y YIEAR562.ROM Yie Ar Kung-Fu (Japan).rom + N4 YIEAR563.ROM Yie Ar Kung-Fu II - The Emperor Yie-Gah (Japan).rom + YP YOKAI564.ROM Yokai Tanken Chimachima (Japan).rom + Y ZAIDE566.ROM Zaider - Battle of Peguss (Japan).rom + Y ZANAC567.ROM Zanac (Japan) (v2).rom + Y ZANAC568.ROM Zanac (Japan).rom + Y ZAXXO569.ROM Zaxxon (Japan).rom + N0 ZENJI570.ROM Zenji (Japan).rom + Y ZEXAS571.ROM Zexas Limited (Japan).rom + Y ZOOM9572.ROM Zoom 909 (Japan).rom +================= TESTED ALL ABOVE ================= diff --git a/Source/Images/d_msxroms2/ReadMe.txt b/Source/Images/d_msxroms2/ReadMe.txt new file mode 100644 index 00000000..be48416a --- /dev/null +++ b/Source/Images/d_msxroms2/ReadMe.txt @@ -0,0 +1,19 @@ +===== MSX ROMs Disk for RomWBW ===== + +This is disk 2 of 2 of the collection of MSX ROMs as provided by Les +Bird (ROM filenames L-Z). These ROMs are "run" by using the +appropriate variant of Les' MSX8 ROM loader. You can download the +loader binaries from https://github.com/lesbird/MSX8. You will need +appropriate hardware to run the loader. + +Please review the file ROMLIST.TXT for information on the current +operational status of the ROM and it's long file name/description. + +This disk (RomWBW slice) is not automatically included with the +RomWBW "combo" disk images. You can simply add it to a combo +image by appending it to the end. After booting your system, +you can use the ASSIGN command to map the slice to a drive letter. +Refer to the RomWBW User Guide for more information on this +process. + +-- WBW 11:15 AM 8/21/2024 diff --git a/Source/Images/d_msxroms2/u0/LADDE313.ROM b/Source/Images/d_msxroms2/u0/LADDE313.ROM new file mode 100644 index 00000000..019fe244 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LADDE313.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LAPTI314.ROM b/Source/Images/d_msxroms2/u0/LAPTI314.ROM new file mode 100644 index 00000000..9f8cb850 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LAPTI314.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LEMAN315.ROM b/Source/Images/d_msxroms2/u0/LEMAN315.ROM new file mode 100644 index 00000000..e56f0232 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LEMAN315.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LEONA317.ROM b/Source/Images/d_msxroms2/u0/LEONA317.ROM new file mode 100644 index 00000000..2c32d4d2 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LEONA317.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LODER319.ROM b/Source/Images/d_msxroms2/u0/LODER319.ROM new file mode 100644 index 00000000..088e5890 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LODER319.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LODER320.ROM b/Source/Images/d_msxroms2/u0/LODER320.ROM new file mode 100644 index 00000000..ed6bfb99 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LODER320.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LORDO321.ROM b/Source/Images/d_msxroms2/u0/LORDO321.ROM new file mode 100644 index 00000000..add678c5 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LORDO321.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LOTLO322.ROM b/Source/Images/d_msxroms2/u0/LOTLO322.ROM new file mode 100644 index 00000000..8e261c7a Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LOTLO322.ROM differ diff --git a/Source/Images/d_msxroms2/u0/LUNAR323.ROM b/Source/Images/d_msxroms2/u0/LUNAR323.ROM new file mode 100644 index 00000000..e521957e Binary files /dev/null and b/Source/Images/d_msxroms2/u0/LUNAR323.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MACAT325.ROM b/Source/Images/d_msxroms2/u0/MACAT325.ROM new file mode 100644 index 00000000..e27a9947 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MACAT325.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MACHI326.ROM b/Source/Images/d_msxroms2/u0/MACHI326.ROM new file mode 100644 index 00000000..0da315b1 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MACHI326.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MACRO327.ROM b/Source/Images/d_msxroms2/u0/MACRO327.ROM new file mode 100644 index 00000000..c4e0fbc6 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MACRO327.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MAGIC328.ROM b/Source/Images/d_msxroms2/u0/MAGIC328.ROM new file mode 100644 index 00000000..a61f859f Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MAGIC328.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MAGIC329.ROM b/Source/Images/d_msxroms2/u0/MAGIC329.ROM new file mode 100644 index 00000000..dca241dd Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MAGIC329.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MANES331.ROM b/Source/Images/d_msxroms2/u0/MANES331.ROM new file mode 100644 index 00000000..86473760 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MANES331.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MAPPY332.ROM b/Source/Images/d_msxroms2/u0/MAPPY332.ROM new file mode 100644 index 00000000..54e5a534 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MAPPY332.ROM differ diff --git a/Source/Images/d_msxroms2/u0/MARIN334.ROM b/Source/Images/d_msxroms2/u0/MARIN334.ROM new file mode 100644 index 00000000..d7ae4d8f Binary files /dev/null and b/Source/Images/d_msxroms2/u0/MARIN334.ROM differ diff --git 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00000000..1a867a7d Binary files /dev/null and b/Source/Images/d_msxroms2/u0/PITFA416.ROM differ diff --git a/Source/Images/d_msxroms2/u0/PLAYB417.ROM b/Source/Images/d_msxroms2/u0/PLAYB417.ROM new file mode 100644 index 00000000..84b9646d Binary files /dev/null and b/Source/Images/d_msxroms2/u0/PLAYB417.ROM differ diff --git a/Source/Images/d_msxroms2/u0/POINY418.ROM b/Source/Images/d_msxroms2/u0/POINY418.ROM new file mode 100644 index 00000000..1507ec77 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/POINY418.ROM differ diff --git a/Source/Images/d_msxroms2/u0/POLIC419.ROM b/Source/Images/d_msxroms2/u0/POLIC419.ROM new file mode 100644 index 00000000..4c1577cf Binary files /dev/null and b/Source/Images/d_msxroms2/u0/POLIC419.ROM differ diff --git a/Source/Images/d_msxroms2/u0/POOYA420.ROM b/Source/Images/d_msxroms2/u0/POOYA420.ROM new file mode 100644 index 00000000..7583d86f Binary files /dev/null and b/Source/Images/d_msxroms2/u0/POOYA420.ROM differ diff --git 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00000000..750db47e Binary files /dev/null and b/Source/Images/d_msxroms2/u0/PUZZL427.ROM differ diff --git a/Source/Images/d_msxroms2/u0/PYRAM428.ROM b/Source/Images/d_msxroms2/u0/PYRAM428.ROM new file mode 100644 index 00000000..dcc28930 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/PYRAM428.ROM differ diff --git a/Source/Images/d_msxroms2/u0/QBERT429.ROM b/Source/Images/d_msxroms2/u0/QBERT429.ROM new file mode 100644 index 00000000..dc5ae0f9 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/QBERT429.ROM differ diff --git a/Source/Images/d_msxroms2/u0/QUEEN430.ROM b/Source/Images/d_msxroms2/u0/QUEEN430.ROM new file mode 100644 index 00000000..6b704611 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/QUEEN430.ROM differ diff --git a/Source/Images/d_msxroms2/u0/RAIDO432.ROM b/Source/Images/d_msxroms2/u0/RAIDO432.ROM new file mode 100644 index 00000000..bc7b4bb1 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/RAIDO432.ROM differ diff --git a/Source/Images/d_msxroms2/u0/RALLY433.ROM b/Source/Images/d_msxroms2/u0/RALLY433.ROM new file mode 100644 index 00000000..7feac636 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/RALLY433.ROM differ diff --git a/Source/Images/d_msxroms2/u0/RAMBO434.ROM b/Source/Images/d_msxroms2/u0/RAMBO434.ROM new file mode 100644 index 00000000..c30e35cf Binary files /dev/null and b/Source/Images/d_msxroms2/u0/RAMBO434.ROM differ diff --git a/Source/Images/d_msxroms2/u0/REALT435.ROM b/Source/Images/d_msxroms2/u0/REALT435.ROM new file mode 100644 index 00000000..e7793ee1 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/REALT435.ROM differ diff --git a/Source/Images/d_msxroms2/u0/REDZO436.ROM b/Source/Images/d_msxroms2/u0/REDZO436.ROM new file mode 100644 index 00000000..fe07529b Binary files /dev/null and b/Source/Images/d_msxroms2/u0/REDZO436.ROM differ diff --git a/Source/Images/d_msxroms2/u0/RENJU438.ROM b/Source/Images/d_msxroms2/u0/RENJU438.ROM new file mode 100644 index 00000000..99f58d4a Binary files /dev/null and b/Source/Images/d_msxroms2/u0/RENJU438.ROM differ diff --git a/Source/Images/d_msxroms2/u0/RISEO439.ROM b/Source/Images/d_msxroms2/u0/RISEO439.ROM new file mode 100644 index 00000000..a9358238 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/RISEO439.ROM differ diff --git a/Source/Images/d_msxroms2/u0/RIVER440.ROM b/Source/Images/d_msxroms2/u0/RIVER440.ROM new file mode 100644 index 00000000..4aecab8e Binary files /dev/null and b/Source/Images/d_msxroms2/u0/RIVER440.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ROADF441.ROM b/Source/Images/d_msxroms2/u0/ROADF441.ROM new file mode 100644 index 00000000..af30c3a1 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ROADF441.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ROBOF443.ROM b/Source/Images/d_msxroms2/u0/ROBOF443.ROM new file mode 100644 index 00000000..fa280613 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ROBOF443.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ROCKN444.ROM b/Source/Images/d_msxroms2/u0/ROCKN444.ROM new file mode 100644 index 00000000..48ea0181 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ROCKN444.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ROGER445.ROM b/Source/Images/d_msxroms2/u0/ROGER445.ROM new file mode 100644 index 00000000..3873d35f Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ROGER445.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ROLLE446.ROM b/Source/Images/d_msxroms2/u0/ROLLE446.ROM new file mode 100644 index 00000000..70e84e2a Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ROLLE446.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ROMLIST.TXT b/Source/Images/d_msxroms2/u0/ROMLIST.TXT new file mode 100644 index 00000000..9bbaed80 --- /dev/null +++ b/Source/Images/d_msxroms2/u0/ROMLIST.TXT @@ -0,0 +1,495 @@ +379 LOADING GAMES OUT OF 481 ROMS + +Some require keyboard support and/or 2 joystick buttons. They are marked with a '?' in the list below +Some require the patcher (MSX8P.COM). They are marked with a 'P' in the list below +Some don't work at all. They are marked with a 'N' in the list below + +Y = (271) WORKS +YP= ( 55) USE MSX8P (PATCHER VERSION NEEDED DUE TO DIRECT VDP/PSG WRITES INSTEAD OF GOING THROUGH THE BIOS) +? = ( 53) RUNS BUT NOT PLAYABLE - POSSIBLY REQUIRES TWO BUTTON JOYSTICK OR UNSUPPORTED KEYBOARD CONTROLS +N = DOES NOT WORK + +STAT SHORT NAME LONG NAME (481 ROMS) +==== ============ ============================================ + Y 10YAR000.ROM 10-Yard Fight (Japan).rom + N0 3DGOL002.ROM 3-D Golf Simulation (Japan) (High Speed).rom + N0 3DGOL003.ROM 3-D Golf Simulation (Japan).rom + N0 3DTEN004.ROM 3D Tennis (Japan).rom + Y ACTMA007.ROM Actman (Japan).rom + Y ADVEN008.ROM Adven' Chuta! (Japan).rom + Y AEJAP005.ROM A.E. (Japan).rom + Y? ALBAT009.ROM Albatros (Japan).rom + NP8 ALCAZ010.ROM Alcazar - The Forgotten Fortress (Japan).rom + YP ALIBA011.ROM Alibaba and 40 Thieves (Japan).rom + YP ALIEN012.ROM Alien 8 (Japan).rom + YP? ALPHA014.ROM Alpha Roid (Japan).rom + YP ALPHA015.ROM Alpha Squadron (Japan).rom + Y AMERI016.ROM American Truck (Japan).rom + YP ANAZA017.ROM Anaza - Kaleidoscope Special (Japan).rom + Y? ANGEL018.ROM Angelo (Japan).rom + Y ANTAR020.ROM Antarctic Adventure (Europe).rom + YP ANTAR021.ROM Antarctic Adventure (Japan).rom + YP ANTYJ022.ROM Anty (Japan).rom + Y AQUAP023.ROM Aqua Polis SOS (Japan).rom + N4 AQUAT024.ROM Aquattack (Japan).rom + Y ARAMO025.ROM Aramo (Japan).rom + YP ARKAN026.ROM Arkanoid (Japan).rom + Y ATHLE027.ROM Athletic Ball (Japan).rom + N ATHLE028.ROM Athletic Land (Japan) (Beta).rom + YP ATHLE029.ROM Athletic Land (Japan).rom + Y ATTAC030.ROM Attack Four Volley Ball (Japan).rom + N4 BACKG032.ROM Back Gammon (Japan).rom + Y BACKG034.ROM Backgammon (Europe).rom + Y BACKT033.ROM Back to the Future (Japan).rom + YP BALAN035.ROM Balance (Japan).rom + Y BANAN036.ROM Banana (Japan).rom + Y BANKP037.ROM Bank Panic (Japan).rom + N5 BASIC038.ROM Basic Lessons 1 (Japan).rom + N BASIC039.ROM Basic Lessons 2 (Japan).rom + N4 BATTE041.ROM Batten Tanuki no Daibouken (Japan) (v1.03).rom + Y BATTL042.ROM Battle Cross (Japan).rom + Y BATTL043.ROM Battleship Clapton II (Japan).rom + Y BCSQU031.ROM B.C.'s Quest (Japan).rom + Y BEACH044.ROM Beach-Head (Europe).rom + N0 BEAMR045.ROM Beam Rider (Japan).rom + Y BECKY046.ROM Becky (Japan).rom + Y BEEFL047.ROM Bee & Flower (Japan).rom + Y BIFAM048.ROM Bifamu (Japan).rom + Y BINAR049.ROM Binary Land (Japan).rom + Y BLACK051.ROM Black Onyx, The (Japan).rom + Y? BLAGG052.ROM Blagger MSX (Europe) (Converted From Tape).rom + YP BLOCK053.ROM Block Hole (Korea) (Unl).rom + Y BLOCK054.ROM Blockade Runner (Japan).rom + Y BOGGY055.ROM Boggy '84 (Japan).rom + Y BOING056.ROM Boing Boing (Spain).rom + N8 BOKOS057.ROM Bokosuka Wars (Japan).rom + Y BOMBE059.ROM Bomber Man (Japan).rom + Y BOMBE060.ROM Bomber Man Special (Japan).rom + Y BOOGI061.ROM Boogie Woogi Jungle (Japan).rom + Y? BOOME062.ROM Boomerang (Japan).rom + Y BOSCO064.ROM Bosconian (Japan).rom + Y BOUKE065.ROM Bouken Roman - Dota (Japan).rom + Y BOULD066.ROM Boulder Dash (Japan).rom + Y BOUNC067.ROM Bouncing Block (Spain).rom + N0 BRAIN068.ROM Brain, The (Japan).rom + N0 BREAK070.ROM Break Out (Japan).rom + Y BROTH071.ROM Brother Adventure (Korea) (Unl).rom + Y BRUCE072.ROM Bruce Lee (Japan).rom + YP BUBBL073.ROM Bubble Bobble (Korea) (Unl).rom + N0 BURGE074.ROM Burgertime (Japan).rom + Y BURUT075.ROM Buru To Marty Kikiippatsu - Inspecteur Z (Japan).rom + Y BUTAM076.ROM Butam Pants (Japan).rom + Y CABBA078.ROM Cabbage Patch Kids (Japan).rom + YP? CANDO079.ROM Candoo Ninja (Japan).rom + Y CANNO080.ROM Cannon Ball (Japan).rom + Y CANNO081.ROM Cannon Fighter (Japan).rom + Y CAPTA082.ROM Captain Chef (Japan).rom + Y CARFI083.ROM Car Fighter (Japan).rom + YP CARJA084.ROM Car Jamboree (Japan).rom + Y CARRA085.ROM Car-Race (Japan).rom + Y CASIO086.ROM Casio Daishogai Keiba (Japan).rom + Y CASIO087.ROM Casio Pachinko-U.F.O. (Japan).rom + Y CASIO088.ROM Casio Ski Command (Japan).rom + Y CASIO089.ROM Casio Worldopen (Japan).rom + Y CASTL090.ROM Castle Excellent (Japan).rom + Y CASTL091.ROM Castle, The (Japan).rom + Y CHACK092.ROM Chack'n Pop (Japan).rom + Y CHALL093.ROM Challenge Derby (Japan).rom + Y CHAMP094.ROM Champion Boxing (Japan).rom + Y? CHAMP095.ROM Champion Ice Hockey (Japan).rom + Y CHAMP096.ROM Champion Kendou (Japan).rom + Y CHAMP097.ROM Champion Pro Wrestling (Japan).rom + Y CHAMP098.ROM Champion Soccer (Japan).rom + Y CHAMP099.ROM Championship Lode Runner (Japan).rom + Y? CHECK100.ROM Checkers in Tantan Tanuki (Japan).rom + NP4 CHESS101.ROM Chess (Japan).rom + NP4 CHESS102.ROM Chess Game, The (Europe).rom + Y CHOPL103.ROM Choplifter (Japan).rom + YP CHORO104.ROM Choro Q (Japan).rom + N4 CHUGA105.ROM Chugaku Hisshu Eibunpo 1 (Japan).rom + Y CIRCU106.ROM Circus Charlie (Japan).rom + Y CITYC107.ROM City Connection (Japan).rom + YP COAST108.ROM Coaster Race (Japan).rom + Y COLOR109.ROM Color Ball (Japan).rom + N0 COLUM110.ROM Columns (Japan).rom + Y COMEC112.ROM Comecocos (Spain).rom + YP COMEO111.ROM Come On! Picot (Japan).rom + N0 COMET113.ROM Comet Tail (Japan).rom + Y COMIC114.ROM Comic Bakery (Japan).rom + YP COMPU115.ROM Computer Billiards (Japan).rom + NP4 COMPU116.ROM Computer Nyuumon - Computer Lessons (Japan).rom + NP5 COMPU117.ROM Computer Othello (Japan).rom + YP COMPU118.ROM Computer Pachinko (Japan).rom + Y CONDO119.ROM Con-Dori (Japan).rom + N8 COSMO121.ROM Cosmo (Japan).rom + Y COSMO122.ROM Cosmo-Explorer (Japan).rom + N0 COURA123.ROM Courageous Perseus (Japan).rom + N0 CRAZY125.ROM Crazy Bullet (Japan).rom + Y CRAZY126.ROM Crazy Cars (Europe).rom + N0 CRAZY127.ROM Crazy Train (Japan).rom + Y CRUSA129.ROM Crusader (Japan).rom + N4 CSOJA077.ROM C-So! (Japan).rom + N4 DAIDA131.ROM Daidasso (Japan).rom + Y DAMBU133.ROM Dam Busters, The (Japan).rom + N0 DANGE134.ROM Danger X4 (Japan).rom + Y DAVID135.ROM David II (Japan).rom + Y DDAYJ130.ROM D-Day (Japan).rom + N0 DECAT137.ROM Decathlon (Japan).rom + N0 DEMON140.ROM Demon Crystal, The (Japan).rom + Y DEVIL142.ROM Devil's Heaven (Japan).rom + Y DIGDU143.ROM Dig Dug (Japan).rom + YP DIPDI145.ROM Dip Dip (Spain).rom + Y DOKID146.ROM Doki Doki Penguin Land (Japan).rom + Y DOORD147.ROM Doordoor (Japan).rom + N4 DOROD148.ROM Dorodon (Japan).rom + YP DOUBL149.ROM Double Dragon (Korea) (Unl).rom + Y? DRCOP150.ROM Dr. Copy (Japan).rom + Y DRAGO151.ROM Dragon Attack (Japan).rom + Y DRAGO154.ROM Dragon Slayer (Japan).rom + YP DRAIN158.ROM Drainer (Japan).rom + Y DRUAG159.ROM Druaga no Tou (Japan).rom + Y? DUNGE161.ROM Dungeon Master (Japan).rom + Y DUNKS162.ROM Dunk Shot (Japan).rom + NF EAGLE164.ROM Eagle Fighter (Japan).rom + N4 EGGER165.ROM Eggerland Mystery (Japan).rom + Y ELEVA166.ROM Elevator Action (Japan).rom + Y? ERIKA167.ROM Erika (Japan).rom + Y EXAIN168.ROM Exa Innova (Japan).rom + N0 EXCHA169.ROM Exchanger (Japan).rom + Y EXERI170.ROM Exerion (Japan).rom + Y EXERI171.ROM Exerion II - Zorni (Japan).rom + YP EXOID172.ROM Exoide-Z (Japan).rom + Y EXOID173.ROM Exoide-Z Area 5 (Japan).rom + N8 F16FI175.ROM F16 Fighting Falcon (Japan).rom + Y FAIRY177.ROM Fairy (Japan).rom + YP FATET176.ROM Fa Tetris (Korea) (Unl).rom + Y FATHO183.ROM Fathom (Japan).rom + Y FINAL184.ROM Final Justice (Japan).rom + Y FINAL185.ROM Final Mahjong (Japan).rom + Y FIRER187.ROM Fire Rescue (Japan).rom + Y FLAPP188.ROM Flappy (Japan).rom + Y FLAPP189.ROM Flappy - Limited 85 (Japan).rom + YP? FLASH190.ROM Flash Point (Korea) (Unl).rom + Y FLASH191.ROM Flash Splash (Japan).rom + Y FLICK192.ROM Flicky (Japan).rom + Y FLICS193.ROM Flics, Les (France).rom + Y FLIPP196.ROM Flipper Slipper (Japan).rom + Y FORMA197.ROM Formation Z (Japan).rom + YP FROGG198.ROM Frogger (Japan).rom + Y FRONT199.ROM Front Line (Japan).rom + Y FRUIT200.ROM Fruit Search (Japan).rom + Y FUNKY201.ROM Funky Mouse (Japan).rom + N8 FUTBO202.ROM Futbol (Spain).rom + Y FUUNT203.ROM Fuun Takeshijyou (Japan).rom + Y GALAG204.ROM Galaga (Japan).rom + Y GALAX205.ROM Galaxian (Japan).rom + N0 GAMEL208.ROM Game Land (Japan).rom + Y? GAMEM209.ROM Game Master (Europe).rom + Y? GAMEM210.ROM Game Master (Japan).rom + N0 GANGM213.ROM Gang Master (Japan).rom + YP GHOST216.ROM Ghostbusters (Europe).rom + Y? GLIDE217.ROM Glider (Japan).rom + Y GOKIB218.ROM Gokiburi Daisakusen - Bug Bomb (Japan).rom + N0 GOLFG219.ROM Golf Game (Japan).rom + YP? GOMOK221.ROM Gomok Narabe - Omo Go (Japan).rom + Y GOONI222.ROM Goonies, The (Japan).rom + Y GPWOR223.ROM GP World (Japan).rom + N9 GREEN224.ROM Green Beret (Europe).rom + Y GROGS225.ROM Grog's Revenge (Japan).rom + Y GUARD226.ROM Guardic (Japan).rom + Y GULKA227.ROM Gulkave (Japan).rom + YP GUNFR228.ROM Gun Fright (Japan).rom + Y GUNJI229.ROM Gunjin Shougi Mars (Japan).rom + YP GYROD230.ROM Gyrodine (Japan).rom + N0 HEROJ231.ROM H.E.R.O. (Japan).rom + Y HADES232.ROM Hades no Monsho (Japan).rom + Y HAFAN233.ROM Hafanuda Koi Koi - Gostop Godori (Japan).rom + YP HANAF235.ROM Hanafuta (Japan).rom + Y HANGO236.ROM Hang-On (Japan).rom + Y HARAP237.ROM Harapeko Pakkun (Japan).rom + Y HAUNT240.ROM Haunted Boynight (Japan).rom + Y HEAVY241.ROM Heavy Boxing (Japan).rom + Y HEIST242.ROM Heist, The (Japan).rom + Y HELIT243.ROM Helitank (Japan).rom + Y HIGHW244.ROM High Way Star (Japan).rom + Y HIGHW245.ROM High Way Star (Korea).rom + YP? HISYA246.ROM Hisya (Japan).rom + Y HITSU247.ROM Hitsuji Yai - Preety Sheep (Japan).rom + Y HOLEI248.ROM Hole in One (Japan).rom + Y? HOLEI249.ROM Hole in One Professional (Japan).rom + Y HONKB250.ROM Honkball (Japan).rom + YP HOPPE251.ROM Hopper (Europe).rom + Y? HUDSO252.ROM Hudson 3D Golf (Japan).rom + Y HUSTL253.ROM Hustle! Chumy (Japan).rom + Y HYDLI254.ROM Hydlide (Japan).rom + Y HYPER257.ROM Hyper Olympic 1 (Japan).rom + Y HYPER258.ROM Hyper Olympic 2 (Japan).rom + Y? HYPER259.ROM Hyper Rally (Japan).rom + Y HYPER260.ROM Hyper Sports 1 (Japan).rom + Y HYPER261.ROM Hyper Sports 2 (Japan).rom + N4 HYPER262.ROM Hyper Sports 3 (Japan).rom + Y ICEWO263.ROM Ice World (Japan).rom + Y IGANI264.ROM Iga Ninpouten - Small Ninja (Japan).rom + Y IGANI265.ROM Iga Ninpouten 2 - Small Ninja 2 (Japan).rom + Y INDIA266.ROM Indian no Bouken (Japan).rom + N0 IRIEG267.ROM Iriegas (Japan).rom + Y IRIEG268.ROM Iriegas - Theseus (Japan).rom + Y ISSUN269.ROM Issunhoushi No Donnamondai (Japan).rom + Y JPWIN270.ROM J.P. Winkle (Japan).rom + Y JANKA272.ROM Janka (Japan).rom + Y JETSE273.ROM Jet Set Willy (Japan).rom + Y JIGSA274.ROM Jigsaw Set (Japan).rom + Y JISSE275.ROM Jissen - 4-nin Mahjong (Japan).rom + Y JUMPJ276.ROM Jump (Japan).rom + Y JUMPC277.ROM Jump Coaster (Japan).rom + YP JUMPL278.ROM Jump Land (Japan).rom + Y JUMPI279.ROM Jumping Rabbit (Japan).rom + N0 JUNOF280.ROM Juno First (Japan).rom + Y JYANF281.ROM Jyan Friend (Japan).rom + Y JYANK282.ROM Jyankyo (Japan).rom + Y JYANY283.ROM Jyanyuu (Japan).rom + N4 KAGEN284.ROM Kage no Densetsu - Legend of Kage, The (Japan).rom + N0 KARAM285.ROM Karamaru (Japan).rom + N0 KEYST287.ROM Keystone Kapers (Japan).rom + YP KICKI288.ROM Kick It (Japan).rom + Y KINAS289.ROM Kinasai (Japan) (Unl).rom + Y KINGB290.ROM King & Balloon (Japan).rom + Y KINGS292.ROM King's Valley (Japan, Europe).rom + Y KINNI294.ROM Kinnikuman - Muscle Man (Japan).rom + YP KNIGH295.ROM Knight Lore (Japan).rom + Y KNIGH296.ROM Knightmare - Majou Densetsu (Japan).rom + Y KONAM300.ROM Konami's Baseball (Japan).rom + Y KONAM301.ROM Konami's Billiards (Europe).rom + Y KONAM302.ROM Konami's Boxing (Japan).rom + N4 KONAM303.ROM Konami's Football (Europe).rom + N4 KONAM304.ROM Konami's Golf (Japan).rom + Y? KONAM305.ROM Konami's Mahjong (Japan).rom + Y? KONAM306.ROM Konami's Ping-Pong (Japan).rom + N4 KONAM307.ROM Konami's Soccer (Japan).rom + Y KONAM308.ROM Konami's Tennis (Japan).rom + Y KONEK309.ROM Koneko no Daibouken - Catboy (Japan).rom + Y KUNGF310.ROM Kung Fu Acho (Japan).rom + Y KUNGF311.ROM Kung Fu Master (Japan).rom + Y KUNGF312.ROM Kung Fu Taigun (Japan).rom + N0 LADDE313.ROM Ladder Building (Japan).rom + YP LAPTI314.ROM Laptick 2 (Japan).rom + Y LEMAN315.ROM Le Mans 2 (Europe).rom + N8 LEONA317.ROM Leonard (Spain).rom + Y LODER319.ROM Lode Runner (Japan).rom + Y LODER320.ROM Lode Runner II (Japan).rom + N0 LORDO321.ROM Lord Over (Japan).rom + N3 LOTLO322.ROM Lot Lot (Japan).rom + Y LUNAR323.ROM Lunar Ball (Japan).rom + N7 MACAT325.ROM Mac Attack (Europe).rom + Y MACHI326.ROM Machinegun Joe vs The Mafia (Japan).rom + Y MACRO327.ROM Macross (Japan).rom + Y MAGIC328.ROM Magical Kid Wiz (Japan).rom + Y MAGIC329.ROM Magical Tree (Japan).rom + Y MANES331.ROM Manes (Japan).rom + Y MAPPY332.ROM Mappy (Japan).rom + N0 MARIN334.ROM Marine Battle (Japan).rom + YP? MARSI335.ROM Mars II (Japan).rom + Y? MASTE337.ROM Master Chess (Europe).rom + Y MEGAL338.ROM Megalopolis SOS (Japan).rom + Y? MIDNI340.ROM Midnight Brothers (Japan).rom + Y? MIDNI341.ROM Midnight Building (Japan).rom + Y? MIDWA342.ROM Midway (Japan).rom + Y? MILCA343.ROM Mil Caras (Spain).rom + Y MINIG344.ROM Mini Golf (Japan).rom + Y MOAIN347.ROM Moai no Hibou (Japan).rom + Y MOBIL348.ROM Mobile Planet Suthirus - Approach from the Westgate (Japan).rom + Y MOBIL349.ROM Mobile-Suit Gundam - Last Shooting (Japan).rom + YP MOKAR350.ROM Mokarimakka (Japan).rom + N0 MOLEJ351.ROM Mole (Japan).rom + Y? MOLEM352.ROM Mole Mole 2 (Japan).rom + YP? MONKE353.ROM Monkey Academy (Japan).rom + Y MONST354.ROM Monster's Fair (Japan).rom + N0 MOONL355.ROM Moon Landing (Japan).rom + Y MOONP356.ROM Moon Patrol (Japan).rom + Y MOONS357.ROM Moonsweeper (Japan).rom + N4 MOPIR358.ROM Mopiranger (Japan).rom + NC MORIT359.ROM Morita Kazuo no Othello (Japan).rom + YP? MOUSE360.ROM Mouser (Japan).rom + Y MRCHI361.ROM Mr. Chin (Japan).rom + Y? MRDOJ362.ROM Mr. Do (Japan).rom + Y MRDOS364.ROM Mr. Do's Wild Ride (Japan).rom + Y MRDOV363.ROM Mr. Do vs Unicorns (Japan).rom + N0 MSX21365.ROM MSX 21 (Japan).rom + Y MSXBA366.ROM MSX Baseball (Japan).rom + Y MSXBA367.ROM MSX Baseball II National (Japan).rom + N0 MSXDE368.ROM MSX Derby (Japan).rom + Y MSXRU369.ROM MSX Rugby (Japan).rom + Y MSXSO370.ROM MSX Soccer (Japan).rom + N0 NAUSI372.ROM Nausicaa (Japan).rom + Y NESSE378.ROM Nessen Koushiyen (Japan).rom + YP NIGHT379.ROM Night Shade (Japan).rom + Y NINJA380.ROM Ninja Jajamaru-kun (Japan).rom + YP NINJA381.ROM Ninja Princess (Japan).rom + Y NINJA382.ROM Ninjakun (Japan).rom + Y NINJA383.ROM Ninjakun Majou (Japan).rom + Y NINJY384.ROM Ninjya Kage (Japan).rom + Y? NYANN386.ROM Nyan Nyan Pro Wrestling (Japan).rom + Y NYORO387.ROM Nyorols (Japan).rom + Y OILSW389.ROM Oil's Well (Japan).rom + Y? OKAMI390.ROM Okami no Su (Japan).rom + Y OMACF388.ROM O'Mac Farmer (Japan).rom + Y OTHEL391.ROM Othello (Japan).rom + Y OYOID392.ROM Oyoide Tango (Japan).rom + Y PACHI394.ROM Pachi Com (Japan).rom + Y PACMA393.ROM Pac-Man (Japan).rom + Y PAIPA395.ROM Pai Panic (Japan).rom + N0 PAIRS396.ROM Pairs (Japan).rom + Y PANTH397.ROM Panther (Japan).rom + N0 PASSB399.ROM Pass Ball (Japan).rom + YP? PASTF400.ROM Pastfinder (Japan).rom + Y? PAYLO401.ROM Pay Load (Japan).rom + Y PEETA402.ROM Peetan (Japan).rom + Y PEGAS403.ROM Pegasus (Japan).rom + Y PENGU405.ROM Penguin-kun Wars (Japan).rom + YP? PICOP406.ROM Pico Pico (Japan).rom + Y PICTU407.ROM Picture Puzzle (Japan).rom + Y? PILLB408.ROM Pillbox (Japan).rom + Y? PINEA410.ROM Pine Applin (Japan).rom + YP? PINGB411.ROM Pingball Maker (Japan).rom + YP PINKY412.ROM Pinky Chase (Japan).rom + Y PIPIJ413.ROM Pipi (Japan).rom + Y PIPPO414.ROM Pippols (Japan).rom + YP PITFA415.ROM Pitfall II - Lost Caverns (Japan).rom + NP8 PITFA416.ROM Pitfall! (Japan).rom + Y PLAYB417.ROM Play Ball (Japan).rom + N4 POINY418.ROM Poiny X Senryosakusen - Operation Thanksgiving (Japan).rom + Y POLIC419.ROM Police Story, The (Japan).rom + YP POOYA420.ROM Pooyan (Japan).rom + Y POPPA421.ROM Poppaq the Fish (Japan).rom + N4 PROFE423.ROM Professional Baseball (Japan).rom + YP? PROFE424.ROM Professional Mahjong (Japan).rom + Y PROTE425.ROM Protector, The (Japan).rom + Y PUZZL427.ROM Puzzle Panic (Japan).rom + Y PYRAM428.ROM Pyramid Warp (Japan).rom + Y QBERT429.ROM Q-bert (Japan).rom + Y QUEEN430.ROM Queen's Golf (Japan).rom + Y RAIDO432.ROM Raid on Bungeling Bay (Japan).rom + Y RALLY433.ROM Rally-X (Japan).rom + YP? RAMBO434.ROM Rambo (Japan).rom + YP? REALT435.ROM Real Tennis (Japan).rom + Y REDZO436.ROM Red Zone (Japan).rom + N0 RENJU438.ROM Renju & Ojama Dogs (Japan).rom + Y RISEO439.ROM Rise Out from Dungeons (Japan).rom + N0 RIVER440.ROM River Raid (Japan).rom + Y ROADF441.ROM Road Fighter (Japan).rom + Y ROBOF443.ROM Robofrog (Japan).rom + NP8 ROCKN444.ROM Rock'n Bolt (Japan).rom + Y ROGER445.ROM Roger Rubbish (Europe).rom + Y? ROLLE446.ROM Roller Ball (Japan).rom + N0 ROTOR447.ROM Rotors (Japan).rom + YP SASAJ450.ROM Sasa (Japan).rom + Y? SAURU451.ROM Saurus Land (Japan).rom + Y SCARL452.ROM Scarlet 7 - The Mightiest Women (Japan).rom + Y SCION453.ROM Scion (Japan).rom + N0 SCOPE454.ROM Scope On - Fight in Space (Japan).rom + Y SCRAM455.ROM Scramble Eggs (Japan).rom + Y SEAHU456.ROM Sea Hunter (Europe).rom + Y SENJY458.ROM Senjyo (Japan).rom + N4 SEWER459.ROM Sewer Sam (Japan).rom + Y SHOUG460.ROM Shougi (Japan).rom + N4 SHOUG461.ROM Shougi 2 (Japan).rom + N0 SHOUG462.ROM Shougi Game (Japan).rom + Y SHOUG463.ROM Shougi Meijin (Japan).rom + Y SHOUG464.ROM Shougi Sinan 1 (Japan).rom + YP SHOUT465.ROM Shout Match (Japan).rom + YP SINBA466.ROM Sinbad (Japan).rom + YP SKOOT467.ROM Skooter (Japan).rom + Y SKYGA468.ROM Sky Galdo (Japan).rom + Y SKYJA469.ROM Sky Jaguar (Japan).rom + N8 SLAPS470.ROM Slapshot (Spain).rom + Y SNAKE471.ROM Snake It (Europe).rom + Y SOUKO473.ROM Soukoban (Japan).rom + Y SPACE474.ROM Space Camp (Japan).rom + Y SPACE475.ROM Space Invaders (Japan).rom + Y SPACE476.ROM Space Maze Attack (Japan).rom + Y SPACE477.ROM Space Trouble (Japan).rom + Y SPACE478.ROM Space Walk (Europe).rom + N0 SPARK479.ROM Sparkie (Japan).rom + Y SPELU480.ROM Spelunker (Japan).rom + N8 SPIDE481.ROM Spider, The (Japan).rom + Y SQUAR483.ROM Square Dancer (Japan).rom + Y SQUIS484.ROM Squish'em (Japan).rom + Y STARB485.ROM Star Blazer (Japan).rom + N0 STARC486.ROM Star Command (Japan).rom + Y STARF487.ROM Star Force (Japan).rom + Y STARS488.ROM Star Soldier (Japan).rom + Y? START489.ROM Star Trap (Japan).rom + Y? STARS490.ROM Starship Simulator (Japan).rom + Y STEPU491.ROM Step Up (Japan).rom + N8 STEPP492.ROM Stepper (Japan).rom + Y STONE493.ROM Stone of Wisdom, The (Japan).rom + N4 STRAN494.ROM Strange Loop (Japan).rom + Y SUPAR495.ROM Suparobo (Japan).rom + N0 SUPER496.ROM Super Billiards (Japan).rom + YP? SUPER499.ROM Super Boy I (Korea) (Unl).rom + YP? SUPER500.ROM Super Boy II (Korea) (Unl).rom + YP SUPER501.ROM Super Bubble Bobble (Korea) (Unl).rom + NP4 SUPER502.ROM Super Cobra (Japan).rom + YP SUPER503.ROM Super Columns (Japan).rom + YP SUPER504.ROM Super Cross Force (Europe).rom + Y SUPER505.ROM Super Drinker (Japan).rom + YP SUPER506.ROM Super Golf (Japan).rom + NP8 SUPER508.ROM Super Pachinko (Japan).rom + Y SUPER510.ROM Super Snake (Japan).rom + Y SUPER511.ROM Super Soccer (Japan).rom + Y SUPER512.ROM Super Tennis (Japan).rom + NP4 SUPER513.ROM Super Tripper (Spain).rom + YP SWEET514.ROM Sweet Acorn (Japan).rom + N4 SWING515.ROM Swing (Japan).rom + Y TANKB517.ROM Tank Battalion (Japan).rom + Y TATIC518.ROM Tatica (Japan).rom + Y TAWAR519.ROM Tawara-kun (Japan).rom + Y TEARO520.ROM Tear of Nile (Japan).rom + NP8 TELEB521.ROM Telebunnie (Japan).rom + Y TENSA522.ROM Tensai Rabbian Daifunsen (Japan).rom + Y? TENSI523.ROM Tensidachino Gogo (Japan).rom + YP TENSI524.ROM Tension (Spain).rom + NP8 TETRA525.ROM Tetra Horror (Japan).rom + Y TETRI526.ROM Tetris (Korea) (Unl).rom + NP8 TETSU527.ROM Tetsuman (Japan).rom + Y THEXD528.ROM Thexder (Japan).rom + Y? THUND529.ROM Thunder Ball (Japan).rom + N6 THUND530.ROM Thunderbolt (Japan).rom + YP TIMEP531.ROM Time Pilot (Japan).rom + YP TOPPL534.ROM Topple Zip (Japan).rom + Y TOPRO533.ROM Top Roller! (Japan).rom + Y TRACK535.ROM Track & Field 1 (Europe).rom + Y TRACK536.ROM Track & Field 2 (Europe).rom + Y TRAFF537.ROM Traffic (Japan).rom + N0 TRIAL538.ROM Trial Ski (Japan).rom + Y TRICK539.ROM Trick Boy (Japan).rom + YP TRITO540.ROM Tritorn (Japan).rom + N0 TRUMP541.ROM Trumpaid (Japan).rom + N8 TURBO543.ROM Turboat (Japan).rom + Y TWINB544.ROM Twin Bee (Japan).rom + YP TWINH545.ROM Twin Hammer (Europe).rom + Y TZRGR546.ROM TZR - Grand Prix Rider (Japan).rom + Y ULTRA547.ROM Ultraman (Japan).rom + YP? VENUS549.ROM Venus Fire (Japan).rom + NP4 VIDEO550.ROM Video Hustler (Japan).rom + Y VOLGU551.ROM Volguard (Japan).rom + Y WARPW552.ROM Warp & Warp (Japan).rom + YP WARRO553.ROM Warroid (Japan).rom + Y? WATER554.ROM Water Driver (Japan).rom + Y WONDE556.ROM Wonder Boy (Japan).rom + NP4 WRANG557.ROM Wrangler (Spain).rom + NP4 WRECK558.ROM Wreck, The (Europe).rom + YP XYXOL559.ROM Xyxolog (Japan).rom + N8 YABYU560.ROM Yab Yum (Netherlands).rom + Y YELLO561.ROM Yellow Submarine (Japan).rom + Y YIEAR562.ROM Yie Ar Kung-Fu (Japan).rom + N4 YIEAR563.ROM Yie Ar Kung-Fu II - The Emperor Yie-Gah (Japan).rom + YP YOKAI564.ROM Yokai Tanken Chimachima (Japan).rom + Y ZAIDE566.ROM Zaider - Battle of Peguss (Japan).rom + Y ZANAC567.ROM Zanac (Japan) (v2).rom + Y ZANAC568.ROM Zanac (Japan).rom + Y ZAXXO569.ROM Zaxxon (Japan).rom + N0 ZENJI570.ROM Zenji (Japan).rom + Y ZEXAS571.ROM Zexas Limited (Japan).rom + Y ZOOM9572.ROM Zoom 909 (Japan).rom +================= TESTED ALL ABOVE ================= diff --git a/Source/Images/d_msxroms2/u0/ROTOR447.ROM b/Source/Images/d_msxroms2/u0/ROTOR447.ROM new file mode 100644 index 00000000..f3cea3f2 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ROTOR447.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SASAJ450.ROM b/Source/Images/d_msxroms2/u0/SASAJ450.ROM new file mode 100644 index 00000000..28efe046 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SASAJ450.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SAURU451.ROM b/Source/Images/d_msxroms2/u0/SAURU451.ROM new file mode 100644 index 00000000..26838656 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SAURU451.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SCARL452.ROM b/Source/Images/d_msxroms2/u0/SCARL452.ROM new file mode 100644 index 00000000..7cc462cf Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SCARL452.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SCION453.ROM b/Source/Images/d_msxroms2/u0/SCION453.ROM new file mode 100644 index 00000000..cb6f9451 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SCION453.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SCOPE454.ROM b/Source/Images/d_msxroms2/u0/SCOPE454.ROM new file mode 100644 index 00000000..d26218ec Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SCOPE454.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SCRAM455.ROM b/Source/Images/d_msxroms2/u0/SCRAM455.ROM new file mode 100644 index 00000000..2ea77e05 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SCRAM455.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SEAHU456.ROM b/Source/Images/d_msxroms2/u0/SEAHU456.ROM new file mode 100644 index 00000000..3b3b0783 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SEAHU456.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SENJY458.ROM b/Source/Images/d_msxroms2/u0/SENJY458.ROM new file mode 100644 index 00000000..2ea1eb01 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SENJY458.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SEWER459.ROM b/Source/Images/d_msxroms2/u0/SEWER459.ROM new file mode 100644 index 00000000..52b08e5d Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SEWER459.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SHOUG460.ROM b/Source/Images/d_msxroms2/u0/SHOUG460.ROM new file mode 100644 index 00000000..7f798d9b Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SHOUG460.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SHOUG461.ROM b/Source/Images/d_msxroms2/u0/SHOUG461.ROM new file mode 100644 index 00000000..afb712e7 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SHOUG461.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SHOUG462.ROM b/Source/Images/d_msxroms2/u0/SHOUG462.ROM new file mode 100644 index 00000000..2d50bafd Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SHOUG462.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SHOUG463.ROM b/Source/Images/d_msxroms2/u0/SHOUG463.ROM new file mode 100644 index 00000000..dac21bb1 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SHOUG463.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SHOUG464.ROM b/Source/Images/d_msxroms2/u0/SHOUG464.ROM new file mode 100644 index 00000000..e2c706c8 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SHOUG464.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SHOUT465.ROM b/Source/Images/d_msxroms2/u0/SHOUT465.ROM new file mode 100644 index 00000000..dfb01c8d Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SHOUT465.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SINBA466.ROM b/Source/Images/d_msxroms2/u0/SINBA466.ROM new file mode 100644 index 00000000..1e9db136 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SINBA466.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SKOOT467.ROM b/Source/Images/d_msxroms2/u0/SKOOT467.ROM new file mode 100644 index 00000000..34839e19 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SKOOT467.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SKYGA468.ROM b/Source/Images/d_msxroms2/u0/SKYGA468.ROM new file mode 100644 index 00000000..21aecf06 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SKYGA468.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SKYJA469.ROM b/Source/Images/d_msxroms2/u0/SKYJA469.ROM new file mode 100644 index 00000000..974b3802 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SKYJA469.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SLAPS470.ROM b/Source/Images/d_msxroms2/u0/SLAPS470.ROM new file mode 100644 index 00000000..ed630e38 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SLAPS470.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SNAKE471.ROM b/Source/Images/d_msxroms2/u0/SNAKE471.ROM new file mode 100644 index 00000000..21f8728c Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SNAKE471.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SOUKO473.ROM b/Source/Images/d_msxroms2/u0/SOUKO473.ROM new file mode 100644 index 00000000..156842b8 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SOUKO473.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPACE474.ROM b/Source/Images/d_msxroms2/u0/SPACE474.ROM new file mode 100644 index 00000000..3c5262f7 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPACE474.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPACE475.ROM b/Source/Images/d_msxroms2/u0/SPACE475.ROM new file mode 100644 index 00000000..a8563ff0 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPACE475.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPACE476.ROM b/Source/Images/d_msxroms2/u0/SPACE476.ROM new file mode 100644 index 00000000..b4c298ff Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPACE476.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPACE477.ROM b/Source/Images/d_msxroms2/u0/SPACE477.ROM new file mode 100644 index 00000000..237d8d68 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPACE477.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPACE478.ROM b/Source/Images/d_msxroms2/u0/SPACE478.ROM new file mode 100644 index 00000000..5ff85c6a Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPACE478.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPARK479.ROM b/Source/Images/d_msxroms2/u0/SPARK479.ROM new file mode 100644 index 00000000..c7ff1e8d Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPARK479.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPELU480.ROM b/Source/Images/d_msxroms2/u0/SPELU480.ROM new file mode 100644 index 00000000..3f8113e5 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPELU480.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SPIDE481.ROM b/Source/Images/d_msxroms2/u0/SPIDE481.ROM new file mode 100644 index 00000000..c48d0587 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SPIDE481.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SQUAR483.ROM b/Source/Images/d_msxroms2/u0/SQUAR483.ROM new file mode 100644 index 00000000..02d888d8 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SQUAR483.ROM differ diff --git a/Source/Images/d_msxroms2/u0/SQUIS484.ROM b/Source/Images/d_msxroms2/u0/SQUIS484.ROM new file mode 100644 index 00000000..872f3be6 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/SQUIS484.ROM differ diff --git a/Source/Images/d_msxroms2/u0/STARB485.ROM b/Source/Images/d_msxroms2/u0/STARB485.ROM new file mode 100644 index 00000000..fa6f401e Binary files /dev/null and b/Source/Images/d_msxroms2/u0/STARB485.ROM differ diff --git a/Source/Images/d_msxroms2/u0/STARC486.ROM b/Source/Images/d_msxroms2/u0/STARC486.ROM new file mode 100644 index 00000000..21ee5f4e Binary files /dev/null and b/Source/Images/d_msxroms2/u0/STARC486.ROM differ diff --git a/Source/Images/d_msxroms2/u0/STARF487.ROM b/Source/Images/d_msxroms2/u0/STARF487.ROM new file mode 100644 index 00000000..d6a4e72b Binary files /dev/null and b/Source/Images/d_msxroms2/u0/STARF487.ROM differ diff --git a/Source/Images/d_msxroms2/u0/STARS488.ROM b/Source/Images/d_msxroms2/u0/STARS488.ROM new file mode 100644 index 00000000..4a9ebfe8 Binary files /dev/null and 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b/Source/Images/d_msxroms2/u0/ZENJI570.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ZEXAS571.ROM b/Source/Images/d_msxroms2/u0/ZEXAS571.ROM new file mode 100644 index 00000000..b671d99f Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ZEXAS571.ROM differ diff --git a/Source/Images/d_msxroms2/u0/ZOOM9572.ROM b/Source/Images/d_msxroms2/u0/ZOOM9572.ROM new file mode 100644 index 00000000..2dbcb313 Binary files /dev/null and b/Source/Images/d_msxroms2/u0/ZOOM9572.ROM differ diff --git a/Source/Images/d_nzcom/ReadMe.txt b/Source/Images/d_nzcom/ReadMe.txt index c6aa5604..e2b27ab7 100644 --- a/Source/Images/d_nzcom/ReadMe.txt +++ b/Source/Images/d_nzcom/ReadMe.txt @@ -1,4 +1,4 @@ -===== NZCOM Disk for RomWBW ===== +===== NZ-COM Disk for RomWBW ===== This disk is one of several ready-to-run disks provided with RomWBW. It contains NZ-COM, which is an implementation of the @@ -19,7 +19,7 @@ The primary documentation for NZ-COM is the "NZCOM Users Manual.pdf" document contained in the Doc/CPM directory of the RomWBW distribution. This document is a supplement to the primary documentation. Additionally, please review the file called RELEASE.NOT on this disk which contains -a variety of updates regarding the NZ-COM distribuition. +a variety of updates regarding the NZ-COM distribution. The starting point for the disk content was the final official release of NZ-COM which is generally available on the Internet. A minimal @@ -30,27 +30,24 @@ use the system effectively. == Usage == -NZCOM is not designed to load directly from the boot tracks of a +NZ-COM is not designed to load directly from the boot tracks of a disk. Instead, it expects to be loaded from an already running OS. This disk has been configured to boot using ZSDOS with a -PROFILE.SUB command file that automatically loads NZCOM. So, NZCOM +PROFILE.SUB command file that automatically loads NZ-COM. So, NZ-COM will load completely without any intervention, but you may notice -that ZSDOS loads first, then ZSDOS loads NZCOM. This is normal. - -There is no DIR command. Use SDZ or ZXD instead. +that ZSDOS loads first, then ZSDOS loads NZ-COM. This is normal. *** TODO: Date stamping *** == Notes == -NZCOM is distributed in an unconfigured state. The following was -done to create a minimal ready-to-run setup for RomWBW: +NZ-COM is distributed in an unconfigured state. The following was +done to create a ready-to-run setup for RomWBW: - Ran MKZCM and saved default configuration to NZCOM.ZCM and NZCOM.ENV. - Extract VT100 TCAP from Z3TCAP.LBR and saved it as TCAP.Z3T. - Created PROFILE.SUB to launch NZCOM at startup. - - Created empty STARTZCM.COM. - Original TCSELECT.COM was removed and replaced with a newer version from the Z3 files. - TCAP.LBR and Z3TCAP.TCP were removed and replaced with @@ -59,6 +56,20 @@ done to create a minimal ready-to-run setup for RomWBW: versions are provided from Common files. - Replaced ZRDOS with ZSDOS in NZCOM.LBR. The standalone ZRDOS.ZRL and ZSDOS.ZRL files were saved. + - Copied ARUNZ.COM to CMDRUN.COM + - Moved all configuration files to 14: per ZCPR3 conventions + - Moved all help and documentation files to 10: per ZCPR3 conventions + - Moved executables to 15: per ZCPR3 conventions + - Updated HELP.COM to search for help files in A10: instead of A15: + - Updated LBRHELP.COM to search for help files in A10: instead of A15: + - Updated STARTZCM with + ZPATH /C=A0:,$$:,A15: /D=A0:,A15: + NZCOM TCAP.Z3T + - Updated NZCOM.NDR in NZCOM.LBR with new directory names: + A 0: SYSTEM A 10: HELP A 14: CONFIG A 15: ROOT + - Moved DOCFILES.LBR to 10: + - Moved all TCJ files to 10: + - Added REN, SAVE, and SP commands to ALIAS.CMD The following additional customizations were also performed: @@ -73,9 +84,9 @@ The following additional customizations were also performed: - Z3LOC.COM - ZCNFG.COM -== NZCOM Files == +== NZ-COM Files == -The following files came from the official NZCOM distribution. These +The following files came from the official NZ-COM distribution. These are generally documented in the "NZCOM Users Manual.pdf" document in the Doc/CPM directory of the RomWBW distribution. Note that some of the files included in the NZ-COM distribution are not listed below because @@ -89,7 +100,7 @@ Applications section below. !VERS--1.2H - Version marker directory entry (empty file) ALIAS.CMD - Sample alias definitions for use with ARUNZ ARUNZ.COM - Alias-RUN-forZ-System command alias execution -BGZRDS19.LBR - ??? +BGZRDS19.LBR - Patch for Backgrounder II CLEDINST.COM - Configure RCP-resident command line editor CLEDSAVE.COM - Save RCP-resident command line editor history CONFIG.LBR - Various configuration files for use with ZCNFG @@ -311,13 +322,4 @@ instructions. User area 3 contains sample audio files that can be played using the TUNE application. -== CP/NET 1.2 (User Area 4) == - -User area 4 contains a full implementation of the CP/NET 1.2 -client provided by Doug Miller. Please read the README.TXT file -in this user area for more information. - -N.B., at a minimum, some of the files in this user area must be copied -to user area 0 for CP/NET to work properly. - --- WBW 11:19 AM 1/22/2024 +-- WBW 7:14 PM 8/17/2024 diff --git a/Source/Images/d_nzcom/u0/NZCOM.LBR b/Source/Images/d_nzcom/u0/NZCOM.LBR index ba93bc11..b62e3240 100644 Binary files a/Source/Images/d_nzcom/u0/NZCOM.LBR and b/Source/Images/d_nzcom/u0/NZCOM.LBR differ diff --git a/Source/Images/d_nzcom/u0/PROFILE.SUB b/Source/Images/d_nzcom/u0/PROFILE.SUB index e7c32d08..f494e311 100644 --- a/Source/Images/d_nzcom/u0/PROFILE.SUB +++ b/Source/Images/d_nzcom/u0/PROFILE.SUB @@ -1,2 +1,2 @@ -NZCOM NZCOM.ZCM TCAP.Z3T - \ No newline at end of file +NZCOM NZCOM.ZCM + \ No newline at end of file diff --git a/Source/Images/d_nzcom/u0/STARTZCM.COM b/Source/Images/d_nzcom/u0/STARTZCM.COM index 2deda943..bfd1ce2b 100644 Binary files a/Source/Images/d_nzcom/u0/STARTZCM.COM and b/Source/Images/d_nzcom/u0/STARTZCM.COM differ diff --git a/Source/Images/d_nzcom/u0/BGZRDS19.LBR b/Source/Images/d_nzcom/u10/BGZRDS19.LBR similarity index 100% rename from Source/Images/d_nzcom/u0/BGZRDS19.LBR rename to Source/Images/d_nzcom/u10/BGZRDS19.LBR diff --git a/Source/Images/d_nzcom/u0/DOCFILES.LBR b/Source/Images/d_nzcom/u10/DOCFILES.LBR similarity index 100% rename from Source/Images/d_nzcom/u0/DOCFILES.LBR rename to Source/Images/d_nzcom/u10/DOCFILES.LBR diff --git a/Source/Images/d_nzcom/u0/HLPFILES.LBR b/Source/Images/d_nzcom/u10/HLPFILES.LBR similarity index 100% rename from Source/Images/d_nzcom/u0/HLPFILES.LBR rename to Source/Images/d_nzcom/u10/HLPFILES.LBR diff --git a/Source/Images/d_nzcom/u0/LSH.WZ b/Source/Images/d_nzcom/u10/LSH.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/LSH.WZ rename to Source/Images/d_nzcom/u10/LSH.WZ diff --git a/Source/Images/d_nzcom/u0/NZ-DBASE.INF b/Source/Images/d_nzcom/u10/NZ-DBASE.INF similarity index 100% rename from Source/Images/d_nzcom/u0/NZ-DBASE.INF rename to Source/Images/d_nzcom/u10/NZ-DBASE.INF diff --git a/Source/Images/d_nzcom/u0/NZBLTZ14.HZP b/Source/Images/d_nzcom/u10/NZBLTZ14.HZP similarity index 100% rename from Source/Images/d_nzcom/u0/NZBLTZ14.HZP rename to Source/Images/d_nzcom/u10/NZBLTZ14.HZP diff --git a/Source/Images/d_nzcom/u0/RELEASE.NOT b/Source/Images/d_nzcom/u10/RELEASE.NOT similarity index 100% rename from Source/Images/d_nzcom/u0/RELEASE.NOT rename to Source/Images/d_nzcom/u10/RELEASE.NOT diff --git a/Source/Images/d_nzcom/u0/TCJ.INF b/Source/Images/d_nzcom/u10/TCJ.INF similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ.INF rename to Source/Images/d_nzcom/u10/TCJ.INF diff --git a/Source/Images/d_nzcom/u0/TCJ25.WZ b/Source/Images/d_nzcom/u10/TCJ25.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ25.WZ rename to Source/Images/d_nzcom/u10/TCJ25.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ26.WZ b/Source/Images/d_nzcom/u10/TCJ26.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ26.WZ rename to Source/Images/d_nzcom/u10/TCJ26.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ27.WZ b/Source/Images/d_nzcom/u10/TCJ27.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ27.WZ rename to Source/Images/d_nzcom/u10/TCJ27.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ28.WZ b/Source/Images/d_nzcom/u10/TCJ28.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ28.WZ rename to Source/Images/d_nzcom/u10/TCJ28.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ29.WZ b/Source/Images/d_nzcom/u10/TCJ29.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ29.WZ rename to Source/Images/d_nzcom/u10/TCJ29.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ30.WZ b/Source/Images/d_nzcom/u10/TCJ30.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ30.WZ rename to Source/Images/d_nzcom/u10/TCJ30.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ31UPD.WZ b/Source/Images/d_nzcom/u10/TCJ31UPD.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ31UPD.WZ rename to Source/Images/d_nzcom/u10/TCJ31UPD.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ32.WZ b/Source/Images/d_nzcom/u10/TCJ32.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ32.WZ rename to Source/Images/d_nzcom/u10/TCJ32.WZ diff --git a/Source/Images/d_nzcom/u0/TCJ33UPD.WZ b/Source/Images/d_nzcom/u10/TCJ33UPD.WZ similarity index 100% rename from Source/Images/d_nzcom/u0/TCJ33UPD.WZ rename to Source/Images/d_nzcom/u10/TCJ33UPD.WZ diff --git a/Source/Images/d_nzcom/u0/ZFILEB38.LZT b/Source/Images/d_nzcom/u10/ZFILEB38.LZT similarity index 100% rename from Source/Images/d_nzcom/u0/ZFILEB38.LZT rename to Source/Images/d_nzcom/u10/ZFILEB38.LZT diff --git a/Source/Images/d_nzcom/u0/ZHELPERS.LZT b/Source/Images/d_nzcom/u10/ZHELPERS.LZT similarity index 100% rename from Source/Images/d_nzcom/u0/ZHELPERS.LZT rename to Source/Images/d_nzcom/u10/ZHELPERS.LZT diff --git a/Source/Images/d_nzcom/u0/ZNODES66.LZT b/Source/Images/d_nzcom/u10/ZNODES66.LZT similarity index 100% rename from Source/Images/d_nzcom/u0/ZNODES66.LZT rename to Source/Images/d_nzcom/u10/ZNODES66.LZT diff --git a/Source/Images/d_nzcom/u0/ZSYSTEM.IZF b/Source/Images/d_nzcom/u10/ZSYSTEM.IZF similarity index 100% rename from Source/Images/d_nzcom/u0/ZSYSTEM.IZF rename to Source/Images/d_nzcom/u10/ZSYSTEM.IZF diff --git a/Source/Images/d_nzcom/u0/CONFIG.LBR b/Source/Images/d_nzcom/u14/CONFIG.LBR similarity index 100% rename from Source/Images/d_nzcom/u0/CONFIG.LBR rename to Source/Images/d_nzcom/u14/CONFIG.LBR diff --git a/Source/Images/d_nzcom/u0/NZBLTZ14.CFG b/Source/Images/d_nzcom/u14/NZBLTZ14.CFG similarity index 100% rename from Source/Images/d_nzcom/u0/NZBLTZ14.CFG rename to Source/Images/d_nzcom/u14/NZBLTZ14.CFG diff --git a/Source/Images/d_nzcom/u0/ALIAS.CMD b/Source/Images/d_nzcom/u15/ALIAS.CMD similarity index 91% rename from Source/Images/d_nzcom/u0/ALIAS.CMD rename to Source/Images/d_nzcom/u15/ALIAS.CMD index 936006c3..7e60b436 100644 Binary files a/Source/Images/d_nzcom/u0/ALIAS.CMD and b/Source/Images/d_nzcom/u15/ALIAS.CMD differ diff --git a/Source/Images/d_nzcom/u0/ARUNZ.COM b/Source/Images/d_nzcom/u15/ARUNZ.COM similarity index 100% rename from Source/Images/d_nzcom/u0/ARUNZ.COM rename to Source/Images/d_nzcom/u15/ARUNZ.COM diff --git a/Source/Images/d_nzcom/u0/CLEDINST.COM b/Source/Images/d_nzcom/u15/CLEDINST.COM similarity index 100% rename from Source/Images/d_nzcom/u0/CLEDINST.COM rename to Source/Images/d_nzcom/u15/CLEDINST.COM diff --git a/Source/Images/d_nzcom/u0/CLEDSAVE.COM b/Source/Images/d_nzcom/u15/CLEDSAVE.COM similarity index 100% rename from Source/Images/d_nzcom/u0/CLEDSAVE.COM rename to Source/Images/d_nzcom/u15/CLEDSAVE.COM diff --git a/Source/Images/d_nzcom/u15/CMDRUN.COM b/Source/Images/d_nzcom/u15/CMDRUN.COM new file mode 100644 index 00000000..041b87c4 Binary files /dev/null and b/Source/Images/d_nzcom/u15/CMDRUN.COM differ diff --git a/Source/Images/d_nzcom/u0/CPSET.COM b/Source/Images/d_nzcom/u15/CPSET.COM similarity index 100% rename from Source/Images/d_nzcom/u0/CPSET.COM rename to Source/Images/d_nzcom/u15/CPSET.COM diff --git a/Source/Images/d_nzcom/u0/EDITNDR.COM b/Source/Images/d_nzcom/u15/EDITNDR.COM similarity index 100% rename from Source/Images/d_nzcom/u0/EDITNDR.COM rename to Source/Images/d_nzcom/u15/EDITNDR.COM diff --git a/Source/Images/d_nzcom/u0/FCP.LBR b/Source/Images/d_nzcom/u15/FCP.LBR similarity index 100% rename from Source/Images/d_nzcom/u0/FCP.LBR rename to Source/Images/d_nzcom/u15/FCP.LBR diff --git a/Source/Images/d_nzcom/u0/FF.COM b/Source/Images/d_nzcom/u15/FF.COM similarity index 100% rename from Source/Images/d_nzcom/u0/FF.COM rename to Source/Images/d_nzcom/u15/FF.COM diff --git a/Source/Images/d_nzcom/u0/HELP.COM b/Source/Images/d_nzcom/u15/HELP.COM similarity index 98% rename from Source/Images/d_nzcom/u0/HELP.COM rename to Source/Images/d_nzcom/u15/HELP.COM index 58b4d6fc..6c014ee6 100644 Binary files a/Source/Images/d_nzcom/u0/HELP.COM and b/Source/Images/d_nzcom/u15/HELP.COM differ diff --git a/Source/Images/d_nzcom/u0/IF.COM b/Source/Images/d_nzcom/u15/IF.COM similarity index 100% rename from Source/Images/d_nzcom/u0/IF.COM rename to Source/Images/d_nzcom/u15/IF.COM diff --git a/Source/Images/d_nzcom/u0/JETLDR.COM b/Source/Images/d_nzcom/u15/JETLDR.COM similarity index 100% rename from Source/Images/d_nzcom/u0/JETLDR.COM rename to Source/Images/d_nzcom/u15/JETLDR.COM diff --git a/Source/Images/d_nzcom/u0/LBRHELP.COM b/Source/Images/d_nzcom/u15/LBRHELP.COM similarity index 97% rename from Source/Images/d_nzcom/u0/LBRHELP.COM rename to Source/Images/d_nzcom/u15/LBRHELP.COM index eb1ef6ee..35f0b6fe 100644 Binary files a/Source/Images/d_nzcom/u0/LBRHELP.COM and b/Source/Images/d_nzcom/u15/LBRHELP.COM differ diff --git a/Source/Images/d_nzcom/u0/LDIR.COM b/Source/Images/d_nzcom/u15/LDIR.COM similarity index 100% rename from Source/Images/d_nzcom/u0/LDIR.COM rename to Source/Images/d_nzcom/u15/LDIR.COM diff --git a/Source/Images/d_nzcom/u0/LPUT.COM b/Source/Images/d_nzcom/u15/LPUT.COM similarity index 100% rename from Source/Images/d_nzcom/u0/LPUT.COM rename to Source/Images/d_nzcom/u15/LPUT.COM diff --git a/Source/Images/d_nzcom/u0/LSH-HELP.COM b/Source/Images/d_nzcom/u15/LSH-HELP.COM similarity index 100% rename from Source/Images/d_nzcom/u0/LSH-HELP.COM rename to Source/Images/d_nzcom/u15/LSH-HELP.COM diff --git a/Source/Images/d_nzcom/u0/LSH.COM b/Source/Images/d_nzcom/u15/LSH.COM similarity index 100% rename from Source/Images/d_nzcom/u0/LSH.COM rename to Source/Images/d_nzcom/u15/LSH.COM diff --git a/Source/Images/d_nzcom/u0/LSHINST.COM b/Source/Images/d_nzcom/u15/LSHINST.COM similarity index 100% rename from Source/Images/d_nzcom/u0/LSHINST.COM rename to Source/Images/d_nzcom/u15/LSHINST.COM diff --git a/Source/Images/d_nzcom/u0/LX.COM b/Source/Images/d_nzcom/u15/LX.COM similarity index 100% rename from Source/Images/d_nzcom/u0/LX.COM rename to Source/Images/d_nzcom/u15/LX.COM diff --git a/Source/Images/d_nzcom/u0/MKZCM.COM b/Source/Images/d_nzcom/u15/MKZCM.COM similarity index 100% rename from Source/Images/d_nzcom/u0/MKZCM.COM rename to Source/Images/d_nzcom/u15/MKZCM.COM diff --git a/Source/Images/d_nzcom/u0/NAME.COM b/Source/Images/d_nzcom/u15/NAME.COM similarity index 100% rename from Source/Images/d_nzcom/u0/NAME.COM rename to Source/Images/d_nzcom/u15/NAME.COM diff --git a/Source/Images/d_nzcom/u0/NZBLITZ.COM b/Source/Images/d_nzcom/u15/NZBLITZ.COM similarity index 100% rename from Source/Images/d_nzcom/u0/NZBLITZ.COM rename to Source/Images/d_nzcom/u15/NZBLITZ.COM diff --git a/Source/Images/d_nzcom/u0/PATH.COM b/Source/Images/d_nzcom/u15/PATH.COM similarity index 100% rename from Source/Images/d_nzcom/u0/PATH.COM rename to Source/Images/d_nzcom/u15/PATH.COM diff --git a/Source/Images/d_nzcom/u0/PUBLIC.COM b/Source/Images/d_nzcom/u15/PUBLIC.COM similarity index 100% rename from Source/Images/d_nzcom/u0/PUBLIC.COM rename to Source/Images/d_nzcom/u15/PUBLIC.COM diff --git a/Source/Images/d_nzcom/u0/PWD.COM b/Source/Images/d_nzcom/u15/PWD.COM similarity index 100% rename from Source/Images/d_nzcom/u0/PWD.COM rename to Source/Images/d_nzcom/u15/PWD.COM diff --git a/Source/Images/d_nzcom/u0/SAINST.COM b/Source/Images/d_nzcom/u15/SAINST.COM similarity index 100% rename from Source/Images/d_nzcom/u0/SAINST.COM rename to Source/Images/d_nzcom/u15/SAINST.COM diff --git a/Source/Images/d_nzcom/u0/SALIAS.COM b/Source/Images/d_nzcom/u15/SALIAS.COM similarity index 100% rename from Source/Images/d_nzcom/u0/SALIAS.COM rename to Source/Images/d_nzcom/u15/SALIAS.COM diff --git a/Source/Images/d_nzcom/u0/SAVENDR.COM b/Source/Images/d_nzcom/u15/SAVENDR.COM similarity index 100% rename from Source/Images/d_nzcom/u0/SAVENDR.COM rename to Source/Images/d_nzcom/u15/SAVENDR.COM diff --git a/Source/Images/d_nzcom/u0/SDZ.COM b/Source/Images/d_nzcom/u15/SDZ.COM similarity index 100% rename from Source/Images/d_nzcom/u0/SDZ.COM rename to Source/Images/d_nzcom/u15/SDZ.COM diff --git a/Source/Images/d_nzcom/u0/SHOW.COM b/Source/Images/d_nzcom/u15/SHOW.COM similarity index 100% rename from Source/Images/d_nzcom/u0/SHOW.COM rename to Source/Images/d_nzcom/u15/SHOW.COM diff --git a/Source/Images/d_nzcom/u0/SUB.COM b/Source/Images/d_nzcom/u15/SUB.COM similarity index 100% rename from Source/Images/d_nzcom/u0/SUB.COM rename to Source/Images/d_nzcom/u15/SUB.COM diff --git a/Source/Images/d_nzcom/u0/TY3ERA.COM b/Source/Images/d_nzcom/u15/TY3ERA.COM similarity index 100% rename from Source/Images/d_nzcom/u0/TY3ERA.COM rename to Source/Images/d_nzcom/u15/TY3ERA.COM diff --git a/Source/Images/d_nzcom/u0/TY3REN.COM b/Source/Images/d_nzcom/u15/TY3REN.COM similarity index 100% rename from Source/Images/d_nzcom/u0/TY3REN.COM rename to Source/Images/d_nzcom/u15/TY3REN.COM diff --git a/Source/Images/d_nzcom/u0/TY4ERA.COM b/Source/Images/d_nzcom/u15/TY4ERA.COM similarity index 100% rename from Source/Images/d_nzcom/u0/TY4ERA.COM rename to Source/Images/d_nzcom/u15/TY4ERA.COM diff --git a/Source/Images/d_nzcom/u0/TY4REN.COM b/Source/Images/d_nzcom/u15/TY4REN.COM similarity index 100% rename from Source/Images/d_nzcom/u0/TY4REN.COM rename to Source/Images/d_nzcom/u15/TY4REN.COM diff --git a/Source/Images/d_nzcom/u0/TY4SAVE.COM b/Source/Images/d_nzcom/u15/TY4SAVE.COM similarity index 100% rename from Source/Images/d_nzcom/u0/TY4SAVE.COM rename to Source/Images/d_nzcom/u15/TY4SAVE.COM diff --git a/Source/Images/d_nzcom/u0/TY4SP.COM b/Source/Images/d_nzcom/u15/TY4SP.COM similarity index 100% rename from Source/Images/d_nzcom/u0/TY4SP.COM rename to Source/Images/d_nzcom/u15/TY4SP.COM diff --git a/Source/Images/d_nzcom/u0/VIEW.COM b/Source/Images/d_nzcom/u15/VIEW.COM similarity index 100% rename from Source/Images/d_nzcom/u0/VIEW.COM rename to Source/Images/d_nzcom/u15/VIEW.COM diff --git a/Source/Images/d_nzcom/u0/XTCAP.COM b/Source/Images/d_nzcom/u15/XTCAP.COM similarity index 100% rename from Source/Images/d_nzcom/u0/XTCAP.COM rename to Source/Images/d_nzcom/u15/XTCAP.COM diff --git a/Source/Images/d_nzcom/u0/ZERR.COM b/Source/Images/d_nzcom/u15/ZERR.COM similarity index 100% rename from Source/Images/d_nzcom/u0/ZERR.COM rename to Source/Images/d_nzcom/u15/ZERR.COM diff --git a/Source/Images/d_nzcom/u0/ZEX.COM b/Source/Images/d_nzcom/u15/ZEX.COM similarity index 100% rename from Source/Images/d_nzcom/u0/ZEX.COM rename to Source/Images/d_nzcom/u15/ZEX.COM diff --git a/Source/Images/d_nzcom/u0/ZF-DIM.COM b/Source/Images/d_nzcom/u15/ZF-DIM.COM similarity index 100% rename from Source/Images/d_nzcom/u0/ZF-DIM.COM rename to Source/Images/d_nzcom/u15/ZF-DIM.COM diff --git a/Source/Images/d_nzcom/u0/ZF-REV.COM b/Source/Images/d_nzcom/u15/ZF-REV.COM similarity index 100% rename from Source/Images/d_nzcom/u0/ZF-REV.COM rename to Source/Images/d_nzcom/u15/ZF-REV.COM diff --git a/Source/Images/d_nzcom/u0/ZFILER.CMD b/Source/Images/d_nzcom/u15/ZFILER.CMD similarity index 100% rename from Source/Images/d_nzcom/u0/ZFILER.CMD rename to Source/Images/d_nzcom/u15/ZFILER.CMD diff --git a/Source/Images/d_nzcom/u0/ZLT.COM b/Source/Images/d_nzcom/u15/ZLT.COM similarity index 100% rename from Source/Images/d_nzcom/u0/ZLT.COM rename to Source/Images/d_nzcom/u15/ZLT.COM diff --git a/Source/Images/fd_nzcom.txt b/Source/Images/fd_nzcom.txt index 140cdd32..96f4ba01 100644 --- a/Source/Images/fd_nzcom.txt +++ b/Source/Images/fd_nzcom.txt @@ -5,23 +5,23 @@ d_nzcom/ReadMe.txt 0: # # Include selected CP/M 2.2 files # -d_cpm22/u0/STAT.COM 0: +d_cpm22/u0/STAT.COM 15: d_cpm22/u0/SUBMIT.COM 0: -d_cpm22/u0/XSUB.COM 0: +d_cpm22/u0/XSUB.COM 15: # # Add RomWBW utilities # -#../../Binary/Apps/*.com 0: -../../Binary/Apps/assign.com 0: -../../Binary/Apps/cpuspd.com 0: -../../Binary/Apps/fat.com 0: -../../Binary/Apps/fdu.com 0: -../../Binary/Apps/rtc.com 0: -../../Binary/Apps/syscopy.com 0: -../../Binary/Apps/talk.com 0: -../../Binary/Apps/htalk.com 0: -../../Binary/Apps/timer.com 0: -../../Binary/Apps/xm.com 0: +#../../Binary/Apps/*.com 15: +../../Binary/Apps/assign.com 15: +../../Binary/Apps/cpuspd.com 15: +../../Binary/Apps/fat.com 15: +../../Binary/Apps/fdu.com 15: +../../Binary/Apps/rtc.com 15: +../../Binary/Apps/syscopy.com 15: +../../Binary/Apps/talk.com 15: +../../Binary/Apps/htalk.com 15: +../../Binary/Apps/timer.com 15: +../../Binary/Apps/xm.com 15: # # Add OS images # @@ -29,11 +29,11 @@ d_cpm22/u0/XSUB.COM 0: # # Add Common Applications # -Common/All/*.* 0: -Common/CPM22/*.* 0: -#Common/Z/u10/*.* 0: -Common/Z/u14/*.* 0: -Common/Z/u15/*.* 0: -Common/Z3/u10/*.* 0: -Common/Z3/u14/*.* 0: -Common/Z3/u15/*.* 0: +Common/All/*.* 15: +Common/CPM22/*.* 15: +#Common/Z/u10/*.* 10: +Common/Z/u14/*.* 14: +Common/Z/u15/*.* 15: +Common/Z3/u10/*.* 10: +Common/Z3/u14/*.* 14: +Common/Z3/u15/*.* 15: diff --git a/Source/Images/hd_bp.txt b/Source/Images/hd_bp.txt index 58f88d7e..789683f9 100644 --- a/Source/Images/hd_bp.txt +++ b/Source/Images/hd_bp.txt @@ -40,6 +40,7 @@ ../../Binary/Apps/vgmplay.com 15: # ../../Binary/Apps/Test/*.com 2: +../../Binary/Apps/Test/*.doc 2: Test/*.* 2: # # Add Tune sample files diff --git a/Source/Images/hd_cpm22.txt b/Source/Images/hd_cpm22.txt index a2f7f94e..8d60965b 100644 --- a/Source/Images/hd_cpm22.txt +++ b/Source/Images/hd_cpm22.txt @@ -36,6 +36,7 @@ d_cpm22/ReadMe.txt 0: ../../Binary/Apps/vgmplay.com 0: # ../../Binary/Apps/Test/*.com 2: +../../Binary/Apps/Test/*.doc 2: Test/*.* 2: # # Add Tune sample files diff --git a/Source/Images/hd_cpm3.txt b/Source/Images/hd_cpm3.txt index ba8383bd..1772d2fa 100644 --- a/Source/Images/hd_cpm3.txt +++ b/Source/Images/hd_cpm3.txt @@ -52,6 +52,7 @@ ../../Binary/Apps/vgmplay.com 0: # ../../Binary/Apps/Test/*.com 2: +../../Binary/Apps/Test/*.doc 2: Test/*.* 2: # # Add Tune sample files diff --git a/Source/Images/hd_msxroms1.txt b/Source/Images/hd_msxroms1.txt new file mode 100644 index 00000000..f0966942 --- /dev/null +++ b/Source/Images/hd_msxroms1.txt @@ -0,0 +1,4 @@ +# +# Add the ReadMe document +# +d_msxroms1/ReadMe.txt 0: diff --git a/Source/Images/hd_msxroms2.txt b/Source/Images/hd_msxroms2.txt new file mode 100644 index 00000000..8bbd751c --- /dev/null +++ b/Source/Images/hd_msxroms2.txt @@ -0,0 +1,4 @@ +# +# Add the ReadMe document +# +d_msxroms2/ReadMe.txt 0: diff --git a/Source/Images/hd_nzcom.txt b/Source/Images/hd_nzcom.txt index bdcdad1c..47378863 100644 --- a/Source/Images/hd_nzcom.txt +++ b/Source/Images/hd_nzcom.txt @@ -5,54 +5,61 @@ d_nzcom/ReadMe.txt 0: # # Include selected CP/M 2.2 files # -d_cpm22/u0/ASM.COM 0: -d_cpm22/u0/LIB.COM 0: -d_cpm22/u0/LINK.COM 0: -d_cpm22/u0/LOAD.COM 0: -d_cpm22/u0/MAC.COM 0: -#d_cpm22/u0/PIP.COM 0: ??? -d_cpm22/u0/RMAC.COM 0: -d_cpm22/u0/STAT.COM 0: +d_cpm22/u0/ASM.COM 15: +d_cpm22/u0/LIB.COM 15: +d_cpm22/u0/LINK.COM 15: +d_cpm22/u0/LOAD.COM 15: +d_cpm22/u0/MAC.COM 15: +#d_cpm22/u0/PIP.COM 15: ??? +d_cpm22/u0/RMAC.COM 15: +d_cpm22/u0/STAT.COM 15: d_cpm22/u0/SUBMIT.COM 0: -d_cpm22/u0/XSUB.COM 0: +d_cpm22/u0/XSUB.COM 15: # # Include ZSDOS files # -d_zsdos/u0/*.* 0: +d_zsdos/u0/*.COM 15: +d_zsdos/u0/*.CFG 14: +d_zsdos/u0/*.UPD 10: +d_zsdos/u0/*.DOC 10: +d_zsdos/u0/*.FOR 10: +d_zsdos/u0/*.TXT 10: +d_zsdos/u0/*.DAT 15: # # Add RomWBW utilities # -#../../Binary/Apps/*.com 0: -../../Binary/Apps/assign.com 0: -../../Binary/Apps/bbcbasic.com 0: -../../Binary/Apps/bbcbasic.txt 0: -../../Binary/Apps/cpuspd.com 0: -../../Binary/Apps/fat.com 0: -../../Binary/Apps/fdu.com 0: -../../Binary/Apps/fdu.doc 0: -../../Binary/Apps/format.com 0: -../../Binary/Apps/mode.com 0: -../../Binary/Apps/rtc.com 0: -../../Binary/Apps/survey.com 0: -../../Binary/Apps/syscopy.com 0: -../../Binary/Apps/sysgen.com 0: -../../Binary/Apps/talk.com 0: -../../Binary/Apps/htalk.com 0: -../../Binary/Apps/tbasic.com 0: -../../Binary/Apps/timer.com 0: -../../Binary/Apps/tune.com 0: -../../Binary/Apps/xm.com 0: -../../Binary/Apps/zmp.com 0: -../../Binary/Apps/zmp.hlp 0: -../../Binary/Apps/zmp.doc 0: -../../Binary/Apps/zmxfer.ovr 0: -../../Binary/Apps/zmterm.ovr 0: -../../Binary/Apps/zminit.ovr 0: -../../Binary/Apps/zmconfig.ovr 0: -../../Binary/Apps/zmd.com 0: -../../Binary/Apps/vgmplay.com 0: +#../../Binary/Apps/*.com 15: +../../Binary/Apps/assign.com 15: +../../Binary/Apps/bbcbasic.com 15: +../../Binary/Apps/bbcbasic.txt 10: +../../Binary/Apps/cpuspd.com 15: +../../Binary/Apps/fat.com 15: +../../Binary/Apps/fdu.com 15: +../../Binary/Apps/fdu.doc 10: +../../Binary/Apps/format.com 15: +../../Binary/Apps/mode.com 15: +../../Binary/Apps/rtc.com 15: +../../Binary/Apps/survey.com 15: +../../Binary/Apps/syscopy.com 15: +../../Binary/Apps/sysgen.com 15: +../../Binary/Apps/talk.com 15: +../../Binary/Apps/htalk.com 15: +../../Binary/Apps/tbasic.com 15: +../../Binary/Apps/timer.com 15: +../../Binary/Apps/tune.com 15: +../../Binary/Apps/xm.com 15: +../../Binary/Apps/zmp.com 15: +../../Binary/Apps/zmp.hlp 15: +../../Binary/Apps/zmp.doc 10: +../../Binary/Apps/zmxfer.ovr 15: +../../Binary/Apps/zmterm.ovr 15: +../../Binary/Apps/zminit.ovr 15: +../../Binary/Apps/zmconfig.ovr 15: +../../Binary/Apps/zmd.com 15: +../../Binary/Apps/vgmplay.com 15: # ../../Binary/Apps/Test/*.com 2: +../../Binary/Apps/Test/*.doc 2: Test/*.* 2: # # Add Tune sample files @@ -67,13 +74,13 @@ Test/*.* 2: # # Add Common Applications # -Common/All/*.* 0: -Common/CPM22/*.* 0: -#Common/Z/u10/*.* 0: -Common/Z/u14/*.* 0: -Common/Z/u15/*.* 0: -Common/Z3/u10/*.* 0: -Common/Z3/u14/*.* 0: -Common/Z3/u15/*.* 0: +Common/All/*.* 15: +Common/CPM22/*.* 15: +#Common/Z/u10/*.* 10: +Common/Z/u14/*.* 14: +Common/Z/u15/*.* 15: +Common/Z3/u10/*.* 10: +Common/Z3/u14/*.* 14: +Common/Z3/u15/*.* 15: Common/SIMH/*.* 13: -Common/UTILS/*.* 0: +Common/UTILS/*.* 15: diff --git a/Source/Images/hd_qpm.txt b/Source/Images/hd_qpm.txt index f8fc8e85..98434857 100644 --- a/Source/Images/hd_qpm.txt +++ b/Source/Images/hd_qpm.txt @@ -40,6 +40,7 @@ d_cpm22/u0/*.* 0: ../../Binary/Apps/vgmplay.com 0: # ../../Binary/Apps/Test/*.com 2: +../../Binary/Apps/Test/*.doc 2: Test/*.* 2: # # Add Tune sample files diff --git a/Source/Images/hd_zpm3.txt b/Source/Images/hd_zpm3.txt index 1532cb55..5f5c0615 100644 --- a/Source/Images/hd_zpm3.txt +++ b/Source/Images/hd_zpm3.txt @@ -51,6 +51,7 @@ ../../Binary/Apps/vgmplay.com 15: # ../../Binary/Apps/Test/*.com 2: +../../Binary/Apps/Test/*.doc 2: Test/*.* 2: # # Add Tune sample files diff --git a/Source/Images/hd_zsdos.txt b/Source/Images/hd_zsdos.txt index 9dc1dcda..1c7fe895 100644 --- a/Source/Images/hd_zsdos.txt +++ b/Source/Images/hd_zsdos.txt @@ -49,6 +49,7 @@ d_cpm22/u0/XSUB.COM 0: ../../Binary/Apps/vgmplay.com 0: # ../../Binary/Apps/Test/*.com 2: +../../Binary/Apps/Test/*.doc 2: Test/*.* 2: # # Add Tune sample files diff --git a/Source/Makefile b/Source/Makefile index add7330d..e741cc4c 100644 --- a/Source/Makefile +++ b/Source/Makefile @@ -2,12 +2,12 @@ # order is actually important, because of build dependencies # -.PHONY: doc prop shared bp images rom zrc z1rcc zzrcc zrc512 +.PHONY: doc prop shared bp images rom zrc z1rcc zzrcc zrc512 fz80 .ONESHELL: .SHELLFLAGS = -ce -all: prop shared bp images rom zrc z1rcc zzrcc zrc512 +all: prop shared bp images rom zrc z1rcc zzrcc zrc512 fz80 doc: $(MAKE) --directory Doc $(ACTION) @@ -54,6 +54,9 @@ zzrcc: zrc512: $(MAKE) --directory ZRC512 $(ACTION) +fz80: + $(MAKE) --directory FZ80 $(ACTION) + clean: ACTION=clean clean: all diff --git a/Source/ReadMe.txt b/Source/ReadMe.txt index 2fe241d8..917092db 100644 --- a/Source/ReadMe.txt +++ b/Source/ReadMe.txt @@ -45,9 +45,33 @@ process. These scripts utilize both batch command files as well as Windows PowerShell. Windows 7 or greater is recommended. If you want to use Windows Vista or XP, you will need to first install PowerShell which available for free from Microsoft. Either 32 or 64 bit versions -of Microsoft Windows are fine.No additional programs need to be +of Microsoft Windows are fine. No additional programs need to be installed to run the build. +You may find that you get messages such as this during the Windows +build process: + +Security warning +Run only scripts that you trust. While scripts from the internet can be +useful, this script can potentially harm your computer. If you trust +this script, use the Unblock-File cmdlet to allow the script to run +without this warning message. Do you want to run +C:\Temp\RomWBW-v3.5.0-dev.67-Package\Source\Images\BuildDisk.ps1? +[D] Do not run [R] Run once [S] Suspend [?] Help (default is "D"): + +These prompts occur if Windows has marked the files as "blocked" +because they were downloaded from the Internet. To unblock all of +the files in the entire RomWBW distribution tree, start PowerShell +and navigate to the root of the distribution. Enter the following +command: + + dir -recurse | unblock-file + +This will unblock all files within the distribution and preclude the +security warning messages. Obviously, you should make sure you have +downloaded the RomWBW distribution from a valid/trustworthy source +before removing the file block protection. + Linux Build System Requirements ------------------------------- @@ -116,9 +140,33 @@ Each of the 4 steps above is described in more detail below. ----------------------------------- The options for a build are primarily controlled by a configuration -file that is included in the build process. In order to customize -your settings, it is easiest to make a copy of an existing -configuration file and make your changes there. +file that is included in the build process. + +RomWBW uses cascading configuration files as indicated below: + +cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +| ++-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM + | + +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD + | + +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS + +The top (master configuration) file defines all possible RomWBW +configuration settings. Each file below the master configuration file +inherits the cumulative settings of the files above it and may +override these settings as desired. + +Other than the top master file, each file must "#INCLUDE" its parent +file. The top two files should not be modified. To customize your +build settings you should modify the default build settings +(config/_std.asm) or preferably create an optional custom +user settings file that includes the default build settings file (see +example Config/SBC_user.asm). + +By creating a custom user settings file, you are less likely to be +impacted by future changes because you will only be inheriting most +of your settings which will be updated by authors as RomWBW evolves. RomWBW uses the concept of a "platform" and "configuration" to define the settings for a build. Platform refers to one of the core @@ -129,23 +177,29 @@ defaults as desired. The platform names are predefined. Refer to the following table to determine the component of the configuration filename: - SBC Retrocomputing ECB Z80 SBC V1/V2 - N8 RetroComputing N8 SBC - MK4 RetroComputing Mark IV Z180 - ZETA Sergey Kiselev's Zeta Z80 - ZETA2 Sergey Kiselev's Zeta V2 Z80 - RCZ80 RCBus Z80 - RCZ180 RCBus Z180 - SCZ180 Stephen Cousins' Z180 Systems - RCZ280 RCBus Z280 - EZZ80 Sergey Kiselev's Easy/Tiny Z80 - DYNO Dyno Z180 Single Board Computer - MBC Andrew Lynch's Nhyodyne Z80 MBC - RPH Andrew Lynch's Rhyophyre Z180 SBC + SBC Z80 SBC (v1 or v2) w/ ECB interface + ZETA Standalone Z80 SBC w/ SBC compatibility + ZETA2 Second version of ZETA with enhanced memory bank switching + N8 MSX-ish Z180 SBC w/ onboard video and sound + MK4 Mark IV Z180 based SBC w/ ECB interface + UNA Any Z80/Z180 computer with UNA BIOS + RCZ80 RCBUS based system with 512K banked RAM/ROM card + RCZ180 RCBUS based system with Z180 CPU + EZZ80 Easy Z80, Z80 SBC w/ RCBUS and CTC + SCZ180 Steve Cousins Z180 based system + DYNO Steve Garcia's Dyno Micro-ATX Motherboard + RCZ280 Z280 CPU on RCBUS or ZZ80MB + MBC Andrew Lynch's Multi Board Computer + RPH Andrew Lynch's RHYOPHYRE Graphics Computer Z80RETRO Peter Wilson's Z80-Retro Computer S100 S100 Computers Z180-based System DUO Andrew Lynch's Duodyne Computer - UNA John Coffman's UNA System + HEATH Les Bird's Heath Z80 Board + EPITX Alan Cox' Mini-ITX System + MON Jacques Pelletier's Monsputer + GMZ180 Doug Jacksons' Genesis Z180 System + NABU NABU w/ Les Bird's RomWBW Option Board + FZ80 S100 Computers FPGA Z80 Configuration files are found in the Source\HBIOS\Config directory. If you look in the this directory, you will see a @@ -170,14 +224,14 @@ and easily revert back to the original if you have problems. It is important to understand how configuration files are processed. They start by inheriting all of the default settings for the -platform. This is accomplished via the "#include" directive near +platform. This is accomplished via the "#INCLUDE" directive near the top of the file. For the "MK4_std.asm" configuration file, this line reads: -#include "cfg_mk4.asm" +#INCLUDE "cfg_MK4.asm" When the configuration file (MK4_std.asm) is processed, it will first -read in all the default platform settings from "cfg_mk4.asm". All of +read in all the default platform settings from "cfg_MK4.asm". All of the platform default configuration files are found in the parent directory (the HBIOS directory). You will see a "cfg_.asm" for each platform in the parent directory. diff --git a/Source/ReadMeDoc.txt b/Source/ReadMeDoc.txt index 0ca671e4..9e8ed406 100644 --- a/Source/ReadMeDoc.txt +++ b/Source/ReadMeDoc.txt @@ -22,12 +22,18 @@ Required for Windows: - MiKTeX (https://miktex.org/) - Install Roboto font from MiKTeX Console -Required for Linux: - - gpp ((apt install gpp) - - Pandoc (dpkg -i pandoc-3.1.8-1-amd64.deb) - - TexLive (apt install texlive-latex-extra texlive-luatex fonts-roboto texlive-fonts-extra) +Required for Ubuntu Linux: + - gpp (apt install gpp) + - Pandoc (apt install pandoc) + - TexLive (apt install texlive texlive-luatex texlive-fonts-extra) -The source directory for the documentation is .../Source/Doc. From this -directory run Build.cmd for Windows or make for Linux to create the -output documents. This will create the final documents and copy them -to their destination directories. \ No newline at end of file +Required for MacOS: + - gpp (brew install gpp) + - pandoc (brew install pandoc) + - TexLive (brew install texlive) + - Roboto Font (brew install --cask font-roboto) + +The source directory for the documentation is /Source/Doc. From this +directory run "Build.cmd" on Windows or "make" on Linux/Mac to create +the output documents. This will create the final documents and copy +them to their destination directories. \ No newline at end of file diff --git a/Source/Z1RCC/Build.cmd b/Source/Z1RCC/Build.cmd index e7ab0eea..3e32d705 100644 --- a/Source/Z1RCC/Build.cmd +++ b/Source/Z1RCC/Build.cmd @@ -5,19 +5,22 @@ set TOOLS=../../Tools set PATH=%TOOLS%\srecord;%PATH% -if exist ..\..\Binary\RCZ180_z1rcc.rom call :build_z1rcc +for %%f in (..\..\Binary\RCZ180_z1rcc_*.rom) do call :build %%~nf goto :eof -:build_z1rcc +:build +echo. +echo Creating %1 disk image... +echo. srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 z1rcc_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 z1rcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 z1rcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ180_z1rcc.rom -binary -offset 0x24000 -o temp.dat -binary -move temp.dat ..\..\Binary\hd1k_z1rcc_prefix.dat +srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\%1.rom -binary -offset 0x24000 -o temp.dat -binary +move temp.dat ..\..\Binary\%1_hd1k_prefix.dat -copy /b ..\..\Binary\hd1k_z1rcc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_z1rcc_combo.img || exit /b +copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b goto :eof diff --git a/Source/Z1RCC/Makefile b/Source/Z1RCC/Makefile index 6890e0d7..eac892d6 100644 --- a/Source/Z1RCC/Makefile +++ b/Source/Z1RCC/Makefile @@ -1,16 +1,13 @@ -HD1KZ1RCCPREFIX = hd1k_z1rcc_prefix.dat -HD1KZ1RCCCOMBOIMG = hd1k_z1rcc_combo.img -Z1RCCROM = ../../Binary/RCZ180_z1rcc.rom -HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \ - ../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img +DEST=../../Binary -OBJECTS := +HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \ + $(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img -ifneq ($(wildcard $(Z1RCCROM)),) - OBJECTS += $(HD1KZ1RCCPREFIX) $(HD1KZ1RCCCOMBOIMG) -endif +ROMS := $(wildcard $(DEST)/RCZ180_z1rcc_*.rom) +ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS)) -DEST=../../Binary +OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS)) +OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS)) TOOLS = ../../Tools @@ -18,13 +15,13 @@ include $(TOOLS)/Makefile.inc DIFFPATH = $(DIFFTO)/Binary -$(HD1KZ1RCCPREFIX): +%_hd1k_prefix.dat: $(DEST)/%.rom srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 z1rcc_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 z1rcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 z1rcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(Z1RCCROM) -binary -offset 0x24000 -o temp.dat -binary + srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $< -binary -offset 0x24000 -o temp.dat -binary mv temp.dat $@ -$(HD1KZ1RCCCOMBOIMG): $(HD1KZ1RCCPREFIX) $(HD1KIMGS) +%_hd1k_combo.img: %_hd1k_prefix.dat $(HD1KIMGS) cat $^ > $@ diff --git a/Source/ZRC/Build.cmd b/Source/ZRC/Build.cmd index 181db8ab..65a188aa 100644 --- a/Source/ZRC/Build.cmd +++ b/Source/ZRC/Build.cmd @@ -5,34 +5,22 @@ set TOOLS=../../Tools set PATH=%TOOLS%\srecord;%PATH% -if exist ..\..\Binary\RCZ80_zrc.rom call :build_zrc - -if exist ..\..\Binary\RCZ80_zrc_ram.rom call :build_zrc_ram - -goto :eof - -:build_zrc - -srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc.rom -binary -offset 0x24000 -o temp.dat -binary -move temp.dat ..\..\Binary\hd1k_zrc_prefix.dat - -copy /b ..\..\Binary\hd1k_zrc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zrc_combo.img || exit /b +for %%f in (..\..\Binary\RCZ80_zrc_*.rom) do call :build %%~nf goto :eof -:build_zrc_ram +:build +echo. +echo Creating %1 disk image... +echo. srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc_ram.rom -binary -offset 0x24000 -o temp.dat -binary -move temp.dat ..\..\Binary\hd1k_zrc_ram_prefix.dat +srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\%1.rom -binary -offset 0x24000 -o temp.dat -binary +move temp.dat ..\..\Binary\%1_hd1k_prefix.dat -copy /b ..\..\Binary\hd1k_zrc_ram_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zrc_ram_combo.img || exit /b +copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b goto :eof diff --git a/Source/ZRC/Makefile b/Source/ZRC/Makefile index 72ebba4f..743e0573 100644 --- a/Source/ZRC/Makefile +++ b/Source/ZRC/Makefile @@ -1,23 +1,13 @@ -HD1KZRCPREFIX = hd1k_zrc_prefix.dat -HD1KZRCCOMBOIMG = hd1k_zrc_combo.img -HD1KZRCRAMPREFIX = hd1k_zrc_ram_prefix.dat -HD1KZRCRAMCOMBOIMG = hd1k_zrc_ram_combo.img -ZRCROM = ../../Binary/RCZ80_zrc.rom -ZRCRAMROM = ../../Binary/RCZ80_zrc_ram.rom -HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \ - ../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img - -OBJECTS := +DEST=../../Binary -ifneq ($(wildcard $(ZRCROM)),) - OBJECTS += $(HD1KZRCPREFIX) $(HD1KZRCCOMBOIMG) -endif +HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \ + $(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img -ifneq ($(wildcard $(ZRCRAMROM)),) - OBJECTS += $(HD1KZRCRAMPREFIX) $(HD1KZRCRAMCOMBOIMG) -endif +ROMS := $(wildcard $(DEST)/RCZ80_zrc_*.rom) +ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS)) -DEST=../../Binary +OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS)) +OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS)) TOOLS = ../../Tools @@ -25,24 +15,13 @@ include $(TOOLS)/Makefile.inc DIFFPATH = $(DIFFTO)/Binary -$(HD1KZRCPREFIX): +%_hd1k_prefix.dat: $(DEST)/%.rom srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCROM) -binary -offset 0x24000 -o temp.dat -binary + srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $< -binary -offset 0x24000 -o temp.dat -binary mv temp.dat $@ -$(HD1KZRCRAMPREFIX): - srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x0 0x200 zrc_cfldr.bin -binary -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRCRAMROM) -binary -offset 0x24000 -o temp.dat -binary - mv temp.dat $@ - -$(HD1KZRCCOMBOIMG): $(HD1KZRCPREFIX) $(HD1KIMGS) - cat $^ > $@ - -$(HD1KZRCRAMCOMBOIMG): $(HD1KZRCRAMPREFIX) $(HD1KIMGS) +%_hd1k_combo.img: %_hd1k_prefix.dat $(HD1KIMGS) cat $^ > $@ diff --git a/Source/ZRC512/Build.cmd b/Source/ZRC512/Build.cmd index dbc18f58..9e5fc81e 100644 --- a/Source/ZRC512/Build.cmd +++ b/Source/ZRC512/Build.cmd @@ -5,19 +5,22 @@ set TOOLS=../../Tools set PATH=%TOOLS%\srecord;%PATH% -if exist ..\..\Binary\RCZ80_zrc512.rom call :build_zrc512 +for %%f in (..\..\Binary\RCZ80_zrc512_*.rom) do call :build %%~nf goto :eof -:build_zrc512 +:build +echo. +echo Creating %1 disk image... +echo. srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 zrc512_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc512_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc512_mon.bin -binary -offset 0x1F000 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ80_zrc512.rom -binary -offset 0x24000 -o temp.dat -binary -move temp.dat ..\..\Binary\hd1k_zrc512_prefix.dat +srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\%1.rom -binary -offset 0x24000 -o temp.dat -binary +move temp.dat ..\..\Binary\%1_hd1k_prefix.dat -copy /b ..\..\Binary\hd1k_zrc512_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zrc512_combo.img || exit /b +copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b goto :eof diff --git a/Source/ZRC512/Makefile b/Source/ZRC512/Makefile index d04611dc..e84c6a5c 100644 --- a/Source/ZRC512/Makefile +++ b/Source/ZRC512/Makefile @@ -1,16 +1,13 @@ -HD1KZRC512PREFIX = hd1k_zrc512_prefix.dat -HD1KZRC512COMBOIMG = hd1k_zrc512_combo.img -ZRC512ROM = ../../Binary/RCZ80_zrc512.rom -HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \ - ../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img +DEST=../../Binary -OBJECTS := +HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \ + $(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img -ifneq ($(wildcard $(ZRC512ROM)),) - OBJECTS += $(HD1KZRC512PREFIX) $(HD1KZRC512COMBOIMG) -endif +ROMS := $(wildcard $(DEST)/RCZ80_zrc512_*.rom) +ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS)) -DEST=../../Binary +OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS)) +OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS)) TOOLS = ../../Tools @@ -18,13 +15,13 @@ include $(TOOLS)/Makefile.inc DIFFPATH = $(DIFFTO)/Binary -$(HD1KZRC512PREFIX): +%_hd1k_prefix.dat: $(DEST)/%.rom srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 zrc512_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 zrc512_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zrc512_mon.bin -binary -offset 0x1F000 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZRC512ROM) -binary -offset 0x24000 -o temp.dat -binary + srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $< -binary -offset 0x24000 -o temp.dat -binary mv temp.dat $@ -$(HD1KZRC512COMBOIMG): $(HD1KZRC512PREFIX) $(HD1KIMGS) +%_hd1k_combo.img: %_hd1k_prefix.dat $(HD1KIMGS) cat $^ > $@ diff --git a/Source/ZSDOS/Clock/ReadMe.txt b/Source/ZSDOS/Clock/ReadMe.txt index 0fc634f7..0685385c 100644 --- a/Source/ZSDOS/Clock/ReadMe.txt +++ b/Source/ZSDOS/Clock/ReadMe.txt @@ -2,10 +2,10 @@ This directory contains the source and assembled versions of the ZSystem Clock Drivers for RomWBW HBIOS. The wbwclk.z80 source file can be compiled using Build.cmd which will -produce a relocatable binary (hbclk.rel). +produce a relocatable binary (wbwclk.rel). -The relocatable binary should be added/updated in the STAMPS.DAT -library. The STAMPS.DAT file is just a standard LU type library and +The relocatable binary should be added/updated in the CLOCKS.DAT +library. The CLOCKS.DAT file is just a standard LU type library and is easily updated using NULU. The members are the relocatable binaries, but with the .REL extension removed. diff --git a/Source/ZZRCC/Build.cmd b/Source/ZZRCC/Build.cmd index f520b11a..d0e105c4 100644 --- a/Source/ZZRCC/Build.cmd +++ b/Source/ZZRCC/Build.cmd @@ -1,41 +1,26 @@ -:: @echo off +@echo off setlocal -set ROMFILE=..\..\Binary\RCZ280_zzrcc.rom -set ROMSIZE=262144 - set TOOLS=../../Tools set PATH=%TOOLS%\srecord;%PATH% -if exist ..\..\Binary\RCZ280_zzrcc.rom call :build_zzrcc - -if exist ..\..\Binary\RCZ280_zzrcc_ram.rom call :build_zzrcc_ram - -goto :eof - -:build_zzrcc - -srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc.rom -binary -offset 0x24000 -o temp.dat -binary -move temp.dat ..\..\Binary\hd1k_zzrcc_prefix.dat - -copy /b ..\..\Binary\hd1k_zzrcc_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrcc_combo.img || exit /b +for %%f in (..\..\Binary\RCZ280_zzrcc_*.rom) do call :build %%~nf goto :eof -:build_zzrcc_ram +:build +echo. +echo Creating %1 disk image... +echo. srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary -srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\RCZ280_zzrcc_ram.rom -binary -offset 0x24000 -o temp.dat -binary -move temp.dat ..\..\Binary\hd1k_zzrcc_ram_prefix.dat +srec_cat temp.dat -binary -exclude 0x24000 0xA4000 ..\..\Binary\%1.rom -binary -offset 0x24000 -o temp.dat -binary +move temp.dat ..\..\Binary\%1_hd1k_prefix.dat -copy /b ..\..\Binary\hd1k_zzrcc_ram_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\hd1k_zzrcc_ram_combo.img || exit /b +copy /b ..\..\Binary\%1_hd1k_prefix.dat + ..\..\Binary\hd1k_cpm22.img + ..\..\Binary\hd1k_zsdos.img + ..\..\Binary\hd1k_nzcom.img + ..\..\Binary\hd1k_cpm3.img + ..\..\Binary\hd1k_zpm3.img + ..\..\Binary\hd1k_ws4.img ..\..\Binary\%1_hd1k_combo.img || exit /b goto :eof diff --git a/Source/ZZRCC/Makefile b/Source/ZZRCC/Makefile index f0bbde6a..ea1249c8 100644 --- a/Source/ZZRCC/Makefile +++ b/Source/ZZRCC/Makefile @@ -1,23 +1,13 @@ -HD1KZZRCCPREFIX = hd1k_zzrcc_prefix.dat -HD1KZZRCCCOMBOIMG = hd1k_zzrcc_combo.img -HD1KZZRCCRAMPREFIX = hd1k_zzrcc_ram_prefix.dat -HD1KZZRCCRAMCOMBOIMG = hd1k_zzrcc_ram_combo.img -ZZRCCROM = ../../Binary/RCZ280_zzrcc.rom -ZZRCCRAMROM = ../../Binary/RCZ280_zzrcc_ram.rom -HD1KIMGS = ../../Binary/hd1k_cpm22.img ../../Binary/hd1k_zsdos.img ../../Binary/hd1k_nzcom.img \ - ../../Binary/hd1k_cpm3.img ../../Binary/hd1k_zpm3.img ../../Binary/hd1k_ws4.img - -OBJECTS := +DEST=../../Binary -ifneq ($(wildcard $(ZZRCCROM)),) - OBJECTS += $(HD1KZZRCCPREFIX) $(HD1KZZRCCCOMBOIMG) -endif +HD1KIMGS = $(DEST)/hd1k_cpm22.img $(DEST)/hd1k_zsdos.img $(DEST)/hd1k_nzcom.img \ + $(DEST)/hd1k_cpm3.img $(DEST)/hd1k_zpm3.img $(DEST)/hd1k_ws4.img -ifneq ($(wildcard $(ZZRCCRAMROM)),) - OBJECTS += $(HD1KZZRCCRAMPREFIX) $(HD1KZZRCCRAMCOMBOIMG) -endif +ROMS := $(wildcard $(DEST)/RCZ280_zzrcc_*.rom) +ROMS := $(patsubst $(DEST)/%.rom,%,$(ROMS)) -DEST=../../Binary +OBJECTS := $(patsubst %,%_hd1k_prefix.dat,$(ROMS)) +OBJECTS += $(patsubst %,%_hd1k_combo.img,$(ROMS)) TOOLS = ../../Tools @@ -25,24 +15,13 @@ include $(TOOLS)/Makefile.inc DIFFPATH = $(DIFFTO)/Binary -$(HD1KZZRCCPREFIX): +%_hd1k_prefix.dat: $(DEST)/%.rom srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCROM) -binary -offset 0x24000 -o temp.dat -binary + srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $< -binary -offset 0x24000 -o temp.dat -binary mv temp.dat $@ -$(HD1KZZRCCRAMPREFIX): - srec_cat -generate 0x0 0x100000 --constant 0x00 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x0 0x200 zzrcc_cfldr.bin -binary -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x1B8 0x200 zzrcc_ptbl.bin -binary -offset 0x1B8 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x1F000 0x20000 zzrcc_mon.bin -binary -offset 0x1F000 -o temp.dat -binary - srec_cat temp.dat -binary -exclude 0x24000 0xA4000 $(ZZRCCRAMROM) -binary -offset 0x24000 -o temp.dat -binary - mv temp.dat $@ - -$(HD1KZZRCCCOMBOIMG): $(HD1KZZRCCPREFIX) $(HD1KIMGS) - cat $^ > $@ - -$(HD1KZZRCCRAMCOMBOIMG): $(HD1KZZRCCRAMPREFIX) $(HD1KIMGS) +%_hd1k_combo.img: %_hd1k_prefix.dat $(HD1KIMGS) cat $^ > $@ diff --git a/Source/ver.inc b/Source/ver.inc index 81923253..0347982f 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 5 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.5.0-dev.45" +#DEFINE BIOSVER "3.5.0-dev.82" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index bcc13c07..4eb00a17 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 5 rup equ 0 rtp equ 0 biosver macro - db "3.5.0-dev.45" + db "3.5.0-dev.82" endm diff --git a/Tools/simh/Sim.cmd b/Tools/simh/Sim.cmd index 3e501ab8..7ba86838 100644 --- a/Tools/simh/Sim.cmd +++ b/Tools/simh/Sim.cmd @@ -1,5 +1,5 @@ @echo off -set ROM=..\..\Binary\SBC_simh.rom +set ROM=..\..\Binary\SBC_simh_std.rom if not "%1"=="" set ROM=..\..\Binary\%1.rom if not exist %ROM% goto romerr :: start C:\Users\WWarthen\Bin\putty.exe -load "SIMH Telnet" diff --git a/Tools/simh/altairz80.exe b/Tools/simh/altairz80.exe index 5e34f627..8222fb91 100644 Binary files a/Tools/simh/altairz80.exe and b/Tools/simh/altairz80.exe differ diff --git a/Tools/simh/altairz80_doc.pdf b/Tools/simh/altairz80_doc.pdf new file mode 100644 index 00000000..00edf44f Binary files /dev/null and b/Tools/simh/altairz80_doc.pdf differ diff --git a/Tools/simh/simh.pdf b/Tools/simh/simh.pdf new file mode 100644 index 00000000..fc903686 Binary files /dev/null and b/Tools/simh/simh.pdf differ diff --git a/Tools/simh/simh_doc.pdf b/Tools/simh/simh_doc.pdf new file mode 100644 index 00000000..efca7269 Binary files /dev/null and b/Tools/simh/simh_doc.pdf differ diff --git a/Tools/simh/simh_faq.pdf b/Tools/simh/simh_faq.pdf new file mode 100644 index 00000000..45c23060 Binary files /dev/null and b/Tools/simh/simh_faq.pdf differ