mirror of https://github.com/wwarthen/RomWBW.git
Phillip Stevens
6 years ago
committed by
GitHub
GitHub
932 changed files with 7657 additions and 6512 deletions
Binary file not shown.
@ -1,28 +0,0 @@ |
|||
COMMON 8F ?? |
|||
CPMSYS 8E 00 |
|||
HBIOS 8D ?? |
|||
TPA 8C 01 |
|||
BUFS 8B 02 |
|||
|
|||
8D:7000 -> 8E:0300 |
|||
|
|||
|
|||
00 -> 8E |
|||
01 -> 8C |
|||
02 -> 8B |
|||
03 -> 8A |
|||
... |
|||
|
|||
if bnk = 0, then hbbnk = 8EH (BID_USR) |
|||
else hbbnk = 8DH (BID_BIOS) - bnk |
|||
|
|||
or a |
|||
jr z,bank0 |
|||
neg ; 2 -> -2 |
|||
add 8DH ; 8D - 2 = 8B |
|||
jp HBX_SETBNK |
|||
bank0: |
|||
ld a,(8EH) |
|||
jp HBX_SETBNK |
|||
ret |
|||
|
|||
@ -0,0 +1,9 @@ |
|||
; global assembler options for BANKED BIOS |
|||
; with Boot Drive swapped into Drive A |
|||
|
|||
true equ -1 |
|||
false equ not true |
|||
|
|||
banked equ true |
|||
|
|||
zpm equ true |
|||
Binary file not shown.
@ -0,0 +1,39 @@ |
|||
; |
|||
;================================================================================================== |
|||
; DYNO STANDARD CONFIGURATION |
|||
;================================================================================================== |
|||
; |
|||
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
|||
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
|||
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
|||
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
|||
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
|||
; YOUR FILE IN THE BUILD PROCESS. |
|||
; |
|||
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
|||
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
|||
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
|||
; SETTINGS. |
|||
; |
|||
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
|||
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
|||
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
|||
; |
|||
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
|||
; DIRECTORIES ABOVE THIS ONE). |
|||
; |
|||
#include "cfg_dyno.asm" |
|||
; |
|||
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ |
|||
; |
|||
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
|||
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) |
|||
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
|||
; |
|||
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
|||
;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG |
|||
;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG |
|||
; |
|||
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
|||
; |
|||
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
|||
@ -0,0 +1,370 @@ |
|||
|
|||
;================================================================================================== |
|||
; Benchmark BQ4845P RTC Driver |
|||
;================================================================================================== |
|||
|
|||
|
|||
; Register Addresses (HEX / BCD): |
|||
|
|||
; +---+-----+--------------+-------------------+------------------+----------------+ |
|||
; |ADR| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | RANGE | REGISTER | |
|||
; +---+-----+--------------+-------------------+------------------+----------------+ |
|||
; | 0 | 0 | 10-Second | 1-Second | 00-59 | Seconds | |
|||
; +---+-----+----+---------+-------------------+------------------+----------------+ |
|||
; | | ALM1|ALM2| | | | | |
|||
; | 1 | | 10-Second | 1-Second | 00-59 | Seconds Alarm | |
|||
; +---+-----+--------------+-------------------+------------------+----------------+ |
|||
; | 2 | 0 | 10-Minute | 1-Minute | 00-59 | Minutes | |
|||
; +---+-----+----+---------+-------------------+------------------+----------------+ |
|||
; | | ALM1|ARM0| | | | | |
|||
; | 3 | | 10-Minute | 1-Minute | 00-59 | Minutes Alarm | |
|||
; +---+-----+----+---------+-------------------+------------------+----------------+ |
|||
; | 4 |PM/AM| 0 | 10-Hour | 1-Hour |01-12 AM/81-92 PM | Hours | |
|||
; +---+-----+----+----+----+-------------------+------------------+----------------+ |
|||
; | | ALM1| | | | | | |
|||
; | 5 |PM/AM|ALM0| 10-Hour | 1-Hour |01-12 AM/81-92 PM | Hours Alarm | |
|||
; +---+-----+----+----+----+-------------------+------------------+----------------+ |
|||
; | 6 | 0 | 0 | 10-Day | 1-Day | 01-31 | Day | |
|||
; +---+-----+----+----+----+-------------------+------------------+----------------+ |
|||
; | 7 | ALM1|ALM0| 10-day | 1-Day | 01-31 | Day Alarm | |
|||
; +---+-----+----+----+----+----+--------------+------------------+----------------+ |
|||
; | 8 | 0 | 0 | 0 | 0 | 0 | Day Of Week | 01-07 | Day Of Week | |
|||
; +---+-----+----+----+----+----+--------------+------------------+----------------+ |
|||
; | 9 | 0 | 0 | 0 |10Mo| 1-Month | 01-12 | Month | |
|||
; +---+-----+----+----+----+-------------------+------------------+----------------+ |
|||
; | A | 10-Year | 1-Year | 00-99 | Year | |
|||
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
|||
; | B | * | WD2| WD1| WD0| RS3| RS2| RS1| RS0| | Rates | |
|||
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
|||
; | C | * | * | * | * | AIE| PIE|PWRE| ABE| | Interrupt | |
|||
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
|||
; | D | * | * | * | * | AF | PF |PWRF| BVF| | Flags | |
|||
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
|||
; | E | * | * | * | * | UTI|STOP|2412| DSE| | Control | |
|||
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
|||
; | F | * | * | * | * | * | * | * | * | | Unused | |
|||
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
|||
|
|||
; * = Unused bits; unwritable and read as 0. |
|||
; 0 = should be set to 0 for valid time/calendar range. |
|||
; Clock calendar data is BCD. Automatic leap year adjustment. |
|||
; PM/AM = 1 for PM; PM/AM = 0 for AM. |
|||
; DSE = 1 enable daylight savings adjustment. |
|||
; 24/12 = 1 enable 24-hour data representation; 24/12 = 0 enables 12-hour data representation. |
|||
; Day-Of-Week coded as Sunday = 1 through Saturday = 7. |
|||
; BVF = 1 for valid battery. |
|||
; STOP = 1 turns the RTC on; STOP = 0 stops the RTC in back-up mode. |
|||
|
|||
; Constants |
|||
|
|||
BQRTC_SEC .EQU BQRTC_BASE + $00 |
|||
BQRTC_SEC_ALM .EQU BQRTC_BASE + $01 |
|||
BQRTC_MIN .EQU BQRTC_BASE + $02 |
|||
BQRTC_MIN_ALM .EQU BQRTC_BASE + $03 |
|||
BQRTC_HOUR .EQU BQRTC_BASE + $04 |
|||
BQRTC_HOUR_ALM .EQU BQRTC_BASE + $05 |
|||
BQRTC_DAY .EQU BQRTC_BASE + $06 |
|||
BQRTC_DAY_ALM .EQU BQRTC_BASE + $07 |
|||
BQRTC_WEEK_DAY .EQU BQRTC_BASE + $08 |
|||
BQRTC_MONTH .EQU BQRTC_BASE + $09 |
|||
BQRTC_YEAR .EQU BQRTC_BASE + $0A |
|||
BQRTC_RATE .EQU BQRTC_BASE + $0B |
|||
BQRTC_INTERRUPT .EQU BQRTC_BASE + $0C |
|||
BQRTC_FLAGS .EQU BQRTC_BASE + $0D |
|||
BQRTC_CONTROL .EQU BQRTC_BASE + $0E |
|||
BQRTC_UNUSED .EQU BQRTC_BASE + $0F |
|||
|
|||
BQRTC_HIGH .EQU %11110000 |
|||
BQRTC_LOW .EQU %00001111 |
|||
BQRTC_WD .EQU %01110000 |
|||
BQRTC_RS .EQU %00001111 |
|||
|
|||
BQRTC_BVF .EQU %00000001 |
|||
BQRTC_PWRF .EQU %00000010 |
|||
BQRTC_PF .EQU %00000100 |
|||
BQRTC_AF .EQU %00001000 |
|||
|
|||
BQRTC_DSE .EQU %00000001 |
|||
BQRTC_2412 .EQU %00000010 |
|||
BQRTC_STOP .EQU %00000100 |
|||
BQRTC_UTI .EQU %00001000 |
|||
|
|||
BQRTC_BUFSIZE .EQU 6 ; 6 BYTE BUFFER (YYMMDDHHMMSS) |
|||
|
|||
; RTC Device Initialization Entry |
|||
|
|||
BQRTC_INIT: |
|||
CALL NEWLINE ; Formatting |
|||
PRTS("BQRTC: IO=0x$") |
|||
LD A, BQRTC_BASE |
|||
CALL PRTHEXBYTE |
|||
|
|||
LD A, BQRTC_DSE | BQRTC_2412 | BQRTC_UTI |
|||
OUT0 (BQRTC_CONTROL), A ; Enable Daylight Savings and 24 Hour |
|||
|
|||
XOR A ; Zero A |
|||
OUT0 (BQRTC_RATE), A ; Disable Periodic Interrupt Rate |
|||
OUT0 (BQRTC_INTERRUPT), A ; Disable Interrupts |
|||
|
|||
CALL BQRTC_LOAD |
|||
; DISPLAY CURRENT TIME |
|||
PRTS(" $") |
|||
LD A, (BQRTC_BUF_MON) |
|||
CALL PRTHEXBYTE |
|||
PRTS("/$") |
|||
LD A, (BQRTC_BUF_DAY) |
|||
CALL PRTHEXBYTE |
|||
PRTS("/$") |
|||
LD A, (BQRTC_BUF_YEAR) |
|||
CALL PRTHEXBYTE |
|||
PRTS(" $") |
|||
LD A, (BQRTC_BUF_HOUR) |
|||
CALL PRTHEXBYTE |
|||
PRTS(":$") |
|||
LD A, (BQRTC_BUF_MIN) |
|||
CALL PRTHEXBYTE |
|||
PRTS(":$") |
|||
LD A, (BQRTC_BUF_SEC) |
|||
CALL PRTHEXBYTE |
|||
|
|||
XOR A ; Signal success |
|||
RET |
|||
|
|||
; RTC Device Function Dispatch Entry |
|||
; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
|||
; B: Function (IN) |
|||
|
|||
BQRTC_DISPATCH: |
|||
LD A, B ; Get requested function |
|||
AND $0F ; Isolate Sub-Function |
|||
JP Z, BQRTC_GETTIM ; Get Time |
|||
DEC A |
|||
JP Z, BQRTC_SETTIM ; Set Time |
|||
DEC A |
|||
JP Z, BQRTC_GETBYT ; Get NVRAM Byte Value |
|||
DEC A |
|||
JP Z, BQRTC_SETBYT ; Set NVRAM Byte Value |
|||
DEC A |
|||
JP Z, BQRTC_GETBLK ; Get NVRAM Data Block Value |
|||
DEC A |
|||
JP Z, BQRTC_SETBLK ; Set NVRAM Data Block Value |
|||
DEC A |
|||
JP Z, BQRTC_GETALM ; Get Alarm |
|||
DEC A |
|||
JP Z, BQRTC_SETALM ; Set Alarm |
|||
; |
|||
; NVRAM FUNCTIONS ARE NOT AVAILABLE |
|||
; |
|||
BQRTC_GETBYT: |
|||
BQRTC_SETBYT: |
|||
BQRTC_GETBLK: |
|||
BQRTC_SETBLK: |
|||
CALL PANIC |
|||
|
|||
; RTC Get Time |
|||
; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
|||
; HL: Date/Time Buffer (OUT) |
|||
; Buffer format is BCD: YYMMDDHHMMSS |
|||
; 24 hour time format is assumed |
|||
; |
|||
BQRTC_GETTIM: |
|||
EX DE, HL |
|||
CALL BQRTC_LOAD |
|||
; Now copy to read destination (Interbank Save) |
|||
LD A, BID_BIOS ; Copy from BIOS bank |
|||
LD (HB_SRCBNK), A ; Set it |
|||
LD A, (HB_INVBNK) ; Copy to current user bank |
|||
LD (HB_DSTBNK), A ; Set it |
|||
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
|||
#IF (INTMODE == 1) |
|||
DI |
|||
#ENDIF |
|||
CALL HB_BNKCPY ; Copy the clock data |
|||
#IF (INTMODE == 1) |
|||
EI |
|||
#ENDIF |
|||
; |
|||
; CLEAN UP AND RETURN |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET ; AND RETURN |
|||
; |
|||
; RTC Set Time |
|||
; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
|||
; HL: Date/Time Buffer (IN) |
|||
; Buffer Format is BCD: YYMMDDHHMMSS |
|||
; 24 hour time format is assumed |
|||
; |
|||
BQRTC_SETTIM: |
|||
; |
|||
; Copy incoming time data to our time buffer |
|||
LD A, (HB_INVBNK) ; Copy from current user bank |
|||
LD (HB_SRCBNK), A ; Set it |
|||
LD A, BID_BIOS ; Copy to BIOS bank |
|||
LD (HB_DSTBNK), A ; Set it |
|||
LD DE, BQRTC_BUF ; Destination Address |
|||
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
|||
#IF (INTMODE == 1) |
|||
DI |
|||
#ENDIF |
|||
CALL HB_BNKCPY ; Copy the clock data |
|||
#IF (INTMODE == 1) |
|||
EI |
|||
#ENDIF |
|||
; Write to clock |
|||
LD HL, BQRTC_BUF |
|||
CALL BQRTC_SUSPEND |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_YEAR), A ; Write Year |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_MONTH), A ; Write Month |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_DAY), A ; Write Day |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_HOUR), A ; Write Hour |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_MIN), A ; Write Minute |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_SEC), A ; Write Second |
|||
CALL BQRTC_RESUME |
|||
; clean up and return |
|||
XOR A ; Signal success |
|||
RET ; And return |
|||
|
|||
; RTC Get Alarm |
|||
; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
|||
; HL: Date/Time Buffer (OUT) |
|||
; Buffer format is BCD: YYMMDDHHMMSS |
|||
; 24 hour time format is assumed |
|||
; |
|||
BQRTC_GETALM: |
|||
EX DE, HL |
|||
LD HL, BQRTC_BUF |
|||
PUSH HL ; Save address of source buffer |
|||
CALL BQRTC_SUSPEND |
|||
XOR A |
|||
LD (HL), A ; Read Year |
|||
INC HL |
|||
LD (HL), A ; Read Month |
|||
INC HL |
|||
IN0 A, (BQRTC_DAY_ALM) ; Read Day |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_HOUR_ALM) ; Read Hour |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_MIN_ALM) ; Read Minute |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_SEC_ALM) ; Read Second |
|||
LD (HL), A |
|||
CALL BQRTC_RESUME |
|||
POP HL ; Restore address of source buffer |
|||
; Now copy to read destination (Interbank Save) |
|||
LD A, BID_BIOS ; Copy from BIOS bank |
|||
LD (HB_SRCBNK), A ; Set it |
|||
LD A, (HB_INVBNK) ; Copy to current user bank |
|||
LD (HB_DSTBNK), A ; Set it |
|||
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
|||
#IF (INTMODE == 1) |
|||
DI |
|||
#ENDIF |
|||
CALL HB_BNKCPY ; Copy the clock data |
|||
#IF (INTMODE == 1) |
|||
EI |
|||
#ENDIF |
|||
; |
|||
; CLEAN UP AND RETURN |
|||
XOR A ; SIGNAL SUCCESS |
|||
RET ; AND RETURN |
|||
; |
|||
; RTC Set Alarm |
|||
; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
|||
; HL: Date/Time Buffer (IN) |
|||
; Buffer Format is BCD: YYMMDDHHMMSS |
|||
; 24 hour time format is assumed |
|||
; |
|||
BQRTC_SETALM: |
|||
; Copy incoming time data to our time buffer |
|||
LD A, (HB_INVBNK) ; Copy from current user bank |
|||
LD (HB_SRCBNK), A ; Set it |
|||
LD A, BID_BIOS ; Copy to BIOS bank |
|||
LD (HB_DSTBNK), A ; Set it |
|||
LD DE, BQRTC_BUF ; Destination Address |
|||
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
|||
#IF (INTMODE == 1) |
|||
DI |
|||
#ENDIF |
|||
CALL HB_BNKCPY ; Copy the clock data |
|||
#IF (INTMODE == 1) |
|||
EI |
|||
#ENDIF |
|||
; Write to clock |
|||
LD HL, BQRTC_BUF_DAY |
|||
CALL BQRTC_SUSPEND |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_DAY_ALM), A ; Write Day |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_HOUR_ALM), A ; Write Hour |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_MIN_ALM), A ; Write Minute |
|||
INC HL |
|||
LD A, (HL) |
|||
OUT0 (BQRTC_SEC_ALM), A ; Write Second |
|||
CALL BQRTC_RESUME |
|||
; clean up and return |
|||
XOR A ; Signal success |
|||
RET ; And return |
|||
|
|||
BQRTC_SUSPEND: |
|||
IN0 A, (BQRTC_CONTROL) ; Suspend Clock |
|||
OR BQRTC_UTI |
|||
OUT0 (BQRTC_CONTROL), A |
|||
RET |
|||
|
|||
BQRTC_RESUME: |
|||
IN0 A, (BQRTC_CONTROL) ; Resume Clock |
|||
AND ~BQRTC_UTI |
|||
OUT0 (BQRTC_CONTROL), A |
|||
RET |
|||
|
|||
BQRTC_LOAD: |
|||
LD HL, BQRTC_BUF |
|||
PUSH HL ; Save address of source buffer |
|||
CALL BQRTC_SUSPEND |
|||
IN0 A, (BQRTC_YEAR) ; Read Year |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_MONTH) ; Read Month |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_DAY) ; Read Day |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_HOUR) ; Read Hour |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_MIN) ; Read Minute |
|||
LD (HL), A |
|||
INC HL |
|||
IN0 A, (BQRTC_SEC) ; Read Second |
|||
LD (HL), A |
|||
CALL BQRTC_RESUME |
|||
POP HL ; Restore address of source buffer |
|||
RET |
|||
|
|||
; Working Variables |
|||
|
|||
BQRTC_BUF: |
|||
BQRTC_BUF_YEAR: .DB 0 ; Year |
|||
BQRTC_BUF_MON: .DB 0 ; Month |
|||
BQRTC_BUF_DAY: .DB 0 ; Day |
|||
BQRTC_BUF_HOUR: .DB 0 ; Hour |
|||
BQRTC_BUF_MIN: .DB 0 ; Minute |
|||
BQRTC_BUF_SEC: .DB 0 ; Second |
|||
@ -0,0 +1,133 @@ |
|||
; |
|||
;================================================================================================== |
|||
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014 |
|||
;================================================================================================== |
|||
; |
|||
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
|||
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD |
|||
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY |
|||
; UNDER THIS DIRECTORY. |
|||
; |
|||
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS |
|||
; FOR THE PLATFORM. |
|||
; |
|||
#DEFINE PLATFORM_NAME "DYNO" |
|||
; |
|||
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] |
|||
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180] |
|||
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
|||
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
|||
; |
|||
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT |
|||
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT |
|||
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT |
|||
; |
|||
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ |
|||
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 |
|||
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) |
|||
; |
|||
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
|||
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] |
|||
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE |
|||
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) |
|||
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) |
|||
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) |
|||
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) |
|||
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) |
|||
; |
|||
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS |
|||
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
|||
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) |
|||
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
|||
; |
|||
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR |
|||
; |
|||
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT |
|||
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS |
|||
; |
|||
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT |
|||
; |
|||
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT |
|||
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS |
|||
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS |
|||
; |
|||
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) |
|||
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS |
|||
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED |
|||
; |
|||
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) |
|||
; |
|||
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
|||
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] |
|||
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
; |
|||
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT |
|||
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) |
|||
; |
|||
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
|||
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] |
|||
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) |
|||
; |
|||
BQRTCENABLE .EQU TRUE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) |
|||
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS |
|||
; |
|||
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
|||
; |
|||
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
|||
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG |
|||
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG |
|||
; |
|||
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
|||
; |
|||
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
|||
; |
|||
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) |
|||
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) |
|||
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM) |
|||
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
|||
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
|||
; |
|||
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
|||
; |
|||
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER |
|||
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180] |
|||
; |
|||
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
|||
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
; |
|||
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
|||
FDMODE .EQU FDMODE_DYNO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO] |
|||
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) |
|||
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111] |
|||
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111] |
|||
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS |
|||
; |
|||
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
|||
; |
|||
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
|||
IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE] |
|||
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) |
|||
; |
|||
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
|||
PPIDEMODE .EQU PPIDEMODE_DYNO ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] |
|||
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) |
|||
; |
|||
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
|||
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] |
|||
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY |
|||
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
|||
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE |
|||
; |
|||
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
|||
; |
|||
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
|||
; |
|||
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) |
|||
; |
|||
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
|||
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) |
|||
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP |
|||
; |
|||
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) |
|||
Binary file not shown.
Binary file not shown.
Some files were not shown because too many files changed in this diff
Loading…
Reference in new issue