Merge pull request #144 from wwarthen/dev

Dev

Source/Doc/Architecture.md

@@ -701,7 +701,7 @@ Write Block Count sectors to buffer address starting at current target
 sector. Current sector must be established by prior seek function; however,
 multiple read/write/verify function calls can be made after a seek
 function. Current sector is incremented after each sector successfully
-written. On error, current sector is sector is sector where error occurred.
+written. On error, current sector is sector where error occurred.
 Blocks written indicates number of sectors successfully written.
 
 Caller must ensure: 1) buffer address is large enough to contain data for

Source/HBIOS/cfg_dyno.asm

@@ -36,6 +36,8 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)

Source/HBIOS/cfg_ezz80.asm

@@ -35,6 +35,8 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;

Source/HBIOS/cfg_master.asm

@@ -35,6 +35,8 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)

Source/HBIOS/cfg_mk4.asm

@@ -31,6 +31,8 @@ RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)

Source/HBIOS/cfg_n8.asm

@@ -31,6 +31,8 @@ RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.EQU	MM_N8		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	0		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 Z180_BASE	.EQU	$40		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)

Source/HBIOS/cfg_rcz180.asm

@@ -36,6 +36,8 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)

Source/HBIOS/cfg_rcz280.asm

@@ -35,6 +35,8 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 Z280_MEMWAIT	.EQU	0		; Z280: MEMORY WAIT STATES (0-3)
 Z280_IOWAIT	.EQU	1		; Z280: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
 Z280_INTWAIT	.EQU	0		; Z280: INT ACK WAIT STATUS (0-3)

Source/HBIOS/cfg_rcz80.asm

@@ -35,6 +35,8 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT

Source/HBIOS/cfg_sbc.asm

@@ -32,6 +32,8 @@ MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;
@@ -202,5 +204,3 @@ AY38910ENABLE	.EQU	FALSE		; AY: AY-3-8910 / YM2149 SOUND DRIVER
 AY_CLK		.EQU	CPUOSC / 4	; DEFAULT TO CPUOSC / 4
 AYMODE		.EQU	AYMODE_SCG	; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
 SPKENABLE	.EQU	FALSE		; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
-;
-FFENABLE	.EQU	TRUE		; ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER

Source/HBIOS/cfg_scz180.asm

@@ -31,6 +31,8 @@ RAMSIZE		.EQU	512		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 MEMMGR		.EQU	MM_Z180		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 RAMBIAS		.EQU	512		; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 Z180_BASE	.EQU	$C0		; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
 Z180_CLKDIV	.EQU	1		; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
 Z180_MEMWAIT	.EQU	0		; Z180: MEMORY WAIT STATES (0-3)

Source/HBIOS/cfg_zeta.asm

@@ -32,6 +32,8 @@ MEMMGR		.EQU	MM_SBC		; MM_[SBC|Z2|N8|Z180|Z280|ZRC]: MEMORY MANAGER
 MPCL_RAM	.EQU	$78		; SBC MEM MGR RAM PAGE SELECT REG (WRITE ONLY)
 MPCL_ROM	.EQU	$7C		; SBC MEM MGR ROM PAGE SELECT REG (WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;

Source/HBIOS/cfg_zeta2.asm

@@ -35,6 +35,8 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+FFENABLE	.EQU	FALSE		; FF: ENABLE FLASH/EEPROM IDENTIFICATION/DRIVER
+;
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;

Source/HBIOS/flashfs.asm

@@ -148,4 +148,4 @@ FF_CHIP(0C2A4H,"MX29F040$  ",512,ST_NORMAL)
 ;
 FF_T_CNT	.EQU	($-FF_TABLE) / 17
 FF_UNKNOWN	.DB	"UNKNOWN$"
-FF_STACK:	.DW	0
+FF_STACK:	.DW	0