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Preliminary support for Dyno Computer

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Dyno Computer is the work of Steve Garcia and much of the code checked in is based on his work.
This commit is contained in:
Wayne Warthen
2020-01-05 15:26:08 -08:00
parent 8bc4a40662
commit 3c8cd5219e
28 changed files with 723 additions and 83 deletions
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78
Source/Apps/FDU/FDU.asm
View File

@@ -44,6 +44,7 @@
; 2018-09-05: v5.3 ADDED SUPPORT FOR SMALLZ80
; - USE EOT=R TO END R/W AFTER ONE SECTOR INSTEAD
; OF USING PULSE TC
; 2020-01-05: V5.4 ADDED SUPPORT FOR DYNO FDC
;
;_______________________________________________________________________________
;
@@ -77,6 +78,7 @@ FDC_N8 .EQU 5
FDC_RCSMC .EQU 6
FDC_RCWDC .EQU 7
FDC_SMZ80 .EQU 8
FDC_DYNO .EQU 9
;
; FDC MODE
;
@@ -211,8 +213,8 @@ INIT5:
XOR A
RET
STR_BANNER .DB "Floppy Disk Utility (FDU) v5.3, 28-Sep-2018$"
STR_BANNER2 .DB "Copyright (C) 2018, Wayne Warthen, GNU GPL v3","$"
STR_BANNER .DB "Floppy Disk Utility (FDU) v5.4, 05-jAN-2020$"
STR_BANNER2 .DB "Copyright (C) 2020, Wayne Warthen, GNU GPL v3","$"
STR_HBIOS .DB " [HBIOS]$"
STR_UBIOS .DB " [UBIOS]$"
;
@@ -232,19 +234,18 @@ FDCSEL:
CALL WRITESTR
;
FDCSEL1:
CALL GETKEY
SUB '0' ; ASCII -> BINARY
CP FDCCNT + 1 ; TOO HIGH?
CALL GETKEYUC
CP 'X' ; EXIT?
JR NZ,FDCSEL2 ; IF NOT, CONTINUE
OR 0FFH ; ELSE SET NZ FOR EXIT REQUEST
RET ; AND RETURN
;
FDCSEL2:
SUB 'A' ; ASCII -> BINARY
CP FDCCNT ; TOO HIGH?
JR NC,FDCSEL1 ; IF SO, TRY AGAIN
;
OR A ; SET FLAGS
JR NZ,FDCSEL2 ; NOT ZERO, KEEP GOING
OR 0FFH ; SET NZ FOR EXIT REQUEST
RET ; AND RETURN
;
FDCSEL2:
; SAVE SELECTED FDC IDENTIFIER
DEC A ; CONVERT TO ZERO-BASED FDC ID
LD (FDCID),A ; RECORD THE FDC ID
RLCA ; TIMES 4
RLCA ; ... FOR 4 BYTE ENTRIES
@@ -282,6 +283,7 @@ FDCTBL: ; LABEL CONFIG DATA
.DW STR_RCSMC, CFG_RCSMC
.DW STR_RCWDC, CFG_RCWDC
.DW STR_SMZ80, CFG_SMZ80
.DW STR_DYNO, CFG_DYNO
FDCCNT .EQU ($-FDCTBL)/4 ; FD CONTROLLER COUNT
;
; FDC LABEL STRINGS
@@ -295,6 +297,7 @@ STR_N8 .TEXT "N8$"
STR_RCSMC .TEXT "RC-SMC$"
STR_RCWDC .TEXT "RC-WDC$"
STR_SMZ80 .TEXT "SMZ80$"
STR_DYNO .TEXT "DYNO$"
;
; FDC CONFIGURATION BLOCKS
;
@@ -405,6 +408,17 @@ CFG_SMZ80:
.DB 0FFH ; PSEUDO DMA DATA PORT
.DB _PCAT ; MODE=
;
CFG_DYNO:
.DB 084H ; FDC MAIN STATUS REGISTER
.DB 085H ; FDC DATA PORT
.DB 0FFH ; DATA INPUT REGISTER
.DB 086H ; DIGITAL OUTPUT REGISTER (LATCH)
.DB 087H ; DCR
.DB 0FFH ; DACK
.DB 086H ; TERMINAL COUNT (W/ DACK)
.DB 0FFH ; PSEUDO DMA DATA PORT
.DB _PCAT ; MODE=
;
FDCID .DB 0 ; FDC IDENTIFIER (0 INDEXED)
FDCBM .DB 0 ; FDC ID BITMAP
FDCLBL .DW 0 ; POINTER TO ACTIVE FDC LABEL STRING
@@ -413,16 +427,17 @@ FDCCFG .DW 0 ; POINTER TO ACTIVE CFG DATA
FSS_MENU:
.TEXT "\r\n"
.TEXT "SELECT FLOPPY DISK CONTROLLER:\r\n"
.TEXT " (0) Exit\r\n"
.TEXT " (1) Disk IO ECB Board\r\n"
.TEXT " (2) Disk IO 3 ECB Board\r\n"
.TEXT " (3) Zeta SBC Onboard FDC\r\n"
.TEXT " (4) Zeta 2 SBC Onboard FDC\r\n"
.TEXT " (5) Dual IDE ECB Board\r\n"
.TEXT " (6) N8 Onboard FDC\r\n"
.TEXT " (7) RC2014 SMC (SMB)\r\n"
.TEXT " (8) RC2014 WDC (SMB)\r\n"
.TEXT " (9) SmallZ80 Expansion\r\n"
.TEXT " (A) Disk IO ECB Board\r\n"
.TEXT " (B) Disk IO 3 ECB Board\r\n"
.TEXT " (C) Zeta SBC Onboard FDC\r\n"
.TEXT " (D) Zeta 2 SBC Onboard FDC\r\n"
.TEXT " (E) Dual IDE ECB Board\r\n"
.TEXT " (F) N8 Onboard FDC\r\n"
.TEXT " (G) RC2014 SMC (SMB)\r\n"
.TEXT " (H) RC2014 WDC (SMB)\r\n"
.TEXT " (I) SmallZ80 Expansion\r\n"
.TEXT " (J) Dyno-Card FDC, D1030\r\n"
.TEXT " (X) Exit\r\n"
.TEXT "=== OPTION ===> $\r\n"
;
;===============================================================================
@@ -1499,8 +1514,9 @@ MD_MAP:
.DB %00000001 ; DIDE POLL
.DB %00000001 ; N8 POLL
.DB %00000001 ; RCSMC POLL
; .DB %00000001 ; RCWDC POLL
.DB %00000001 ; RCWDC POLL
.DB %00000001 ; SMZ80 POLL
.DB %00000001 ; DYNO POLL
;
; MEDIA DESCRIPTION BLOCK
;
@@ -1861,7 +1877,7 @@ FM_DRAW0B: ; ZETA, DIO3
LD A,(FST_DOR)
AND 00000010B
JR FM_DRAW1
FM_DRAW0C: ; DIDE, N8, ZETA2, RCWDC, SMZ80
FM_DRAW0C: ; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO
LD A,(FST_DOR)
AND 11110000B
JR FM_DRAW1
@@ -2014,7 +2030,7 @@ FM_MOTOR0B: ; ZETA, DIO3
LD A,(FST_DOR)
AND 00000010B
JR FM_MOTOR1
FM_MOTOR0C: ; DIDE, N8, ZETA2, RCWDC, SMZ80
FM_MOTOR0C: ; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO
LD A,(FST_DOR)
AND 11110000B
JR FM_MOTOR1
@@ -2753,7 +2769,7 @@ FC_INIT1: ; DIO
FC_INIT2: ; ZETA, DIO3
LD A,(FCD_DORB)
JR FC_INIT5
FC_INIT3: ; DIDE, N8, ZETA2, RCWDC, SMZ80
FC_INIT3: ; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO
LD A,(FCD_DORC)
JR FC_INIT5
FC_INIT4: ; WDSMC
@@ -2797,7 +2813,7 @@ FC_RESETFDC1: ; ZETA, DIO3, RCSMC
POP AF
OUT (C),A
JR FC_RESETFDC3
FC_RESETFDC2: ; DIDE, N8, ZETA2, RCWDC, SMZ80
FC_RESETFDC2: ; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO
LD A,0
OUT (C),A
LD A,(FST_DOR)
@@ -2824,7 +2840,7 @@ FC_PULSETC:
;RES 0,A
;OUT (C),A
;JR FC_PULSETC2
;FC_PULSETC1: ; DIDE, N8, ZETA2, RCWDC, SMZ80
;FC_PULSETC1: ; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO
;LD C,(IY+CFG_TC)
;IN A,(C)
;JR FC_PULSETC2
@@ -2856,7 +2872,7 @@ FC_MOTORON2: ; ZETA, DIO3
LD HL,FST_DOR ; POINT TO FDC_DOR
SET 1,(HL)
JR FC_MOTORON5
FC_MOTORON3: ; DIDE, N8, ZETA2, RCWDC, SMZ80
FC_MOTORON3: ; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO
LD HL,FST_DOR ; POINT TO FDC_DOR
LD A,(HL) ; START WITH CURRENT DOR
AND 11111100B ; GET RID OF ANY ACTIVE DS BITS
@@ -2920,7 +2936,7 @@ FC_MOTOROFF2: ; ZETA, DIO3
LD HL,FST_DOR ; POINT TO FDC_DOR
RES 1,(HL)
JR FC_MOTOROFF5
FC_MOTOROFF3: ; DIDE, N8, ZETA2, RCWDC, SMZ80
FC_MOTOROFF3: ; DIDE, N8, ZETA2, RCWDC, SMZ80, DYNO
LD HL,FST_DOR ; POINT TO FDC_DOR
LD A,DORC_INIT
LD (HL),A
@@ -3786,7 +3802,7 @@ DORB_BR500 .EQU 10100000B ; 500KBPS
;
DORB_INIT .EQU DORB_BR250
;
; *** DIDE/N8/ZETA2/RCWDC/SMZ80 ***
; *** DIDE/N8/ZETA2/RCWDC/SMZ80/DYNO ***
;
DORC_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED
;

13
Source/Apps/FDU/FDU.txt
View File

@@ -1,9 +1,9 @@
================================================================
Floppy Disk Utility (FDU) v5.3 for RetroBrew Computers
Disk IO / Zeta / Dual-IDE / N8 / RC2014 / SmallZ80
Disk IO / Zeta / Dual-IDE / N8 / RC2014 / SmallZ80 / Dyno
================================================================
Updated September 5, 2018
Updated January 5, 2020
by Wayne Warthen (wwarthen@gmail.com)
Application to test the hardware functionality of the Floppy
@@ -77,6 +77,7 @@ supported:
- RC2014 w/ SMC
- RC2014 w/ WDC
- SmallZ80
- Dyno
You must be using either a RomWBW or UBA based OS version.
@@ -96,7 +97,7 @@ appropriate cable:
Disk IO - no twist in cable, drive unit 0/1 must be selected by jumper on drive
DISK IO 3, Zeta, Zeta 2, RC2014 - cable with twist, unit 0 after twist, unit 1 before twist
DIDE, N8, Mark IV, SmallZ80 - cable with twist, unit 0 before twist, unit 1 after twist
DIDE, N8, Mark IV, SmallZ80, Dyno - cable with twist, unit 0 before twist, unit 1 after twist
Note that FDU does not utilize your systems ROM or OS to
access the floppy system. FDU interacts directly with
@@ -154,6 +155,9 @@ JP2 (TC): 2-3.
SmallZ80 does not have any relevant jumper settings. The
hardwired I/O ranges are assumed in the code.
Dyno does not have any relevant jumper settings. The
hardwired I/O ranges are assumed in the code.
Modes of Operation
------------------
@@ -505,3 +509,6 @@ WW 9/5/2018: v5.3
condition is no longer considered an error, but a successful end of
operation.
- Added support for SmallZ80
WW 5/1/2020: v5.4
- Added support for Dyno (based on work by Steve Garcia)

2
Source/CBIOS/ver.inc
View File

@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.23"
#DEFINE BIOSVER "2.9.2-pre.24"

2
Source/CPM3/ver.inc
View File

@@ -3,5 +3,5 @@ rmn equ 9
rup equ 2
rtp equ 0
biosver macro
db "2.9.2-pre.23"
db "2.9.2-pre.24"
endm

2
Source/HBIOS/Build.ps1
View File

@@ -20,7 +20,7 @@ param([string]$Platform = "", [string]$Config = "", [string]$RomSize = "512", [s
# UNA BIOS is simply imbedded, it is not built here.
#
$PlatformListZ80 = "SBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "UNA"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180"
$PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO"
#
# Establish the build platform. It may have been passed in on the command line. Validate

39
Source/HBIOS/Config/DYNO_std.asm Normal file
View File

@@ -0,0 +1,39 @@
;
;==================================================================================================
; DYNO STANDARD CONFIGURATION
;==================================================================================================
;
; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS
; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE
; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
; YOUR FILE IN THE BUILD PROCESS.
;
; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
; SETTINGS.
;
; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
;
; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
; DIRECTORIES ABOVE THIS ONE).
;
#include "cfg_dyno.asm"
;
CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ
;
Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG
;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG
;
FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
;
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)

5
Source/HBIOS/Config/DYNO_wbw.asm Normal file
View File

@@ -0,0 +1,5 @@
#DEFINE PLATFORM_NAME "DYNO (wbw)"
;
#include "cfg_dyno.asm"
;
FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)

370
Source/HBIOS/bqrtc.asm Normal file
View File

@@ -0,0 +1,370 @@
;==================================================================================================
; Benchmark BQ4845P RTC Driver
;==================================================================================================
; Register Addresses (HEX / BCD):
; +---+-----+--------------+-------------------+------------------+----------------+
; |ADR| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | RANGE | REGISTER |
; +---+-----+--------------+-------------------+------------------+----------------+
; | 0 | 0 | 10-Second | 1-Second | 00-59 | Seconds |
; +---+-----+----+---------+-------------------+------------------+----------------+
; | | ALM1|ALM2| | | | |
; | 1 | | 10-Second | 1-Second | 00-59 | Seconds Alarm |
; +---+-----+--------------+-------------------+------------------+----------------+
; | 2 | 0 | 10-Minute | 1-Minute | 00-59 | Minutes |
; +---+-----+----+---------+-------------------+------------------+----------------+
; | | ALM1|ARM0| | | | |
; | 3 | | 10-Minute | 1-Minute | 00-59 | Minutes Alarm |
; +---+-----+----+---------+-------------------+------------------+----------------+
; | 4 |PM/AM| 0 | 10-Hour | 1-Hour |01-12 AM/81-92 PM | Hours |
; +---+-----+----+----+----+-------------------+------------------+----------------+
; | | ALM1| | | | | |
; | 5 |PM/AM|ALM0| 10-Hour | 1-Hour |01-12 AM/81-92 PM | Hours Alarm |
; +---+-----+----+----+----+-------------------+------------------+----------------+
; | 6 | 0 | 0 | 10-Day | 1-Day | 01-31 | Day |
; +---+-----+----+----+----+-------------------+------------------+----------------+
; | 7 | ALM1|ALM0| 10-day | 1-Day | 01-31 | Day Alarm |
; +---+-----+----+----+----+----+--------------+------------------+----------------+
; | 8 | 0 | 0 | 0 | 0 | 0 | Day Of Week | 01-07 | Day Of Week |
; +---+-----+----+----+----+----+--------------+------------------+----------------+
; | 9 | 0 | 0 | 0 |10Mo| 1-Month | 01-12 | Month |
; +---+-----+----+----+----+-------------------+------------------+----------------+
; | A | 10-Year | 1-Year | 00-99 | Year |
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+
; | B | * | WD2| WD1| WD0| RS3| RS2| RS1| RS0| | Rates |
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+
; | C | * | * | * | * | AIE| PIE|PWRE| ABE| | Interrupt |
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+
; | D | * | * | * | * | AF | PF |PWRF| BVF| | Flags |
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+
; | E | * | * | * | * | UTI|STOP|2412| DSE| | Control |
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+
; | F | * | * | * | * | * | * | * | * | | Unused |
; +---+-----+----+----+----+----+----+----+----+------------------+----------------+
; * = Unused bits; unwritable and read as 0.
; 0 = should be set to 0 for valid time/calendar range.
; Clock calendar data is BCD. Automatic leap year adjustment.
; PM/AM = 1 for PM; PM/AM = 0 for AM.
; DSE = 1 enable daylight savings adjustment.
; 24/12 = 1 enable 24-hour data representation; 24/12 = 0 enables 12-hour data representation.
; Day-Of-Week coded as Sunday = 1 through Saturday = 7.
; BVF = 1 for valid battery.
; STOP = 1 turns the RTC on; STOP = 0 stops the RTC in back-up mode.
; Constants
BQRTC_SEC .EQU BQRTC_BASE + $00
BQRTC_SEC_ALM .EQU BQRTC_BASE + $01
BQRTC_MIN .EQU BQRTC_BASE + $02
BQRTC_MIN_ALM .EQU BQRTC_BASE + $03
BQRTC_HOUR .EQU BQRTC_BASE + $04
BQRTC_HOUR_ALM .EQU BQRTC_BASE + $05
BQRTC_DAY .EQU BQRTC_BASE + $06
BQRTC_DAY_ALM .EQU BQRTC_BASE + $07
BQRTC_WEEK_DAY .EQU BQRTC_BASE + $08
BQRTC_MONTH .EQU BQRTC_BASE + $09
BQRTC_YEAR .EQU BQRTC_BASE + $0A
BQRTC_RATE .EQU BQRTC_BASE + $0B
BQRTC_INTERRUPT .EQU BQRTC_BASE + $0C
BQRTC_FLAGS .EQU BQRTC_BASE + $0D
BQRTC_CONTROL .EQU BQRTC_BASE + $0E
BQRTC_UNUSED .EQU BQRTC_BASE + $0F
BQRTC_HIGH .EQU %11110000
BQRTC_LOW .EQU %00001111
BQRTC_WD .EQU %01110000
BQRTC_RS .EQU %00001111
BQRTC_BVF .EQU %00000001
BQRTC_PWRF .EQU %00000010
BQRTC_PF .EQU %00000100
BQRTC_AF .EQU %00001000
BQRTC_DSE .EQU %00000001
BQRTC_2412 .EQU %00000010
BQRTC_STOP .EQU %00000100
BQRTC_UTI .EQU %00001000
BQRTC_BUFSIZE .EQU 6 ; 6 BYTE BUFFER (YYMMDDHHMMSS)
; RTC Device Initialization Entry
BQRTC_INIT:
CALL NEWLINE ; Formatting
PRTS("BQRTC: IO=0x$")
LD A, BQRTC_BASE
CALL PRTHEXBYTE
LD A, BQRTC_DSE | BQRTC_2412 | BQRTC_UTI
OUT0 (BQRTC_CONTROL), A ; Enable Daylight Savings and 24 Hour
XOR A ; Zero A
OUT0 (BQRTC_RATE), A ; Disable Periodic Interrupt Rate
OUT0 (BQRTC_INTERRUPT), A ; Disable Interrupts
CALL BQRTC_LOAD
; DISPLAY CURRENT TIME
PRTS(" $")
LD A, (BQRTC_BUF_MON)
CALL PRTHEXBYTE
PRTS("/$")
LD A, (BQRTC_BUF_DAY)
CALL PRTHEXBYTE
PRTS("/$")
LD A, (BQRTC_BUF_YEAR)
CALL PRTHEXBYTE
PRTS(" $")
LD A, (BQRTC_BUF_HOUR)
CALL PRTHEXBYTE
PRTS(":$")
LD A, (BQRTC_BUF_MIN)
CALL PRTHEXBYTE
PRTS(":$")
LD A, (BQRTC_BUF_SEC)
CALL PRTHEXBYTE
XOR A ; Signal success
RET
; RTC Device Function Dispatch Entry
; A: Result (OUT), 0=OK, Z=OK, NZ=Error
; B: Function (IN)
BQRTC_DISPATCH:
LD A, B ; Get requested function
AND $0F ; Isolate Sub-Function
JP Z, BQRTC_GETTIM ; Get Time
DEC A
JP Z, BQRTC_SETTIM ; Set Time
DEC A
JP Z, BQRTC_GETBYT ; Get NVRAM Byte Value
DEC A
JP Z, BQRTC_SETBYT ; Set NVRAM Byte Value
DEC A
JP Z, BQRTC_GETBLK ; Get NVRAM Data Block Value
DEC A
JP Z, BQRTC_SETBLK ; Set NVRAM Data Block Value
DEC A
JP Z, BQRTC_GETALM ; Get Alarm
DEC A
JP Z, BQRTC_SETALM ; Set Alarm
;
; NVRAM FUNCTIONS ARE NOT AVAILABLE
;
BQRTC_GETBYT:
BQRTC_SETBYT:
BQRTC_GETBLK:
BQRTC_SETBLK:
CALL PANIC
; RTC Get Time
; A: Result (OUT), 0=OK, Z=OK, NZ=Error
; HL: Date/Time Buffer (OUT)
; Buffer format is BCD: YYMMDDHHMMSS
; 24 hour time format is assumed
;
BQRTC_GETTIM:
EX DE, HL
CALL BQRTC_LOAD
; Now copy to read destination (Interbank Save)
LD A, BID_BIOS ; Copy from BIOS bank
LD (HB_SRCBNK), A ; Set it
LD A, (HB_INVBNK) ; Copy to current user bank
LD (HB_DSTBNK), A ; Set it
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes
#IF (INTMODE == 1)
DI
#ENDIF
CALL HB_BNKCPY ; Copy the clock data
#IF (INTMODE == 1)
EI
#ENDIF
;
; CLEAN UP AND RETURN
XOR A ; SIGNAL SUCCESS
RET ; AND RETURN
;
; RTC Set Time
; A: Result (OUT), 0=OK, Z=OK, NZ=Error
; HL: Date/Time Buffer (IN)
; Buffer Format is BCD: YYMMDDHHMMSS
; 24 hour time format is assumed
;
BQRTC_SETTIM:
;
; Copy incoming time data to our time buffer
LD A, (HB_INVBNK) ; Copy from current user bank
LD (HB_SRCBNK), A ; Set it
LD A, BID_BIOS ; Copy to BIOS bank
LD (HB_DSTBNK), A ; Set it
LD DE, BQRTC_BUF ; Destination Address
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes
#IF (INTMODE == 1)
DI
#ENDIF
CALL HB_BNKCPY ; Copy the clock data
#IF (INTMODE == 1)
EI
#ENDIF
; Write to clock
LD HL, BQRTC_BUF
CALL BQRTC_SUSPEND
LD A, (HL)
OUT0 (BQRTC_YEAR), A ; Write Year
INC HL
LD A, (HL)
OUT0 (BQRTC_MONTH), A ; Write Month
INC HL
LD A, (HL)
OUT0 (BQRTC_DAY), A ; Write Day
INC HL
LD A, (HL)
OUT0 (BQRTC_HOUR), A ; Write Hour
INC HL
LD A, (HL)
OUT0 (BQRTC_MIN), A ; Write Minute
INC HL
LD A, (HL)
OUT0 (BQRTC_SEC), A ; Write Second
CALL BQRTC_RESUME
; clean up and return
XOR A ; Signal success
RET ; And return
; RTC Get Alarm
; A: Result (OUT), 0=OK, Z=OK, NZ=Error
; HL: Date/Time Buffer (OUT)
; Buffer format is BCD: YYMMDDHHMMSS
; 24 hour time format is assumed
;
BQRTC_GETALM:
EX DE, HL
LD HL, BQRTC_BUF
PUSH HL ; Save address of source buffer
CALL BQRTC_SUSPEND
XOR A
LD (HL), A ; Read Year
INC HL
LD (HL), A ; Read Month
INC HL
IN0 A, (BQRTC_DAY_ALM) ; Read Day
LD (HL), A
INC HL
IN0 A, (BQRTC_HOUR_ALM) ; Read Hour
LD (HL), A
INC HL
IN0 A, (BQRTC_MIN_ALM) ; Read Minute
LD (HL), A
INC HL
IN0 A, (BQRTC_SEC_ALM) ; Read Second
LD (HL), A
CALL BQRTC_RESUME
POP HL ; Restore address of source buffer
; Now copy to read destination (Interbank Save)
LD A, BID_BIOS ; Copy from BIOS bank
LD (HB_SRCBNK), A ; Set it
LD A, (HB_INVBNK) ; Copy to current user bank
LD (HB_DSTBNK), A ; Set it
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes
#IF (INTMODE == 1)
DI
#ENDIF
CALL HB_BNKCPY ; Copy the clock data
#IF (INTMODE == 1)
EI
#ENDIF
;
; CLEAN UP AND RETURN
XOR A ; SIGNAL SUCCESS
RET ; AND RETURN
;
; RTC Set Alarm
; A: Result (OUT), 0=OK, Z=OK, NZ=Error
; HL: Date/Time Buffer (IN)
; Buffer Format is BCD: YYMMDDHHMMSS
; 24 hour time format is assumed
;
BQRTC_SETALM:
; Copy incoming time data to our time buffer
LD A, (HB_INVBNK) ; Copy from current user bank
LD (HB_SRCBNK), A ; Set it
LD A, BID_BIOS ; Copy to BIOS bank
LD (HB_DSTBNK), A ; Set it
LD DE, BQRTC_BUF ; Destination Address
LD BC, BQRTC_BUFSIZE ; Length is 6 bytes
#IF (INTMODE == 1)
DI
#ENDIF
CALL HB_BNKCPY ; Copy the clock data
#IF (INTMODE == 1)
EI
#ENDIF
; Write to clock
LD HL, BQRTC_BUF_DAY
CALL BQRTC_SUSPEND
LD A, (HL)
OUT0 (BQRTC_DAY_ALM), A ; Write Day
INC HL
LD A, (HL)
OUT0 (BQRTC_HOUR_ALM), A ; Write Hour
INC HL
LD A, (HL)
OUT0 (BQRTC_MIN_ALM), A ; Write Minute
INC HL
LD A, (HL)
OUT0 (BQRTC_SEC_ALM), A ; Write Second
CALL BQRTC_RESUME
; clean up and return
XOR A ; Signal success
RET ; And return
BQRTC_SUSPEND:
IN0 A, (BQRTC_CONTROL) ; Suspend Clock
OR BQRTC_UTI
OUT0 (BQRTC_CONTROL), A
RET
BQRTC_RESUME:
IN0 A, (BQRTC_CONTROL) ; Resume Clock
AND ~BQRTC_UTI
OUT0 (BQRTC_CONTROL), A
RET
BQRTC_LOAD:
LD HL, BQRTC_BUF
PUSH HL ; Save address of source buffer
CALL BQRTC_SUSPEND
IN0 A, (BQRTC_YEAR) ; Read Year
LD (HL), A
INC HL
IN0 A, (BQRTC_MONTH) ; Read Month
LD (HL), A
INC HL
IN0 A, (BQRTC_DAY) ; Read Day
LD (HL), A
INC HL
IN0 A, (BQRTC_HOUR) ; Read Hour
LD (HL), A
INC HL
IN0 A, (BQRTC_MIN) ; Read Minute
LD (HL), A
INC HL
IN0 A, (BQRTC_SEC) ; Read Second
LD (HL), A
CALL BQRTC_RESUME
POP HL ; Restore address of source buffer
RET
; Working Variables
BQRTC_BUF:
BQRTC_BUF_YEAR: .DB 0 ; Year
BQRTC_BUF_MON: .DB 0 ; Month
BQRTC_BUF_DAY: .DB 0 ; Day
BQRTC_BUF_HOUR: .DB 0 ; Hour
BQRTC_BUF_MIN: .DB 0 ; Minute
BQRTC_BUF_SEC: .DB 0 ; Second

133
Source/HBIOS/cfg_dyno.asm Normal file
View File

@@ -0,0 +1,133 @@
;
;==================================================================================================
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014
;==================================================================================================
;
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY
; UNDER THIS DIRECTORY.
;
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS
; FOR THE PLATFORM.
;
#DEFINE PLATFORM_NAME "DYNO"
;
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT
;
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)
;
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180]
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY)
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY)
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
;
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
;
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR
;
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS
;
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT
;
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
;
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED)
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED
;
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE)
;
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI]
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM)
;
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU TRUE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG
;
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM)
;
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM)
;
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM)
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM)
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM)
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM)
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM)
;
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM)
;
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180]
;
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_DYNO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS
;
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
;
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE]
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_DYNO ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM)
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT]
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE
;
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
;
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM)
;
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM)
;
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM)
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP
;
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM)

9
Source/HBIOS/cfg_ezz80.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "EASYZ80"
;
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -65,6 +65,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
@@ -108,7 +111,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -122,7 +125,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_master.asm
View File

@@ -10,7 +10,7 @@
;
#DEFINE PLATFORM_NAME "ROMWBW"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -87,6 +87,9 @@ DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
@@ -149,7 +152,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_NONE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_NONE ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -164,7 +167,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_NONE ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_NONE ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_mk4.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "MARK IV"
;
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_MK4 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -72,6 +72,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
@@ -104,7 +107,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -119,7 +122,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_DIO3 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_n8.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "N8"
;
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_N8 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -75,6 +75,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU FALSE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
@@ -107,7 +110,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_N8 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -122,7 +125,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_N8 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_N8 ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_rcz180.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "RC2014"
;
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_RCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -68,6 +68,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
@@ -113,7 +116,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -127,7 +130,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_rcz80.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "RC2014"
;
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_RCZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -64,6 +64,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
@@ -117,7 +120,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -131,7 +134,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_sbc.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "SBC"
;
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_SBC ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -66,6 +66,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
@@ -107,7 +110,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_DIO3 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -122,7 +125,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU FALSE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_scz180.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "SCZ180"
;
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_SCZ180 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -63,6 +63,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
;
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM)
@@ -108,7 +111,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -122,7 +125,7 @@ IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_RC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

2
Source/HBIOS/cfg_una.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "UNA"
;
PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_UNA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
BIOS .EQU BIOS_UNA ; HARDWARE BIOS: BIOS_[WBW|UNA]
;
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT

9
Source/HBIOS/cfg_zeta.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "ZETA"
;
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_ZETA ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z80 ; CPU_[Z80|Z180]: CPU FAMILY
BIOS .EQU BIOS_WBW ; BIOS_[WBW|UNA]: HARDWARE BIOS
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -60,6 +60,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
@@ -87,7 +90,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_ZETA ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -98,7 +101,7 @@ RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

9
Source/HBIOS/cfg_zeta2.asm
View File

@@ -13,7 +13,7 @@
;
#DEFINE PLATFORM_NAME "ZETA V2"
;
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180]
PLATFORM .EQU PLT_ZETA2 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO]
CPUFAM .EQU CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180]
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA]
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE
@@ -65,6 +65,9 @@ DSRTCENABLE .EQU TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM)
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC]
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!)
;
BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM)
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS
;
UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM)
UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ
UARTSBC .EQU TRUE ; UART: AUTO-DETECT SBC/ZETA ONBOARD UART
@@ -92,7 +95,7 @@ MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM)
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
;
FDENABLE .EQU TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
FDMODE .EQU FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3]
FDMODE .EQU FDMODE_ZETA2 ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO]
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL)
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111]
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111]
@@ -103,7 +106,7 @@ RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
;
PPIDEENABLE .EQU FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC]
PPIDEMODE .EQU PPIDEMODE_SBC ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO]
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL)
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY)
;

18
Source/HBIOS/fd.asm
View File

@@ -53,6 +53,14 @@ FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER
FDC_DCR .EQU $48 ; CONFIGURATION CONTROL REGISTER
FDC_TC .EQU $58 ; TERMINAL COUNT (W/ DACK)
#ENDIF
#IF (FDMODE == FDMODE_DYNO)
FDC_BASE .EQU $84
FDC_MSR .EQU FDC_BASE + $00 ; 8272 MAIN STATUS REGISTER
FDC_DATA .EQU FDC_BASE + $01 ; 8272 DATA PORT
FDC_DOR .EQU FDC_BASE + $02 ; DIGITAL OUTPUT REGISTER
FDC_DCR .EQU FDC_BASE + $03 ; CONFIGURATION CONTROL REGISTER
FDC_TC .EQU FDC_BASE + $02 ; TERMINAL COUNT (W/ DACK)
#ENDIF
;
; DISK OPERATIONS
;
@@ -391,7 +399,7 @@ DOR_INIT .EQU 11100000B ; INITIAL DEFAULT LATCH VALUE
;
; *** DIDE/N8/ZETA V2 ***
;
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_DYNO))
DOR_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED
DOR_BR250 .EQU DOR_INIT
DOR_BR500 .EQU DOR_INIT
@@ -1227,7 +1235,7 @@ FC_SETDOR
;
; SET FST_DCR
;
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_RCWDC))
;
FC_SETDCR
LD (FST_DCR),A
@@ -1259,7 +1267,7 @@ FC_RESETFDC:
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_RCSMC))
RES 7,A
#ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_RCWDC))
LD A,0
#ENDIF
CALL FC_SETDOR
@@ -1274,7 +1282,7 @@ FC_RESETFDC:
; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE
;
FC_PULSETC:
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_RCWDC))
IN A,(FDC_TC)
#ELSE
LD A,(FST_DOR)
@@ -1327,7 +1335,7 @@ FC_MOTORON1:
CP C ; COMPARE TO NEW MOTOR BITS
RET Z ; SKIP DELAY, MOTOR WAS ALREADY ON
#ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC) | (FDMODE == FDMODE_RCWDC))
; SETUP DCR FOR DIDE HARDWARE
LD A,(FCD_DCR) ; GET NEW DCR VALUE
CALL FC_SETDCR ; AND IMPLEMENT IT

15
Source/HBIOS/hbios.asm
View File

@@ -1488,6 +1488,9 @@ HB_INITTBL:
#IF (DSRTCENABLE)
.DW DSRTC_INIT
#ENDIF
#IF (BQRTCENABLE)
.DW BQRTC_INIT
#ENDIF
#IF (VDUENABLE)
.DW VDU_INIT
#ENDIF
@@ -1966,6 +1969,9 @@ RTC_DISPATCH:
#ENDIF
#IF (DSRTCENABLE)
JP DSRTC_DISPATCH
#ENDIF
#IF (BQRTCENABLE)
JP BQRTC_DISPATCH
#ENDIF
;CALL PANIC
OR $FF
@@ -2753,6 +2759,15 @@ SIZ_DSRTC .EQU $ - ORG_DSRTC
.ECHO " bytes.\n"
#ENDIF
;
#IF (BQRTCENABLE)
ORG_BQRTC .EQU $
#INCLUDE "bqrtc.asm"
SIZ_BQRTC .EQU $ - ORG_BQRTC
.ECHO "BQRTC occupies "
.ECHO SIZ_BQRTC
.ECHO " bytes.\n"
#ENDIF
;
#IF (ASCIENABLE)
ORG_ASCI .EQU $
#INCLUDE "asci.asm"

4
Source/HBIOS/ppide.asm
View File

@@ -25,6 +25,10 @@ PPIDE_IO_BASE .EQU $44
PPIDE_IO_BASE .EQU $80
#ENDIF
;
#IF (PPIDEMODE == PPIDEMODE_DYNO)
PPIDE_IO_BASE .EQU $4C
#ENDIF
;
PPIDE_IO_DATALO .EQU PPIDE_IO_BASE + 0 ; IDE DATA BUS LSB (8255 PORT A)
PPIDE_IO_DATAHI .EQU PPIDE_IO_BASE + 1 ; IDE DATA BUS MSB (8255 PORT B)
PPIDE_IO_CTL .EQU PPIDE_IO_BASE + 2 ; IDE ADDRESS BUS AND CONTROL SIGNALS (8255 PORT C)

6
Source/HBIOS/std.asm
View File

@@ -12,6 +12,7 @@
; 8. RCZ180 RC2014 based system with Z180 CPU
; 9. EZZ80 Easy Z80, Z80 SBC w/ RC2014 bus and CTC
; 10. SCZ180 Steve Cousins Z180 based system
; 11. DYNO Steve Garcia's Dyno Micro-ATX Motherboard
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;
@@ -41,6 +42,7 @@ PLT_RCZ80 .EQU 7 ; RC2014 W Z80
PLT_RCZ180 .EQU 8 ; RC2014 W/ Z180
PLT_EZZ80 .EQU 9 ; EASY Z80
PLT_SCZ180 .EQU 10 ; SCZ180
PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD
;
#IF (BIOS == BIOS_WBW)
#INCLUDE "hbios.inc"
@@ -132,7 +134,7 @@ FDMODE_N8 .EQU 5 ; N8
FDMODE_DIO3 .EQU 6 ; DISKIO V3
FDMODE_RCSMC .EQU 7 ; RC2014 SMC 9266 @ $40 (SCOTT BAKER)
FDMODE_RCWDC .EQU 8 ; RC2014 WDC 37C65 @ $40 (SCOTT BAKER)
FDMODE_DYNO .EQU 9 ; DYNO WDC 37C65 @ $84
;
; IDE MODE SELECTIONS
;
@@ -142,6 +144,7 @@ IDEMODE_DIDE .EQU 2 ; DUAL IDE
IDEMODE_MK4 .EQU 3 ; MARK IV ONBOARD IDE (8 BIT)
IDEMODE_RC .EQU 4 ; RC2014 CF MODULE (8 BIT) @ $10 (SPENCER OWEN)
IDEMODE_SMB .EQU 5 ; RC2014 IDE MODULE (8 BIT) @ $E0 (SCOTT BAKER)
IDEMODE_DYNO .EQU 6 ; DYNO IDE MODULE (8 BIT) @4A
;
; PPIDE MODE SELECTIONS
;
@@ -151,6 +154,7 @@ PPIDEMODE_DIO3 .EQU 2 ; DISKIO V3 PARALLEL PORT
PPIDEMODE_MFP .EQU 3 ; MULTIFUNCTION / PIC
PPIDEMODE_N8 .EQU 4 ; MULTIFUNCTION / PIC
PPIDEMODE_RC .EQU 5 ; RC2014 PPIDE MODULE @ $20 (ED BRINDLEY)
PPIDEMODE_DYNO .EQU 6 ; DYNO PPIDE @ $4C
;
; SD MODE SELECTIONS
;

2
Source/HBIOS/ver.inc
View File

@@ -2,4 +2,4 @@
#DEFINE RMN 9
#DEFINE RUP 2
#DEFINE RTP 0
#DEFINE BIOSVER "2.9.2-pre.23"
#DEFINE BIOSVER "2.9.2-pre.24"