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Browse Source
Dyno Computer is the work of Steve Garcia and much of the code checked in is based on his work.pull/80/head
Wayne Warthen
6 years ago
28 changed files with 723 additions and 83 deletions
@ -0,0 +1,39 @@ |
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; |
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;================================================================================================== |
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; DYNO STANDARD CONFIGURATION |
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;================================================================================================== |
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; |
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE |
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; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY. THIS FILE CONTAINS |
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; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS. IT IS INTENDED THAT YOU MAKE |
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; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS. |
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; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY |
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; YOUR FILE IN THE BUILD PROCESS. |
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; |
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; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM. |
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; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO |
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; ANYTHING AS IS. THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON |
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; SETTINGS. |
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; |
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; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE, |
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; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING |
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; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS! |
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; |
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; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO |
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; DIRECTORIES ABOVE THIS ONE). |
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; |
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#include "cfg_dyno.asm" |
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; |
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CPUOSC .SET 18432000 ; CPU OSC FREQ IN MHZ |
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; |
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Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
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Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3) |
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Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
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; |
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ASCIENABLE .SET TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
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;ASCI0CFG .SET SER_115200_8N1 ; ASCI 0: SERIAL LINE CONFIG |
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;ASCI1CFG .SET SER_115200_8N1 ; ASCI 1: SERIAL LINE CONFIG |
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; |
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FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
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; |
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PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
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@ -0,0 +1,5 @@ |
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#DEFINE PLATFORM_NAME "DYNO (wbw)" |
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; |
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#include "cfg_dyno.asm" |
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; |
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FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
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@ -0,0 +1,370 @@ |
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;================================================================================================== |
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; Benchmark BQ4845P RTC Driver |
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;================================================================================================== |
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; Register Addresses (HEX / BCD): |
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; +---+-----+--------------+-------------------+------------------+----------------+ |
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; |ADR| D7 | D6 | D5 | D4 | D3 | D2 | D1 | D0 | RANGE | REGISTER | |
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; +---+-----+--------------+-------------------+------------------+----------------+ |
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; | 0 | 0 | 10-Second | 1-Second | 00-59 | Seconds | |
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; +---+-----+----+---------+-------------------+------------------+----------------+ |
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; | | ALM1|ALM2| | | | | |
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; | 1 | | 10-Second | 1-Second | 00-59 | Seconds Alarm | |
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; +---+-----+--------------+-------------------+------------------+----------------+ |
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; | 2 | 0 | 10-Minute | 1-Minute | 00-59 | Minutes | |
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; +---+-----+----+---------+-------------------+------------------+----------------+ |
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; | | ALM1|ARM0| | | | | |
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; | 3 | | 10-Minute | 1-Minute | 00-59 | Minutes Alarm | |
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; +---+-----+----+---------+-------------------+------------------+----------------+ |
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; | 4 |PM/AM| 0 | 10-Hour | 1-Hour |01-12 AM/81-92 PM | Hours | |
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; +---+-----+----+----+----+-------------------+------------------+----------------+ |
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; | | ALM1| | | | | | |
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; | 5 |PM/AM|ALM0| 10-Hour | 1-Hour |01-12 AM/81-92 PM | Hours Alarm | |
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; +---+-----+----+----+----+-------------------+------------------+----------------+ |
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; | 6 | 0 | 0 | 10-Day | 1-Day | 01-31 | Day | |
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; +---+-----+----+----+----+-------------------+------------------+----------------+ |
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; | 7 | ALM1|ALM0| 10-day | 1-Day | 01-31 | Day Alarm | |
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; +---+-----+----+----+----+----+--------------+------------------+----------------+ |
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; | 8 | 0 | 0 | 0 | 0 | 0 | Day Of Week | 01-07 | Day Of Week | |
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; +---+-----+----+----+----+----+--------------+------------------+----------------+ |
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; | 9 | 0 | 0 | 0 |10Mo| 1-Month | 01-12 | Month | |
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; +---+-----+----+----+----+-------------------+------------------+----------------+ |
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; | A | 10-Year | 1-Year | 00-99 | Year | |
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; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
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; | B | * | WD2| WD1| WD0| RS3| RS2| RS1| RS0| | Rates | |
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; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
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; | C | * | * | * | * | AIE| PIE|PWRE| ABE| | Interrupt | |
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; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
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; | D | * | * | * | * | AF | PF |PWRF| BVF| | Flags | |
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; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
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; | E | * | * | * | * | UTI|STOP|2412| DSE| | Control | |
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; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
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; | F | * | * | * | * | * | * | * | * | | Unused | |
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; +---+-----+----+----+----+----+----+----+----+------------------+----------------+ |
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; * = Unused bits; unwritable and read as 0. |
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; 0 = should be set to 0 for valid time/calendar range. |
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; Clock calendar data is BCD. Automatic leap year adjustment. |
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; PM/AM = 1 for PM; PM/AM = 0 for AM. |
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; DSE = 1 enable daylight savings adjustment. |
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; 24/12 = 1 enable 24-hour data representation; 24/12 = 0 enables 12-hour data representation. |
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; Day-Of-Week coded as Sunday = 1 through Saturday = 7. |
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; BVF = 1 for valid battery. |
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; STOP = 1 turns the RTC on; STOP = 0 stops the RTC in back-up mode. |
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; Constants |
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BQRTC_SEC .EQU BQRTC_BASE + $00 |
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BQRTC_SEC_ALM .EQU BQRTC_BASE + $01 |
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BQRTC_MIN .EQU BQRTC_BASE + $02 |
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BQRTC_MIN_ALM .EQU BQRTC_BASE + $03 |
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BQRTC_HOUR .EQU BQRTC_BASE + $04 |
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BQRTC_HOUR_ALM .EQU BQRTC_BASE + $05 |
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BQRTC_DAY .EQU BQRTC_BASE + $06 |
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BQRTC_DAY_ALM .EQU BQRTC_BASE + $07 |
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BQRTC_WEEK_DAY .EQU BQRTC_BASE + $08 |
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BQRTC_MONTH .EQU BQRTC_BASE + $09 |
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BQRTC_YEAR .EQU BQRTC_BASE + $0A |
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BQRTC_RATE .EQU BQRTC_BASE + $0B |
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BQRTC_INTERRUPT .EQU BQRTC_BASE + $0C |
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BQRTC_FLAGS .EQU BQRTC_BASE + $0D |
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BQRTC_CONTROL .EQU BQRTC_BASE + $0E |
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BQRTC_UNUSED .EQU BQRTC_BASE + $0F |
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BQRTC_HIGH .EQU %11110000 |
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BQRTC_LOW .EQU %00001111 |
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BQRTC_WD .EQU %01110000 |
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BQRTC_RS .EQU %00001111 |
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BQRTC_BVF .EQU %00000001 |
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BQRTC_PWRF .EQU %00000010 |
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BQRTC_PF .EQU %00000100 |
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BQRTC_AF .EQU %00001000 |
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BQRTC_DSE .EQU %00000001 |
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BQRTC_2412 .EQU %00000010 |
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BQRTC_STOP .EQU %00000100 |
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BQRTC_UTI .EQU %00001000 |
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BQRTC_BUFSIZE .EQU 6 ; 6 BYTE BUFFER (YYMMDDHHMMSS) |
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; RTC Device Initialization Entry |
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BQRTC_INIT: |
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CALL NEWLINE ; Formatting |
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PRTS("BQRTC: IO=0x$") |
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LD A, BQRTC_BASE |
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CALL PRTHEXBYTE |
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LD A, BQRTC_DSE | BQRTC_2412 | BQRTC_UTI |
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OUT0 (BQRTC_CONTROL), A ; Enable Daylight Savings and 24 Hour |
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XOR A ; Zero A |
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OUT0 (BQRTC_RATE), A ; Disable Periodic Interrupt Rate |
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OUT0 (BQRTC_INTERRUPT), A ; Disable Interrupts |
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CALL BQRTC_LOAD |
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; DISPLAY CURRENT TIME |
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PRTS(" $") |
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LD A, (BQRTC_BUF_MON) |
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CALL PRTHEXBYTE |
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PRTS("/$") |
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LD A, (BQRTC_BUF_DAY) |
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CALL PRTHEXBYTE |
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PRTS("/$") |
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LD A, (BQRTC_BUF_YEAR) |
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CALL PRTHEXBYTE |
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PRTS(" $") |
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LD A, (BQRTC_BUF_HOUR) |
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CALL PRTHEXBYTE |
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PRTS(":$") |
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LD A, (BQRTC_BUF_MIN) |
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CALL PRTHEXBYTE |
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PRTS(":$") |
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LD A, (BQRTC_BUF_SEC) |
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CALL PRTHEXBYTE |
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XOR A ; Signal success |
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RET |
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; RTC Device Function Dispatch Entry |
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; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
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; B: Function (IN) |
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BQRTC_DISPATCH: |
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LD A, B ; Get requested function |
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AND $0F ; Isolate Sub-Function |
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JP Z, BQRTC_GETTIM ; Get Time |
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DEC A |
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JP Z, BQRTC_SETTIM ; Set Time |
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DEC A |
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JP Z, BQRTC_GETBYT ; Get NVRAM Byte Value |
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DEC A |
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JP Z, BQRTC_SETBYT ; Set NVRAM Byte Value |
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DEC A |
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JP Z, BQRTC_GETBLK ; Get NVRAM Data Block Value |
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DEC A |
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JP Z, BQRTC_SETBLK ; Set NVRAM Data Block Value |
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DEC A |
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JP Z, BQRTC_GETALM ; Get Alarm |
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DEC A |
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JP Z, BQRTC_SETALM ; Set Alarm |
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; |
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; NVRAM FUNCTIONS ARE NOT AVAILABLE |
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; |
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BQRTC_GETBYT: |
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BQRTC_SETBYT: |
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BQRTC_GETBLK: |
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BQRTC_SETBLK: |
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CALL PANIC |
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; RTC Get Time |
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; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
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; HL: Date/Time Buffer (OUT) |
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; Buffer format is BCD: YYMMDDHHMMSS |
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; 24 hour time format is assumed |
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; |
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BQRTC_GETTIM: |
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EX DE, HL |
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CALL BQRTC_LOAD |
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; Now copy to read destination (Interbank Save) |
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LD A, BID_BIOS ; Copy from BIOS bank |
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LD (HB_SRCBNK), A ; Set it |
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LD A, (HB_INVBNK) ; Copy to current user bank |
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LD (HB_DSTBNK), A ; Set it |
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LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
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#IF (INTMODE == 1) |
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DI |
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#ENDIF |
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CALL HB_BNKCPY ; Copy the clock data |
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#IF (INTMODE == 1) |
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EI |
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#ENDIF |
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; |
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; CLEAN UP AND RETURN |
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XOR A ; SIGNAL SUCCESS |
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RET ; AND RETURN |
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; |
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; RTC Set Time |
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; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
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; HL: Date/Time Buffer (IN) |
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; Buffer Format is BCD: YYMMDDHHMMSS |
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; 24 hour time format is assumed |
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; |
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BQRTC_SETTIM: |
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; |
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; Copy incoming time data to our time buffer |
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LD A, (HB_INVBNK) ; Copy from current user bank |
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LD (HB_SRCBNK), A ; Set it |
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LD A, BID_BIOS ; Copy to BIOS bank |
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LD (HB_DSTBNK), A ; Set it |
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LD DE, BQRTC_BUF ; Destination Address |
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LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
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#IF (INTMODE == 1) |
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DI |
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#ENDIF |
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CALL HB_BNKCPY ; Copy the clock data |
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#IF (INTMODE == 1) |
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EI |
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#ENDIF |
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; Write to clock |
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LD HL, BQRTC_BUF |
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CALL BQRTC_SUSPEND |
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LD A, (HL) |
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OUT0 (BQRTC_YEAR), A ; Write Year |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_MONTH), A ; Write Month |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_DAY), A ; Write Day |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_HOUR), A ; Write Hour |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_MIN), A ; Write Minute |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_SEC), A ; Write Second |
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CALL BQRTC_RESUME |
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; clean up and return |
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XOR A ; Signal success |
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RET ; And return |
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; RTC Get Alarm |
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; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
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; HL: Date/Time Buffer (OUT) |
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; Buffer format is BCD: YYMMDDHHMMSS |
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; 24 hour time format is assumed |
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; |
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BQRTC_GETALM: |
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EX DE, HL |
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LD HL, BQRTC_BUF |
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PUSH HL ; Save address of source buffer |
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CALL BQRTC_SUSPEND |
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XOR A |
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LD (HL), A ; Read Year |
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INC HL |
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LD (HL), A ; Read Month |
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INC HL |
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IN0 A, (BQRTC_DAY_ALM) ; Read Day |
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LD (HL), A |
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INC HL |
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IN0 A, (BQRTC_HOUR_ALM) ; Read Hour |
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LD (HL), A |
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INC HL |
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IN0 A, (BQRTC_MIN_ALM) ; Read Minute |
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LD (HL), A |
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INC HL |
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IN0 A, (BQRTC_SEC_ALM) ; Read Second |
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LD (HL), A |
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CALL BQRTC_RESUME |
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POP HL ; Restore address of source buffer |
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; Now copy to read destination (Interbank Save) |
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LD A, BID_BIOS ; Copy from BIOS bank |
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LD (HB_SRCBNK), A ; Set it |
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LD A, (HB_INVBNK) ; Copy to current user bank |
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LD (HB_DSTBNK), A ; Set it |
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LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
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#IF (INTMODE == 1) |
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DI |
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#ENDIF |
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CALL HB_BNKCPY ; Copy the clock data |
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#IF (INTMODE == 1) |
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EI |
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#ENDIF |
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; |
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; CLEAN UP AND RETURN |
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XOR A ; SIGNAL SUCCESS |
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RET ; AND RETURN |
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; |
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; RTC Set Alarm |
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; A: Result (OUT), 0=OK, Z=OK, NZ=Error |
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; HL: Date/Time Buffer (IN) |
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; Buffer Format is BCD: YYMMDDHHMMSS |
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; 24 hour time format is assumed |
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; |
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BQRTC_SETALM: |
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; Copy incoming time data to our time buffer |
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LD A, (HB_INVBNK) ; Copy from current user bank |
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LD (HB_SRCBNK), A ; Set it |
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LD A, BID_BIOS ; Copy to BIOS bank |
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LD (HB_DSTBNK), A ; Set it |
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LD DE, BQRTC_BUF ; Destination Address |
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LD BC, BQRTC_BUFSIZE ; Length is 6 bytes |
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#IF (INTMODE == 1) |
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DI |
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#ENDIF |
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CALL HB_BNKCPY ; Copy the clock data |
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#IF (INTMODE == 1) |
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EI |
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#ENDIF |
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; Write to clock |
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LD HL, BQRTC_BUF_DAY |
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CALL BQRTC_SUSPEND |
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LD A, (HL) |
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OUT0 (BQRTC_DAY_ALM), A ; Write Day |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_HOUR_ALM), A ; Write Hour |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_MIN_ALM), A ; Write Minute |
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INC HL |
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LD A, (HL) |
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OUT0 (BQRTC_SEC_ALM), A ; Write Second |
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CALL BQRTC_RESUME |
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; clean up and return |
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XOR A ; Signal success |
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RET ; And return |
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BQRTC_SUSPEND: |
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IN0 A, (BQRTC_CONTROL) ; Suspend Clock |
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OR BQRTC_UTI |
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OUT0 (BQRTC_CONTROL), A |
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RET |
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BQRTC_RESUME: |
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IN0 A, (BQRTC_CONTROL) ; Resume Clock |
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AND ~BQRTC_UTI |
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OUT0 (BQRTC_CONTROL), A |
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RET |
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BQRTC_LOAD: |
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LD HL, BQRTC_BUF |
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PUSH HL ; Save address of source buffer |
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CALL BQRTC_SUSPEND |
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IN0 A, (BQRTC_YEAR) ; Read Year |
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LD (HL), A |
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INC HL |
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IN0 A, (BQRTC_MONTH) ; Read Month |
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LD (HL), A |
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INC HL |
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IN0 A, (BQRTC_DAY) ; Read Day |
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LD (HL), A |
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INC HL |
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IN0 A, (BQRTC_HOUR) ; Read Hour |
||||
|
LD (HL), A |
||||
|
INC HL |
||||
|
IN0 A, (BQRTC_MIN) ; Read Minute |
||||
|
LD (HL), A |
||||
|
INC HL |
||||
|
IN0 A, (BQRTC_SEC) ; Read Second |
||||
|
LD (HL), A |
||||
|
CALL BQRTC_RESUME |
||||
|
POP HL ; Restore address of source buffer |
||||
|
RET |
||||
|
|
||||
|
; Working Variables |
||||
|
|
||||
|
BQRTC_BUF: |
||||
|
BQRTC_BUF_YEAR: .DB 0 ; Year |
||||
|
BQRTC_BUF_MON: .DB 0 ; Month |
||||
|
BQRTC_BUF_DAY: .DB 0 ; Day |
||||
|
BQRTC_BUF_HOUR: .DB 0 ; Hour |
||||
|
BQRTC_BUF_MIN: .DB 0 ; Minute |
||||
|
BQRTC_BUF_SEC: .DB 0 ; Second |
||||
@ -0,0 +1,133 @@ |
|||||
|
; |
||||
|
;================================================================================================== |
||||
|
; ROMWBW 2.X CONFIGURATION DEFAULTS FOR RC2014 |
||||
|
;================================================================================================== |
||||
|
; |
||||
|
; THIS FILE CONTAINS THE FULL SET OF DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM |
||||
|
; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, YOU SHOULD |
||||
|
; OVERRIDE ANY SETTINGS YOU WANT USING A CONFIGURATION FILE IN THE CONFIG DIRECTORY |
||||
|
; UNDER THIS DIRECTORY. |
||||
|
; |
||||
|
; THIS FILE CAN BE CONSIDERED A REFERENCE THAT LISTS ALL POSSIBLE CONFIGURATION SETTINGS |
||||
|
; FOR THE PLATFORM. |
||||
|
; |
||||
|
#DEFINE PLATFORM_NAME "DYNO" |
||||
|
; |
||||
|
PLATFORM .EQU PLT_DYNO ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCZ180|EZZ80|SCZ180|DYNO] |
||||
|
CPUFAM .EQU CPU_Z180 ; CPU FAMILY: CPU_[Z80|Z180] |
||||
|
BIOS .EQU BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] |
||||
|
BATCOND .EQU FALSE ; ENABLE LOW BATTERY WARNING MESSAGE |
||||
|
; |
||||
|
BOOTTYPE .EQU BT_MENU ; BT_[MENU|AUTO], IF AUTO, BOOT DEFAULT AFTER TIMEOUT |
||||
|
BOOT_TIMEOUT .EQU 20 ; AUTO BOOT TIMEOUT IN SECONDS, 0 FOR IMMEDIATE BOOT |
||||
|
BOOT_DEFAULT .EQU 'Z' ; AUTO BOOT SELECTION TO INVOKE AT TIMEOUT |
||||
|
; |
||||
|
CPUOSC .EQU 18432000 ; CPU OSC FREQ IN MHZ |
||||
|
INTMODE .EQU 2 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2 |
||||
|
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM) |
||||
|
; |
||||
|
RAMSIZE .EQU 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) |
||||
|
MEMMGR .EQU MM_Z180 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180] |
||||
|
RAMBIAS .EQU 512 ; OFFSET OF START OF RAM IN PHYSICAL ADDRESS SPACE |
||||
|
MPGSEL_0 .EQU $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) |
||||
|
MPGSEL_1 .EQU $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) |
||||
|
MPGSEL_2 .EQU $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) |
||||
|
MPGSEL_3 .EQU $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) |
||||
|
MPGENA .EQU $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) |
||||
|
; |
||||
|
Z180_BASE .EQU $C0 ; Z180: I/O BASE ADDRESS FOR INTERNAL REGISTERS |
||||
|
Z180_CLKDIV .EQU 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2 |
||||
|
Z180_MEMWAIT .EQU 0 ; Z180: MEMORY WAIT STATES (0-3) |
||||
|
Z180_IOWAIT .EQU 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3) |
||||
|
; |
||||
|
RTCIO .EQU $0C ; RTC LATCH REGISTER ADR |
||||
|
; |
||||
|
KIOENABLE .EQU FALSE ; ENABLE ZILOG KIO SUPPORT |
||||
|
KIOBASE .EQU $80 ; KIO BASE I/O ADDRESS |
||||
|
; |
||||
|
CTCENABLE .EQU FALSE ; ENABLE ZILOG CTC SUPPORT |
||||
|
; |
||||
|
DIAGENABLE .EQU FALSE ; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT |
||||
|
DIAGPORT .EQU $00 ; DIAGNOSTIC PORT ADDRESS |
||||
|
DIAGDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS |
||||
|
; |
||||
|
LEDENABLE .EQU FALSE ; ENABLES STATUS LED (SINGLE LED) |
||||
|
LEDPORT .EQU $0E ; STATUS LED PORT ADDRESS |
||||
|
LEDDISKIO .EQU TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED |
||||
|
; |
||||
|
DSKYENABLE .EQU FALSE ; ENABLES DSKY (DO NOT COMBINE WITH PPIDE) |
||||
|
; |
||||
|
CRTACT .EQU FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP |
||||
|
VDAEMU .EQU EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] |
||||
|
ANSITRACE .EQU 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
; |
||||
|
HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT |
||||
|
SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) |
||||
|
; |
||||
|
DSRTCENABLE .EQU FALSE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) |
||||
|
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTC_[STD|MFPIC] |
||||
|
DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) |
||||
|
; |
||||
|
BQRTCENABLE .EQU TRUE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) |
||||
|
BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS |
||||
|
; |
||||
|
UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) |
||||
|
; |
||||
|
ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) |
||||
|
ASCI0CFG .EQU DEFSERCFG ; ASCI 0: SERIAL LINE CONFIG |
||||
|
ASCI1CFG .EQU DEFSERCFG ; ASCI 1: SERIAL LINE CONFIG |
||||
|
; |
||||
|
ACIAENABLE .EQU FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) |
||||
|
; |
||||
|
SIOENABLE .EQU FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) |
||||
|
; |
||||
|
VDUENABLE .EQU FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) |
||||
|
CVDUENABLE .EQU FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) |
||||
|
NECENABLE .EQU FALSE ; NEC: ENABLE NEC UPD7220 VIDEO/KBD DRIVER (NEC.ASM) |
||||
|
TMSENABLE .EQU FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) |
||||
|
VGAENABLE .EQU FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) |
||||
|
; |
||||
|
SPKENABLE .EQU FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) |
||||
|
; |
||||
|
AYENABLE .EQU FALSE ; AY: ENABLE AY PSG SOUND DRIVER |
||||
|
AYMODE .EQU AYMODE_RCZ180 ; AY: DRIVER MODE: AYMODE_[SCG/N8/RCZ80/RCZ180] |
||||
|
; |
||||
|
MDENABLE .EQU TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) |
||||
|
MDTRACE .EQU 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
; |
||||
|
FDENABLE .EQU FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) |
||||
|
FDMODE .EQU FDMODE_DYNO ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|DIDE|N8|DIO3|DYNO] |
||||
|
FDTRACE .EQU 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) |
||||
|
FDMEDIA .EQU FDM144 ; FD: DEFAULT MEDIA FORMAT FDM[720|144|360|120|111] |
||||
|
FDMEDIAALT .EQU FDM720 ; FD: ALTERNATE MEDIA FORMAT FDM[720|144|360|120|111] |
||||
|
FDMAUTO .EQU TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS |
||||
|
; |
||||
|
RFENABLE .EQU FALSE ; RF: ENABLE RAM FLOPPY DRIVER |
||||
|
; |
||||
|
IDEENABLE .EQU FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) |
||||
|
IDEMODE .EQU IDEMODE_RC ; IDE: DRIVER MODE: IDEMODE_[DIO|DIDE] |
||||
|
IDETRACE .EQU 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
IDE8BIT .EQU TRUE ; IDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) |
||||
|
; |
||||
|
PPIDEENABLE .EQU TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) |
||||
|
PPIDEMODE .EQU PPIDEMODE_DYNO ; PPIDE: DRIVER MODE: PPIDEMODE_[SBC|DIO3|MFP|N8|RC|DYNO] |
||||
|
PPIDETRACE .EQU 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
PPIDE8BIT .EQU FALSE ; PPIDE: USE 8-BIT TRANSFERS (CF CARDS MOSTLY) |
||||
|
; |
||||
|
SDENABLE .EQU FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) |
||||
|
SDMODE .EQU SDMODE_PPI ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT] |
||||
|
SDCNT .EQU 1 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD & SC ONLY |
||||
|
SDTRACE .EQU 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) |
||||
|
SDCSIOFAST .EQU FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE |
||||
|
; |
||||
|
PRPENABLE .EQU FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) |
||||
|
; |
||||
|
PPPENABLE .EQU FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) |
||||
|
; |
||||
|
HDSKENABLE .EQU FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) |
||||
|
; |
||||
|
PIO_4P .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD |
||||
|
PIO_ZP .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) |
||||
|
PPI_SBC .EQU FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP |
||||
|
; |
||||
|
UFENABLE .EQU FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) |
||||
Loading…
Reference in new issue