From 3eac8d164c1ffe209f18fd85d17269103e2be594 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 22 May 2020 15:40:36 -0700 Subject: [PATCH] Cleanup - Minor build script cleanup for DUART driver --- Binary/RomList.txt | 56 +++++++++++++------------------------ Doc/ChangeLog.txt | 1 + Source/HBIOS/cfg_dyno.asm | 2 ++ Source/HBIOS/cfg_ezz80.asm | 9 ++++++ Source/HBIOS/cfg_master.asm | 9 ++++++ Source/HBIOS/cfg_mk4.asm | 2 ++ Source/HBIOS/cfg_n8.asm | 2 ++ Source/HBIOS/cfg_rcz180.asm | 9 ++++++ Source/HBIOS/cfg_sbc.asm | 2 ++ Source/HBIOS/cfg_scz180.asm | 9 ++++++ Source/HBIOS/cfg_zeta.asm | 4 ++- Source/HBIOS/cfg_zeta2.asm | 2 ++ 12 files changed, 69 insertions(+), 38 deletions(-) diff --git a/Binary/RomList.txt b/Binary/RomList.txt index 7f1eea75..f507226f 100644 --- a/Binary/RomList.txt +++ b/Binary/RomList.txt @@ -34,7 +34,7 @@ image to use for each platform: RC2014 w/ Z80 RCZ80_std.rom RC2014 w/ Z180 RCZ180_nat.rom (native Z180 memory addressing) RC2014 w/ Z180 RCZ180_ext.rom (external 512K RAM/ROM module) - SC-series SC126, SC130 + SC-series SC126, SC130, SC131 Easy Z80 EZZ180_std.rom Dyno DYNO_std.rom @@ -52,11 +52,6 @@ ROM on-the-fly. It is an excellent way to test a ROM Image before actually burning it. Similarly, the .img files can be loaded using the UNA FAT loader for testing. -WARNING: In a few cases the .com file is too big to load. If you get -a message like "Full" or "BAD LOAD" when trying to load one of the -.com files, it is too big. In these cases, you will not be able to -test the ROM prior to programming it. - All of the standard ROM Images are configured for: - 512KB ROM Disk - 512KB RAM Disk @@ -66,10 +61,10 @@ All of the standard ROM Images are configured for: * RC2014 and Stephen Cousins' kits run at 115,200Kbps baud All hard disk type devices (IDE, PPIDE, CF Card, SD Card) will be -automatically assigned two drive letters per device. The drive -letters will refer to the first 2 slices of the device. The ASSIGN -command can be used to display and reassign drives to disk devices -and slices as desired. +automatically assigned at least two drive letters per device. The +drive letters will refer to the first 2 slices of the device. The +ASSIGN command can be used to display and reassign drives to disk +devices and slices as desired. Standard ROM Image Notes ------------------------ @@ -153,35 +148,28 @@ MK4 (MK4_std.rom): RCZ80 (RCZ80_std.rom): - Assumes CPU oscillator of 7.3728 MHz - Requires 512K RAM/ROM module - - Auto detects Serial I/O Module (ACIA) and Dual Serial - Module (SIO/2). Either one may be used. + - Auto detects Serial I/O Module (ACIA), Dual Serial + Module (SIO/2), and EP Dual UART. - Console on whichever serial module is installed, - but will use the SIO/2 if both are installed. Baud - rate is determined by hardware, but normally 115200. - - Includes support for RC2014 Compact Flash Module - - Support for RC2014 PPIDE Module may be enabled in config + order of priority is UART, SIO, then ACIA. + - Baud rate is determined by hardware, but normally 115200. + - Auto support for RC2014 Compact Flash Module + - Auto support for RC2014 PPIDE Module - Support for Scott Baker SIO board may be enabled in config - Support for Scott Baker floppy controllers (SMC & WDC) may be enabled in config - Support for J.B. Lang TMS9918 video card may be enabled in config RCZ80 w/ KIO (RCZ80_kio.rom): - - Assumes CPU oscillator of 7.3728 MHz - - Requires 512K RAM/ROM module + - Save as RCZ80_std - Requires KIO module - - Console on KIO primary serial port at 115200 baud - - Includes support for RC2014 Compact Flash Module - - Includes support for RC2014 PPIDE Module - - Support for Scott Baker SIO board may be enabled in config - - Support for Scott Baker floppy controllers (SMC & WDC) may - be enabled in config - - Support for J.B. Lang TMS9918 video card may be enabled in config + - SIO ports provided by KIO RCZ180 (RCZ180_nat.rom & RCZ180_ext.rom): - Assumes CPU oscillator of 18.432 MHz - Console on Z180 onboard primary ASCI serial port at 115200 baud - - Includes support for RC2014 Compact Flash Module - - Includes support for RC2014 PPIDE Module + - Auto support for RC2014 Compact Flash Module + - Auto support for RC2014 PPIDE Module - Support for alternative serial modules may be enabled in config - Support for Scott Baker floppy controllers (SMC & WDC) may be enabled in config @@ -195,14 +183,8 @@ RCZ180 (RCZ180_nat.rom & RCZ180_ext.rom): memory, such as the 512K RAM/ROM module. SCZ180 (SCZ180_126.rom, SCZ180_130.rom, SCZ180_131.rom): - - Assumes CPU oscillator of 18.432 MHz - - Console on Z180 onboard primary ASCI serial port at 115200 baud - - Includes support for RC2014 Compact Flash Module - - Includes support for RC2014 PPIDE Module - - Support for alternative serial modules may be enabled in config - - Support for Scott Baker floppy controllers (SMC & WDC) may - be enabled in config - - Support for J.B. Lang TMS9918 video card may be enabled in config + - Same as RCZ180 + - Adds auto support for SPI SD Card - The 3 different variants of SCZ180 are provided to match the 3 corresponding systems (SC126, SC130, and SC131) designed by Stephen Cousins. @@ -211,8 +193,8 @@ EZZ80 (EZZ80_std.rom): - Assumes CPU oscillator of 10.000 MHz - Console on primary SIO serial port at 115200 baud - Includes support for on-board SIO - - Includes support for RC2014 Compact Flash Module - - Includes support for RC2014 PPIDE Module + - Auto support for RC2014 Compact Flash Module + - Auto support for RC2014 PPIDE Module DYNO (DYNO_std.rom): - Assumes CPU oscillator of 18.432 MHz diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 2f7c0b98..49e26095 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -4,6 +4,7 @@ Version 3.1.1 - WBW: Preliminary hard disk partition support (backward compatible) - WBW: Change Propeller VGA signal timings to 60Hz refresh - WBW: Enhanced SYSTEM RESET function to allow a warm start back to boot loader +- C?O: Add DUART driver Version 3.1 ----------- diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm index 2ad866b1..5a996286 100644 --- a/Source/HBIOS/cfg_dyno.asm +++ b/Source/HBIOS/cfg_dyno.asm @@ -74,6 +74,8 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) ; ASCIENABLE .EQU TRUE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm index 4b20048b..00041a49 100644 --- a/Source/HBIOS/cfg_ezz80.asm +++ b/Source/HBIOS/cfg_ezz80.asm @@ -76,6 +76,15 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm index 398cb095..4e0e3b6a 100644 --- a/Source/HBIOS/cfg_master.asm +++ b/Source/HBIOS/cfg_master.asm @@ -98,6 +98,15 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; UARTENABLE .EQU FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm index 64b05213..62dfd646 100644 --- a/Source/HBIOS/cfg_mk4.asm +++ b/Source/HBIOS/cfg_mk4.asm @@ -81,6 +81,8 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm index e0f2f176..41add6c6 100644 --- a/Source/HBIOS/cfg_n8.asm +++ b/Source/HBIOS/cfg_n8.asm @@ -84,6 +84,8 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm index 31cdf6fe..75c93b06 100644 --- a/Source/HBIOS/cfg_rcz180.asm +++ b/Source/HBIOS/cfg_rcz180.asm @@ -77,6 +77,15 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm index ce15dbb6..2bb6d10a 100644 --- a/Source/HBIOS/cfg_sbc.asm +++ b/Source/HBIOS/cfg_sbc.asm @@ -77,6 +77,8 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm index 3b5f1c0e..547b3b50 100644 --- a/Source/HBIOS/cfg_scz180.asm +++ b/Source/HBIOS/cfg_scz180.asm @@ -72,6 +72,15 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .EQU 2 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .EQU $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .EQU DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .EQU DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .EQU $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .EQU DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .EQU DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm index 319402a9..6793d291 100644 --- a/Source/HBIOS/cfg_zeta.asm +++ b/Source/HBIOS/cfg_zeta.asm @@ -61,10 +61,12 @@ DSRTCCHG .EQU FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) BQRTCENABLE .EQU FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) BQRTC_BASE .EQU $50 ; BQRTC: I/O BASE ADDRESS ; +INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; -INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) ; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm index f7e1a4e0..eecac1ec 100644 --- a/Source/HBIOS/cfg_zeta2.asm +++ b/Source/HBIOS/cfg_zeta2.asm @@ -76,6 +76,8 @@ INTRTCENABLE .EQU FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) HTIMENABLE .EQU FALSE ; ENABLE SIMH TIMER SUPPORT SIMRTCENABLE .EQU FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) ; +DUARTENABLE .EQU FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +; UARTENABLE .EQU TRUE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) UARTOSC .EQU 1843200 ; UART: OSC FREQUENCY IN MHZ UARTCFG .EQU DEFSERCFG ; UART: LINE CONFIG FOR UART PORTS