diff --git a/Binary/RomList.txt b/Binary/RomList.txt
index 312308f2..fe87f73a 100644
--- a/Binary/RomList.txt
+++ b/Binary/RomList.txt
@@ -198,7 +198,7 @@ RCZ280 (RCZ280_ext.rom, RCZ280_nat.rom, RCZ280_nat_zz.rom):
  - Built-in Z280 UART (Z2U) is buffered and interrupt driven only
    on _nat and _nat_zz variants.  It uses polling I/O on _ext.
  - Console on whichever serial module is installed,
-   order of priority is UART, SIO, DUART, ACIA, Z2U
+   order of priority is Z2U, UART, SIO, DUART, ACIA
  - Baud rate is determined by hardware, but normally 115200.
  - Auto support for RC2014 Compact Flash Module
  - Auto support for RC2014 PPIDE Module
@@ -221,9 +221,9 @@ RCZ280 (RCZ280_ext.rom, RCZ280_nat.rom, RCZ280_nat_zz.rom):
 
 SCZ180 (SCZ180_126.rom, SCZ180_130.rom, SCZ180_131.rom, SCZ140.rom):
  - Same as RCZ180
- - Adds auto support for SPI SD Card
- - The 3 different variants of SCZ180 are provided to match the
-   3 corresponding systems (SC126, SC130, SC131, and SC140)
+ - Adds auto support for onboard SPI SD Card
+ - The 4 different variants of SCZ180 are provided to match the
+   4 corresponding systems (SC126, SC130, SC131, and SC140)
    designed by Stephen Cousins.
  - Support for PropIO V2 may be enabled in config (PRPENABLE).  If
    enabled, will auto-detect and install associated
diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt
index 1ffeef76..c6b5f8b0 100644
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -22,6 +22,7 @@ Version 3.1.1
 - WBW: Add support for ZZRCC
 - WBW: Allow selection of RAM/ROM disk individually in build
 - WBW: Support 256KB ROM size
+- WBW: CP/M 3 RTC support is now complete (reads and writes RTC date/time)
 
 Version 3.1
 -----------
diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh
index 6c351ae0..117fa459 100755
--- a/Source/HBIOS/Build.sh
+++ b/Source/HBIOS/Build.sh
@@ -25,6 +25,8 @@ config=$2
 romsize=$3
 romname=$4
 
+export platform
+
 # prompt if no match
 platforms=($(find Config -name \*.asm -print | \
 	sed -e 's,Config/,,' -e 's/_.*$//' | sort -u))
diff --git a/Source/HBIOS/Config/RCZ280_nat_zzr.asm b/Source/HBIOS/Config/RCZ280_nat_zzr.asm
index ac12b876..a8f7da73 100644
--- a/Source/HBIOS/Config/RCZ280_nat_zzr.asm
+++ b/Source/HBIOS/Config/RCZ280_nat_zzr.asm
@@ -28,8 +28,7 @@
 ;
 #include "Config/RCZ280_nat.asm"
 ;
-;CPUOSC		.SET	29491200	; CPU OSC FREQ IN MHZ
-CPUOSC		.SET	24000000	; CPU OSC FREQ IN MHZ
+CPUOSC		.SET	29491200	; CPU OSC FREQ IN MHZ
 ;
 RAMSIZE		.SET	384		; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
 RAM_RESERVE	.SET	128		; RESERVE FIRST N KB OF RAM (USUALLY 0)
diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile
index a5a480f8..ed639fdf 100644
--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -44,13 +44,20 @@ TOOLS =../../Tools
 OTHERS =  *.img *.rom *.com *.bin *.z80 cpm.sys zsys.sys Build.inc RomDisk.tmp font*.asm *.dat
 include $(TOOLS)/Makefile.inc
 
+ifneq ($(findstring $(platform), N8 MK4 RCZ180 SCZ180 DYNO),)
+	TASM=$(BINDIR)/uz80as -t hd64180
+endif
+
+ifneq ($(findstring $(platform), RCZ280),)
+	TASM=$(BINDIR)/uz80as -t z280
+endif
+
 ifeq ($(DIFFMAKE),1)
 	DIFFBUILD := -d $(DIFFTO)/Source/HBIOS
 endif
 
 DIFFPATH = $(DIFFTO)/Binary
 
-
 ROMSIZE=512
 
 N8_std.rom: ROMSIZE=512
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 717dcce5..a5e0cd49 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -812,7 +812,7 @@ HBX_INT:	; COMMON INTERRUPT ROUTING CODE
 	POP	HL			; RESTORE HL
 ;
 	CALL	HBX_RETI		; RETI FOR Z80 PERIPHERALS
-	.DB	$ED,$55			; RETIL
+	RETIL
 ;
 HBX_RETI:	
 	RETI
@@ -1192,8 +1192,6 @@ Z280_INITZ:
 ;
 	DIAG(%00000011)
 	LED($00)
-	
-	; ok
 ;
 ; CHECK BATTERY BACKUP STATUS BEFORE WE COPY PROXY TO UPPER MEMORY
 ;
@@ -1662,7 +1660,7 @@ Z280_TC	.EQU	CPUOSC / 4 / 50 / 2	; TIME CONSTANT
 ;
 	LD	A,%10100000		; CONFIG: C, RE, IE
 	OUT	(Z280_CT0_CFG),A	; SET C/T 0
-	LD	HL,Z280_TC		; TIME CONSTANT & COUNTER
+	LD	HL,CPUOSC / 50 / 16	; TIME CONSTANT & COUNTER
 	LD	C,Z280_CT0_TC		; SET C/T 0
 	OUTW	(C),HL
 	LD	C,Z280_CT0_CT		; SET C/T 0
@@ -1887,12 +1885,12 @@ HB_Z280BUS1:
 #IF (CPUFAM == CPU_Z280)
 	LD	A,Z280_MEMLOWAIT
 	CALL	PRTDECB
-	CALL	PRTSTRD
-	.TEXT	" MEM LO W/S, $"
+	LD	A,'/'
+	CALL	COUT
 	LD	A,Z280_MEMHIWAIT
 	CALL	PRTDECB
 	CALL	PRTSTRD
-	.TEXT	" MEM HI W/S, $"
+	.TEXT	" MEM W/S, $"
 #ELSE
 	XOR	A
   #IF (CPUFAM == CPU_Z180)
@@ -3669,8 +3667,11 @@ Z280_TIMINT:
 	PUSH	DE
 	PUSH	HL
 ;
-	; CALL PRIMARY TIMER LOGIC
-	CALL	HB_TIMINT
+	; CALL PRIMARY TIMER LOGIC ON EVERY OTHER INT
+	LD	A,(Z280_TIMCTR)
+	XOR	$FF
+	LD	(Z280_TIMCTR),A
+	CALL	Z,HB_TIMINT
 ;
 	; SELECT I/O PAGE $FE (SAVING PREVIOUS VALUE)
 	LD	C,Z280_IOPR		; REG C POINTS TO I/O PAGE REGISTER
@@ -3695,7 +3696,9 @@ Z280_TIMINT:
 	POP	BC
 	POP	AF
 ;
-	.DB	$ED,$55			; RETIL
+	RETIL
+;
+Z280_TIMCTR	.DB	0		; USED TO DIVIDE TIMER INTS
 ;
 #ENDIF
 ;
@@ -3879,7 +3882,7 @@ Z280_DIAG:
 	CALL	PRTHEXWORDHL		; DUMP MSR
 	EX	(SP),HL			; MSR TO STK, RECOVER HL
 ;
-	;.DB	$ED,$55			; RETIL
+	;RETIL
 	DI
 	HALT
 ;
diff --git a/Source/HBIOS/z2u.asm b/Source/HBIOS/z2u.asm
index c8452943..d4ac9ac3 100644
--- a/Source/HBIOS/z2u.asm
+++ b/Source/HBIOS/z2u.asm
@@ -245,7 +245,7 @@ Z2U_INTRCV4:
 	POP	BC
 	POP	AF
 ;
-	.DB	$ED,$55			; RETIL
+	RETIL
 #ENDIF
 ;
 ; DRIVER FUNCTION TABLE
diff --git a/Source/ver.inc b/Source/ver.inc
index 53785179..44657b4a 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.66"
+#DEFINE BIOSVER	"3.1.1-pre.67"
diff --git a/Source/ver.lib b/Source/ver.lib
index a20b1715..4f77d20d 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.66"
+	db	"3.1.1-pre.67"
 	endm
diff --git a/Tools/Makefile.inc b/Tools/Makefile.inc
index 46d8dc48..f7def88d 100644
--- a/Tools/Makefile.inc
+++ b/Tools/Makefile.inc
@@ -35,7 +35,7 @@ DIFFPATH := $(DIFFTO)/$(RELPATH)
 CASEFN = $(TOOLS)/unix/casefn.sh
 
 ZXCC=$(BINDIR)/zx
-TASM=$(BINDIR)/uz80as -t hd64180
+TASM=$(BINDIR)/uz80as -t z80
 OPENSPIN=$(BINDIR)/openspin
 BSTC=$(BINDIR)//bstc
 CPMCP=$(BINDIR)/cpmcp
diff --git a/Tools/tasm32/TASM280.TAB b/Tools/tasm32/TASM280.TAB
index 00d32d2f..f8644eec 100644
--- a/Tools/tasm32/TASM280.TAB
+++ b/Tools/tasm32/TASM280.TAB
@@ -438,6 +438,7 @@ RET  PE      E8   1 NOP 1
 RET  PO      E0   1 NOP 1
 RET  Z       C8   1 NOP 1
 RETI ""      4DED 2 NOP 1
+RETIL ""     55ED 2 NOP 1	/* Z280 */
 RETN ""      45ED 2 NOP 1
 
 RL   (HL)    16CB 2 NOP 1
diff --git a/Tools/unix/uz80as/targets.c b/Tools/unix/uz80as/targets.c
index 742ef674..1b8bbc9d 100644
--- a/Tools/unix/uz80as/targets.c
+++ b/Tools/unix/uz80as/targets.c
@@ -14,6 +14,7 @@
 
 extern const struct target s_target_z80;
 extern const struct target s_target_hd64180;
+extern const struct target s_target_z280;
 extern const struct target s_target_gbcpu;
 extern const struct target s_target_dp2200;
 extern const struct target s_target_dp2200ii;
@@ -40,6 +41,7 @@ extern const struct target s_target_m68hc11;
 static const struct target *s_targets[] = {
 	&s_target_z80,
 	&s_target_hd64180,
+	&s_target_z280,
 	&s_target_gbcpu,
 	&s_target_dp2200,
 	&s_target_dp2200ii,
diff --git a/Tools/unix/uz80as/z80.c b/Tools/unix/uz80as/z80.c
index 446e2097..60df3c08 100644
--- a/Tools/unix/uz80as/z80.c
+++ b/Tools/unix/uz80as/z80.c
@@ -47,146 +47,146 @@
  */
 
 static const struct matchtab s_matchtab_z80[] = {
-	{ "LD b,b", "40b0c1.", 3, 0 },
+	{ "LD b,b", "40b0c1.", 7, 0 },
 	{ "LD p,p", "DD.40b0c1.", 1, 1 },
 	{ "LD q,q", "FD.40b0c1.", 1, 1 },
-	{ "LD b,(HL)", "46b0.", 3, 0 },
-	{ "LD b,(e)", "d1.46b0.00.", 3, 0, "ii" },
-	{ "LD b,(ca)", "d1.46b0.d2.", 3, 0, "ii" },
-	{ "LD A,I", "ED.57.", 3, 0 },
-	{ "LD A,R", "ED.5F.", 3, 0 },
-	{ "LD A,(BC)", "0A.", 3, 0 },
-	{ "LD A,(DE)", "1A.", 3, 0 },
-	{ "LD A,(a)", "3A.e0", 3, 0 },
-	{ "LD b,a", "06b0.d1.", 3, 0, "e8" },
+	{ "LD b,(HL)", "46b0.", 7, 0 },
+	{ "LD b,(e)", "d1.46b0.00.", 7, 0, "ii" },
+	{ "LD b,(ca)", "d1.46b0.d2.", 7, 0, "ii" },
+	{ "LD A,I", "ED.57.", 7, 0 },
+	{ "LD A,R", "ED.5F.", 7, 0 },
+	{ "LD A,(BC)", "0A.", 7, 0 },
+	{ "LD A,(DE)", "1A.", 7, 0 },
+	{ "LD A,(a)", "3A.e0", 7, 0 },
+	{ "LD b,a", "06b0.d1.", 7, 0, "e8" },
 	{ "LD p,a", "DD.06b0.d1.", 1, 1, "e8" },
 	{ "LD q,a", "FD.06b0.d1.", 1, 1, "e8" },
-	{ "LD I,A", "ED.47.", 3, 0 },
-	{ "LD R,A", "ED.4F.", 3, 0 },
-	{ "LD SP,HL", "F9.", 3, 0 },
-	{ "LD SP,e", "d0.F9.", 3, 0 },
-	{ "LD HL,(HL)", "ED.26.", 2, 0 }, // Z280
-	{ "LD HL,(a)", "2A.e0", 3, 0 },
-	{ "LD d,(a)", "ED.4Bf0.e1", 3, 0 },
-	{ "LD d,a", "01f0.e1", 3, 0 },
-	{ "LD e,(a)", "d0.2A.e1", 3, 0 },
-	{ "LD e,a", "d0.21.e1", 3, 0 },
-	{ "LD (HL),DE", "ED.1E.", 2, 0 }, // Z280
-	{ "LD (HL),b", "70c0.", 3, 0 },
-	{ "LD (HL),a", "36.d0.", 3, 0, "e8" },
-	{ "LD (BC),A", "02.", 3, 0 },
-	{ "LD (DE),A", "12.", 3, 0 },
-	{ "LD (e),b", "d0.70c1.00.", 3, 0, "ii" },
-	{ "LD (ca),b", "d0.70c2.d1.", 3, 0, "ii" },
-	{ "LD (e),a", "d0.36.00.d1.", 3, 0, "iie8" },
-	{ "LD (ca),a", "d0.36.d1.d2.", 3, 0, "iie8" },
-	{ "LD (a),A", "32.e0", 3, 0 },
-	{ "LD (a),HL", "22.e0", 3, 0 },
-	{ "LD (a),d", "ED.43f1.e0", 3, 0 },
-	{ "LD (a),e", "d1.22.e0", 3, 0 },
-	{ "PUSH f", "C5f0.", 3, 0 },
-	{ "PUSH e", "d0.E5.", 3, 0 },
-	{ "POP f", "C1f0.", 3, 0 },
-	{ "POP e", "d0.E1.", 3, 0 },
-	{ "EX DE,HL", "EB.", 3, 0 },
-	{ "EX AF,AF'", "08.", 3, 0 },
-	{ "EX (SP),HL", "E3.", 3, 0 },
-	{ "EX (SP),e", "d0.E3.", 3, 0 },
-	{ "EXX", "D9.", 3, 0 },
-	{ "LDI", "ED.A0.", 3, 0 },
-	{ "LDIR", "ED.B0.", 3, 0 },
-	{ "LDD", "ED.A8.", 3, 0 },
-	{ "LDDR", "ED.B8.", 3, 0 },
-	{ "CPI", "ED.A1.", 3, 0 },
-	{ "CPIR", "ED.B1.", 3, 0 },
-	{ "CPD", "ED.A9.", 3, 0 },
-	{ "CPDR", "ED.B9.", 3, 0 },
-	{ "ADD HL,A", "ED.6D.", 2, 0 }, // Z280
-	{ "ADD HL,d", "09f0.", 3, 0 },
-	{ "ADD IX,i", "DD.09f0.", 3, 0 },
-	{ "ADD IY,j", "FD.09f0.", 3, 0 },
-	{ "ADC HL,d", "ED.4Af0.", 3, 0 },
-	{ "SBC HL,d", "ED.42f0.", 3, 0 },
-	{ "g A,b", "m080b0c1.", 3, 0 },
+	{ "LD I,A", "ED.47.", 7, 0 },
+	{ "LD R,A", "ED.4F.", 7, 0 },
+	{ "LD SP,HL", "F9.", 7, 0 },
+	{ "LD SP,e", "d0.F9.", 7, 0 },
+	{ "LD HL,(HL)", "ED.26.", 4, 0 }, // Z280
+	{ "LD HL,(a)", "2A.e0", 7, 0 },
+	{ "LD d,(a)", "ED.4Bf0.e1", 7, 0 },
+	{ "LD d,a", "01f0.e1", 7, 0 },
+	{ "LD e,(a)", "d0.2A.e1", 7, 0 },
+	{ "LD e,a", "d0.21.e1", 7, 0 },
+	{ "LD (HL),DE", "ED.1E.", 4, 0 }, // Z280
+	{ "LD (HL),b", "70c0.", 7, 0 },
+	{ "LD (HL),a", "36.d0.", 7, 0, "e8" },
+	{ "LD (BC),A", "02.", 7, 0 },
+	{ "LD (DE),A", "12.", 7, 0 },
+	{ "LD (e),b", "d0.70c1.00.", 7, 0, "ii" },
+	{ "LD (ca),b", "d0.70c2.d1.", 7, 0, "ii" },
+	{ "LD (e),a", "d0.36.00.d1.", 7, 0, "iie8" },
+	{ "LD (ca),a", "d0.36.d1.d2.", 7, 0, "iie8" },
+	{ "LD (a),A", "32.e0", 7, 0 },
+	{ "LD (a),HL", "22.e0", 7, 0 },
+	{ "LD (a),d", "ED.43f1.e0", 7, 0 },
+	{ "LD (a),e", "d1.22.e0", 7, 0 },
+	{ "PUSH f", "C5f0.", 7, 0 },
+	{ "PUSH e", "d0.E5.", 7, 0 },
+	{ "POP f", "C1f0.", 7, 0 },
+	{ "POP e", "d0.E1.", 7, 0 },
+	{ "EX DE,HL", "EB.", 7, 0 },
+	{ "EX AF,AF'", "08.", 7, 0 },
+	{ "EX (SP),HL", "E3.", 7, 0 },
+	{ "EX (SP),e", "d0.E3.", 7, 0 },
+	{ "EXX", "D9.", 7, 0 },
+	{ "LDI", "ED.A0.", 7, 0 },
+	{ "LDIR", "ED.B0.", 7, 0 },
+	{ "LDD", "ED.A8.", 7, 0 },
+	{ "LDDR", "ED.B8.", 7, 0 },
+	{ "CPI", "ED.A1.", 7, 0 },
+	{ "CPIR", "ED.B1.", 7, 0 },
+	{ "CPD", "ED.A9.", 7, 0 },
+	{ "CPDR", "ED.B9.", 7, 0 },
+	{ "ADD HL,A", "ED.6D.", 4, 0 }, // Z280
+	{ "ADD HL,d", "09f0.", 7, 0 },
+	{ "ADD IX,i", "DD.09f0.", 7, 0 },
+	{ "ADD IY,j", "FD.09f0.", 7, 0 },
+	{ "ADC HL,d", "ED.4Af0.", 7, 0 },
+	{ "SBC HL,d", "ED.42f0.", 7, 0 },
+	{ "g A,b", "m080b0c1.", 7, 0 },
 	{ "g A,p", "DD.m080b0c1.", 1, 1 },
 	{ "g A,q", "FD.m080b0c1.", 1, 1 },
-	{ "g A,(HL)", "m086b0.", 3, 0 },
-	{ "g A,(ca)", "m0d1.86b0.d2.", 3, 0, "ii" },
-	{ "g A,a", "m0C6b0.d1.", 3, 0, "e8" },
-	{ "g b", "n080b0c1.", 3, 0 },
+	{ "g A,(HL)", "m086b0.", 7, 0 },
+	{ "g A,(ca)", "m0d1.86b0.d2.", 7, 0, "ii" },
+	{ "g A,a", "m0C6b0.d1.", 7, 0, "e8" },
+	{ "g b", "n080b0c1.", 7, 0 },
 	{ "g p", "DD.n080b0c1.", 1, 1 },
 	{ "g q", "FD.n080b0c1.", 1, 1 },
-	{ "g (HL)", "n086b0.", 3, 0 },
-	{ "g (ca)", "n0d1.86b0.d2.", 3, 0, "ii" },
-	{ "g a", "n0C6b0.d1.", 3, 0, "e8" },
-	{ "h b", "04b1c0.", 3, 0 },
+	{ "g (HL)", "n086b0.", 7, 0 },
+	{ "g (ca)", "n0d1.86b0.d2.", 7, 0, "ii" },
+	{ "g a", "n0C6b0.d1.", 7, 0, "e8" },
+	{ "h b", "04b1c0.", 7, 0 },
 	{ "h p", "DD.04b1c0.", 1, 1 },
 	{ "h q", "FD.04b1c0.", 1, 1 },
-	{ "h (HL)", "34c0.", 3, 0 },
-	{ "h (ca)", "d1.34c0.d2.", 3, 0, "ii" },
-	{ "h (e)", "d1.34c0.00.", 3, 0, "ii" },
-	{ "INC d", "03f0.", 3, 0 },
-	{ "INC e", "d0.23.", 3, 0 },
-	{ "DEC d", "0Bf0.", 3, 0 },
-	{ "DEC e", "d0.2B.", 3, 0 },
-	{ "DAA", "27.", 3, 0 },
-	{ "CPL", "2F.", 3, 0 },
-	{ "NEG", "ED.44.", 3, 0 },
-	{ "CCF", "3F.", 3, 0 },
-	{ "SCF", "37.", 3, 0 },
-	{ "NOP", "00.", 3, 0 },
-	{ "HALT", "76.", 3, 0 },
-	{ "DI", "F3.", 3, 0 },
-	{ "EI", "FB.", 3, 0 },
-	{ "IM a", "ED.k0.", 3, 0, "tt" },
-	{ "RLCA", "07.", 3, 0 },
-	{ "RLA", "17.", 3, 0 },
-	{ "RRCA", "0F.", 3, 0 },
-	{ "RRA", "1F.", 3, 0 },
+	{ "h (HL)", "34c0.", 7, 0 },
+	{ "h (ca)", "d1.34c0.d2.", 7, 0, "ii" },
+	{ "h (e)", "d1.34c0.00.", 7, 0, "ii" },
+	{ "INC d", "03f0.", 7, 0 },
+	{ "INC e", "d0.23.", 7, 0 },
+	{ "DEC d", "0Bf0.", 7, 0 },
+	{ "DEC e", "d0.2B.", 7, 0 },
+	{ "DAA", "27.", 7, 0 },
+	{ "CPL", "2F.", 7, 0 },
+	{ "NEG", "ED.44.", 7, 0 },
+	{ "CCF", "3F.", 7, 0 },
+	{ "SCF", "37.", 7, 0 },
+	{ "NOP", "00.", 7, 0 },
+	{ "HALT", "76.", 7, 0 },
+	{ "DI", "F3.", 7, 0 },
+	{ "EI", "FB.", 7, 0 },
+	{ "IM a", "ED.k0.", 7, 0, "tt" },
+	{ "RLCA", "07.", 7, 0 },
+	{ "RLA", "17.", 7, 0 },
+	{ "RRCA", "0F.", 7, 0 },
+	{ "RRA", "1F.", 7, 0 },
 	{ "SLL b", "CB.30c0.", 1, 1 },
 	{ "SLL (HL)", "CB.36.", 1, 1 },
 	{ "SLL (ca)", "d0.CB.d1.36.", 1, 1, "ii" },
 	{ "SLL (ca),b", "d0.CB.d1.30c2.", 1, 1, "ii" },
-	{ "k b", "CB.00b0c1.", 3, 0 },
-	{ "k (HL)", "CB.06b0.", 3, 0 },
-	{ "k (ca)", "d1.CB.d2.06b0.", 3, 0, "ii" },
+	{ "k b", "CB.00b0c1.", 7, 0 },
+	{ "k (HL)", "CB.06b0.", 7, 0 },
+	{ "k (ca)", "d1.CB.d2.06b0.", 7, 0, "ii" },
 	{ "k (ca),b", "d1.CB.d2.00b0c3.", 1, 1, "ii" },
-	{ "RLD", "ED.6F.", 3, 0 },
-	{ "RRD", "ED.67.", 3, 0 },
-	{ "l a,b", "CB.00g0b1c2.", 3, 0, "b3" },
-	{ "l a,(HL)", "CB.06g0b1.", 3, 0, "b3" },
-	{ "l a,(ca)", "d2.CB.d3.06g0b1.", 3, 0, "b3ii" },
+	{ "RLD", "ED.6F.", 7, 0 },
+	{ "RRD", "ED.67.", 7, 0 },
+	{ "l a,b", "CB.00g0b1c2.", 7, 0, "b3" },
+	{ "l a,(HL)", "CB.06g0b1.", 7, 0, "b3" },
+	{ "l a,(ca)", "d2.CB.d3.06g0b1.", 7, 0, "b3ii" },
 	{ "RES a,(ca),b", "d1.CB.d2.80b0c3.", 1, 1, "b3ii" },
 	{ "SET a,(ca),b", "d1.CB.d2.C0b0c3.", 1, 1, "b3ii" },
-	{ "JP (HL)", "E9.", 3, 0 },
-	{ "JP (e)", "d0.E9.", 3, 0 },
-	{ "JP m,a", "C2b0.e1", 3, 0 },
-	{ "JP a", "C3.e0", 3, 0 },
-	{ "JR n,a", "20b0.i1.", 3, 0, "r8" },
-	{ "JR a", "18.i0.", 3, 0, "r8" },
-	{ "DJNZ a", "10.i0.", 3, 0, "r8" },
-	{ "CALL m,a", "C4b0.e1", 3, 0 },
-	{ "CALL a", "CD.e0", 3, 0 },
-	{ "RETI", "ED.4D.", 3, 0 },
-	{ "RETN", "ED.45.", 3, 0 },
-	{ "RET m", "C0b0.", 3, 0 },
-	{ "RET", "C9.", 3, 0 },
-	{ "RST a", "C7j0.", 3, 0, "ss" },
-	{ "IN b,(C)", "ED.40b0.", 3, 0 },
-	{ "IN A,(a)", "DB.d0.", 3, 0, "e8" },
-	{ "IN F,(a)", "ED.70.", 3, 0 },
+	{ "JP (HL)", "E9.", 7, 0 },
+	{ "JP (e)", "d0.E9.", 7, 0 },
+	{ "JP m,a", "C2b0.e1", 7, 0 },
+	{ "JP a", "C3.e0", 7, 0 },
+	{ "JR n,a", "20b0.i1.", 7, 0, "r8" },
+	{ "JR a", "18.i0.", 7, 0, "r8" },
+	{ "DJNZ a", "10.i0.", 7, 0, "r8" },
+	{ "CALL m,a", "C4b0.e1", 7, 0 },
+	{ "CALL a", "CD.e0", 7, 0 },
+	{ "RETI", "ED.4D.", 7, 0 },
+	{ "RETN", "ED.45.", 7, 0 },
+	{ "RET m", "C0b0.", 7, 0 },
+	{ "RET", "C9.", 7, 0 },
+	{ "RST a", "C7j0.", 7, 0, "ss" },
+	{ "IN b,(C)", "ED.40b0.", 7, 0 },
+	{ "IN A,(a)", "DB.d0.", 7, 0, "e8" },
+	{ "IN F,(a)", "ED.70.", 7, 0 },
 	{ "IN (C)", "ED.70.", 1, 1 },
-	{ "INI", "ED.A2.", 3, 0 },
-	{ "INIR", "ED.B2.", 3, 0 },
-	{ "IND", "ED.AA.", 3, 0 },
-	{ "INDR", "ED.BA.", 3, 0 },
+	{ "INI", "ED.A2.", 7, 0 },
+	{ "INIR", "ED.B2.", 7, 0 },
+	{ "IND", "ED.AA.", 7, 0 },
+	{ "INDR", "ED.BA.", 7, 0 },
 	{ "OUT (C),0", "ED.71.", 1, 1 },
-	{ "OUT (C),b", "ED.41b0.", 3, 0 },
-	{ "OUT (a),A", "D3.d0.", 3, 0, "e8" },
-	{ "OUTI", "ED.A3.", 3, 0 },
-	{ "OTIR", "ED.B3.", 3, 0 },
-	{ "OUTD", "ED.AB.", 3, 0 },
-	{ "OTDR", "ED.BB.", 3, 0 },
+	{ "OUT (C),b", "ED.41b0.", 7, 0 },
+	{ "OUT (a),A", "D3.d0.", 7, 0, "e8" },
+	{ "OUTI", "ED.A3.", 7, 0 },
+	{ "OTIR", "ED.B3.", 7, 0 },
+	{ "OUTD", "ED.AB.", 7, 0 },
+	{ "OTDR", "ED.BB.", 7, 0 },
 	/* hd64180 added instructions */
 	{ "IN0 b,(a)", "ED.00b0.d1.", 2, 0, "e8" }, 
 	{ "OUT0 (a),b", "ED.01b1.d0.", 2, 0, "e8" },
@@ -201,14 +201,15 @@ static const struct matchtab s_matchtab_z80[] = {
 	{ "TST a", "ED.64.d0.", 2, 0, "e8" },
 	{ "TSTIO a", "ED.74.d0.", 2, 0, "e8" },
 	/* Z280 added instructions */
-	{ "PCACHE", "ED.65.", 2, 0 },
-	{ "LDCTL (C),HL", "ED.6E.", 2, 0 },
-	{ "LDCTL HL,(C)", "ED.66.", 2, 0 },
-	{ "LDCTL USP,HL", "ED.8F.", 2, 0 },
-	{ "LDCTL IY,(C)", "FD.ED.66.", 2, 0 },
-	{ "LDCTL (C),IY", "FD.ED.6E.", 2, 0 },
-	{ "MULTU A,a", "FD.ED.F9.d0.", 2, 0 },
-	{ "OUTW (C),HL", "ED.BF.", 2, 0 },
+	{ "PCACHE", "ED.65.", 4, 0 },
+	{ "LDCTL (C),HL", "ED.6E.", 4, 0 },
+	{ "LDCTL HL,(C)", "ED.66.", 4, 0 },
+	{ "LDCTL USP,HL", "ED.8F.", 4, 0 },
+	{ "LDCTL IY,(C)", "FD.ED.66.", 4, 0 },
+	{ "LDCTL (C),IY", "FD.ED.6E.", 4, 0 },
+	{ "MULTU A,a", "FD.ED.F9.d0.", 4, 0 },
+	{ "OUTW (C),HL", "ED.BF.", 4, 0 },
+	{ "RETIL", "ED.55.", 4, 0 },
 	{ NULL, NULL },
 };
 
@@ -374,3 +375,14 @@ const struct target s_target_hd64180 = {
 	.pat_next_str = pat_next_str_z80,
 	.mask = 2
 };
+
+const struct target s_target_z280 = {
+	.id = "z280",
+	.descr = "Zilog Z280",
+	.matcht = s_matchtab_z80,
+	.matchf = match_z80,
+	.genf = gen_z80,
+	.pat_char_rewind = pat_char_rewind_z80,
+	.pat_next_str = pat_next_str_z80,
+	.mask = 4
+};