Perliminary support for Sergey's Z80-512K

- Watchdog functionality will be enabled if a system timer is operational.
- LED indicates boot progress and thereafter disk I/O.

Doc/ChangeLog.txt

@@ -16,6 +16,7 @@ Version 3.1.1
 - PMS: Added "updater.asm" which allows uploading and updating ROM in one step
 - WBW: Support for Z280 w/ native memory and interrupt mode 3
 - WBW: Support for Z280 UART (interrupt driven only in interrupt mode 3)
+- WBW: Add support Z80-512K (watchdog and LED)
 
 Version 3.1
 -----------

Source/HBIOS/Config/RCZ80_skz.asm

@@ -0,0 +1,34 @@
+;
+;==================================================================================================
+;   RC2014 Z80 STANDARD CONFIGURATION W/ SERGEY KISELEV Z80 + 512K CPU
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE	PLATFORM_NAME	"RC2014 (SKZ)"
+;
+#DEFINE	BOOT_DEFAULT	"H"		; DEFAULT BOOT LOADER CMD ON <CR> OR AUTO BOOT
+;
+#include "Config/RCZ80_std.asm"
+;
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
+LEDPORT		.SET	$6E		; STATUS LED PORT ADDRESS
+;
+WDOGMODE	.SET	WDOG_SKZ	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]

Source/HBIOS/Makefile

@@ -18,6 +18,7 @@ else
 	OBJECTS += RCZ80_mt.rom RCZ80_mt.com RCZ80_mt.upd
 	OBJECTS += RCZ80_duart.rom RCZ80_duart.com RCZ80_duart.upd
 	OBJECTS += RCZ80_std.rom RCZ80_std.com RCZ80_std.upd
+	OBJECTS += RCZ80_skz.rom RCZ80_skz.com RCZ80_skz.upd
 	OBJECTS += RCZ80_zrc.rom RCZ80_zrc.com RCZ80_zrc.upd
 	OBJECTS += SBC_simh.rom SBC_simh.com SBC_simh.upd
 	OBJECTS += SBC_std.rom SBC_std.com SBC_std.upd

Source/HBIOS/cfg_dyno.asm

@@ -50,6 +50,8 @@ CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_ezz80.asm

@@ -36,7 +36,6 @@ MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
-WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 ;
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
 KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
@@ -53,6 +52,9 @@ CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_EZZ80	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_master.asm

@@ -57,7 +57,6 @@ MK4_SD		.EQU	$89		; MK4: SD CARD CONTROL REGISTER ADR
 MK4_RTC		.EQU	$8A		; MK4: RTC LATCH REGISTER ADR
 ;
 RTCIO		.EQU	$70		; RTC LATCH REGISTER ADR
-WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
 PPIBASE		.EQU	$60		; PRIMARY PARALLEL PORT REGISTERS BASE ADR
 ;
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
@@ -75,6 +74,9 @@ CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6F		; WATCHDOG REGISTER ADR
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_mk4.asm

@@ -53,6 +53,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_n8.asm

@@ -56,6 +56,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_rcz180.asm

@@ -53,6 +53,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_rcz280.asm

@@ -56,6 +56,8 @@ CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_rcz80.asm

@@ -52,6 +52,9 @@ CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+WDOGIO		.EQU	$6E		; WATCHDOG REGISTER ADR
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_sbc.asm

@@ -50,6 +50,8 @@ CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_scz180.asm

@@ -48,6 +48,8 @@ CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$0D		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_zeta.asm

@@ -42,6 +42,8 @@ CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/cfg_zeta2.asm

@@ -53,6 +53,8 @@ CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
 EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
 ;
+WDOGMODE	.EQU	WDOG_NONE	; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ]
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS

Source/HBIOS/hbios.asm

@@ -1960,6 +1960,42 @@ NOT_REC_M1:
 IS_REC_M1:
 	CALL	CALLLIST
 ;
+; IF WATCHDOG FUNCTIONALITY IS REQUESTED, CHECK TO MAKE SURE
+; WE ARE GETTING INTERRUPTS.  IF SO, ENABLE THE WATCHDOG.
+;
+#IF (WDOGMODE != WDOG_NONE)
+	CALL	NEWLINE
+	PRTS("WDOG: $")
+	PRTS("MODE=$")
+
+  #IF (WDOGMODE == WDOG_EZZ80)
+	PRTS("EZZ80$")
+  #ENDIF
+;
+  #IF (WDOGMODE == WDOG_SKZ)
+	PRTS("SKZ$")
+	LD	HL,(HB_TICKS)		; GET LOW WORD
+	LD	A,H			; CHECK FOR
+	OR	L			; ... ZERO
+	JR	Z,HB_WDOFF		; SKIP IF NOT TICKING
+	IN	A,($6D)			; GET PORT VALUE
+	SET	5,A			; SET WDOG ENABLE BIT
+	OUT	($6D),A			; DO IT
+  #ENDIF
+;
+	PRTS(" IO=0x$")
+	LD	A,WDOGIO
+	CALL	PRTHEXBYTE
+	PRTS(" ENABLED$")
+	JR	HB_WDZ
+;
+HB_WDOFF:
+	PRTS(" DISABLED$")
+;
+HB_WDZ:
+;
+#ENDIF
+;
 ; RECORD HEAP CURB AT THE CURRENT VALUE OF HEAP TOP.  HEAP CURB
 ; MARKS THE POINT IN THE HEAP AFTER WHICH MEMORY IS RELEASED
 ; WHEN AN HBIOS RESET IS PEFORMED.
@@ -3580,7 +3616,7 @@ HB_TICK1:
 	IN0	A,(Z180_TMDR0L)
 #ENDIF
 ;
-#IF (PLATFORM == PLT_EZZ80)
+#IF (WDOGMODE != WDOG_NONE)
 	; PULSE WATCHDOG
 	OUT	(WDOGIO),A		; VALUE IS IRRELEVANT
 #ENDIF

Source/HBIOS/std.asm

@@ -309,6 +309,12 @@ EMUTYP_NONE	.EQU	0		; NONE
 EMUTYP_TTY	.EQU	1		; TTY
 EMUTYP_ANSI	.EQU	2		; ANSI
 ;
+; WATCHDOG TYPES
+;
+WDOG_NONE	.EQU	0		; NONE
+WDOG_EZZ80	.EQU	1		; EASY Z80 WATCHDOG
+WDOG_SKZ	.EQU	2		; SK Z80 CPU W/ 512K
+;
 ; DEVICE DRIVER TO BE INITIALIZED FIRST. FIRST CIO DRIVER, UNIT 0 INITIALIZED BECOMES PRIMARY CONSOLE.
 ; IS AN INDEX INTO THE ENABLED INITIALIZATION DRIVER LIST i.e. ASCI, UART, SIO, ACIA, PIO, UF ETC.
 ; EXAMPLE: IF ONLY UART, SIO AND PIO ARE ENABLE AND THE SIO IS DESIRED AS THE PRIMARY CONSOLE,

Source/ver.inc

@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.43"
+#DEFINE BIOSVER	"3.1.1-pre.44"

Source/ver.lib

@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.43"
+	db	"3.1.1-pre.44"
 	endm