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Prelim speed management framework

pull/252/head
b1ackmai1er 4 years ago
parent
commit
47d9c4008d
  1. 2
      Source/HBIOS/Config/MBC_std.asm
  2. 2
      Source/HBIOS/cfg_master.asm
  3. 2
      Source/HBIOS/cfg_mbc.asm
  4. 2
      Source/HBIOS/cfg_sbc.asm
  5. 29
      Source/HBIOS/hbios.asm
  6. 11
      Source/HBIOS/std.asm

2
Source/HBIOS/Config/MBC_std.asm

@ -34,4 +34,4 @@ FDENABLE .SET TRUE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM)
PPIDEENABLE .SET TRUE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
;
DSKYENABLE .SET FALSE ; ENABLES DSKY
DSKYMODE .SET DSKYMODE_NG ; DSKY VERTSION: DSKYMODE_[V1|NG]
DSKYMODE .SET DSKYMODE_NG ; DSKY VERSION: DSKYMODE_[V1|NG]

2
Source/HBIOS/cfg_master.asm

@ -20,6 +20,8 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)

2
Source/HBIOS/cfg_mbc.asm

@ -23,6 +23,8 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)

2
Source/HBIOS/cfg_sbc.asm

@ -23,6 +23,8 @@ TICKFREQ .EQU 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ)
;
BOOT_TIMEOUT .EQU -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE
;
CPUSPDCAP .EQU SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO
CPUSPDDEF .EQU SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW
CPUOSC .EQU 8000000 ; CPU OSC FREQ IN MHZ
INTMODE .EQU 0 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280)
DEFSERCFG .EQU SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG (SEE STD.ASM)

29
Source/HBIOS/hbios.asm

@ -187,6 +187,22 @@ RTCDEF .EQU 0 ; ALLOWS DRIVERS TO SET BITS
RTCDEF .SET RTCDEF | %00000001 ; SC128 I2C SCL BIT
#ENDIF
;
#IF (!(CPUSPDCAP==SPD_FIXED) & (PLATFORM==PLT_MBC))
#IF (CPUSPDDEF==SPD_HIGH)
RTCDEF .SET RTCDEF | %00001000 ; DEFAULT SPEED HIGH
#ELSE
RTCDEF .SET RTCDEF | %00000000 ; DEFAULT SPEED LOW
#ENDIF
#ENDIF
;
#IF (!(CPUSPDCAP==SPD_FIXED) & (PLATFORM==PLT_SBC))
#IF (CPUSPDDEF==SPD_HIGH)
RTCDEF .SET RTCDEF | %00000000 ; DEFAULT SPEED HIGH
#ELSE
RTCDEF .SET RTCDEF | %00001000 ; DEFAULT SPEED LOW
#ENDIF
#ENDIF
;
;
;
#IFNDEF APPBOOT
@ -1068,6 +1084,11 @@ Z280_BOOTERR .TEXT "\r\n\r\n*** Application mode boot not supported under Z280 n
;
DI ; NO INTERRUPTS
IM 1 ; INTERRUPT MODE 1
#IF ((PLATFORM=PLT_MBC) | (PLATFORM=PLT_SBC))
LD A,(HB_RTCVAL) ; SET DEFAULT
OUT (RTCIO),A ; SPEED
#ENDIF
;
#IF (DIAGENABLE)
LD A,%00000001
@ -2327,14 +2348,6 @@ HB_WDZ:
PRTX(STR_BANNER)
#ENDIF
;
; EXPERIMENTAL!!!
; ENGAGE TURBO...
;
; LD A,(HB_RTCVAL)
; SET 3,A
; OUT (RTCIO),A
; LD (HB_RTCVAL),A
;
INITSYS3:
CALL PRTSUM ; PRINT UNIT/DEVICE SUMMARY TABLE
;

11
Source/HBIOS/std.asm

@ -384,6 +384,17 @@ WDOG_NONE .EQU 0 ; NONE
WDOG_EZZ80 .EQU 1 ; EASY Z80 WATCHDOG
WDOG_SKZ .EQU 2 ; SK Z80 CPU W/ 512K
;
; SYSTEM SPEED CAPABILITIES
;
SPD_FIXED .EQU 0 ; PLATFORM SPEED FIXED AND CANNOT CHANGE SPEEDS
SPD_HILO .EQU 1 ; PLATFORM CAN CHANGE BETWEEN TWO SPEEDS
;
; SYSTEM SPEED CHARACTERISTICS
;
SPD_UNSUP .EQU 0 ; PLATFORM CAN CHANGE SPEEDS BUT IS UNSUPPORTED
SPD_HIGH .EQU 1 ; PLATFORM CAN CHANGE SPEED, STARTS HIGH
SPD_LOW .EQU 2 ; PLATFORM CAN CHANGE SPEED, STARTS LOW
;
#INCLUDE "build.inc" ; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
;
#IF (BIOS == BIOS_WBW)

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