From 490e3e49f8ef5ccc6ba8da11b360b8815ecc4485 Mon Sep 17 00:00:00 2001
From: b1ackmai1er <39449559+b1ackmai1er@users.noreply.github.com>
Date: Sun, 29 Jul 2018 14:48:01 +0800
Subject: [PATCH] Add definable base address for SIO

---
 Source/HBIOS/plt_sbc.inc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Source/HBIOS/plt_sbc.inc b/Source/HBIOS/plt_sbc.inc
index e74806a2..d0795108 100644
--- a/Source/HBIOS/plt_sbc.inc
+++ b/Source/HBIOS/plt_sbc.inc
@@ -19,3 +19,4 @@ MPGENA		.EQU	SBC_BASE + $1C	; PAGING ENABLE REGISTER - BIT 0 = 1  (WRITE ONLY)
 ;
 RTC		.EQU	SBC_BASE + $10	; ADDRESS OF RTC LATCH AND INPUT PORT
 PPIBASE		.EQU	SBC_BASE + $00	; PPI 82C55 I/O IS DECODED TO PORT 60-67
+SIOBASE	.EQU	$B0				; ZILOG PERIPHERALS DEFAULT				;PS