mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
Improve Z180 Variant Handling
- There were several places that RomWBW was making incorrect assumptions about what the older Z180 CPUs could do. These have been corrected.
This commit is contained in:
Wayne Warthen
@@ -1,6 +1,6 @@
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;
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;==================================================================================================
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; N8 STANDARD CONFIGURATION
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; RHYOPHYRE STANDARD CONFIGURATION
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;==================================================================================================
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;
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; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
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@@ -34,6 +34,8 @@ Z180_CLKDIV .SET 1 ; Z180: CHK DIV: 0=OSC/2, 1=OSC, 2=OSC*2
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Z180_MEMWAIT .SET 0 ; Z180: MEMORY WAIT STATES (0-3)
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Z180_IOWAIT .SET 1 ; Z180: I/O WAIT STATES TO ADD ABOVE 1 W/S BUILT-IN (0-3)
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;
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RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!)
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;
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CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP
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;
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PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
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@@ -621,6 +621,24 @@ ASCI_DETECT:
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; DUE TO ENCODING BAUD IS ALWAYS DIVISIBLE BY 75
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; Z180 DIVISOR IS ALWAYS A FACTOR OF 160
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;
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; CNTLB= XXPXDSSS
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; FAILSAVE = 00100000
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;
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; PS (PRESCALE): 0=/10, 1=/30
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; DR (DIVIDE RATIO): 0=/16, 1=/64
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; SS2 SS1 SS0
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; --- --- ---
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; 0 0 0 /1
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; 0 0 1 /2
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; 0 1 0 /4
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; 0 1 1 /8
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; 1 0 0 /16
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; 1 0 1 /32
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; 1 1 0 /64
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;
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; FAILSAFE: CLOCK / 30 / 16 / 1 = CLOCK / 480
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; IF CLOCK=18432000, BAUD=38400
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;
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; X := CPU_HZ / 160 / 75 ==> SIMPLIFIED ==> X := CPU_KHZ / 12
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; X := X / (BAUD / 75)
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; IF X % 3 == 0, THEN (PS := 1, X := X / 3) ELSE PS=0
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@@ -66,16 +66,16 @@
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; RTC LATCH WRITE
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; ---------------
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;
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; BIT SBC SBC-004 MFPIC N8 N8-CSIO MK4 SC130 SC131 SC126 MBC RPH
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; ----- ------- ------- ------- ------- ------- ------- ------- ------- --------------- ------- -------
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; D7 RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT -- -- RTC_OUT,I2C_SDA RTC_OUT RTC_OUT
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; D6 RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK -- -- RTC_CLK RTC_CLK RTC_CLK
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; D5 /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE -- -- /RTC_WE /RTC_WE /RTC_WE
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; D4 RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE -- -- RTC_CE RTC_CE RTC_CE
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; D3 NC CLKSEL /RTC_CE NC NC NC -- -- /SPI_CS2 CLKSEL NC
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; D2 NC SPK RTC_CLK SPI_CS SPI_CS NC /SPI_CS1/SPI_CS1/SPI_CS1 SPK NC
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; D1 -- -- RTC_WE SPI_CLK NC NC -- -- FS LED1 NC
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; D0 -- -- RTC_OUT SPI_DI NC NC -- -- I2C_SCL LED0 NC
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; BIT SBC SBC-004 MFPIC N8 N8-CSIO MK4 SC130 SC131 SC126 MBC RPH
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; ----- ------- ------- ------- ------- ------- ------- ------- ------- --------------- ------- -------
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; D7 RTC_OUT RTC_OUT -- RTC_OUT RTC_OUT RTC_OUT -- -- RTC_OUT,I2C_SDA RTC_OUT RTC_OUT
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; D6 RTC_CLK RTC_CLK -- RTC_CLK RTC_CLK RTC_CLK -- -- RTC_CLK RTC_CLK RTC_CLK
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; D5 /RTC_WE /RTC_WE -- /RTC_WE /RTC_WE /RTC_WE -- -- /RTC_WE /RTC_WE /RTC_WE
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; D4 RTC_CE RTC_CE -- RTC_CE RTC_CE RTC_CE -- -- RTC_CE RTC_CE RTC_CE
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; D3 NC CLKSEL /RTC_CE NC NC NC -- -- /SPI_CS2 CLKSEL --
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; D2 NC SPK RTC_CLK SPI_CS SPI_CS NC /SPI_CS1/SPI_CS1/SPI_CS1 SPK --
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; D1 -- -- RTC_WE SPI_CLK NC NC -- -- FS LED1 --
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; D0 -- -- RTC_OUT SPI_DI NC NC -- -- I2C_SCL LED0 --
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;
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; RTC LATCH READ
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; --------------
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@@ -1946,20 +1946,20 @@ HB_CPUSPD2:
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;
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LD HL,(HB_CPUOSC) ; INIT HL TO CPU OSC FREQ (KHZ)
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;
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#IF (Z180_CLKDIV == 0)
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; ADJUST HL TO REFLECT HALF SPEED OPERATION
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SRL H ; ADJUST HL ASSUMING
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RR L ; HALF SPEED OPERATION
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#ENDIF
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;
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#IF (Z180_CLKDIV == 1)
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#IF (Z180_CLKDIV >= 1)
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LD A,(HB_CPUTYPE) ; GET CPU TYPE
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CP 2 ; Z8S180 REV K OR BETTER?
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JR C,HB_CPU3 ; IF NOT, NOT POSSIBLE!
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; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED
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LD A,$80
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OUT0 (Z180_CCR),A
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; HL ALREADY REFLECTS FULL SPEED OPERATION
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; ADJUST HL TO REFLECT FULL SPEED OPERATION
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SLA L
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RL H
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#ENDIF
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;
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#IF (Z180_CLKDIV >= 2)
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@@ -4102,19 +4102,33 @@ SYS_GETCPUSPD1:
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#ENDIF
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;
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#IF (CPUFAM == CPU_Z180)
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IN0 A,(Z180_CMR) ; GET CLOCK MULTIPLIER
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RLCA ; ROTATE BIT TO BIT 0
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AND %00000001 ; ISOLATE IT
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LD H,A ; SAVE IN H
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LD HL,0 ; INIT CPU SPEED TO HALF
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LD A,(HB_CPUTYPE) ; LOAD CPUTYPE
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CP 2 ; S-CLASS OR ABOVE?
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JR C,SYS_GETCPUSPD1 ; IF NOT, NO CCR/CMR
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;
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; GET CCR BIT
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IN0 A,(Z180_CCR) ; GET CLOCK CONTROL
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RLCA ; ROTATE BIT TO BIT 0
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AND %00000001 ; ISOLATE IT
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LD L,A ; SAVE IN L
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;
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LD A,(HB_CPUTYPE) ; LOAD CPUTYPE
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CP 3 ; REV. N?
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JR C,SYS_GETCPUSPD1 ; IF NOT, NO CMR
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;
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; GET CMR BIT
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IN0 A,(Z180_CMR) ; GET CLOCK MULTIPLIER
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RLCA ; ROTATE BIT TO BIT 0
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AND %00000001 ; ISOLATE IT
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LD H,A ; SAVE IN H
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;
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SYS_GETCPUSPD1:
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; CALC FINAL MULTIPLIER TO L
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XOR A ; CLEAR ACCUM
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ADD A,H ; ADD IN CMR BIT
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ADD A,L ; ADD IN CCR BIT
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LD L,A ; SAVE RESULT IN L
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;
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; DCNTL = MMII????
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IN0 A,(Z180_DCNTL) ; GET WAIT STATES
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RLCA ; ROTATE MEM WS BITS
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@@ -4378,6 +4392,29 @@ SYS_SETCPUSPD3:
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#ENDIF
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;
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#IF (CPUFAM == CPU_Z180)
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; VERIFY THAT REQUESTED SETTINGS ARE ALLOWED BY HARDWARE
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LD A,L ; GET SPEED REQUESTED
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CP $FF ; NO CHANGE?
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JR Z,SYS_SETCPUSPD0A ; SKIP CHECK
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LD A,(HB_CPUTYPE) ; 1=ORIG, 2=REVK, 3=REVN
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INC L ; 1=HALF,2=FULL,3=DOUBLE
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CP L ; TOO HIGH FOR CPU TYPE?
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JP C,SYS_SETCPUSPD_ERR ; CPU CAN'T DO SPD MULT
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DEC L ; RESTORE ORIG REQUEST
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SYS_SETCPUSPD0A:
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LD A,D ; MEM WS
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CP $FF ; NO CHANGE?
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JR Z,SYS_SETCPUSPD0B ; SKIP CHECK
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CP 4 ; TOO HIGH?
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JP NC,SYS_SETCPUSPD_ERR ; >3 IS TOO HIGH
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SYS_SETCPUSPD0B:
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LD A,D ; I/O WS
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CP $FF ; NO CHANGE?
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JR Z,SYS_SETCPUSPD0C ; SKIP CHECK
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CP 4 ; TOO HIGH?
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JP NC,SYS_SETCPUSPD_ERR ; >3 IS TOO HIGH
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SYS_SETCPUSPD0C:
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;
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PUSH DE ; SAVE WAIT STATES FOR NOW
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; BEFORE IMPLEMENTING THE NEW CPU SPEED, WE SWITCH THE
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; WAIT STATES TO MAXIMUM BECAUSE WE MAY BE IMPLEMENTING
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@@ -4404,11 +4441,11 @@ SYS_SETCPUSPD1:
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LD C,%10000000 ; SET CCR BIT
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SYS_SETCPUSPD2:
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;
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; IMPLEMENT THE NEW CPU SPEED
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IN0 A,(Z180_CMR)
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AND ~%10000000
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OR B
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OUT0 (Z180_CMR),A
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;
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IN0 A,(Z180_CCR)
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AND ~%10000000
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OR C
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@@ -2,4 +2,4 @@
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#DEFINE RMN 1
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#DEFINE RUP 1
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#DEFINE RTP 0
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#DEFINE BIOSVER "3.1.1-pre.167"
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#DEFINE BIOSVER "3.1.1-pre.168"
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@@ -3,5 +3,5 @@ rmn equ 1
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rup equ 1
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rtp equ 0
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biosver macro
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db "3.1.1-pre.167"
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db "3.1.1-pre.168"
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endm
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