From 4b80f36fd06c7c9806b732ce6c402af231355138 Mon Sep 17 00:00:00 2001
From: Dean Netherton <dinoboards@netherton.org>
Date: Sat, 20 Jul 2024 13:22:12 +1000
Subject: [PATCH] ez80: configure and display memory and i/o timings

---
 Source/HBIOS/Config/RCEZ80_std.asm |  3 +++
 Source/HBIOS/cfg_rcez80.asm        | 10 ++++++++
 Source/HBIOS/ez80instr.inc         |  2 ++
 Source/HBIOS/hbios.asm             | 39 ++++++++++++++++++++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/Source/HBIOS/Config/RCEZ80_std.asm b/Source/HBIOS/Config/RCEZ80_std.asm
index b72ac5ec..3b492d2f 100644
--- a/Source/HBIOS/Config/RCEZ80_std.asm
+++ b/Source/HBIOS/Config/RCEZ80_std.asm
@@ -66,3 +66,6 @@ SDCNT		.SET	1		; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT SC ONLY
 IMMENABLE	.SET	FALSE		; IMM: ENABLE IMM DISK DRIVER (IMM.ASM)
 ;
 PRPENABLE	.SET	FALSE		; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM)
+
+EZ80_IO_FREQ	.SET	8000
+EZ80_MEM_FREQ	.SET	8000
diff --git a/Source/HBIOS/cfg_rcez80.asm b/Source/HBIOS/cfg_rcez80.asm
index 5beab79f..cb030938 100644
--- a/Source/HBIOS/cfg_rcez80.asm
+++ b/Source/HBIOS/cfg_rcez80.asm
@@ -44,6 +44,16 @@ MPGSEL_2	.EQU	$7A		; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY)
 MPGSEL_3	.EQU	$7B		; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY)
 MPGENA		.EQU	$7C		; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY)
 ;
+; BUS TIMING FOR PAGED MEMORY ACCESS (CS3)
+EZ80_MEM_CYCLES	.EQU	3		; EZ80 CYCLES FOR MEMORY (1-15)
+EZ80_MEM_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_MEM_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
+;
+; BUS TIMING FOR EXTERNAL I/O ACCESS (CS2)
+EZ80_IO_CYCLES	.EQU	3		; EZ80 CYCLES FOR IO (1-15)
+EZ80_IO_FREQ	.EQU	8000		; CALCULATE APPROPRIATE BUS CYCLES TO ACHIVE APPOX BUS FREQUENCY
+EZ80_IO_ASSIGN	.EQU	0		; 0 -> USE FREQ, 1 -> USE CYCLES
+;
 RTCIO		.EQU	$C0		; RTC LATCH REGISTER ADR
 ;
 KIOENABLE	.EQU	FALSE		; ENABLE ZILOG KIO SUPPORT
diff --git a/Source/HBIOS/ez80instr.inc b/Source/HBIOS/ez80instr.inc
index f8af7d1a..1aa5492c 100644
--- a/Source/HBIOS/ez80instr.inc
+++ b/Source/HBIOS/ez80instr.inc
@@ -14,6 +14,8 @@
   #DEFINE EZ80_UTIL_INIT	XOR A \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_UTIL_EHL_TO_HL	XOR A \ LD B, 1 \ EZ80_FN
   #DEFINE EZ80_UTIL_HL_TO_EHL	XOR A \ LD B, 2 \ EZ80_FN
+  #DEFINE EZ80_UTIL_SET_BUSTM 	XOR A \ LD B, 3 \ EZ80_FN
+  #DEFINE EZ80_UTIL_SET_BUSFQ 	XOR A \ LD B, 4 \ EZ80_FN
 
   #DEFINE EZ80_RTC_INIT 	LD A, 1 \ LD B, 0 \ EZ80_FN
   #DEFINE EZ80_RTC_GET_TIME 	LD A, 1	\ LD B, 1 \ EZ80_FN
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index 5cceb051..27c22d74 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -2148,6 +2148,15 @@ HB_CLRIVT_Z:
 	LD	(CB_CPUKHZ), HL
 	LD	(HB_CPUOSC), HL
 
+	LD	HL, EZ80_MEM_FREQ
+	LD	DE, EZ80_IO_FREQ
+	EZ80_UTIL_SET_BUSFQ()		; H -> CS3 CYCLES, L -> CS2 CYCLES
+
+	LD	A, H
+	LD	(EZ80_PLT_C3CYL), A
+	LD	A, L
+	LD	(EZ80_PLT_C2CYL), A
+
 	JR	PLT_DESCR_END
 
 PLT_DESCR:
@@ -2171,6 +2180,12 @@ EZ80_PLT_RESVRD:
 	.DB	ROMSIZE >> 8
 	.DB	0 		; RESERVED
 	.DB	0 		; RESERVED
+
+EZ80_PLT_C3CYL:
+	.DB	EZ80_MEM_CYCLES
+EZ80_PLT_C2CYL:
+	.DB	EZ80_IO_CYCLES
+
 PLT_DESCR_END:
 
 	LD	HL,5
@@ -2962,7 +2977,16 @@ HB_Z280BUS1:
 ;--------------------------------------------------------------------------------------------------
 ;
 	CALL	NEWLINE
+;
+; DISPLAY MEMORY TIMINGS
+;
+#IF (CPUFAM == CPU_EZ80)
+	LD	A,(EZ80_PLT_C3CYL)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" MEM B/C, $"
 
+#ELSE
 #IF (CPUFAM == CPU_Z280)
 	LD	A,Z280_MEMLOWAIT
 	CALL	PRTDECB
@@ -2981,6 +3005,17 @@ HB_Z280BUS1:
 	CALL	PRTSTRD
 	.TEXT	" MEM W/S, $"
 #ENDIF
+#ENDIF ; CPUFAM = CPU_EZ80
+;
+; DISPLAY I/O TIMINGS
+;
+#IF (CPUFAM == CPU_EZ80)
+	LD	A,(EZ80_PLT_C2CYL)
+	CALL	PRTDECB
+	CALL	PRTSTRD
+	.TEXT	" I/O B/C$"
+
+#ELSE
 	LD	A,1
 #IF (CPUFAM == CPU_Z180)
 	LD	A,Z180_IOWAIT + 1
@@ -2999,6 +3034,10 @@ HB_Z280BUS1:
 	CALL	PRTSTRD
 	.TEXT	" INT W/S$"
 #ENDIF
+#ENDIF //CPUFAM = CPU_EZ80
+;
+; DISPLAY INTERRUPT MODE
+;
 #IF (INTMODE > 0)
 	CALL	PRTSTRD
 	.TEXT	", INT MODE $"