From 4ce0e1f657bc5fc46e84d5951089de9cd049707a Mon Sep 17 00:00:00 2001
From: Wayne Warthen <wwarthen@gmail.com>
Date: Mon, 20 Apr 2020 13:08:49 -0700
Subject: [PATCH] Handle CTC anomaly

Small update to accommodate CTC behavior that occurs when the CTC trigger is more than half the CTC clock.
---
 Source/HBIOS/sio.asm | 52 +++++++++++++++++++++++++++++++++++++++++++-
 Source/ver.inc       |  2 +-
 Source/ver.lib       |  2 +-
 3 files changed, 53 insertions(+), 3 deletions(-)

diff --git a/Source/HBIOS/sio.asm b/Source/HBIOS/sio.asm
index eceea12d..631cb605 100644
--- a/Source/HBIOS/sio.asm
+++ b/Source/HBIOS/sio.asm
@@ -589,6 +589,55 @@ SIO_INITDEV1D:
 	PRTS(" DIV=$")
 	CALL	PRTHEXWORD
 #ENDIF
+;
+#IF (CTCENABLE)
+;
+	LD	A,(IY+13)		; GET CTC CHANNEL
+	INC	A			; $FF -> 0
+	JR	Z,SIO_ADJDONE		; NO CTC CHANNEL, BYPASS
+;
+	; HERE WE NEED TO ACCOUNT FOR A SPECIAL CASE OF THE CTC.
+	; IF THE CTC TRIGGER RATE IS MORE THAN HALF OF THE CTC CLOCK,
+	; THEN THE CTC WILL ONLY COUNT EVERY OTHER TRIGGER PULSE.
+	; IN THIS SITUATION, WE NEED TO CUT THE DIVISOR IN HALF
+	; TO ACCOUNT FOR THIS.
+	; FOR NOW, I JUST TEST TO SEE IF THE CTC TRIGGER AND THE CTC
+	; CLOCK ARE THE SAME.  I DOUBT THERE IS ANY REALISTIC
+	; SCENARIO WHERE THE TRIGGER IS GREATER THAN HALF THE
+	; CLOCK BUT ALSO NOT EQUAL TO THE CLOCK.
+	; I DON'T DEFINITELY KNOW THE CTC CLOCK FREQ, BUT ASSUME IT
+	; IS THE SAME AS THE CPU CLOCK, WHICH IT SHOULD BE.
+	; FINALLY, NOTE THAT I AM COMPARING AGAINST THE CPU SPEED
+	; DECLARED IN THE BUILD CONFIG, NOT THE DYNAMICALLY MEASURED
+	; CPU SPEED.  THIS IS CORRECT BECAUSE WE ARE REALLY TRYING TO
+	; TEST IF THE CPU CLOCK AND THE TRIGGER FREQ ARE THE *SAME*.
+	; ONLY COMPARING THE HIGH WORD VALUES, THAT SHOULD BE ENOUGH.
+;
+	LD	A,$FF & (CPUOSC >> 24)	; HIGH BYTE OF CPU FREQ
+	CP	(IY+12)			; CP TO HIGH BYTE OF TRG
+	JR	NZ,SIO_ADJDONE		; IF NE, SKIP ADJUSTMENT
+	LD	A,$FF & (CPUOSC >> 16)	; HIGH BYTE OF CPU FREQ
+	CP	(IY+11)			; CP TO HIGH BYTE OF TRG
+	JR	NZ,SIO_ADJDONE		; IF NE, SKIP ADJUSTMENT
+;
+	SRL	B			; RIGHT SHIFT HL
+	RR	C			; ... TO DIVIDE BY 2
+	JR	NC,SIO_ADJDONE		; DONE IF NO CARRY
+;
+	; IF CARRY, RESULTANT CIVISOR IS UNWORKABLE
+	POP	DE			; POP STACK
+	JR	SIO_INITFAIL		; AND FAIL
+	
+	; *** CHECK FOR CARRY??? ***
+;
+  #IF (SIODEBUG)
+	PRTS(" DIV=$")
+	CALL	PRTHEXWORD
+  #ENDIF
+;
+SIO_ADJDONE:
+;
+#ENDIF
 ;
 	; NOW THAT WE HAVE THE TARGET BAUD RATE DIVISOR, WE WILL
 	; ATTEMPT TO IMPLEMENT IT.  THE SIO ITSELF CAN APPLY
@@ -628,7 +677,7 @@ SIO_INITDEV2:
 	OR	B			; ZERO BITS TO SHIFT?
 	JR	Z,SIO_INITDEV4		; BYPASS SHIFTING IF SO
 SIO_INITDEV3:
-	RR	H			; SHIFT HL RIGHT BY
+	SRL	H			; SHIFT HL RIGHT BY
 	RR	L			; ONE BIT
 	DJNZ	SIO_INITDEV3		; UNTIL ALL BITS DONE
 SIO_INITDEV4:
@@ -646,6 +695,7 @@ SIO_INITDEV4:
 #ENDIF
 ;
 #IF (CTCENABLE)
+;
 	LD	A,(IY+13)		; GET CTC CHANNEL
 	INC	A			; $FF -> 0
 	JR	Z,SIO_NOCTC		; NO CTC CHANNEL, BYPASS
diff --git a/Source/ver.inc b/Source/ver.inc
index 6dd55708..000b172a 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	0
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1-pre.5"
+#DEFINE BIOSVER	"3.1-pre.6"
diff --git a/Source/ver.lib b/Source/ver.lib
index 9d060b23..ec372ea7 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	0
 rtp	equ	0
 biosver	macro
-	db	"3.1-pre.5"
+	db	"3.1-pre.6"
 	endm