mirror of
https://github.com/wwarthen/RomWBW.git
synced 2026-02-06 14:11:48 -06:00
HBIOS driver and BPBIOS refinements
- Refined sd, ide, and ppide drivers to improve hardware compatibility - Improved BPBIOS build process
This commit is contained in:
Wayne Warthen
@@ -1,123 +1,229 @@
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=============================================================================
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ORIGINAL DISTRIBUTION ENVIRONMENT
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-----------------------------------------------------------------------------
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A - Environment - FE00H F - Named Dirs - FC00H
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Size (# recs)- 2 # of Entries - 14
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B - Flow Ctrl Pkg - FA00H G - External Path - FDF4H
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Size (# recs)- 4 # of Entries - 5
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C - I/O Package - EC00H H - Shell Stack - FD00H
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Size (# recs)- 12 # of Entries - 4
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D - Res Cmd Proc - F200H Entry Size - 32
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Size (# recs)- 16 I - Msg Buffer - FD80H
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E - Command Line - FF00H J - Ext. FCB - FDD0H
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Size (bytes) - 203 K - Ext. Stack - FFD0H
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=============================================================================
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BPBIOS for RomWBW / HBIOS
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-------------------------
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=============================================================================
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STANDARD ENVIRONMENT (HBIOS IMBEDDED IN BPBIOS)
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-----------------------------------------------------------------------------
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A - Environment - FE00H F - Named Dirs - FC00H
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Size (# recs)- 2 # of Entries - 14
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B - Flow Ctrl Pkg - FA00H G - External Path - FDF4H
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Size (# recs)- 4 # of Entries - 5
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C - I/O Package - EC00H H - Shell Stack - FD00H
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Size (# recs)- 12 # of Entries - 4
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D - Res Cmd Proc - F200H Entry Size - 32
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Size (# recs)- 16 I - Msg Buffer - FD80H
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E - Command Line - FF00H J - Ext. FCB - FDD0H
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Size (bytes) - 203 K - Ext. Stack - FFD0H
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=============================================================================
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The build process included in this directory constructs multiple BPBIOS OS images that
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can be loaded dynamically on a running RomWBW CP/M-like system. Normally, you would
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boot CP/M and then load the desired variant. On a running system, you would enter
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something like "LDSYS BP34T". This document describes the specifics of the build
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process and the image variations which are identified by naming convention.
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=============================================================================
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X ENVIRONMENT (HBIOS @ FC00): ALL SEGMENTS SHIFTED DOWN BY $400
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-----------------------------------------------------------------------------
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A - Environment - FA00H F - Named Dirs - F800H
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Size (# recs)- 2 # of Entries - 14
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B - Flow Ctrl Pkg - F600H G - External Path - F9F4H
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Size (# recs)- 4 # of Entries - 5
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C - I/O Package - E800H H - Shell Stack - F900H
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Size (# recs)- 12 # of Entries - 4
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D - Res Cmd Proc - EE00H Entry Size - 32
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Size (# recs)- 16 I - Msg Buffer - F980H
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E - Command Line - FB00H J - Ext. FCB - F9D0H
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Size (bytes) - 171 K - Ext. Stack - FBB0H
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=============================================================================
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Each image is composed of three basic components: Command Processor (CCP), Disk
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Operating System (DOS), and Basic I/O System (BIOS). The CCP and DOS components
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are pre-built, relocatable binaries. The BIOS (BPBIOS) is assembled into a relocatable
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binary by the build, then the build links together all three components to form the
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final loadable image (.IMG) file. The linking process is performed by the custom BPBIOS
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linker (BPBUILD.COM). In addition to linking the 3 components, BPBUILD also sets
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adjusts the ZCPR environment configuration.
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=============================================================================
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T ENVIRONMENT (HBIOS @ FC00): ALL SEGMENTS REARRANGED
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-----------------------------------------------------------------------------
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A - Environment - EA00H F - Named Dirs - E800H
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Size (# recs)- 2 # of Entries - 14
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B - Flow Ctrl Pkg - FA00H G - External Path - E9F4H
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Size (# recs)- 4 # of Entries - 5
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C - I/O Package - EC00H H - Shell Stack - E900H
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Size (# recs)- 12 # of Entries - 4
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D - Res Cmd Proc - F200H Entry Size - 32
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Size (# recs)- 16 I - Msg Buffer - E980H
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E - Command Line - EB00H J - Ext. FCB - E9D0H
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Size (bytes) - 171 K - Ext. Stack - EBB0H
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=============================================================================
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BPBUILD is designed to be run interactively. However, it can be started with an
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existing OS image to edit an existing image file. In order to achieve an automated
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build process with no interaction, this directory contains several template image (.DAT)
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files that have environment configurations defined below. The build process passes the desired
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tempate file to BPBUILD on the command line and uses input redirection to automate the
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running of BPBUILD.
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=============================================================================
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N ENVIRONMENT (HBIOS IMBEDDED IN BPBIOS): SMALL HBIOS STUB AT FFE0-FFFF
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-----------------------------------------------------------------------------
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A - Environment - FE00H F - Named Dirs - FC00H
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Size (# recs)- 2 # of Entries - 14
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B - Flow Ctrl Pkg - FA00H G - External Path - FDF4H
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Size (# recs)- 4 # of Entries - 5
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C - I/O Package - EC00H H - Shell Stack - FD00H
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Size (# recs)- 12 # of Entries - 4
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D - Res Cmd Proc - F200H Entry Size - 32
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Size (# recs)- 16 I - Msg Buffer - FD80H
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E - Command Line - FF00H J - Ext. FCB - FDD0H
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Size (bytes) - 171 K - Ext. Stack - FFB0H
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=============================================================================
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The CCP can be ZCPR 3.3 (ZCPR33?.REL), ZCPR 3.4 (Z34.REL), or ZCPR 4.1 (Z41.ZRL). ZCPR 3.3
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uses static references to the ZCPR segments, so a custom version of it must be assembled.
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The ZCPR33 subdirectory provides a build process for doing this. It produces a specific
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version for each of the memory segment configurations (ZCPR33T.REL & ZCPR33N.REL).
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The DOS can be ZSDOS 1.1 (ZSDOS.ZRL) or ZSDOS 2.03 (ZS203.ZRL). These are both pre-built
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relocatable binaries. Note that only certain version combinations of ZSDOS and ZCPR are
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possible as indicated below. Additionally, ZSDOS 2.X requires a banked BIOS.
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ZCPR 3.X == ZSDOS 1.X
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ZCPR 4.X == ZSDOS 2.X
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COMPONENT BP33 BP33BNK BP34 BP34BNK BP41
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BPBIOS must be assembled for the target configuration. BPBIOS includes a DEF-WW-???????.LIB
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file during assembly which sets various equates to contol the features and behavior of
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BPBIOS. The most critical ones are:
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BANKED: If YES, BPBIOS implements memory banking features
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ZSDOS2: If YES, BPBIOS is built to utilize ZSDOS 2.X specifics features
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INTPXY: If YES, BPBIOS implements HBIOS proxy code internally w/ stub at FFE0H-FFFFH
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The table below illustrates the target build configurations along with the
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.DAT and .LIB files which are utilized for the specific configuration. The "?"
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is replaced with a letter that represents one of the ZCPR memory segment configurations
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described later in this document.
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BP33?.DAT DEF-WW-Z33?.LIB Non-Banked BPBIOS w/ ZCPR 3.3 & ZSDOS 1.1
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BP33?BNK.DAT DEF-WW-Z33?BNK.LIB Banked BPBIOS w/ ZCPR 3.3 & ZSDOS 1.1
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BP34?.DAT DEF-WW-Z34?.LIB Non-Banked BPBIOS w/ ZCPR 3.4 & ZSDOS 1.1
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BP34?BNK.DAT DEF-WW-Z34?BNK.LIB Banked BPBIOS w/ ZCPR 3.4 & ZSDOS 1.1
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BP41?BNK.DAT DEF-WW-Z41?BNK.LIB Banked BPBIOS w/ ZCPR 4.1 & ZSDOS 2.03
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The table below illustrates the BPBIOS equates used and the specific CCP/DOS/BIOS
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components that are used to generate each configuration. As above, the "?" is
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replaced with a letter that represents one of the ZCPR memory segment configurations
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described later in this document.
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BP33? BP33?BNK BP34? BP34?BNK BP41?BNK
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-------------- -------------- -------------- -------------- -------------- --------------
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CCP ZCPR33.REL ZCPR33.REL Z34.REL Z34.REL Z41.ZRL
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BANKED NO YES NO YES YES
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ZSDOS2 NO NO NO NO YES
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-------------- -------------- -------------- -------------- -------------- --------------
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CCP ZCPR33?.REL ZCPR33?.REL Z34.REL Z34.REL Z41.ZRL
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DOS ZSDOS.ZRL ZSDOS.ZRL ZSDOS.ZRL ZSDOS.ZRL ZS203.ZRL
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BIOS BP33.REL BP33BNK.REL BP34.REL BP34BNK.REL BP41.REL
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NOTE: Implementing the environment changes in ZCPR33 requires building a new ZCPR33 from source!!!
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SEGMENT Original Std Type X Type T Type N
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-------------- -------------- -------------- -------------- -------------- --------------
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Environment FE00 FE00 FA00 EA00 FE00
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# Recs 2 2 2 2 2
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Flow Ctl Pkg FA00 FA00 F600 FA00 FA00
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# Recs 4 4 4 4 4
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I/O Pkg EC00 EC00 E800 EC00 EC00
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# Recs 12 12 12 12 12
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Res Cmd Pkg F200 F200 EE00 F200 F200
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# Recs 16 16 16 16 16
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Cmd Line FF00 FF00 FB00 EB00 FF00
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# Bytes 203 203 171 171 171
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Named Dirs FC00 FC00 F800 E800 FC00
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# Ents 14 14 14 14 14
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Ext Path FDF4 FDF4 F9F4 E9F4 FDF4
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# Ents 5 5 5 5 5
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Shell Stack FD00 FD00 F900 E900 FD00
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# Ents 4 4 4 4 4
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Ent Size 32 32 32 32 32
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Msg Buffer FD80 FD80 F980 E980 FD80
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Ext FCB FDD0 FDD0 F9D0 E9D0 FDD0
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Ext Stack FFD0 FFD0 FBB0 EBB0 FFB0
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In addition to the configuration options above, ZCPR also utilizes a
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defined set of memory segments in upper memory. The location and size of these
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segments have many ramifications and general ZCPR / BPBIOS documents
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should be consulted to understand these. The build process used here
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produces several different configurations which can be loaded at runtime.
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The original distributed memory segment configuration occupies the top
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of memory which, unfortunately, conflicts with the RomWBW HBIOS need to
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occupt this space.
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Although RomWBW HBIOS is implemented in it's own dedicated memory bank, it
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requires a small proxy at the top of memory which acts as a mechansim to
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route calls to HBIOS. There are two ways to implement this upper memory
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proxy. The full proxy occupies FE00H-FFFFH and implements all of the
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HBIOS routing code. Alternatively, a mini proxy can be utilized to
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minimize the dedicated proxy space in upper memory. The mini proxy
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requires just 20H bytes at the top of memory (FFE0H-FFFFH), but requires
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that the bulk of the proxy code be implemented internally in BPBIOS.
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Type X: All segments shifted down by size of HBIOS Proxy (1024 bytes)
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Type T: Segments rearranged to allow space for HBIOS Proxy
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FC00-FFFF --> EA00-EBFF
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Environment, Cmd Line, Named Dirs, Ext Path, Shell Stack, Msg Buffer, Ext FCB, Ext Stack
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Type N: Frees up HBIOS interface area at FFE0-FFFF by shrinking Cmd Line and shifting
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Ext Stack down by 32 bytes
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Taking the above into account, the build process implements a couple of
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memory segment configurations that are compatible with RomWBW HBIOS.
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Essentially, these configurations rearrange the ZCPR memory segments
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to free up the area required by the HBIOS full or mini proxy. Note
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that this is a bit complicated because there are some constraints on
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the locations of certain segments.
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First, the RCP, FCP, and IOP segments contain executable code which is
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pre-built and intended to run at specific locations. Specifically, the
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SYS.RCP, SYS.FCP, and SYS.IOP files provided with the BPBIOS distribution
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must be loaded at their original intended location. In theory, new
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versions of these files could be created to load at different locations,
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but that is not the approach taken here. Instead, the memory segment
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configurations are designed to keep these 3 components at the same
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location as the original distribution.
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If built with INTPXY=NO, then LDSYS BP34T, BP34TBNK, or BP41T
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If built with INTPXY=YES, then LDSYS BP33N, BP33NBNK, BP34N, BP34NBNK, or BP41N
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BPBIOS is assembled as relocatable code. Subsequently, the BPBUILD tool
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is used to link BPBIOS with the CCP and DOS relocatable code to produce
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the absolute image (.IMG file). Note that BPBUILD does more than just
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linking. As part of it's work, BPBUILD adjusts the built-in environment
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segment to customize the final image for the desired location and size
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of Z-System segments.
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The following table summarizes the original memory segment configuration and the
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two new configurations utilized by this build process. As indicated above, the
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original configuration is incompatible with RomWBW HBIOS because it occupies the
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very top of memory. This configuration is shown below purely to document the
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original distribued configuration.
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SEGMENT Original T Config N Config
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-------------- -------------- -------------- --------------
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Environment FE00 EA00* FE00
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# Recs 2 2 2
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Flow Ctl Pkg FA00 FA00 FA00
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# Recs 4 4 4
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I/O Pkg EC00 EC00 EC00
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# Recs 12 12 12
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Res Cmd Pkg F200 F200 F200
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# Recs 16 16 16
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Cmd Line FF00 EB00* FF00
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# Bytes 203 203 171*
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Named Dirs FC00 FC00 FC00
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# Ents 14 14 14
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Ext Path FDF4 FDF4 FDF4
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# Ents 5 5 5
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Shell Stack FD00 FD00 FD00
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# Ents 4 4 4
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Ent Size 32 32 32
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Msg Buffer FD80 FD80 FD80
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Ext FCB FDD0 FDD0 FDD0
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Ext Stack FFD0 EBD0* FFB0*
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User Space E900 E700* E900
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Size 300 300 300
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Wheel Byte FDFF FDFF FDFF
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The sections below provide a more detailed description of the memory
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segment configurations.
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=============================================================================
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ORIGINAL DISTRIBUTION CONFIGURATION (NO HBIOS):
|
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This is the original distribution configuration of BPBIOS which
|
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occupies all upper RAM (to FFFFH). So, there is no room for the
|
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HBIOS proxy and, therefore, is not compatibile with RomWBW. This
|
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configuration is documented only for reference. It is not built
|
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by the build process and is not compatible with RomWBW HBIOS.
|
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-----------------------------------------------------------------------------
|
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A - Environment - FE00H F - Named Dirs - FC00H
|
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Size (# recs)- 2 # of Entries - 14
|
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B - Flow Ctrl Pkg - FA00H G - External Path - FDF4H
|
||||
Size (# recs)- 4 # of Entries - 5
|
||||
C - I/O Package - EC00H H - Shell Stack - FD00H
|
||||
Size (# recs)- 12 # of Entries - 4
|
||||
D - Res Cmd Proc - F200H Entry Size - 32
|
||||
Size (# recs)- 16 I - Msg Buffer - FD80H
|
||||
E - Command Line - FF00H J - Ext. FCB - FDD0H
|
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Size (bytes) - 203 K - Ext. Stack - FFD0H
|
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=============================================================================
|
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|
||||
=============================================================================
|
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T CONFIGURATION (HBIOS FULL PROXY @ FC00-FFFF):
|
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This configuration uses a modified layout of the ZSystem segments so
|
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that critical segments can be located at the same address as the
|
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"stock" configuration. Some segments are built with an assumed
|
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memory location and will generally fail if they are not loaded in
|
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that location. The Flow Control Package (FCP) and Resident
|
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Command Processor (RCP) are very sensitive to this. This configuration
|
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places them at their original locations, so they work well.
|
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-----------------------------------------------------------------------------
|
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A - Environment - EA00H F - Named Dirs - FC00H
|
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Size (# recs)- 2 # of Entries - 14
|
||||
B - Flow Ctrl Pkg - FA00H G - External Path - FDF4H
|
||||
Size (# recs)- 4 # of Entries - 5
|
||||
C - I/O Package - EC00H H - Shell Stack - FD00H
|
||||
Size (# recs)- 12 # of Entries - 4
|
||||
D - Res Cmd Proc - F200H Entry Size - 32
|
||||
Size (# recs)- 16 I - Msg Buffer - FD80H
|
||||
E - Command Line - EB00H J - Ext. FCB - FDD0H
|
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Size (bytes) - 203 K - Ext. Stack - EBD0H
|
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=============================================================================
|
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|
||||
=============================================================================
|
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N CONFIGURATION (HBIOS MINI PROXY @ FFE0-FFFF):
|
||||
This configuration frees up the top 20H bytes of memory to make space for the
|
||||
HBIOS mini-proxy. It does this by shrinking Cmd Line and shifting the Ext Stack
|
||||
down by 32 bytes. This configuration will only work if INTPXY=YES in HBIOS.
|
||||
-----------------------------------------------------------------------------
|
||||
A - Environment - FE00H F - Named Dirs - FC00H
|
||||
Size (# recs)- 2 # of Entries - 14
|
||||
B - Flow Ctrl Pkg - FA00H G - External Path - FDF4H
|
||||
Size (# recs)- 4 # of Entries - 5
|
||||
C - I/O Package - EC00H H - Shell Stack - FD00H
|
||||
Size (# recs)- 12 # of Entries - 4
|
||||
D - Res Cmd Proc - F200H Entry Size - 32
|
||||
Size (# recs)- 16 I - Msg Buffer - FD80H
|
||||
E - Command Line - FF00H J - Ext. FCB - FDD0H
|
||||
Size (bytes) - 171 K - Ext. Stack - FFB0H
|
||||
=============================================================================
|
||||
|
||||
BPBIOS is designed to invoke a command at startup (autostart command). There
|
||||
are 3 ZEX command files customized for this build. They are Z33.ZEX, Z34.ZEX,
|
||||
and Z41.ZEX. BPBIOS is customized to launch the ZEX command file corresponding
|
||||
to the version of ZCPR being linked with it.
|
||||
|
||||
The table below summarizes the loadable image files created by the build
|
||||
process:
|
||||
|
||||
ZCPR ZSDOS BPBIOS STARTUP T (INTPXY=NO) N (INTPXY=YES)
|
||||
------ ------ -------------- -------------- -------------- --------------
|
||||
v3.3 v1.1 NON-BANKED Z33.ZEX BP33T.IMG BP33N.IMG
|
||||
v3.3 v1.1 BANKED Z33.ZEX BP33TBNK.IMG BP33NBNK.IMG
|
||||
v3.4 v1.1 NON-BANKED Z34.ZEX BP34T.IMG BP34N.IMG
|
||||
v3.4 v1.1 BANKED Z34.ZEX BP34TBNK.IMG BP34NBNK.IMG
|
||||
v4.1 v2.03 BANKED Z41.ZEX BP41TBNK.IMG BP41NBNK.IMG
|
||||
|
||||
WARNING: Once an N configuration image has been loaded, it is no longer
|
||||
possible to load a T configuration without rebooting. This constraint
|
||||
exists because the N configurations wipe out all but the top 20H bytes
|
||||
of memory. The T configurations rely on the full 200H byte HBIOS
|
||||
proxy.
|
||||
|
||||
@@ -8,253 +8,22 @@ set ZXBINDIR=../../tools/cpm/bin/
|
||||
set ZXLIBDIR=../../tools/cpm/lib/
|
||||
set ZXINCDIR=../../tools/cpm/include/
|
||||
|
||||
rem
|
||||
rem Z33 + ZSDOS11 w/ Non-banked BPBIOS
|
||||
rem
|
||||
|
||||
copy def-ww-z33.lib def-ww.lib
|
||||
zx ZMAC -BPBIO-WW -/P
|
||||
if exist bp33.prn del bp33.prn
|
||||
ren bpbio-ww.prn bp33.prn
|
||||
pushd ZCPR33 && call Build.cmd && popd
|
||||
|
||||
pause
|
||||
|
||||
if exist bp33.rel del bp33.rel
|
||||
ren bpbio-ww.rel bp33.rel
|
||||
call :makebp 33t
|
||||
call :makebp 33tbnk
|
||||
call :makebp 33n
|
||||
call :makebp 33nbnk
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33.img del bp33.img
|
||||
if exist bpsys.img ren bpsys.img bp33.img
|
||||
call :makebp 34t
|
||||
call :makebp 34tbnk
|
||||
call :makebp 34n
|
||||
call :makebp 34nbnk
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33x.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33x.img del bp33x.img
|
||||
if exist bpsys.img ren bpsys.img bp33x.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33t.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33t.img del bp33t.img
|
||||
if exist bpsys.img ren bpsys.img bp33t.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33n.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33n.img del bp33n.img
|
||||
if exist bpsys.img ren bpsys.img bp33n.img
|
||||
|
||||
rem goto :startup
|
||||
|
||||
rem
|
||||
rem Z33 + ZSDOS11 w/ Banked BPBIOS
|
||||
rem
|
||||
|
||||
copy def-ww-z33bnk.lib def-ww.lib
|
||||
zx ZMAC -BPBIO-WW -/P
|
||||
if exist bp33bnk.prn del bp33bnk.prn
|
||||
ren bpbio-ww.prn bp33bnk.prn
|
||||
|
||||
if exist bp33bnk.rel del bp33bnk.rel
|
||||
ren bpbio-ww.rel bp33bnk.rel
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33bnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33bnk.img del bp33bnk.img
|
||||
if exist bpsys.img ren bpsys.img bp33bnk.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33xbnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33xbnk.img del bp33xbnk.img
|
||||
if exist bpsys.img ren bpsys.img bp33xbnk.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33tbnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33tbnk.img del bp33tbnk.img
|
||||
if exist bpsys.img ren bpsys.img bp33tbnk.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp33nbnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp33nbnk.img del bp33nbnk.img
|
||||
if exist bpsys.img ren bpsys.img bp33nbnk.img
|
||||
|
||||
rem
|
||||
rem Z34 + ZSDOS11 w/ Non-banked BPBIOS
|
||||
rem
|
||||
|
||||
copy def-ww-z34.lib def-ww.lib
|
||||
zx ZMAC -BPBIO-WW -/P
|
||||
if exist bp34.prn del bp34.prn
|
||||
ren bpbio-ww.prn bp34.prn
|
||||
|
||||
if exist bp34.rel del bp34.rel
|
||||
ren bpbio-ww.rel bp34.rel
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34.img del bp34.img
|
||||
if exist bpsys.img ren bpsys.img bp34.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34x.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34x.img del bp34x.img
|
||||
if exist bpsys.img ren bpsys.img bp34x.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34t.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34t.img del bp34t.img
|
||||
if exist bpsys.img ren bpsys.img bp34t.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34n.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34n.img del bp34n.img
|
||||
if exist bpsys.img ren bpsys.img bp34n.img
|
||||
|
||||
rem goto :startup
|
||||
|
||||
rem
|
||||
rem Z34 + ZSDOS11 w/ Banked BPBIOS
|
||||
rem
|
||||
|
||||
copy def-ww-z34bnk.lib def-ww.lib
|
||||
zx ZMAC -BPBIO-WW -/P
|
||||
if exist bp34bnk.prn del bp34bnk.prn
|
||||
ren bpbio-ww.prn bp34bnk.prn
|
||||
|
||||
if exist bp34bnk.rel del bp34bnk.rel
|
||||
ren bpbio-ww.rel bp34bnk.rel
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34bnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34bnk.img del bp34bnk.img
|
||||
if exist bpsys.img ren bpsys.img bp34bnk.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34xbnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34xbnk.img del bp34xbnk.img
|
||||
if exist bpsys.img ren bpsys.img bp34xbnk.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34tbnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34tbnk.img del bp34tbnk.img
|
||||
if exist bpsys.img ren bpsys.img bp34tbnk.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp34nbnk.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp34nbnk.img del bp34nbnk.img
|
||||
if exist bpsys.img ren bpsys.img bp34nbnk.img
|
||||
|
||||
rem
|
||||
rem Z41 + ZSDOS2 w/ Banked BPBIOS
|
||||
rem
|
||||
|
||||
copy def-ww-z41.lib def-ww.lib
|
||||
zx ZMAC -BPBIO-WW -/P
|
||||
if exist bp41.prn del bp41.prn
|
||||
ren bpbio-ww.prn bp41.prn
|
||||
|
||||
if exist bp41.rel del bp41.rel
|
||||
ren bpbio-ww.rel bp41.rel
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp41.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp41.img del bp41.img
|
||||
if exist bpsys.img ren bpsys.img bp41.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp41x.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp41x.img del bp41x.img
|
||||
if exist bpsys.img ren bpsys.img bp41x.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp41t.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp41t.img del bp41t.img
|
||||
if exist bpsys.img ren bpsys.img bp41t.img
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp41n.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp41n.img del bp41n.img
|
||||
if exist bpsys.img ren bpsys.img bp41n.img
|
||||
|
||||
:startup
|
||||
call :makebp 41tbnk
|
||||
call :makebp 41nbnk
|
||||
|
||||
pause
|
||||
|
||||
@@ -266,8 +35,41 @@ cpmcp.exe -f wbw_hd0 ../../Output/hd0.img *.img 0:
|
||||
cpmrm.exe -f wbw_hd0 ../../Output/hd0.img 0:*.rel
|
||||
cpmcp.exe -f wbw_hd0 ../../Output/hd0.img *.rel 0:
|
||||
|
||||
rem cpmrm.exe -f wbw_hd0 ../../Output/hd0.img 0:*.dat
|
||||
rem cpmcp.exe -f wbw_hd0 ../../Output/hd0.img *.dat 0:
|
||||
|
||||
cpmrm.exe -f wbw_hd0 ../../Output/hd0.img 0:*.zex
|
||||
cpmcp.exe -f wbw_hd0 ../../Output/hd0.img *.zex 0:
|
||||
|
||||
cpmrm.exe -f wbw_hd0 ../../Output/hd0.img 0:myterm.z3t
|
||||
cpmcp.exe -f wbw_hd0 ../../Output/hd0.img myterm.z3t 0:myterm.z3t
|
||||
cpmcp.exe -f wbw_hd0 ../../Output/hd0.img myterm.z3t 0:myterm.z3t
|
||||
|
||||
goto :eof
|
||||
|
||||
:makebp
|
||||
|
||||
set VER=%1
|
||||
echo.
|
||||
echo Building BPBIOS Variant "%VER%"...
|
||||
echo.
|
||||
|
||||
copy def-ww-z%VER%.lib def-ww.lib
|
||||
if exist bpbio-ww.rel del bpbio-ww.rel
|
||||
zx ZMAC -BPBIO-WW -/P
|
||||
if exist bp%VER%.prn del bp%VER%.prn
|
||||
ren bpbio-ww.prn bp%VER%.prn
|
||||
|
||||
rem pause
|
||||
|
||||
if exist bpsys.img del bpsys.img
|
||||
zx bpbuild -bp%VER%.dat <bpbld1.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
ren bpsys.img bpsys.$$$
|
||||
zx bpbuild -bpsys.$$$ <bpbld2.rsp
|
||||
if exist bpsys.$$$ del bpsys.$$$
|
||||
if exist bp%VER%.img del bp%VER%.img
|
||||
if exist bpsys.img ren bpsys.img bp%VER%.img
|
||||
|
||||
rem pause
|
||||
|
||||
goto :eof
|
||||
|
||||
@@ -3,4 +3,6 @@ if exist *.prn del *.prn
|
||||
if exist *.err del *.err
|
||||
if exist *.img del *.img
|
||||
if exist bp*.rel del bp*.rel
|
||||
if exist *.bak del *.bak
|
||||
if exist *.bak del *.bak
|
||||
|
||||
pushd ZCPR33 && call Clean.cmd && popd
|
||||
|
||||
8
Source/BPBIOS/ZCPR33/@WBW.txt
Normal file
8
Source/BPBIOS/ZCPR33/@WBW.txt
Normal file
@@ -0,0 +1,8 @@
|
||||
This directory contains the official ZCPR 3.3 source with minor customizations
|
||||
to support the BPBIOS build in the parent directory:
|
||||
|
||||
- Modified to produce a relocatable image compatibile with BPBUILD
|
||||
- Build process (Build.cmd) creates ZCPR33T.REL and ZCPR33N.REL based
|
||||
on Z3BASET.LIB and B3BASEN.LIB from parent directory.
|
||||
|
||||
See "@WBW Z3ENV.txt" file in parent directory for more information.
|
||||
@@ -8,8 +8,10 @@ set ZXBINDIR=../../../tools/cpm/bin/
|
||||
set ZXLIBDIR=../../../tools/cpm/lib/
|
||||
set ZXINCDIR=../../../tools/cpm/include/
|
||||
|
||||
copy ..\z3base.lib .
|
||||
copy ..\z3baset.lib .
|
||||
zx ZMAC -zcpr33t.z80 -/P
|
||||
copy zcpr33t.rel ..
|
||||
|
||||
zx ZMAC -zcpr33.z80 -/P
|
||||
|
||||
copy zcpr33.rel ..
|
||||
copy ..\z3basen.lib .
|
||||
zx ZMAC -zcpr33n.z80 -/P
|
||||
copy zcpr33n.rel ..
|
||||
|
||||
@@ -1,128 +1,226 @@
|
||||
; B/P Bios System Z3 Definition File.
|
||||
; Z3BASE - Dynamic Configuration
|
||||
;
|
||||
; ZCPR33 is copyright 1987 by Echelon, Inc. All rights reserved. End-user
|
||||
; distribution and duplication permitted for non-commercial purposes only.
|
||||
; Any commercial use of ZCPR33, defined as any situation where the duplicator
|
||||
; recieves revenue by duplicating or distributing ZCPR33 by itself or in
|
||||
; conjunction with any hardware or software product, is expressly prohibited
|
||||
; unless authorized in writing by Echelon.
|
||||
;
|
||||
; This is a special version of Z3BASE, inspired by Joe Wright's Z3BASE
|
||||
; for Z-Com. All segment addresses are automatically derived when the
|
||||
; CCP equate is set. The benefit of this is that reconfiguration of the
|
||||
; system after initial installation is greatly eased.
|
||||
;
|
||||
; Although this version of Z3BASE is being distributed with ZCPR 3.3, any
|
||||
; previous version of Z3BASE can be used to assemble the Z33 Command
|
||||
; Processor. No new symbols are needed. So, if you have an existing
|
||||
; Z3BASE, go ahead and use it.
|
||||
;
|
||||
; Instructions:
|
||||
;
|
||||
; The user should first design the ZCPR3 memory usage using the chart
|
||||
; below. (Echelon recommends the chart be filled out, even though it is
|
||||
; not read by the assembler, so that your system will be self-documenting.)
|
||||
; Then set the CCP equate for the beginning address of ZCPR3. Next, examine
|
||||
; and change the SEGn equates which follow in the file to ensure that the
|
||||
; system segments and buffers are placed at the proper addresses.
|
||||
;
|
||||
; This file has been customized for use with AMPRO hard disk systems. The
|
||||
; target configuration has support for hard disks up to 49 Meg, extended
|
||||
; IOP support, and 28-entry NDR.
|
||||
;
|
||||
;****************************************************************
|
||||
;* *
|
||||
;* Z3BASE.LIB -- Base Addresses for ZCPR 3.3/Z-System *
|
||||
;* *
|
||||
;* Segments: *
|
||||
;* *
|
||||
;* Segment Function *
|
||||
;* ------- -------- *
|
||||
;* ZRDOS Echelon Z80 Replacement Disk Operating *
|
||||
;* System, Version 1.7 (Public ZRDOS Plus) *
|
||||
;* CBIOSZ Ampro-compatible BIOS with additional *
|
||||
;* ZCPR3 initialization routines *
|
||||
;* ZCPR3 Echelon Z80 Command Processor *
|
||||
;* Replacement, Version 3.3 (ZCPR3) *
|
||||
;* *.ENV All Environment Descriptors *
|
||||
;* *.FCP All Flow Command Packages *
|
||||
;* *.NDR All Named Directory Definition Files *
|
||||
;* *.RCP All Resident Command Packages *
|
||||
;* *.IOP All Input/Output Packages *
|
||||
;* *
|
||||
;* *
|
||||
;* Memory Map of System (for CCP EQU 0BC00H): *
|
||||
;* *
|
||||
;* Address Range Size Function *
|
||||
;* ------------- ------- -------- *
|
||||
;* 0 - FF 256 b Standard CP/M Buffers except *
|
||||
;* 100 - C3FF ~49 K Transient Program Area *
|
||||
;* BC00 - C3FF 2K ZCPR 3.3 Command Processor *
|
||||
;* C400 - D1FF 3.5 K ZRDOS *
|
||||
;* D200 - EAFF 6.25K Ampro BIOS w/hard disk buffers *
|
||||
;* EB00 - F2FF 2 K Resident Command Package *
|
||||
;* F300 - F8FF 1.5 K Input/Output Package *
|
||||
;* F900 - FAFF .5 K Flow Command Package *
|
||||
;* FB00 - FB7F 128 b ZCPR3 Shell Stack *
|
||||
;* FB80 - FBCF 80 b ZCPR3 Message Buffers *
|
||||
;* FBD0 - FBF3 36 b ZCPR3 External FCB *
|
||||
;* FBF4 - FBFE 11 b ZCPR3 External Path *
|
||||
;* FBFF 1 b Wheel Byte *
|
||||
;* FC00 - FDFF .5 K Memory-Based Named Directory *
|
||||
;* FE00 - FEFF 256 b Environment Descriptor *
|
||||
;* Bytes 00H-7FH: Z3 Parameters *
|
||||
;* Bytes 80H-FFH: Z3 TCAP *
|
||||
;* FF00 - FFCF 208 B Multiple Command Line Buffer *
|
||||
;* FD00 - FFFF 48 b ZCPR3 External Stack *
|
||||
;****************************************************************
|
||||
|
||||
; This file is adapted from the basic Z3BASE.LIB configuration file used for
|
||||
; most ZCPR33 systems. It has added the new definitions for the Resident
|
||||
; User Space defined in B/P Bios descriptions.
|
||||
;=========================================================================
|
||||
;== NOTE: The Starting Address of the User Space marks the lower ==
|
||||
;== base of memory and MUST be entered. B/P Bios Utilities use ==
|
||||
;== this address to locate many portions of the operating system. ==
|
||||
;=========================================================================
|
||||
; To change your systems definition, first sketch out the memory map in the
|
||||
; comment table, then set the equates to reflect the memory map, doing any
|
||||
; required calculations for element sizes and required spaces. As an
|
||||
; alternative, just leave this file alone and configure everything with
|
||||
; the utilities provided.
|
||||
FALSE equ 0
|
||||
TRUE equ NOT FALSE
|
||||
|
||||
; FFE0 - FFFF 32 Bytes HBIOS Reserved
|
||||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack
|
||||
; FF00 - FFAF 176 Bytes Multiple Command Line Buffer
|
||||
; FE00 - FEFF 256 Bytes Environment Descriptor
|
||||
; Bytes 00H-7FH: Z3 Parameters
|
||||
; Bytes 80H-FFH: Z3 TCAP
|
||||
; FDFF 1 Byte Wheel byte
|
||||
; FDF4 - FDFE 11 Bytes Path (5 elements)
|
||||
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB
|
||||
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers
|
||||
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack
|
||||
; FC00 - FCFF 256 Bytes Named Directory Buffer
|
||||
; FA00 - FBFF 512 Bytes Flow Command Package
|
||||
; F200 - F9FF 2.0 KBytes Resident Command Package
|
||||
; EC00 - F1FF 1.5 KBytes IO Package
|
||||
; E900 - EBFF .75 KBytes Resident User Space
|
||||
Z3REV EQU 33 ; ZCPR3 REV NUMBER
|
||||
MSIZE EQU 54 ; SIZE OF CPM SYSTEM
|
||||
|
||||
; The remainder is for the Operating System. Exact sizes vary depending
|
||||
; primarily on the Number and sizes of Hard Drive Partitions, but may be:
|
||||
BASE EQU 0
|
||||
|
||||
; D100 - EBFF 5.0 KBytes B/P BIOS (unbanked version)
|
||||
; C300 - D0FF 3.5 KBytes ZSDOS 1.0 BDOS
|
||||
; BB00 - C2FF 2 KBytes ZCPR 3.3 Command Processor
|
||||
; 0100 - BAFF ~46 KBytes Transient Program Area
|
||||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
|
||||
;========================================================================
|
||||
CCP EQU 0BC00H ; ZCPR3 COMMAND PROCESSOR
|
||||
|
||||
FALSE EQU 0
|
||||
TRUE EQU NOT FALSE
|
||||
seg1 equ CCP+2F00h ; 11.75k from CCP to here (adding 2k ZCPR,
|
||||
; 3.5k DOS, and 6.25k BIOS).
|
||||
|
||||
YES EQU TRUE
|
||||
NO EQU FALSE
|
||||
;
|
||||
; RCP definition. Set RCPS to 0 to eliminate RCP
|
||||
;
|
||||
|
||||
; The External Stack is placed in the very top position in memory. It is
|
||||
; mandatory for B/P Bios and ZCPR 3.3.
|
||||
RCPS EQU 16 ; 16 128-byte Blocks (2K bytes)
|
||||
|
||||
;EXTSTK EQU 0FFD0H ; ZCPR3 External Stack
|
||||
EXTSTK EQU 0FFB0H ; ZCPR3 External Stack
|
||||
EXTSTKS EQU YES
|
||||
IF RCPS NE 0
|
||||
RCP EQU seg1 ; RESIDENT COMMAND PACKAGE
|
||||
ELSE
|
||||
RCP EQU 0
|
||||
ENDIF
|
||||
|
||||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
|
||||
; place it above the Environment. It is mandatory for ZCPR 3.3.
|
||||
seg2 equ seg1+[rcps*128]
|
||||
|
||||
Z3CL EQU 0FF00H ; ZCPR3 Command Line Buffer
|
||||
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
Z3CLS EQU 176-5 ; Size of Command Line Buffer-5
|
||||
;
|
||||
; IOP definition. Set IOPS to 0 to eliminate IOP
|
||||
;
|
||||
IOPS EQU 12 ; 12 128-byte Blocks (1.5K bytes)
|
||||
|
||||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
|
||||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
|
||||
IF IOPS NE 0
|
||||
IOP EQU seg2 ; REDIRECTABLE I/O PACKAGE
|
||||
ELSE
|
||||
IOP EQU 0
|
||||
ENDIF
|
||||
|
||||
Z3ENV EQU 0FE00H ; Environment Descriptors
|
||||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
|
||||
seg3 equ seg2+[iops*128]
|
||||
|
||||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
|
||||
;
|
||||
; FCP definition. Set FCPS to 0 to eliminate FCP
|
||||
;
|
||||
|
||||
Z3WHL EQU 0FDFFH ; Wheel Byte Address
|
||||
Z3WHLS EQU YES
|
||||
FCPS EQU 4 ; 4 128-byte Blocks (0.5K bytes)
|
||||
|
||||
; The Path is mandatory for ZCPR 3.3.
|
||||
IF FCPS NE 0
|
||||
fcp equ seg3
|
||||
ELSE
|
||||
fcp equ 0
|
||||
ENDIF
|
||||
|
||||
EXPATH EQU 0FDF4H ; External Path starting Address
|
||||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
|
||||
; This defines 5 2-byte Path Elements
|
||||
|
||||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
|
||||
|
||||
EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB
|
||||
EXTFCBS EQU YES
|
||||
|
||||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
|
||||
|
||||
Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer
|
||||
Z3MSGS EQU YES
|
||||
seg4 equ seg3+[fcps*128]
|
||||
|
||||
;
|
||||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
|
||||
;
|
||||
|
||||
SHSTK EQU 0FD00H ; Shell Stack Starting Address
|
||||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
|
||||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
|
||||
SHSTKS EQU 4 ; NUMBER OF SHSIZE-BYTE SHELL STACK ENTRIES
|
||||
SHSIZE EQU 32 ; SIZE OF A SHELL STACK ENTRY
|
||||
; (STACK SIZE = SHSTKS * SHSIZE)
|
||||
IF SHSTKS NE 0
|
||||
SHSTK EQU seg4
|
||||
ELSE
|
||||
SHSTK EQU 0
|
||||
ENDIF
|
||||
|
||||
seg5 equ seg4+[shstks*shsize]
|
||||
|
||||
;
|
||||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
|
||||
;
|
||||
Z3MSG EQU seg5 ; ZCPR3 MESSAGE BUFFER
|
||||
|
||||
seg6 equ seg5+80
|
||||
|
||||
;
|
||||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
EXTFCB EQU seg6 ; ZCPR3 EXTERNAL FCB
|
||||
|
||||
seg7 equ seg6+36
|
||||
|
||||
;
|
||||
; The Path is mandatory for ZCPR 3.3. No more than 5 path elements can be
|
||||
; used with this Z3BASE.LIB file.
|
||||
;
|
||||
|
||||
EXPATH EQU seg7 ; EXTERNAL PATH
|
||||
EXPATHS EQU 5 ; 5 2-byte Path Elements
|
||||
; (PATH SIZE = EXPATHS*2 + 1)
|
||||
|
||||
seg8 equ seg7+[expaths*2]+1
|
||||
|
||||
;
|
||||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
Z3WHL EQU seg8 ; WHEEL BYTE ADDRESS
|
||||
|
||||
seg9 equ seg8+1
|
||||
|
||||
;
|
||||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
|
||||
; the named directory buffer.
|
||||
; the named directory buffer. If Z3NDIRS is changed, also change the seg10
|
||||
; equate below.
|
||||
;
|
||||
Z3NDIRS EQU 28 ; 28 18-byte Named Directory Elements permitted
|
||||
; (NDIR SIZE = Z3NDIRS*18 + 1 for trailing 0)
|
||||
IF Z3NDIRS NE 0
|
||||
Z3NDIR EQU seg9 ; ZCPR3 NAMED DIRECTORY AREA
|
||||
ELSE
|
||||
Z3NDIR EQU 0
|
||||
ENDIF
|
||||
|
||||
Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer
|
||||
Z3NDIRS EQU 14 ; Number of Named Directory Elements
|
||||
; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes)
|
||||
seg10 equ seg9+512 ; add 512 for 28-entry NDR
|
||||
; add 256 for 14-entry NDR ("standard")
|
||||
; add 0 if Z3NDIRS is set to 0
|
||||
|
||||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
|
||||
;
|
||||
; The ZCPR3 External Environment Descriptor is mandatory for ZCPR 3.3.
|
||||
; Echelon recommends you work this out so that your ENV begins at address
|
||||
; FE00h, but this is only a recommendation and not mandatory.
|
||||
;
|
||||
|
||||
FCP EQU 0FA00H ; Start of Flow Command Package
|
||||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
|
||||
Z3ENV EQU seg10 ; ENVIRONMENT DESCRIPTORS
|
||||
Z3ENVS EQU 2 ; SIZE OF ENVIRONMENT DESCRIPTOR IN 128-BYTE BLOCKS
|
||||
|
||||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
|
||||
seg11 equ seg10+[z3envs*128]
|
||||
|
||||
RCP EQU 0F200H ; Start of Resident Command Processor
|
||||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
|
||||
;
|
||||
; The ZCPR3 External Command Line Buffer is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
; IO Package definition. Set IOPS to 0 to eliminate IOP
|
||||
Z3CL EQU seg11 ; ZCPR3 COMMAND LINE BUFFER
|
||||
Z3CLS EQU 208 ; SIZE OF COMMAND LINE BUFFER
|
||||
|
||||
IOP EQU 0EC00H ; Start of IO Package
|
||||
IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
|
||||
seg12 equ seg11+z3cls
|
||||
|
||||
;=========================================================================
|
||||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
|
||||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
|
||||
; MUST BE PRESENT!
|
||||
;
|
||||
; The ZCPR3 External Stack is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
USPC EQU 0E900H ; Start of Resident User Space (MANDATORY)
|
||||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
|
||||
EXTSTK EQU seg12 ; ZCPR3 EXTERNAL STACK
|
||||
|
||||
;--- End of Z3BASE.LIB ---
|
||||
|
||||
; end of Z3BASE.LIB
|
||||
|
||||
@@ -1,226 +0,0 @@
|
||||
; Z3BASE - Dynamic Configuration
|
||||
;
|
||||
; ZCPR33 is copyright 1987 by Echelon, Inc. All rights reserved. End-user
|
||||
; distribution and duplication permitted for non-commercial purposes only.
|
||||
; Any commercial use of ZCPR33, defined as any situation where the duplicator
|
||||
; recieves revenue by duplicating or distributing ZCPR33 by itself or in
|
||||
; conjunction with any hardware or software product, is expressly prohibited
|
||||
; unless authorized in writing by Echelon.
|
||||
;
|
||||
; This is a special version of Z3BASE, inspired by Joe Wright's Z3BASE
|
||||
; for Z-Com. All segment addresses are automatically derived when the
|
||||
; CCP equate is set. The benefit of this is that reconfiguration of the
|
||||
; system after initial installation is greatly eased.
|
||||
;
|
||||
; Although this version of Z3BASE is being distributed with ZCPR 3.3, any
|
||||
; previous version of Z3BASE can be used to assemble the Z33 Command
|
||||
; Processor. No new symbols are needed. So, if you have an existing
|
||||
; Z3BASE, go ahead and use it.
|
||||
;
|
||||
; Instructions:
|
||||
;
|
||||
; The user should first design the ZCPR3 memory usage using the chart
|
||||
; below. (Echelon recommends the chart be filled out, even though it is
|
||||
; not read by the assembler, so that your system will be self-documenting.)
|
||||
; Then set the CCP equate for the beginning address of ZCPR3. Next, examine
|
||||
; and change the SEGn equates which follow in the file to ensure that the
|
||||
; system segments and buffers are placed at the proper addresses.
|
||||
;
|
||||
; This file has been customized for use with AMPRO hard disk systems. The
|
||||
; target configuration has support for hard disks up to 49 Meg, extended
|
||||
; IOP support, and 28-entry NDR.
|
||||
;
|
||||
;****************************************************************
|
||||
;* *
|
||||
;* Z3BASE.LIB -- Base Addresses for ZCPR 3.3/Z-System *
|
||||
;* *
|
||||
;* Segments: *
|
||||
;* *
|
||||
;* Segment Function *
|
||||
;* ------- -------- *
|
||||
;* ZRDOS Echelon Z80 Replacement Disk Operating *
|
||||
;* System, Version 1.7 (Public ZRDOS Plus) *
|
||||
;* CBIOSZ Ampro-compatible BIOS with additional *
|
||||
;* ZCPR3 initialization routines *
|
||||
;* ZCPR3 Echelon Z80 Command Processor *
|
||||
;* Replacement, Version 3.3 (ZCPR3) *
|
||||
;* *.ENV All Environment Descriptors *
|
||||
;* *.FCP All Flow Command Packages *
|
||||
;* *.NDR All Named Directory Definition Files *
|
||||
;* *.RCP All Resident Command Packages *
|
||||
;* *.IOP All Input/Output Packages *
|
||||
;* *
|
||||
;* *
|
||||
;* Memory Map of System (for CCP EQU 0BC00H): *
|
||||
;* *
|
||||
;* Address Range Size Function *
|
||||
;* ------------- ------- -------- *
|
||||
;* 0 - FF 256 b Standard CP/M Buffers except *
|
||||
;* 100 - C3FF ~49 K Transient Program Area *
|
||||
;* BC00 - C3FF 2K ZCPR 3.3 Command Processor *
|
||||
;* C400 - D1FF 3.5 K ZRDOS *
|
||||
;* D200 - EAFF 6.25K Ampro BIOS w/hard disk buffers *
|
||||
;* EB00 - F2FF 2 K Resident Command Package *
|
||||
;* F300 - F8FF 1.5 K Input/Output Package *
|
||||
;* F900 - FAFF .5 K Flow Command Package *
|
||||
;* FB00 - FB7F 128 b ZCPR3 Shell Stack *
|
||||
;* FB80 - FBCF 80 b ZCPR3 Message Buffers *
|
||||
;* FBD0 - FBF3 36 b ZCPR3 External FCB *
|
||||
;* FBF4 - FBFE 11 b ZCPR3 External Path *
|
||||
;* FBFF 1 b Wheel Byte *
|
||||
;* FC00 - FDFF .5 K Memory-Based Named Directory *
|
||||
;* FE00 - FEFF 256 b Environment Descriptor *
|
||||
;* Bytes 00H-7FH: Z3 Parameters *
|
||||
;* Bytes 80H-FFH: Z3 TCAP *
|
||||
;* FF00 - FFCF 208 B Multiple Command Line Buffer *
|
||||
;* FD00 - FFFF 48 b ZCPR3 External Stack *
|
||||
;****************************************************************
|
||||
|
||||
FALSE equ 0
|
||||
TRUE equ NOT FALSE
|
||||
|
||||
Z3REV EQU 33 ; ZCPR3 REV NUMBER
|
||||
MSIZE EQU 54 ; SIZE OF CPM SYSTEM
|
||||
|
||||
BASE EQU 0
|
||||
|
||||
CCP EQU 0BC00H ; ZCPR3 COMMAND PROCESSOR
|
||||
|
||||
seg1 equ CCP+2F00h ; 11.75k from CCP to here (adding 2k ZCPR,
|
||||
; 3.5k DOS, and 6.25k BIOS).
|
||||
|
||||
;
|
||||
; RCP definition. Set RCPS to 0 to eliminate RCP
|
||||
;
|
||||
|
||||
RCPS EQU 16 ; 16 128-byte Blocks (2K bytes)
|
||||
|
||||
IF RCPS NE 0
|
||||
RCP EQU seg1 ; RESIDENT COMMAND PACKAGE
|
||||
ELSE
|
||||
RCP EQU 0
|
||||
ENDIF
|
||||
|
||||
seg2 equ seg1+[rcps*128]
|
||||
|
||||
;
|
||||
; IOP definition. Set IOPS to 0 to eliminate IOP
|
||||
;
|
||||
IOPS EQU 12 ; 12 128-byte Blocks (1.5K bytes)
|
||||
|
||||
IF IOPS NE 0
|
||||
IOP EQU seg2 ; REDIRECTABLE I/O PACKAGE
|
||||
ELSE
|
||||
IOP EQU 0
|
||||
ENDIF
|
||||
|
||||
seg3 equ seg2+[iops*128]
|
||||
|
||||
;
|
||||
; FCP definition. Set FCPS to 0 to eliminate FCP
|
||||
;
|
||||
|
||||
FCPS EQU 4 ; 4 128-byte Blocks (0.5K bytes)
|
||||
|
||||
IF FCPS NE 0
|
||||
fcp equ seg3
|
||||
ELSE
|
||||
fcp equ 0
|
||||
ENDIF
|
||||
|
||||
seg4 equ seg3+[fcps*128]
|
||||
|
||||
;
|
||||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
|
||||
;
|
||||
|
||||
SHSTKS EQU 4 ; NUMBER OF SHSIZE-BYTE SHELL STACK ENTRIES
|
||||
SHSIZE EQU 32 ; SIZE OF A SHELL STACK ENTRY
|
||||
; (STACK SIZE = SHSTKS * SHSIZE)
|
||||
IF SHSTKS NE 0
|
||||
SHSTK EQU seg4
|
||||
ELSE
|
||||
SHSTK EQU 0
|
||||
ENDIF
|
||||
|
||||
seg5 equ seg4+[shstks*shsize]
|
||||
|
||||
;
|
||||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
|
||||
;
|
||||
Z3MSG EQU seg5 ; ZCPR3 MESSAGE BUFFER
|
||||
|
||||
seg6 equ seg5+80
|
||||
|
||||
;
|
||||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
EXTFCB EQU seg6 ; ZCPR3 EXTERNAL FCB
|
||||
|
||||
seg7 equ seg6+36
|
||||
|
||||
;
|
||||
; The Path is mandatory for ZCPR 3.3. No more than 5 path elements can be
|
||||
; used with this Z3BASE.LIB file.
|
||||
;
|
||||
|
||||
EXPATH EQU seg7 ; EXTERNAL PATH
|
||||
EXPATHS EQU 5 ; 5 2-byte Path Elements
|
||||
; (PATH SIZE = EXPATHS*2 + 1)
|
||||
|
||||
seg8 equ seg7+[expaths*2]+1
|
||||
|
||||
;
|
||||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
Z3WHL EQU seg8 ; WHEEL BYTE ADDRESS
|
||||
|
||||
seg9 equ seg8+1
|
||||
|
||||
;
|
||||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
|
||||
; the named directory buffer. If Z3NDIRS is changed, also change the seg10
|
||||
; equate below.
|
||||
;
|
||||
Z3NDIRS EQU 28 ; 28 18-byte Named Directory Elements permitted
|
||||
; (NDIR SIZE = Z3NDIRS*18 + 1 for trailing 0)
|
||||
IF Z3NDIRS NE 0
|
||||
Z3NDIR EQU seg9 ; ZCPR3 NAMED DIRECTORY AREA
|
||||
ELSE
|
||||
Z3NDIR EQU 0
|
||||
ENDIF
|
||||
|
||||
seg10 equ seg9+512 ; add 512 for 28-entry NDR
|
||||
; add 256 for 14-entry NDR ("standard")
|
||||
; add 0 if Z3NDIRS is set to 0
|
||||
|
||||
;
|
||||
; The ZCPR3 External Environment Descriptor is mandatory for ZCPR 3.3.
|
||||
; Echelon recommends you work this out so that your ENV begins at address
|
||||
; FE00h, but this is only a recommendation and not mandatory.
|
||||
;
|
||||
|
||||
Z3ENV EQU seg10 ; ENVIRONMENT DESCRIPTORS
|
||||
Z3ENVS EQU 2 ; SIZE OF ENVIRONMENT DESCRIPTOR IN 128-BYTE BLOCKS
|
||||
|
||||
seg11 equ seg10+[z3envs*128]
|
||||
|
||||
;
|
||||
; The ZCPR3 External Command Line Buffer is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
Z3CL EQU seg11 ; ZCPR3 COMMAND LINE BUFFER
|
||||
Z3CLS EQU 208 ; SIZE OF COMMAND LINE BUFFER
|
||||
|
||||
seg12 equ seg11+z3cls
|
||||
|
||||
;
|
||||
; The ZCPR3 External Stack is mandatory for ZCPR 3.3.
|
||||
;
|
||||
|
||||
EXTSTK EQU seg12 ; ZCPR3 EXTERNAL STACK
|
||||
|
||||
; end of Z3BASE.LIB
|
||||
|
||||
@@ -14,8 +14,9 @@
|
||||
; alternative, just leave this file alone and configure everything with
|
||||
; the utilities provided.
|
||||
|
||||
; FFD0 - FFFF 48 Bytes ZCPR3 External Stack
|
||||
; FF00 - FFCF 208 Bytes Multiple Command Line Buffer
|
||||
; FFE0 - FFFF 32 Bytes HBIOS Reserved
|
||||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack
|
||||
; FF00 - FFAF 176 Bytes Multiple Command Line Buffer
|
||||
; FE00 - FEFF 256 Bytes Environment Descriptor
|
||||
; Bytes 00H-7FH: Z3 Parameters
|
||||
; Bytes 80H-FFH: Z3 TCAP
|
||||
@@ -49,14 +50,16 @@ NO EQU FALSE
|
||||
; The External Stack is placed in the very top position in memory. It is
|
||||
; mandatory for B/P Bios and ZCPR 3.3.
|
||||
|
||||
EXTSTK EQU 0FFD0H ; ZCPR3 External Stack
|
||||
;EXTSTK EQU 0FFD0H ; ZCPR3 External Stack
|
||||
EXTSTK EQU 0FFB0H ; ZCPR3 External Stack
|
||||
EXTSTKS EQU YES
|
||||
|
||||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
|
||||
; place it above the Environment. It is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3CL EQU 0FF00H ; ZCPR3 Command Line Buffer
|
||||
Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
Z3CLS EQU 176-5 ; Size of Command Line Buffer-5
|
||||
|
||||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
|
||||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
|
||||
126
Source/BPBIOS/ZCPR33/z3baset.lib
Normal file
126
Source/BPBIOS/ZCPR33/z3baset.lib
Normal file
@@ -0,0 +1,126 @@
|
||||
; B/P Bios System Z3 Definition File.
|
||||
|
||||
; This file is adapted from the basic Z3BASE.LIB configuration file used for
|
||||
; most ZCPR33 systems. It has added the new definitions for the Resident
|
||||
; User Space defined in B/P Bios descriptions.
|
||||
;=========================================================================
|
||||
;== NOTE: The Starting Address of the User Space marks the lower ==
|
||||
;== base of memory and MUST be entered. B/P Bios Utilities use ==
|
||||
;== this address to locate many portions of the operating system. ==
|
||||
;=========================================================================
|
||||
; To change your systems definition, first sketch out the memory map in the
|
||||
; comment table, then set the equates to reflect the memory map, doing any
|
||||
; required calculations for element sizes and required spaces. As an
|
||||
; alternative, just leave this file alone and configure everything with
|
||||
; the utilities provided.
|
||||
|
||||
; FE00 - FFFF 512 Bytes HBIOS Reserved
|
||||
; FDFF 1 Byte Wheel byte
|
||||
; FDF4 - FDFE 11 Bytes Path (5 elements)
|
||||
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB
|
||||
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers
|
||||
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack
|
||||
; FC00 - FCFF 256 Bytes Named Directory Buffer
|
||||
; FA00 - FBFF 512 Bytes Flow Command Package
|
||||
; F200 - F9FF 2.0 KBytes Resident Command Package
|
||||
; EC00 - F1FF 1.5 KBytes IO Package
|
||||
; EBD0 - EBFF 48 Bytes ZCPR3 External Stack
|
||||
; EB00 - EBAF 176 Bytes Multiple Command Line Buffer
|
||||
; EA00 - EAFF 256 Bytes Environment Descriptor
|
||||
; Bytes 00H-7FH: Z3 Parameters
|
||||
; Bytes 80H-FFH: Z3 TCAP
|
||||
; E700 - E9FF .75 KBytes Resident User Space
|
||||
|
||||
; The remainder is for the Operating System. Exact sizes vary depending
|
||||
; primarily on the Number and sizes of Hard Drive Partitions, but may be:
|
||||
|
||||
; D300 - E6FF 5.0 KBytes B/P BIOS (unbanked version)
|
||||
; C500 - D2FF 3.5 KBytes ZSDOS 1.0 BDOS
|
||||
; BD00 - C4FF 2 KBytes ZCPR 3.3 Command Processor
|
||||
; 0100 - BCFF ~47 KBytes Transient Program Area
|
||||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
|
||||
;========================================================================
|
||||
|
||||
FALSE EQU 0
|
||||
TRUE EQU NOT FALSE
|
||||
|
||||
YES EQU TRUE
|
||||
NO EQU FALSE
|
||||
|
||||
; The External Stack is placed in the very top position in memory. It is
|
||||
; mandatory for B/P Bios and ZCPR 3.3.
|
||||
|
||||
EXTSTK EQU 0EBD0H ; ZCPR3 External Stack
|
||||
EXTSTKS EQU YES
|
||||
|
||||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
|
||||
; place it above the Environment. It is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3CL EQU 0EB00H ; ZCPR3 Command Line Buffer
|
||||
Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
|
||||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
|
||||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
|
||||
|
||||
Z3ENV EQU 0EA00H ; Environment Descriptors
|
||||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
|
||||
|
||||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3WHL EQU 0FDFFH ; Wheel Byte Address
|
||||
Z3WHLS EQU YES
|
||||
|
||||
; The Path is mandatory for ZCPR 3.3.
|
||||
|
||||
EXPATH EQU 0FDF4H ; External Path starting Address
|
||||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
|
||||
; This defines 5 2-byte Path Elements
|
||||
|
||||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
|
||||
|
||||
EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB
|
||||
EXTFCBS EQU YES
|
||||
|
||||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
|
||||
|
||||
Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer
|
||||
Z3MSGS EQU YES
|
||||
|
||||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
|
||||
|
||||
SHSTK EQU 0FD00H ; Shell Stack Starting Address
|
||||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
|
||||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
|
||||
|
||||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
|
||||
; the named directory buffer.
|
||||
|
||||
Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer
|
||||
Z3NDIRS EQU 14 ; Number of Named Directory Elements
|
||||
; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes)
|
||||
|
||||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
|
||||
|
||||
FCP EQU 0FA00H ; Start of Flow Command Package
|
||||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
|
||||
|
||||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
|
||||
|
||||
RCP EQU 0F200H ; Start of Resident Command Processor
|
||||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
|
||||
|
||||
; IO Package definition. Set IOPS to 0 to eliminate IOP
|
||||
|
||||
IOP EQU 0EC00H ; Start of IO Package
|
||||
IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
|
||||
|
||||
;=========================================================================
|
||||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
|
||||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
|
||||
; MUST BE PRESENT!
|
||||
|
||||
USPC EQU 0E700H ; Start of Resident User Space (MANDATORY)
|
||||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
|
||||
|
||||
;--- End of Z3BASE.LIB ---
|
||||
|
||||
@@ -137,7 +137,7 @@ tfcb equ base+005ch ; Default FCB buffer
|
||||
tfcb2 equ tfcb+16 ; 2nd FCB
|
||||
tbuff equ base+0080h ; Default disk I/O buffer
|
||||
tpa equ base+0100h ; Base of TPA
|
||||
;bios equ ccp+0800h+0e00h ; BIOS location
|
||||
bios equ ccp+0800h+0e00h ; BIOS location
|
||||
|
||||
|
||||
; ---------- Error codes
|
||||
@@ -262,10 +262,6 @@ curdr equ z3msg+2fh ; Currently logged drive
|
||||
|
||||
if not rel ; If generating absolute code
|
||||
org ccp
|
||||
else
|
||||
common /_BIOS_/
|
||||
bios equ $
|
||||
cseg
|
||||
endif ;not rel
|
||||
|
||||
|
||||
|
||||
@@ -78,7 +78,7 @@
|
||||
; which are used to customize ZCPR33 for the user's working environment.
|
||||
; NOTE -- TRUE & FALSE are defined in Z3BASE.
|
||||
|
||||
maclib z3base.lib
|
||||
maclib z3basen.lib
|
||||
maclib z33hdr.lib
|
||||
|
||||
; Check that the configuration includes the required facilities
|
||||
@@ -137,7 +137,7 @@ tfcb equ base+005ch ; Default FCB buffer
|
||||
tfcb2 equ tfcb+16 ; 2nd FCB
|
||||
tbuff equ base+0080h ; Default disk I/O buffer
|
||||
tpa equ base+0100h ; Base of TPA
|
||||
bios equ ccp+0800h+0e00h ; BIOS location
|
||||
;bios equ ccp+0800h+0e00h ; BIOS location
|
||||
|
||||
|
||||
; ---------- Error codes
|
||||
@@ -262,6 +262,10 @@ curdr equ z3msg+2fh ; Currently logged drive
|
||||
|
||||
if not rel ; If generating absolute code
|
||||
org ccp
|
||||
else
|
||||
common /_BIOS_/
|
||||
bios equ $
|
||||
cseg
|
||||
endif ;not rel
|
||||
|
||||
|
||||
4042
Source/BPBIOS/ZCPR33/zcpr33t.z80
Normal file
4042
Source/BPBIOS/ZCPR33/zcpr33t.z80
Normal file
File diff suppressed because it is too large
Load Diff
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
BIN
Source/BPBIOS/bp41nbnk.dat
Normal file
BIN
Source/BPBIOS/bp41nbnk.dat
Normal file
Binary file not shown.
Binary file not shown.
BIN
Source/BPBIOS/bp41tbnk.dat
Normal file
BIN
Source/BPBIOS/bp41tbnk.dat
Normal file
Binary file not shown.
Binary file not shown.
@@ -98,7 +98,13 @@ WRUAL EQU 2 ; DOS code for unallocated write
|
||||
LOCKF EQU LOW [NOT AUTOSL] ;Lock flag for format default
|
||||
ALONE EQU FALSE ; Boot code equate
|
||||
IF Z3
|
||||
MACLIB Z3BASE.LIB ; Include ENV definitions
|
||||
; MACLIB Z3BASE.LIB ; Include ENV definitions
|
||||
IF CONF_T
|
||||
MACLIB Z3BASET.LIB
|
||||
ENDIF
|
||||
IF CONF_N
|
||||
MACLIB Z3BASEN.LIB
|
||||
ENDIF
|
||||
ENDIF
|
||||
PAGE
|
||||
;* * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
|
||||
|
||||
@@ -371,11 +371,11 @@ BLKMV: POP BC ; And number of bytes to move
|
||||
; Get and save the internal HBIOS physical disk
|
||||
; buffer address which is assumed to be in the
|
||||
; HBIOS bank.
|
||||
LD B,19H ; Set buffer function call
|
||||
LD B,18H ; Get buffer function call (assumes already allocated!!!)
|
||||
LD HL,0 ; ... with address 0 to get HBIOS buf adr
|
||||
CALL HBX_INVOKE ; ... to return internal HBIOS buffer adr
|
||||
LD (HB_DSKBUF),HL ; Record the buffer address
|
||||
|
||||
|
||||
IF HAVIOP
|
||||
LD HL,IOPRET
|
||||
LD (BIOSJT+1),HL
|
||||
|
||||
373
Source/BPBIOS/def-ww-z33n.lib
Normal file
373
Source/BPBIOS/def-ww-z33n.lib
Normal file
@@ -0,0 +1,373 @@
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
|
||||
; B/P BIOS Configuration and Equate File. ** System Dependant **
|
||||
; - D-X Designs Pty Ltd P112 CPU Board - **********************
|
||||
; Tailor your system here.
|
||||
;
|
||||
; 30 Aug 01 - Cleaned up for GPL release. HFB
|
||||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
|
||||
; 5 Jan 97 - Reformatted to Standard. HFB
|
||||
; 10 Jun 96 - Initial Test Release. HFB
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
|
||||
; BIOS Configuration Equates and Macros
|
||||
|
||||
DATE MACRO
|
||||
DEFB '17 Jan 14' ; Date of this version
|
||||
ENDM
|
||||
|
||||
AUTOCL MACRO
|
||||
DEFB 8,'ZEX Z33 ',0 ; Autostart command line
|
||||
ENDM
|
||||
|
||||
;--- Basic System and Z-System Section ---
|
||||
|
||||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
|
||||
IF MOVCPM
|
||||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
|
||||
ELSE
|
||||
VERS EQU 21H ; Version number w/Device Swapping permitted
|
||||
ENDIF
|
||||
BANKED EQU NO ; Is this a banked BIOS?
|
||||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
|
||||
INROM EQU NO ; Alternate bank in ROM?
|
||||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU YES ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU NO ; Set for Segment Configuration T
|
||||
CONF_N EQU YES ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
|
||||
; No = Include Common RAM transfer buffer
|
||||
|
||||
;--- Character Device Section ---
|
||||
|
||||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
|
||||
; NO = Only use the 4 defined Char Devices
|
||||
ESCC_B EQU NO ; Include ESCC Channel B Driver?
|
||||
; The following two devices result in non-standard data rates
|
||||
; with the standard 16.00 MHz crystal in the P112. If a more
|
||||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc)
|
||||
; is used, the ports become usable.
|
||||
; Driver code for ASCI0 and ASCI1 includes an option for
|
||||
; assembling Polled or Interrupt-driven buffered input.
|
||||
; Select the desired option for ASCI0 with the BUFFA0 flag,
|
||||
; and BUFFA1 for ASCI1.
|
||||
ASCI_0 EQU false ; Include ASCI0 Driver?
|
||||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver?
|
||||
ASCI_1 EQU false ; Include ASCI1 Driver?
|
||||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver?
|
||||
|
||||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
|
||||
; ..must be 2^n with n<8
|
||||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
|
||||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
|
||||
|
||||
;--- Clock and Time Section ---
|
||||
|
||||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
|
||||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC?
|
||||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No)
|
||||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count)
|
||||
|
||||
;--- Floppy Diskette Section ---
|
||||
|
||||
BIOERM EQU yes ; Print BIOS error messages?
|
||||
CALCSK EQU YES ; Calculate skew table?
|
||||
AUTOSL EQU YES ; Auto select floppy formats?
|
||||
; If AUTOSL=True, the next two are active...
|
||||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
|
||||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
|
||||
FLOPY8 EQU no ; Include 8" Floppy Formats?
|
||||
MORDPB EQU NO ; Include additional Floppy DPB Formats?
|
||||
|
||||
;--- RAM Disk Section ---
|
||||
|
||||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
|
||||
|
||||
;--- Hard Disk Section ---
|
||||
|
||||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
|
||||
; (Pick 1 of 3 options below)
|
||||
SCSI EQU NO ; YES = Use SCSI Driver
|
||||
IDE EQU NO ; YES = Use IDE Driver
|
||||
HDSK EQU YES ; YES = Use SIMH HDSK Driver
|
||||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
|
||||
; (DMA not implemented for GIDE)
|
||||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
|
||||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
|
||||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
|
||||
|
||||
;--- Logical Drive Section ---
|
||||
|
||||
DRV_A EQU no ; Set each of these equates for the drive and
|
||||
DRV_B EQU no ; partition complement of your system. Assume
|
||||
DRV_C EQU no ; that A-D are Floppies.
|
||||
DRV_D EQU no
|
||||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk
|
||||
DRV_F EQU yes ; Partitions
|
||||
DRV_G EQU yes
|
||||
DRV_H EQU yes
|
||||
DRV_I EQU yes
|
||||
DRV_J EQU yes
|
||||
DRV_K EQU yes
|
||||
DRV_L EQU yes
|
||||
DRV_M EQU RAMDSK ; This is Yes for RAM drive
|
||||
DRV_N EQU yes
|
||||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled
|
||||
DRV_P EQU no
|
||||
|
||||
;========== Configuration Unique Equates (P112) ===========
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
|
||||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
|
||||
; systems with dynamic RAMs.
|
||||
NOWAIT EQU NO ; Set to NO to use configured Wait States in
|
||||
; Hard Disk Driver. Yes to eliminate Waits.
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
|
||||
; memory in 32k increments. In P112, the ROM occupies the first 32k
|
||||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper
|
||||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
|
||||
|
||||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
|
||||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
|
||||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
|
||||
BNKU EQU 00H ; User Area Bank 58000H
|
||||
; (set to 0 to disable)
|
||||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
|
||||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
|
||||
; With both on-board RAMs only (MEM1 or MEM2),
|
||||
; the maximum Bank number is 11 (0BH).
|
||||
|
||||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
|
||||
|
||||
CNTLA0 EQU 00H ; Control Port ASCI 0
|
||||
CNTLA1 EQU 01H ; Control Port ASCI 1
|
||||
STAT0 EQU 04H ; Serial port 0 Status
|
||||
STAT1 EQU 05H ; Serial port 1 Status
|
||||
TDR0 EQU 06H ; Serial port 0 Output Data
|
||||
TDR1 EQU 07H ; Serial port 1 Output Data
|
||||
RDR0 EQU 08H ; Serial port 0 Input Data
|
||||
RDR1 EQU 09H ; Serial Port 1 Input Data
|
||||
CNTR EQU 0AH ; HD64180 Counter port
|
||||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
|
||||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
|
||||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
|
||||
RLDR0H EQU 0FH ; CTC0 Reload Count, High
|
||||
TCR EQU 10H ; Interrupt Control Register
|
||||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
|
||||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
|
||||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
|
||||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
|
||||
FRC EQU 18H ; Free-Running Counter
|
||||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
|
||||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
|
||||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
|
||||
DSTAT EQU 30H ; DMA Status/Control port
|
||||
DMODE EQU 31H ; DMA Mode Control port
|
||||
DCNTL EQU 32H ; DMA/WAIT Control Register
|
||||
IL EQU 33H ; Interrupt Segment Register
|
||||
ITC EQU 34H ; Interrupt/Trap Control Register
|
||||
RCR EQU 36H ; HD64180 Refresh Control register
|
||||
CBR EQU 38H ; MMU Common Base Register
|
||||
BBR EQU 39H ; MMU Bank Base Register
|
||||
CBAR EQU 3AH ; MMU Common/Bank Area Register
|
||||
OMCR EQU 3EH ; Operation Mode Control Reg
|
||||
ICR EQU 3FH ; I/O Control Register
|
||||
|
||||
; Some bit definitions used with the Z-180 on-chip peripherals:
|
||||
|
||||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
|
||||
RDRF EQU 80H ; ACSI Received Character available
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Extended Features of Z80182 for P112
|
||||
|
||||
WSGCS EQU 0D8H ; Wait-State Generator CS
|
||||
ENH182 EQU 0D9H ; Z80182 Enhancements Register
|
||||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
|
||||
RAMUBR EQU 0E6H ; RAM End Boundary
|
||||
RAMLBR EQU 0E7H ; RAM Start Boundary
|
||||
ROMBR EQU 0E8H ; ROM Boundary
|
||||
FIFOCTL EQU 0E9H ; FIFO Control Register
|
||||
RTOTC EQU 0EAH ; RX Time-Out Time Constant
|
||||
TTOTC EQU 0EBH ; TX Time-Out Time Constant
|
||||
FCR EQU 0ECH ; FIFO Register
|
||||
SCR EQU 0EFH ; System Pin Control
|
||||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
|
||||
THR EQU 0F0H ; MIMIN TX Holding Register (W)
|
||||
IER EQU 0F1H ; Interrupt Enable Register
|
||||
LCR EQU 0F3H ; Line Control Register
|
||||
MCR EQU 0F4H ; Modem Control Register
|
||||
LSR EQU 0F5H ; Line Status Register
|
||||
MDMSR EQU 0F6H ; Modem Status Register
|
||||
MSCR EQU 0F7H ; MIMIC Scratch Register
|
||||
DLATL EQU 0F8H ; Divisor Latch (Low)
|
||||
DLATM EQU 0F9H ; Divisor Latch (High)
|
||||
TTCR EQU 0FAH ; TX Time Constant
|
||||
RTCR EQU 0FBH ; RX Time Constant
|
||||
IVEC EQU 0FCH ; MIMIC Interrupt Vector
|
||||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
|
||||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
|
||||
MMCR EQU 0FFH ; MIMIC Master Control Register
|
||||
|
||||
; Z80182 PIO Registers
|
||||
|
||||
DDRA EQU 0EDH ; Data Direction Register A
|
||||
DRA EQU 0EEH ; Port A Data
|
||||
DDRB EQU 0E4H ; Data Direction Register B
|
||||
DRB EQU 0E5H ; Data B Data
|
||||
DDRC EQU 0DDH ; Data Direction Register C
|
||||
DRC EQU 0DEH ; Data C Data
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; ESCC Registers on Z80182
|
||||
|
||||
SCCACNT EQU 0E0H ; ESCC Control Channel A
|
||||
SCCAD EQU 0E1H ; ESCC Data Channel A
|
||||
SCCBCNT EQU 0E2H ; ESCC Control Channel B
|
||||
SCCBD EQU 0E3H ; ESCC Data Channel B
|
||||
|
||||
; [E]SCC Internal Register Definitions
|
||||
|
||||
RR0 EQU 00H
|
||||
RR1 EQU 01H
|
||||
RR2 EQU 02H
|
||||
RR3 EQU 03H
|
||||
RR6 EQU 06H
|
||||
RR7 EQU 07H
|
||||
RR10 EQU 0AH
|
||||
RR12 EQU 0CH
|
||||
RR13 EQU 0DH
|
||||
RR15 EQU 0FH
|
||||
|
||||
WR0 EQU 00H
|
||||
WR1 EQU 01H
|
||||
WR2 EQU 02H
|
||||
WR3 EQU 03H
|
||||
WR4 EQU 04H
|
||||
WR5 EQU 05H
|
||||
WR6 EQU 06H
|
||||
WR7 EQU 07H
|
||||
WR9 EQU 09H
|
||||
WR10 EQU 0AH
|
||||
WR11 EQU 0BH
|
||||
WR12 EQU 0CH
|
||||
WR13 EQU 0DH
|
||||
WR14 EQU 0EH
|
||||
WR15 EQU 0FH
|
||||
|
||||
; FDC37C665/6 Parallel Port in Standard AT Mode
|
||||
|
||||
DPORT EQU 8CH ; Data Port
|
||||
SPORT EQU 8DH ; Status Port
|
||||
CPORT EQU 8EH ; Control Port
|
||||
|
||||
; FDC37C665/6 Configuration Control (access internal registers)
|
||||
|
||||
CFCNTL EQU 90H ; Configuration control port
|
||||
CFDATA EQU 91H ; Configuration data port
|
||||
|
||||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
|
||||
|
||||
DCR EQU 92H ; Drive Control Register (Digital Output)
|
||||
MSR EQU 94H ; Main Status Register
|
||||
DR EQU 95H ; Data/Command Register
|
||||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
|
||||
|
||||
_DMA EQU 0A0H ; Diskette DMA Address
|
||||
|
||||
; FDC37C665/6 Serial Port (National 16550 compatible)
|
||||
|
||||
_RBR EQU 68H ;R Receiver Buffer
|
||||
_THR EQU 68H ;W Transmit Holding Reg
|
||||
_IER EQU 69H ;RW Interrupt-Enable Reg
|
||||
_IIR EQU 6AH ;R Interrupt Ident. Reg
|
||||
_FCR EQU 6AH ;W FIFO Control Reg
|
||||
_LCR EQU 6BH ;RW Line Control Reg
|
||||
_MCR EQU 6CH ;RW Modem Control Reg
|
||||
_LSR EQU 6DH ;RW Line Status Reg
|
||||
_MMSR EQU 6EH ;RW Modem Status Reg
|
||||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
|
||||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
|
||||
_DLM EQU 69H ;RW Divisor MSB | set High
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
|
||||
|
||||
IF HARDDSK
|
||||
NCR EQU 40H ; Base of NCR 5380
|
||||
|
||||
; 5380 Chip Registers
|
||||
|
||||
NCRDAT EQU NCR ; Current SCSI Data (Read)
|
||||
; Output Data Register (Write)
|
||||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
|
||||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
|
||||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
|
||||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
|
||||
NCRST EQU NCR+5 ; Bus & Status Register (Read)
|
||||
; Start DMA Send (Write)
|
||||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
|
||||
; Start DMA Initiator Receive (Write)
|
||||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
|
||||
|
||||
; Bit Assignments for NCR 5380 Ports as indicated
|
||||
|
||||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
|
||||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
|
||||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
|
||||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
|
||||
|
||||
B_BSY EQU 01000000B ; *Busy (NCRBUS)
|
||||
B_REQ EQU 00100000B ; *Request (NCRBUS)
|
||||
B_MSG EQU 00010000B ; *Message (NCRBUS)
|
||||
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
|
||||
B_IO EQU 00000100B ; *I/O (NCRBUS)
|
||||
B_SEL EQU 00000010B ; *Select (NCRBUS)
|
||||
|
||||
B_PHAS EQU 00001000B ; Phase Match (NCRST)
|
||||
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
|
||||
|
||||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
|
||||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
|
||||
ENDIF ;harddsk
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
|
||||
; Set the base GIDE equate to the jumper setting on the GIDE board.
|
||||
|
||||
IF IDE
|
||||
GIDE EQU 50H ; Set base of 16 byte address range
|
||||
|
||||
IDEDOR EQU GIDE+6 ; Digital Output Register
|
||||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
|
||||
IDEErr EQU GIDE+9 ; IDE Error Register
|
||||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
|
||||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
|
||||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
|
||||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
|
||||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
|
||||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
|
||||
|
||||
CMDHOM EQU 10H ; Home Drive Heads
|
||||
CMDRD EQU 20H ; Read Sector Command (w/retry)
|
||||
CMDWR EQU 30H ; Write Sector Command (w/retry)
|
||||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
|
||||
CMDFMT EQU 50H ; Format Track Command
|
||||
CMDDIAG EQU 90H ; Execute Diagnostics Command
|
||||
CMDINIT EQU 91H ; Initialize Drive Params Command
|
||||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
|
||||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
|
||||
CMDPWQ EQU 0E5H ; Power Status Query Command
|
||||
CMDID EQU 0ECH ; Read Drive Ident Data Command
|
||||
ENDIF ;ide
|
||||
;=================== End Unique Equates =======================
|
||||
|
||||
373
Source/BPBIOS/def-ww-z33nbnk.lib
Normal file
373
Source/BPBIOS/def-ww-z33nbnk.lib
Normal file
@@ -0,0 +1,373 @@
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
|
||||
; B/P BIOS Configuration and Equate File. ** System Dependant **
|
||||
; - D-X Designs Pty Ltd P112 CPU Board - **********************
|
||||
; Tailor your system here.
|
||||
;
|
||||
; 30 Aug 01 - Cleaned up for GPL release. HFB
|
||||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
|
||||
; 5 Jan 97 - Reformatted to Standard. HFB
|
||||
; 10 Jun 96 - Initial Test Release. HFB
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
|
||||
; BIOS Configuration Equates and Macros
|
||||
|
||||
DATE MACRO
|
||||
DEFB '17 Jan 14' ; Date of this version
|
||||
ENDM
|
||||
|
||||
AUTOCL MACRO
|
||||
DEFB 8,'ZEX Z33 ',0 ; Autostart command line
|
||||
ENDM
|
||||
|
||||
;--- Basic System and Z-System Section ---
|
||||
|
||||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
|
||||
IF MOVCPM
|
||||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
|
||||
ELSE
|
||||
VERS EQU 21H ; Version number w/Device Swapping permitted
|
||||
ENDIF
|
||||
BANKED EQU YES ; Is this a banked BIOS?
|
||||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
|
||||
INROM EQU NO ; Alternate bank in ROM?
|
||||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU YES ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU NO ; Set for Segment Configuration T
|
||||
CONF_N EQU YES ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
|
||||
; No = Include Common RAM transfer buffer
|
||||
|
||||
;--- Character Device Section ---
|
||||
|
||||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
|
||||
; NO = Only use the 4 defined Char Devices
|
||||
ESCC_B EQU no ; Include ESCC Channel B Driver?
|
||||
; The following two devices result in non-standard data rates
|
||||
; with the standard 16.00 MHz crystal in the P112. If a more
|
||||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc)
|
||||
; is used, the ports become usable.
|
||||
; Driver code for ASCI0 and ASCI1 includes an option for
|
||||
; assembling Polled or Interrupt-driven buffered input.
|
||||
; Select the desired option for ASCI0 with the BUFFA0 flag,
|
||||
; and BUFFA1 for ASCI1.
|
||||
ASCI_0 EQU false ; Include ASCI0 Driver?
|
||||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver?
|
||||
ASCI_1 EQU false ; Include ASCI1 Driver?
|
||||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver?
|
||||
|
||||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
|
||||
; ..must be 2^n with n<8
|
||||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
|
||||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
|
||||
|
||||
;--- Clock and Time Section ---
|
||||
|
||||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
|
||||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC?
|
||||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No)
|
||||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count)
|
||||
|
||||
;--- Floppy Diskette Section ---
|
||||
|
||||
BIOERM EQU yes ; Print BIOS error messages?
|
||||
CALCSK EQU YES ; Calculate skew table?
|
||||
AUTOSL EQU YES ; Auto select floppy formats?
|
||||
; If AUTOSL=True, the next two are active...
|
||||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
|
||||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
|
||||
FLOPY8 EQU no ; Include 8" Floppy Formats?
|
||||
MORDPB EQU NO ; Include additional Floppy DPB Formats?
|
||||
|
||||
;--- RAM Disk Section ---
|
||||
|
||||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
|
||||
|
||||
;--- Hard Disk Section ---
|
||||
|
||||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
|
||||
; (Pick 1 of 3 options below)
|
||||
SCSI EQU NO ; YES = Use SCSI Driver
|
||||
IDE EQU NO ; YES = Use IDE Driver
|
||||
HDSK EQU YES ; YES = Use SIMH HDSK Driver
|
||||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
|
||||
; (DMA not implemented for GIDE)
|
||||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
|
||||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
|
||||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
|
||||
|
||||
;--- Logical Drive Section ---
|
||||
|
||||
DRV_A EQU no ; Set each of these equates for the drive and
|
||||
DRV_B EQU no ; partition complement of your system. Assume
|
||||
DRV_C EQU no ; that A-D are Floppies.
|
||||
DRV_D EQU no
|
||||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk
|
||||
DRV_F EQU yes ; Partitions
|
||||
DRV_G EQU yes
|
||||
DRV_H EQU yes
|
||||
DRV_I EQU yes
|
||||
DRV_J EQU yes
|
||||
DRV_K EQU yes
|
||||
DRV_L EQU yes
|
||||
DRV_M EQU RAMDSK ; This is Yes for RAM drive
|
||||
DRV_N EQU yes
|
||||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled
|
||||
DRV_P EQU no
|
||||
|
||||
;========== Configuration Unique Equates (P112) ===========
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
|
||||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
|
||||
; systems with dynamic RAMs.
|
||||
NOWAIT EQU NO ; Set to NO to use configured Wait States in
|
||||
; Hard Disk Driver. Yes to eliminate Waits.
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
|
||||
; memory in 32k increments. In P112, the ROM occupies the first 32k
|
||||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper
|
||||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
|
||||
|
||||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
|
||||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
|
||||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
|
||||
BNKU EQU 00H ; User Area Bank 58000H
|
||||
; (set to 0 to disable)
|
||||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
|
||||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
|
||||
; With both on-board RAMs only (MEM1 or MEM2),
|
||||
; the maximum Bank number is 11 (0BH).
|
||||
|
||||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
|
||||
|
||||
CNTLA0 EQU 00H ; Control Port ASCI 0
|
||||
CNTLA1 EQU 01H ; Control Port ASCI 1
|
||||
STAT0 EQU 04H ; Serial port 0 Status
|
||||
STAT1 EQU 05H ; Serial port 1 Status
|
||||
TDR0 EQU 06H ; Serial port 0 Output Data
|
||||
TDR1 EQU 07H ; Serial port 1 Output Data
|
||||
RDR0 EQU 08H ; Serial port 0 Input Data
|
||||
RDR1 EQU 09H ; Serial Port 1 Input Data
|
||||
CNTR EQU 0AH ; HD64180 Counter port
|
||||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
|
||||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
|
||||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
|
||||
RLDR0H EQU 0FH ; CTC0 Reload Count, High
|
||||
TCR EQU 10H ; Interrupt Control Register
|
||||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
|
||||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
|
||||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
|
||||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
|
||||
FRC EQU 18H ; Free-Running Counter
|
||||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
|
||||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
|
||||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
|
||||
DSTAT EQU 30H ; DMA Status/Control port
|
||||
DMODE EQU 31H ; DMA Mode Control port
|
||||
DCNTL EQU 32H ; DMA/WAIT Control Register
|
||||
IL EQU 33H ; Interrupt Segment Register
|
||||
ITC EQU 34H ; Interrupt/Trap Control Register
|
||||
RCR EQU 36H ; HD64180 Refresh Control register
|
||||
CBR EQU 38H ; MMU Common Base Register
|
||||
BBR EQU 39H ; MMU Bank Base Register
|
||||
CBAR EQU 3AH ; MMU Common/Bank Area Register
|
||||
OMCR EQU 3EH ; Operation Mode Control Reg
|
||||
ICR EQU 3FH ; I/O Control Register
|
||||
|
||||
; Some bit definitions used with the Z-180 on-chip peripherals:
|
||||
|
||||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
|
||||
RDRF EQU 80H ; ACSI Received Character available
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Extended Features of Z80182 for P112
|
||||
|
||||
WSGCS EQU 0D8H ; Wait-State Generator CS
|
||||
ENH182 EQU 0D9H ; Z80182 Enhancements Register
|
||||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
|
||||
RAMUBR EQU 0E6H ; RAM End Boundary
|
||||
RAMLBR EQU 0E7H ; RAM Start Boundary
|
||||
ROMBR EQU 0E8H ; ROM Boundary
|
||||
FIFOCTL EQU 0E9H ; FIFO Control Register
|
||||
RTOTC EQU 0EAH ; RX Time-Out Time Constant
|
||||
TTOTC EQU 0EBH ; TX Time-Out Time Constant
|
||||
FCR EQU 0ECH ; FIFO Register
|
||||
SCR EQU 0EFH ; System Pin Control
|
||||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
|
||||
THR EQU 0F0H ; MIMIN TX Holding Register (W)
|
||||
IER EQU 0F1H ; Interrupt Enable Register
|
||||
LCR EQU 0F3H ; Line Control Register
|
||||
MCR EQU 0F4H ; Modem Control Register
|
||||
LSR EQU 0F5H ; Line Status Register
|
||||
MDMSR EQU 0F6H ; Modem Status Register
|
||||
MSCR EQU 0F7H ; MIMIC Scratch Register
|
||||
DLATL EQU 0F8H ; Divisor Latch (Low)
|
||||
DLATM EQU 0F9H ; Divisor Latch (High)
|
||||
TTCR EQU 0FAH ; TX Time Constant
|
||||
RTCR EQU 0FBH ; RX Time Constant
|
||||
IVEC EQU 0FCH ; MIMIC Interrupt Vector
|
||||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
|
||||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
|
||||
MMCR EQU 0FFH ; MIMIC Master Control Register
|
||||
|
||||
; Z80182 PIO Registers
|
||||
|
||||
DDRA EQU 0EDH ; Data Direction Register A
|
||||
DRA EQU 0EEH ; Port A Data
|
||||
DDRB EQU 0E4H ; Data Direction Register B
|
||||
DRB EQU 0E5H ; Data B Data
|
||||
DDRC EQU 0DDH ; Data Direction Register C
|
||||
DRC EQU 0DEH ; Data C Data
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; ESCC Registers on Z80182
|
||||
|
||||
SCCACNT EQU 0E0H ; ESCC Control Channel A
|
||||
SCCAD EQU 0E1H ; ESCC Data Channel A
|
||||
SCCBCNT EQU 0E2H ; ESCC Control Channel B
|
||||
SCCBD EQU 0E3H ; ESCC Data Channel B
|
||||
|
||||
; [E]SCC Internal Register Definitions
|
||||
|
||||
RR0 EQU 00H
|
||||
RR1 EQU 01H
|
||||
RR2 EQU 02H
|
||||
RR3 EQU 03H
|
||||
RR6 EQU 06H
|
||||
RR7 EQU 07H
|
||||
RR10 EQU 0AH
|
||||
RR12 EQU 0CH
|
||||
RR13 EQU 0DH
|
||||
RR15 EQU 0FH
|
||||
|
||||
WR0 EQU 00H
|
||||
WR1 EQU 01H
|
||||
WR2 EQU 02H
|
||||
WR3 EQU 03H
|
||||
WR4 EQU 04H
|
||||
WR5 EQU 05H
|
||||
WR6 EQU 06H
|
||||
WR7 EQU 07H
|
||||
WR9 EQU 09H
|
||||
WR10 EQU 0AH
|
||||
WR11 EQU 0BH
|
||||
WR12 EQU 0CH
|
||||
WR13 EQU 0DH
|
||||
WR14 EQU 0EH
|
||||
WR15 EQU 0FH
|
||||
|
||||
; FDC37C665/6 Parallel Port in Standard AT Mode
|
||||
|
||||
DPORT EQU 8CH ; Data Port
|
||||
SPORT EQU 8DH ; Status Port
|
||||
CPORT EQU 8EH ; Control Port
|
||||
|
||||
; FDC37C665/6 Configuration Control (access internal registers)
|
||||
|
||||
CFCNTL EQU 90H ; Configuration control port
|
||||
CFDATA EQU 91H ; Configuration data port
|
||||
|
||||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
|
||||
|
||||
DCR EQU 92H ; Drive Control Register (Digital Output)
|
||||
MSR EQU 94H ; Main Status Register
|
||||
DR EQU 95H ; Data/Command Register
|
||||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
|
||||
|
||||
_DMA EQU 0A0H ; Diskette DMA Address
|
||||
|
||||
; FDC37C665/6 Serial Port (National 16550 compatible)
|
||||
|
||||
_RBR EQU 68H ;R Receiver Buffer
|
||||
_THR EQU 68H ;W Transmit Holding Reg
|
||||
_IER EQU 69H ;RW Interrupt-Enable Reg
|
||||
_IIR EQU 6AH ;R Interrupt Ident. Reg
|
||||
_FCR EQU 6AH ;W FIFO Control Reg
|
||||
_LCR EQU 6BH ;RW Line Control Reg
|
||||
_MCR EQU 6CH ;RW Modem Control Reg
|
||||
_LSR EQU 6DH ;RW Line Status Reg
|
||||
_MMSR EQU 6EH ;RW Modem Status Reg
|
||||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
|
||||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
|
||||
_DLM EQU 69H ;RW Divisor MSB | set High
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
|
||||
|
||||
IF HARDDSK
|
||||
NCR EQU 40H ; Base of NCR 5380
|
||||
|
||||
; 5380 Chip Registers
|
||||
|
||||
NCRDAT EQU NCR ; Current SCSI Data (Read)
|
||||
; Output Data Register (Write)
|
||||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
|
||||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
|
||||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
|
||||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
|
||||
NCRST EQU NCR+5 ; Bus & Status Register (Read)
|
||||
; Start DMA Send (Write)
|
||||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
|
||||
; Start DMA Initiator Receive (Write)
|
||||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
|
||||
|
||||
; Bit Assignments for NCR 5380 Ports as indicated
|
||||
|
||||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
|
||||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
|
||||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
|
||||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
|
||||
|
||||
B_BSY EQU 01000000B ; *Busy (NCRBUS)
|
||||
B_REQ EQU 00100000B ; *Request (NCRBUS)
|
||||
B_MSG EQU 00010000B ; *Message (NCRBUS)
|
||||
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
|
||||
B_IO EQU 00000100B ; *I/O (NCRBUS)
|
||||
B_SEL EQU 00000010B ; *Select (NCRBUS)
|
||||
|
||||
B_PHAS EQU 00001000B ; Phase Match (NCRST)
|
||||
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
|
||||
|
||||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
|
||||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
|
||||
ENDIF ;harddsk
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
|
||||
; Set the base GIDE equate to the jumper setting on the GIDE board.
|
||||
|
||||
IF IDE
|
||||
GIDE EQU 50H ; Set base of 16 byte address range
|
||||
|
||||
IDEDOR EQU GIDE+6 ; Digital Output Register
|
||||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
|
||||
IDEErr EQU GIDE+9 ; IDE Error Register
|
||||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
|
||||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
|
||||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
|
||||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
|
||||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
|
||||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
|
||||
|
||||
CMDHOM EQU 10H ; Home Drive Heads
|
||||
CMDRD EQU 20H ; Read Sector Command (w/retry)
|
||||
CMDWR EQU 30H ; Write Sector Command (w/retry)
|
||||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
|
||||
CMDFMT EQU 50H ; Format Track Command
|
||||
CMDDIAG EQU 90H ; Execute Diagnostics Command
|
||||
CMDINIT EQU 91H ; Initialize Drive Params Command
|
||||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
|
||||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
|
||||
CMDPWQ EQU 0E5H ; Power Status Query Command
|
||||
CMDID EQU 0ECH ; Read Drive Ident Data Command
|
||||
ENDIF ;ide
|
||||
;=================== End Unique Equates =======================
|
||||
|
||||
@@ -34,6 +34,9 @@ FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU NO ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU YES ; Set for Segment Configuration T
|
||||
CONF_N EQU NO ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
@@ -33,7 +33,10 @@ MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU no ; Include IOP code into Jump table?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU NO ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU YES ; Set for Segment Configuration T
|
||||
CONF_N EQU NO ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
373
Source/BPBIOS/def-ww-z34n.lib
Normal file
373
Source/BPBIOS/def-ww-z34n.lib
Normal file
@@ -0,0 +1,373 @@
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
|
||||
; B/P BIOS Configuration and Equate File. ** System Dependant **
|
||||
; - D-X Designs Pty Ltd P112 CPU Board - **********************
|
||||
; Tailor your system here.
|
||||
;
|
||||
; 30 Aug 01 - Cleaned up for GPL release. HFB
|
||||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
|
||||
; 5 Jan 97 - Reformatted to Standard. HFB
|
||||
; 10 Jun 96 - Initial Test Release. HFB
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
|
||||
; BIOS Configuration Equates and Macros
|
||||
|
||||
DATE MACRO
|
||||
DEFB '17 Jan 14' ; Date of this version
|
||||
ENDM
|
||||
|
||||
AUTOCL MACRO
|
||||
DEFB 8,'ZEX Z34 ',0 ; Autostart command line
|
||||
ENDM
|
||||
|
||||
;--- Basic System and Z-System Section ---
|
||||
|
||||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
|
||||
IF MOVCPM
|
||||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
|
||||
ELSE
|
||||
VERS EQU 21H ; Version number w/Device Swapping permitted
|
||||
ENDIF
|
||||
BANKED EQU NO ; Is this a banked BIOS?
|
||||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
|
||||
INROM EQU NO ; Alternate bank in ROM?
|
||||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU YES ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU NO ; Set for Segment Configuration T
|
||||
CONF_N EQU YES ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
|
||||
; No = Include Common RAM transfer buffer
|
||||
|
||||
;--- Character Device Section ---
|
||||
|
||||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
|
||||
; NO = Only use the 4 defined Char Devices
|
||||
ESCC_B EQU no ; Include ESCC Channel B Driver?
|
||||
; The following two devices result in non-standard data rates
|
||||
; with the standard 16.00 MHz crystal in the P112. If a more
|
||||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc)
|
||||
; is used, the ports become usable.
|
||||
; Driver code for ASCI0 and ASCI1 includes an option for
|
||||
; assembling Polled or Interrupt-driven buffered input.
|
||||
; Select the desired option for ASCI0 with the BUFFA0 flag,
|
||||
; and BUFFA1 for ASCI1.
|
||||
ASCI_0 EQU false ; Include ASCI0 Driver?
|
||||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver?
|
||||
ASCI_1 EQU false ; Include ASCI1 Driver?
|
||||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver?
|
||||
|
||||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
|
||||
; ..must be 2^n with n<8
|
||||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
|
||||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
|
||||
|
||||
;--- Clock and Time Section ---
|
||||
|
||||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
|
||||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC?
|
||||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No)
|
||||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count)
|
||||
|
||||
;--- Floppy Diskette Section ---
|
||||
|
||||
BIOERM EQU yes ; Print BIOS error messages?
|
||||
CALCSK EQU YES ; Calculate skew table?
|
||||
AUTOSL EQU YES ; Auto select floppy formats?
|
||||
; If AUTOSL=True, the next two are active...
|
||||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
|
||||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
|
||||
FLOPY8 EQU no ; Include 8" Floppy Formats?
|
||||
MORDPB EQU NO ; Include additional Floppy DPB Formats?
|
||||
|
||||
;--- RAM Disk Section ---
|
||||
|
||||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
|
||||
|
||||
;--- Hard Disk Section ---
|
||||
|
||||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
|
||||
; (Pick 1 of 3 options below)
|
||||
SCSI EQU NO ; YES = Use SCSI Driver
|
||||
IDE EQU NO ; YES = Use IDE Driver
|
||||
HDSK EQU YES ; YES = Use SIMH HDSK Driver
|
||||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
|
||||
; (DMA not implemented for GIDE)
|
||||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
|
||||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
|
||||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
|
||||
|
||||
;--- Logical Drive Section ---
|
||||
|
||||
DRV_A EQU no ; Set each of these equates for the drive and
|
||||
DRV_B EQU no ; partition complement of your system. Assume
|
||||
DRV_C EQU no ; that A-D are Floppies.
|
||||
DRV_D EQU no
|
||||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk
|
||||
DRV_F EQU yes ; Partitions
|
||||
DRV_G EQU yes
|
||||
DRV_H EQU yes
|
||||
DRV_I EQU yes
|
||||
DRV_J EQU yes
|
||||
DRV_K EQU yes
|
||||
DRV_L EQU yes
|
||||
DRV_M EQU RAMDSK ; This is Yes for RAM drive
|
||||
DRV_N EQU yes
|
||||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled
|
||||
DRV_P EQU no
|
||||
|
||||
;========== Configuration Unique Equates (P112) ===========
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
|
||||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
|
||||
; systems with dynamic RAMs.
|
||||
NOWAIT EQU NO ; Set to NO to use configured Wait States in
|
||||
; Hard Disk Driver. Yes to eliminate Waits.
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
|
||||
; memory in 32k increments. In P112, the ROM occupies the first 32k
|
||||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper
|
||||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
|
||||
|
||||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
|
||||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
|
||||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
|
||||
BNKU EQU 00H ; User Area Bank 58000H
|
||||
; (set to 0 to disable)
|
||||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
|
||||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
|
||||
; With both on-board RAMs only (MEM1 or MEM2),
|
||||
; the maximum Bank number is 11 (0BH).
|
||||
|
||||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
|
||||
|
||||
CNTLA0 EQU 00H ; Control Port ASCI 0
|
||||
CNTLA1 EQU 01H ; Control Port ASCI 1
|
||||
STAT0 EQU 04H ; Serial port 0 Status
|
||||
STAT1 EQU 05H ; Serial port 1 Status
|
||||
TDR0 EQU 06H ; Serial port 0 Output Data
|
||||
TDR1 EQU 07H ; Serial port 1 Output Data
|
||||
RDR0 EQU 08H ; Serial port 0 Input Data
|
||||
RDR1 EQU 09H ; Serial Port 1 Input Data
|
||||
CNTR EQU 0AH ; HD64180 Counter port
|
||||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
|
||||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
|
||||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
|
||||
RLDR0H EQU 0FH ; CTC0 Reload Count, High
|
||||
TCR EQU 10H ; Interrupt Control Register
|
||||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
|
||||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
|
||||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
|
||||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
|
||||
FRC EQU 18H ; Free-Running Counter
|
||||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
|
||||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
|
||||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
|
||||
DSTAT EQU 30H ; DMA Status/Control port
|
||||
DMODE EQU 31H ; DMA Mode Control port
|
||||
DCNTL EQU 32H ; DMA/WAIT Control Register
|
||||
IL EQU 33H ; Interrupt Segment Register
|
||||
ITC EQU 34H ; Interrupt/Trap Control Register
|
||||
RCR EQU 36H ; HD64180 Refresh Control register
|
||||
CBR EQU 38H ; MMU Common Base Register
|
||||
BBR EQU 39H ; MMU Bank Base Register
|
||||
CBAR EQU 3AH ; MMU Common/Bank Area Register
|
||||
OMCR EQU 3EH ; Operation Mode Control Reg
|
||||
ICR EQU 3FH ; I/O Control Register
|
||||
|
||||
; Some bit definitions used with the Z-180 on-chip peripherals:
|
||||
|
||||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
|
||||
RDRF EQU 80H ; ACSI Received Character available
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Extended Features of Z80182 for P112
|
||||
|
||||
WSGCS EQU 0D8H ; Wait-State Generator CS
|
||||
ENH182 EQU 0D9H ; Z80182 Enhancements Register
|
||||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
|
||||
RAMUBR EQU 0E6H ; RAM End Boundary
|
||||
RAMLBR EQU 0E7H ; RAM Start Boundary
|
||||
ROMBR EQU 0E8H ; ROM Boundary
|
||||
FIFOCTL EQU 0E9H ; FIFO Control Register
|
||||
RTOTC EQU 0EAH ; RX Time-Out Time Constant
|
||||
TTOTC EQU 0EBH ; TX Time-Out Time Constant
|
||||
FCR EQU 0ECH ; FIFO Register
|
||||
SCR EQU 0EFH ; System Pin Control
|
||||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
|
||||
THR EQU 0F0H ; MIMIN TX Holding Register (W)
|
||||
IER EQU 0F1H ; Interrupt Enable Register
|
||||
LCR EQU 0F3H ; Line Control Register
|
||||
MCR EQU 0F4H ; Modem Control Register
|
||||
LSR EQU 0F5H ; Line Status Register
|
||||
MDMSR EQU 0F6H ; Modem Status Register
|
||||
MSCR EQU 0F7H ; MIMIC Scratch Register
|
||||
DLATL EQU 0F8H ; Divisor Latch (Low)
|
||||
DLATM EQU 0F9H ; Divisor Latch (High)
|
||||
TTCR EQU 0FAH ; TX Time Constant
|
||||
RTCR EQU 0FBH ; RX Time Constant
|
||||
IVEC EQU 0FCH ; MIMIC Interrupt Vector
|
||||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
|
||||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
|
||||
MMCR EQU 0FFH ; MIMIC Master Control Register
|
||||
|
||||
; Z80182 PIO Registers
|
||||
|
||||
DDRA EQU 0EDH ; Data Direction Register A
|
||||
DRA EQU 0EEH ; Port A Data
|
||||
DDRB EQU 0E4H ; Data Direction Register B
|
||||
DRB EQU 0E5H ; Data B Data
|
||||
DDRC EQU 0DDH ; Data Direction Register C
|
||||
DRC EQU 0DEH ; Data C Data
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; ESCC Registers on Z80182
|
||||
|
||||
SCCACNT EQU 0E0H ; ESCC Control Channel A
|
||||
SCCAD EQU 0E1H ; ESCC Data Channel A
|
||||
SCCBCNT EQU 0E2H ; ESCC Control Channel B
|
||||
SCCBD EQU 0E3H ; ESCC Data Channel B
|
||||
|
||||
; [E]SCC Internal Register Definitions
|
||||
|
||||
RR0 EQU 00H
|
||||
RR1 EQU 01H
|
||||
RR2 EQU 02H
|
||||
RR3 EQU 03H
|
||||
RR6 EQU 06H
|
||||
RR7 EQU 07H
|
||||
RR10 EQU 0AH
|
||||
RR12 EQU 0CH
|
||||
RR13 EQU 0DH
|
||||
RR15 EQU 0FH
|
||||
|
||||
WR0 EQU 00H
|
||||
WR1 EQU 01H
|
||||
WR2 EQU 02H
|
||||
WR3 EQU 03H
|
||||
WR4 EQU 04H
|
||||
WR5 EQU 05H
|
||||
WR6 EQU 06H
|
||||
WR7 EQU 07H
|
||||
WR9 EQU 09H
|
||||
WR10 EQU 0AH
|
||||
WR11 EQU 0BH
|
||||
WR12 EQU 0CH
|
||||
WR13 EQU 0DH
|
||||
WR14 EQU 0EH
|
||||
WR15 EQU 0FH
|
||||
|
||||
; FDC37C665/6 Parallel Port in Standard AT Mode
|
||||
|
||||
DPORT EQU 8CH ; Data Port
|
||||
SPORT EQU 8DH ; Status Port
|
||||
CPORT EQU 8EH ; Control Port
|
||||
|
||||
; FDC37C665/6 Configuration Control (access internal registers)
|
||||
|
||||
CFCNTL EQU 90H ; Configuration control port
|
||||
CFDATA EQU 91H ; Configuration data port
|
||||
|
||||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
|
||||
|
||||
DCR EQU 92H ; Drive Control Register (Digital Output)
|
||||
MSR EQU 94H ; Main Status Register
|
||||
DR EQU 95H ; Data/Command Register
|
||||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
|
||||
|
||||
_DMA EQU 0A0H ; Diskette DMA Address
|
||||
|
||||
; FDC37C665/6 Serial Port (National 16550 compatible)
|
||||
|
||||
_RBR EQU 68H ;R Receiver Buffer
|
||||
_THR EQU 68H ;W Transmit Holding Reg
|
||||
_IER EQU 69H ;RW Interrupt-Enable Reg
|
||||
_IIR EQU 6AH ;R Interrupt Ident. Reg
|
||||
_FCR EQU 6AH ;W FIFO Control Reg
|
||||
_LCR EQU 6BH ;RW Line Control Reg
|
||||
_MCR EQU 6CH ;RW Modem Control Reg
|
||||
_LSR EQU 6DH ;RW Line Status Reg
|
||||
_MMSR EQU 6EH ;RW Modem Status Reg
|
||||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
|
||||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
|
||||
_DLM EQU 69H ;RW Divisor MSB | set High
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
|
||||
|
||||
IF HARDDSK
|
||||
NCR EQU 40H ; Base of NCR 5380
|
||||
|
||||
; 5380 Chip Registers
|
||||
|
||||
NCRDAT EQU NCR ; Current SCSI Data (Read)
|
||||
; Output Data Register (Write)
|
||||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
|
||||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
|
||||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
|
||||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
|
||||
NCRST EQU NCR+5 ; Bus & Status Register (Read)
|
||||
; Start DMA Send (Write)
|
||||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
|
||||
; Start DMA Initiator Receive (Write)
|
||||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
|
||||
|
||||
; Bit Assignments for NCR 5380 Ports as indicated
|
||||
|
||||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
|
||||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
|
||||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
|
||||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
|
||||
|
||||
B_BSY EQU 01000000B ; *Busy (NCRBUS)
|
||||
B_REQ EQU 00100000B ; *Request (NCRBUS)
|
||||
B_MSG EQU 00010000B ; *Message (NCRBUS)
|
||||
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
|
||||
B_IO EQU 00000100B ; *I/O (NCRBUS)
|
||||
B_SEL EQU 00000010B ; *Select (NCRBUS)
|
||||
|
||||
B_PHAS EQU 00001000B ; Phase Match (NCRST)
|
||||
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
|
||||
|
||||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
|
||||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
|
||||
ENDIF ;harddsk
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
|
||||
; Set the base GIDE equate to the jumper setting on the GIDE board.
|
||||
|
||||
IF IDE
|
||||
GIDE EQU 50H ; Set base of 16 byte address range
|
||||
|
||||
IDEDOR EQU GIDE+6 ; Digital Output Register
|
||||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
|
||||
IDEErr EQU GIDE+9 ; IDE Error Register
|
||||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
|
||||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
|
||||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
|
||||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
|
||||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
|
||||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
|
||||
|
||||
CMDHOM EQU 10H ; Home Drive Heads
|
||||
CMDRD EQU 20H ; Read Sector Command (w/retry)
|
||||
CMDWR EQU 30H ; Write Sector Command (w/retry)
|
||||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
|
||||
CMDFMT EQU 50H ; Format Track Command
|
||||
CMDDIAG EQU 90H ; Execute Diagnostics Command
|
||||
CMDINIT EQU 91H ; Initialize Drive Params Command
|
||||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
|
||||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
|
||||
CMDPWQ EQU 0E5H ; Power Status Query Command
|
||||
CMDID EQU 0ECH ; Read Drive Ident Data Command
|
||||
ENDIF ;ide
|
||||
;=================== End Unique Equates =======================
|
||||
|
||||
373
Source/BPBIOS/def-ww-z34nbnk.lib
Normal file
373
Source/BPBIOS/def-ww-z34nbnk.lib
Normal file
@@ -0,0 +1,373 @@
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
|
||||
; B/P BIOS Configuration and Equate File. ** System Dependant **
|
||||
; - D-X Designs Pty Ltd P112 CPU Board - **********************
|
||||
; Tailor your system here.
|
||||
;
|
||||
; 30 Aug 01 - Cleaned up for GPL release. HFB
|
||||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
|
||||
; 5 Jan 97 - Reformatted to Standard. HFB
|
||||
; 10 Jun 96 - Initial Test Release. HFB
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
|
||||
; BIOS Configuration Equates and Macros
|
||||
|
||||
DATE MACRO
|
||||
DEFB '17 Jan 14' ; Date of this version
|
||||
ENDM
|
||||
|
||||
AUTOCL MACRO
|
||||
DEFB 8,'ZEX Z34 ',0 ; Autostart command line
|
||||
ENDM
|
||||
|
||||
;--- Basic System and Z-System Section ---
|
||||
|
||||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
|
||||
IF MOVCPM
|
||||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
|
||||
ELSE
|
||||
VERS EQU 21H ; Version number w/Device Swapping permitted
|
||||
ENDIF
|
||||
BANKED EQU YES ; Is this a banked BIOS?
|
||||
ZSDOS2 EQU NO ; Yes = Banked Dos, No = CP/M 2.2 Compatible
|
||||
INROM EQU NO ; Alternate bank in ROM?
|
||||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU YES ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU NO ; Set for Segment Configuration T
|
||||
CONF_N EQU YES ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
|
||||
; No = Include Common RAM transfer buffer
|
||||
|
||||
;--- Character Device Section ---
|
||||
|
||||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
|
||||
; NO = Only use the 4 defined Char Devices
|
||||
ESCC_B EQU no ; Include ESCC Channel B Driver?
|
||||
; The following two devices result in non-standard data rates
|
||||
; with the standard 16.00 MHz crystal in the P112. If a more
|
||||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc)
|
||||
; is used, the ports become usable.
|
||||
; Driver code for ASCI0 and ASCI1 includes an option for
|
||||
; assembling Polled or Interrupt-driven buffered input.
|
||||
; Select the desired option for ASCI0 with the BUFFA0 flag,
|
||||
; and BUFFA1 for ASCI1.
|
||||
ASCI_0 EQU false ; Include ASCI0 Driver?
|
||||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver?
|
||||
ASCI_1 EQU false ; Include ASCI1 Driver?
|
||||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver?
|
||||
|
||||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
|
||||
; ..must be 2^n with n<8
|
||||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
|
||||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
|
||||
|
||||
;--- Clock and Time Section ---
|
||||
|
||||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
|
||||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC?
|
||||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No)
|
||||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count)
|
||||
|
||||
;--- Floppy Diskette Section ---
|
||||
|
||||
BIOERM EQU yes ; Print BIOS error messages?
|
||||
CALCSK EQU YES ; Calculate skew table?
|
||||
AUTOSL EQU YES ; Auto select floppy formats?
|
||||
; If AUTOSL=True, the next two are active...
|
||||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
|
||||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
|
||||
FLOPY8 EQU no ; Include 8" Floppy Formats?
|
||||
MORDPB EQU NO ; Include additional Floppy DPB Formats?
|
||||
|
||||
;--- RAM Disk Section ---
|
||||
|
||||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
|
||||
|
||||
;--- Hard Disk Section ---
|
||||
|
||||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
|
||||
; (Pick 1 of 3 options below)
|
||||
SCSI EQU NO ; YES = Use SCSI Driver
|
||||
IDE EQU NO ; YES = Use IDE Driver
|
||||
HDSK EQU YES ; YES = Use SIMH HDSK Driver
|
||||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
|
||||
; (DMA not implemented for GIDE)
|
||||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
|
||||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
|
||||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
|
||||
|
||||
;--- Logical Drive Section ---
|
||||
|
||||
DRV_A EQU no ; Set each of these equates for the drive and
|
||||
DRV_B EQU no ; partition complement of your system. Assume
|
||||
DRV_C EQU no ; that A-D are Floppies.
|
||||
DRV_D EQU no
|
||||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk
|
||||
DRV_F EQU yes ; Partitions
|
||||
DRV_G EQU yes
|
||||
DRV_H EQU yes
|
||||
DRV_I EQU yes
|
||||
DRV_J EQU yes
|
||||
DRV_K EQU yes
|
||||
DRV_L EQU yes
|
||||
DRV_M EQU RAMDSK ; This is Yes for RAM drive
|
||||
DRV_N EQU yes
|
||||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled
|
||||
DRV_P EQU no
|
||||
|
||||
;========== Configuration Unique Equates (P112) ===========
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
|
||||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
|
||||
; systems with dynamic RAMs.
|
||||
NOWAIT EQU NO ; Set to NO to use configured Wait States in
|
||||
; Hard Disk Driver. Yes to eliminate Waits.
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
|
||||
; memory in 32k increments. In P112, the ROM occupies the first 32k
|
||||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper
|
||||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
|
||||
|
||||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
|
||||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
|
||||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
|
||||
BNKU EQU 00H ; User Area Bank 58000H
|
||||
; (set to 0 to disable)
|
||||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
|
||||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
|
||||
; With both on-board RAMs only (MEM1 or MEM2),
|
||||
; the maximum Bank number is 11 (0BH).
|
||||
|
||||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
|
||||
|
||||
CNTLA0 EQU 00H ; Control Port ASCI 0
|
||||
CNTLA1 EQU 01H ; Control Port ASCI 1
|
||||
STAT0 EQU 04H ; Serial port 0 Status
|
||||
STAT1 EQU 05H ; Serial port 1 Status
|
||||
TDR0 EQU 06H ; Serial port 0 Output Data
|
||||
TDR1 EQU 07H ; Serial port 1 Output Data
|
||||
RDR0 EQU 08H ; Serial port 0 Input Data
|
||||
RDR1 EQU 09H ; Serial Port 1 Input Data
|
||||
CNTR EQU 0AH ; HD64180 Counter port
|
||||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
|
||||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
|
||||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
|
||||
RLDR0H EQU 0FH ; CTC0 Reload Count, High
|
||||
TCR EQU 10H ; Interrupt Control Register
|
||||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
|
||||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
|
||||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
|
||||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
|
||||
FRC EQU 18H ; Free-Running Counter
|
||||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
|
||||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
|
||||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
|
||||
DSTAT EQU 30H ; DMA Status/Control port
|
||||
DMODE EQU 31H ; DMA Mode Control port
|
||||
DCNTL EQU 32H ; DMA/WAIT Control Register
|
||||
IL EQU 33H ; Interrupt Segment Register
|
||||
ITC EQU 34H ; Interrupt/Trap Control Register
|
||||
RCR EQU 36H ; HD64180 Refresh Control register
|
||||
CBR EQU 38H ; MMU Common Base Register
|
||||
BBR EQU 39H ; MMU Bank Base Register
|
||||
CBAR EQU 3AH ; MMU Common/Bank Area Register
|
||||
OMCR EQU 3EH ; Operation Mode Control Reg
|
||||
ICR EQU 3FH ; I/O Control Register
|
||||
|
||||
; Some bit definitions used with the Z-180 on-chip peripherals:
|
||||
|
||||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
|
||||
RDRF EQU 80H ; ACSI Received Character available
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Extended Features of Z80182 for P112
|
||||
|
||||
WSGCS EQU 0D8H ; Wait-State Generator CS
|
||||
ENH182 EQU 0D9H ; Z80182 Enhancements Register
|
||||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
|
||||
RAMUBR EQU 0E6H ; RAM End Boundary
|
||||
RAMLBR EQU 0E7H ; RAM Start Boundary
|
||||
ROMBR EQU 0E8H ; ROM Boundary
|
||||
FIFOCTL EQU 0E9H ; FIFO Control Register
|
||||
RTOTC EQU 0EAH ; RX Time-Out Time Constant
|
||||
TTOTC EQU 0EBH ; TX Time-Out Time Constant
|
||||
FCR EQU 0ECH ; FIFO Register
|
||||
SCR EQU 0EFH ; System Pin Control
|
||||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
|
||||
THR EQU 0F0H ; MIMIN TX Holding Register (W)
|
||||
IER EQU 0F1H ; Interrupt Enable Register
|
||||
LCR EQU 0F3H ; Line Control Register
|
||||
MCR EQU 0F4H ; Modem Control Register
|
||||
LSR EQU 0F5H ; Line Status Register
|
||||
MDMSR EQU 0F6H ; Modem Status Register
|
||||
MSCR EQU 0F7H ; MIMIC Scratch Register
|
||||
DLATL EQU 0F8H ; Divisor Latch (Low)
|
||||
DLATM EQU 0F9H ; Divisor Latch (High)
|
||||
TTCR EQU 0FAH ; TX Time Constant
|
||||
RTCR EQU 0FBH ; RX Time Constant
|
||||
IVEC EQU 0FCH ; MIMIC Interrupt Vector
|
||||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
|
||||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
|
||||
MMCR EQU 0FFH ; MIMIC Master Control Register
|
||||
|
||||
; Z80182 PIO Registers
|
||||
|
||||
DDRA EQU 0EDH ; Data Direction Register A
|
||||
DRA EQU 0EEH ; Port A Data
|
||||
DDRB EQU 0E4H ; Data Direction Register B
|
||||
DRB EQU 0E5H ; Data B Data
|
||||
DDRC EQU 0DDH ; Data Direction Register C
|
||||
DRC EQU 0DEH ; Data C Data
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; ESCC Registers on Z80182
|
||||
|
||||
SCCACNT EQU 0E0H ; ESCC Control Channel A
|
||||
SCCAD EQU 0E1H ; ESCC Data Channel A
|
||||
SCCBCNT EQU 0E2H ; ESCC Control Channel B
|
||||
SCCBD EQU 0E3H ; ESCC Data Channel B
|
||||
|
||||
; [E]SCC Internal Register Definitions
|
||||
|
||||
RR0 EQU 00H
|
||||
RR1 EQU 01H
|
||||
RR2 EQU 02H
|
||||
RR3 EQU 03H
|
||||
RR6 EQU 06H
|
||||
RR7 EQU 07H
|
||||
RR10 EQU 0AH
|
||||
RR12 EQU 0CH
|
||||
RR13 EQU 0DH
|
||||
RR15 EQU 0FH
|
||||
|
||||
WR0 EQU 00H
|
||||
WR1 EQU 01H
|
||||
WR2 EQU 02H
|
||||
WR3 EQU 03H
|
||||
WR4 EQU 04H
|
||||
WR5 EQU 05H
|
||||
WR6 EQU 06H
|
||||
WR7 EQU 07H
|
||||
WR9 EQU 09H
|
||||
WR10 EQU 0AH
|
||||
WR11 EQU 0BH
|
||||
WR12 EQU 0CH
|
||||
WR13 EQU 0DH
|
||||
WR14 EQU 0EH
|
||||
WR15 EQU 0FH
|
||||
|
||||
; FDC37C665/6 Parallel Port in Standard AT Mode
|
||||
|
||||
DPORT EQU 8CH ; Data Port
|
||||
SPORT EQU 8DH ; Status Port
|
||||
CPORT EQU 8EH ; Control Port
|
||||
|
||||
; FDC37C665/6 Configuration Control (access internal registers)
|
||||
|
||||
CFCNTL EQU 90H ; Configuration control port
|
||||
CFDATA EQU 91H ; Configuration data port
|
||||
|
||||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
|
||||
|
||||
DCR EQU 92H ; Drive Control Register (Digital Output)
|
||||
MSR EQU 94H ; Main Status Register
|
||||
DR EQU 95H ; Data/Command Register
|
||||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
|
||||
|
||||
_DMA EQU 0A0H ; Diskette DMA Address
|
||||
|
||||
; FDC37C665/6 Serial Port (National 16550 compatible)
|
||||
|
||||
_RBR EQU 68H ;R Receiver Buffer
|
||||
_THR EQU 68H ;W Transmit Holding Reg
|
||||
_IER EQU 69H ;RW Interrupt-Enable Reg
|
||||
_IIR EQU 6AH ;R Interrupt Ident. Reg
|
||||
_FCR EQU 6AH ;W FIFO Control Reg
|
||||
_LCR EQU 6BH ;RW Line Control Reg
|
||||
_MCR EQU 6CH ;RW Modem Control Reg
|
||||
_LSR EQU 6DH ;RW Line Status Reg
|
||||
_MMSR EQU 6EH ;RW Modem Status Reg
|
||||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
|
||||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
|
||||
_DLM EQU 69H ;RW Divisor MSB | set High
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
|
||||
|
||||
IF HARDDSK
|
||||
NCR EQU 40H ; Base of NCR 5380
|
||||
|
||||
; 5380 Chip Registers
|
||||
|
||||
NCRDAT EQU NCR ; Current SCSI Data (Read)
|
||||
; Output Data Register (Write)
|
||||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
|
||||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
|
||||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
|
||||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
|
||||
NCRST EQU NCR+5 ; Bus & Status Register (Read)
|
||||
; Start DMA Send (Write)
|
||||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
|
||||
; Start DMA Initiator Receive (Write)
|
||||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
|
||||
|
||||
; Bit Assignments for NCR 5380 Ports as indicated
|
||||
|
||||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
|
||||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
|
||||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
|
||||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
|
||||
|
||||
B_BSY EQU 01000000B ; *Busy (NCRBUS)
|
||||
B_REQ EQU 00100000B ; *Request (NCRBUS)
|
||||
B_MSG EQU 00010000B ; *Message (NCRBUS)
|
||||
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
|
||||
B_IO EQU 00000100B ; *I/O (NCRBUS)
|
||||
B_SEL EQU 00000010B ; *Select (NCRBUS)
|
||||
|
||||
B_PHAS EQU 00001000B ; Phase Match (NCRST)
|
||||
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
|
||||
|
||||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
|
||||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
|
||||
ENDIF ;harddsk
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
|
||||
; Set the base GIDE equate to the jumper setting on the GIDE board.
|
||||
|
||||
IF IDE
|
||||
GIDE EQU 50H ; Set base of 16 byte address range
|
||||
|
||||
IDEDOR EQU GIDE+6 ; Digital Output Register
|
||||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
|
||||
IDEErr EQU GIDE+9 ; IDE Error Register
|
||||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
|
||||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
|
||||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
|
||||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
|
||||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
|
||||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
|
||||
|
||||
CMDHOM EQU 10H ; Home Drive Heads
|
||||
CMDRD EQU 20H ; Read Sector Command (w/retry)
|
||||
CMDWR EQU 30H ; Write Sector Command (w/retry)
|
||||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
|
||||
CMDFMT EQU 50H ; Format Track Command
|
||||
CMDDIAG EQU 90H ; Execute Diagnostics Command
|
||||
CMDINIT EQU 91H ; Initialize Drive Params Command
|
||||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
|
||||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
|
||||
CMDPWQ EQU 0E5H ; Power Status Query Command
|
||||
CMDID EQU 0ECH ; Read Drive Ident Data Command
|
||||
ENDIF ;ide
|
||||
;=================== End Unique Equates =======================
|
||||
|
||||
@@ -33,7 +33,10 @@ MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU no ; Include IOP code into Jump table?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU NO ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU YES ; Set for Segment Configuration T
|
||||
CONF_N EQU NO ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
@@ -33,7 +33,10 @@ MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU no ; Include IOP code into Jump table?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU NO ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU YES ; Set for Segment Configuration T
|
||||
CONF_N EQU NO ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
372
Source/BPBIOS/def-ww-z41nbnk.lib
Normal file
372
Source/BPBIOS/def-ww-z41nbnk.lib
Normal file
@@ -0,0 +1,372 @@
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::**********************
|
||||
; B/P BIOS Configuration and Equate File. ** System Dependant **
|
||||
; - D-X Designs Pty Ltd P112 CPU Board - **********************
|
||||
; Tailor your system here.
|
||||
;
|
||||
; 30 Aug 01 - Cleaned up for GPL release. HFB
|
||||
; 11 May 97 - Added GIDE and adjusted HD equates. HFB
|
||||
; 5 Jan 97 - Reformatted to Standard. HFB
|
||||
; 10 Jun 96 - Initial Test Release. HFB
|
||||
;:::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
|
||||
; BIOS Configuration Equates and Macros
|
||||
|
||||
DATE MACRO
|
||||
DEFB '17 Jan 14' ; Date of this version
|
||||
ENDM
|
||||
|
||||
AUTOCL MACRO
|
||||
DEFB 8,'ZEX Z41 ',0 ; Autostart command line
|
||||
ENDM
|
||||
|
||||
;--- Basic System and Z-System Section ---
|
||||
|
||||
MOVCPM EQU no ; Integrate into MOVCPM "type" loader?
|
||||
IF MOVCPM
|
||||
VERS EQU 13H ; Version number in BCD (Hex) (Major/Minor)
|
||||
ELSE
|
||||
VERS EQU 21H ; Version number w/Device Swapping permitted
|
||||
ENDIF
|
||||
BANKED EQU YES ; Is this a banked BIOS?
|
||||
ZSDOS2 EQU YES ; Yes = Banked Dos, No = CP/M 2.2 Compatible
|
||||
INROM EQU NO ; Alternate bank in ROM?
|
||||
MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU YES ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU NO ; Set for Segment Configuration T
|
||||
CONF_N EQU YES ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
IBMOVS EQU NO ; Yes = Inter-bank Moves allowed (Z180/64180)
|
||||
; No = Include Common RAM transfer buffer
|
||||
;--- Character Device Section ---
|
||||
|
||||
MORDEV EQU NO ; YES = Include any extra Char Device Drivers
|
||||
; NO = Only use the 4 defined Char Devices
|
||||
ESCC_B EQU no ; Include ESCC Channel B Driver?
|
||||
; The following two devices result in non-standard data rates
|
||||
; with the standard 16.00 MHz crystal in the P112. If a more
|
||||
; "standard" crystal is used (12.288, 18.432, 24.576 MHz etc)
|
||||
; is used, the ports become usable.
|
||||
; Driver code for ASCI0 and ASCI1 includes an option for
|
||||
; assembling Polled or Interrupt-driven buffered input.
|
||||
; Select the desired option for ASCI0 with the BUFFA0 flag,
|
||||
; and BUFFA1 for ASCI1.
|
||||
ASCI_0 EQU false ; Include ASCI0 Driver?
|
||||
BUFFA0 EQU false ; Use buffered ASCI0 Input Driver?
|
||||
ASCI_1 EQU false ; Include ASCI1 Driver?
|
||||
BUFFA1 EQU false ; Use buffered ASCI1 Input Driver?
|
||||
|
||||
QSIZE EQU 32 ; size of interrupt typeahead buffers (if used)
|
||||
; ..must be 2^n with n<8
|
||||
RTSCTS EQU no ; Include RTS/CTS code on Serial Outputs?
|
||||
XONOFF EQU no ; Include Xon/Xoff handshaking in Serial lines?
|
||||
|
||||
;--- Clock and Time Section ---
|
||||
|
||||
CLOCK EQU YES ; Include ZSDOS Clock Driver Code?
|
||||
DS1202 EQU YES ; Use Dallas DS-1202 instead of Interrupt RTC?
|
||||
CLKSET EQU YES ; Allow DS-1202 Clock Sets? (Error if No)
|
||||
TICTOC EQU NO ;== NOT USED IN P112 ("heartbeat" count)
|
||||
|
||||
;--- Floppy Diskette Section ---
|
||||
|
||||
BIOERM EQU yes ; Print BIOS error messages?
|
||||
CALCSK EQU YES ; Calculate skew table?
|
||||
AUTOSL EQU YES ; Auto select floppy formats?
|
||||
; If AUTOSL=True, the next two are active...
|
||||
FDDMA EQU no ; Use DMA Control for Floppy Drive Transfers?
|
||||
FLOPYH EQU no ; Include "Hi-Density" Floppy Formats?
|
||||
FLOPY8 EQU no ; Include 8" Floppy Formats?
|
||||
MORDPB EQU NO ; Include additional Floppy DPB Formats?
|
||||
|
||||
;--- RAM Disk Section ---
|
||||
|
||||
RAMDSK EQU YES ; YES = Make RAM-Disk Code, NO = No code made
|
||||
|
||||
;--- Hard Disk Section ---
|
||||
|
||||
HARDDSK EQU YES ; YES = Add Hard-disk Code, NO = Floppy Only
|
||||
; (Pick 1 of 3 options below)
|
||||
SCSI EQU NO ; YES = Use SCSI Driver
|
||||
IDE EQU NO ; YES = Use IDE Driver
|
||||
HDSK EQU YES ; YES = Use SIMH HDSK Driver
|
||||
HDDMA EQU NO ; Use DMA-Controlled Hard Disk Data Transfers?
|
||||
; (DMA not implemented for GIDE)
|
||||
UNIT_0 EQU YES ; Hard Disk Physical Unit 1
|
||||
UNIT_1 EQU YES ; Hard Disk Physical Unit 2
|
||||
UNIT_2 EQU YES ; Hard Disk Physical Unit 3
|
||||
|
||||
;--- Logical Drive Section ---
|
||||
|
||||
DRV_A EQU no ; Set each of these equates for the drive and
|
||||
DRV_B EQU no ; partition complement of your system. Assume
|
||||
DRV_C EQU no ; that A-D are Floppies.
|
||||
DRV_D EQU no
|
||||
DRV_E EQU yes ; Assume that E-L and N-P are Hard Disk
|
||||
DRV_F EQU yes ; Partitions
|
||||
DRV_G EQU yes
|
||||
DRV_H EQU yes
|
||||
DRV_I EQU yes
|
||||
DRV_J EQU yes
|
||||
DRV_K EQU yes
|
||||
DRV_L EQU yes
|
||||
DRV_M EQU RAMDSK ; This is Yes for RAM drive
|
||||
DRV_N EQU yes
|
||||
DRV_O EQU ~RAMDSK ; Use HBIOS RAM disk if BPBIOS RAM disk is not enabled
|
||||
DRV_P EQU no
|
||||
|
||||
;========== Configuration Unique Equates (P112) ===========
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>> W A R N I N G <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
;>>> Do NOT Alter these unless you KNOW what you're doing <<<
|
||||
;>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
|
||||
|
||||
REFRSH EQU NO ; Set to NO for only Static RAM, needed for
|
||||
; systems with dynamic RAMs.
|
||||
NOWAIT EQU NO ; Set to NO to use configured Wait States in
|
||||
; Hard Disk Driver. Yes to eliminate Waits.
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; For Z-180/HD64180 systems, The Bank numbers should reflect Physical
|
||||
; memory in 32k increments. In P112, the ROM occupies the first 32k
|
||||
; increment and is ambiguously addressed occupying 0-1FFFFH. The upper
|
||||
; memory bounds (BNKU, BNK3 and BNKM) should be set for your configuration.
|
||||
|
||||
BNK0 EQU BID_USR ; First TPA Bank (switched in/out) 40000H
|
||||
BNK1 EQU BID_HB ; Second TPA Bank (Common Bank) 48000H
|
||||
BNK2 EQU BID_SYS ; System Bank (BIOS, DOS, CPR) 50000H
|
||||
BNKU EQU 00H ; User Area Bank 58000H
|
||||
; (set to 0 to disable)
|
||||
BNK3 EQU BID_RAMD ; First Bank for RAM disk 60000H
|
||||
BNKM EQU BID_RAMM ; Maximum Bank # F8000H
|
||||
; With both on-board RAMs only (MEM1 or MEM2),
|
||||
; the maximum Bank number is 11 (0BH).
|
||||
|
||||
;=========== CPU-dependent Equates, Zilog Z-180/Hitachi HD64180 ==========
|
||||
|
||||
CNTLA0 EQU 00H ; Control Port ASCI 0
|
||||
CNTLA1 EQU 01H ; Control Port ASCI 1
|
||||
STAT0 EQU 04H ; Serial port 0 Status
|
||||
STAT1 EQU 05H ; Serial port 1 Status
|
||||
TDR0 EQU 06H ; Serial port 0 Output Data
|
||||
TDR1 EQU 07H ; Serial port 1 Output Data
|
||||
RDR0 EQU 08H ; Serial port 0 Input Data
|
||||
RDR1 EQU 09H ; Serial Port 1 Input Data
|
||||
CNTR EQU 0AH ; HD64180 Counter port
|
||||
TMDR0L EQU 0CH ; HD64180 DMA channel reg (low)
|
||||
TMDR0H EQU 0DH ; HD64180 DMA channel reg (hi)
|
||||
RLDR0L EQU 0EH ; CTC0 Reload Count, Low
|
||||
RLDR0H EQU 0FH ; CTC0 Reload Count, High
|
||||
TCR EQU 10H ; Interrupt Control Register
|
||||
TMDR1L EQU 14H ; Timer Data Reg Ch1 (Low)
|
||||
TMDR1H EQU 15H ; Timer Data Reg Ch1 (High)
|
||||
RLDR1L EQU 16H ; Timer Reload Reg Ch1 (Low)
|
||||
RLDR1H EQU 17H ; Timer Reload Reg Ch1 (High)
|
||||
FRC EQU 18H ; Free-Running Counter
|
||||
CCR EQU 1FH ; CPU Control Register (ZS8180/Z80182)
|
||||
SAR0L EQU 20H ; DMA Channel 0 Register start (8 ports)
|
||||
MAR1L EQU 28H ; DMA Channel 1 Register start (8 ports)
|
||||
DSTAT EQU 30H ; DMA Status/Control port
|
||||
DMODE EQU 31H ; DMA Mode Control port
|
||||
DCNTL EQU 32H ; DMA/WAIT Control Register
|
||||
IL EQU 33H ; Interrupt Segment Register
|
||||
ITC EQU 34H ; Interrupt/Trap Control Register
|
||||
RCR EQU 36H ; HD64180 Refresh Control register
|
||||
CBR EQU 38H ; MMU Common Base Register
|
||||
BBR EQU 39H ; MMU Bank Base Register
|
||||
CBAR EQU 3AH ; MMU Common/Bank Area Register
|
||||
OMCR EQU 3EH ; Operation Mode Control Reg
|
||||
ICR EQU 3FH ; I/O Control Register
|
||||
|
||||
; Some bit definitions used with the Z-180 on-chip peripherals:
|
||||
|
||||
TDRE EQU 02H ; ACSI Transmitter Buffer Empty
|
||||
RDRF EQU 80H ; ACSI Received Character available
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Extended Features of Z80182 for P112
|
||||
|
||||
WSGCS EQU 0D8H ; Wait-State Generator CS
|
||||
ENH182 EQU 0D9H ; Z80182 Enhancements Register
|
||||
PINMUX EQU 0DFH ; Interrupt Edge/Pin Mux Register
|
||||
RAMUBR EQU 0E6H ; RAM End Boundary
|
||||
RAMLBR EQU 0E7H ; RAM Start Boundary
|
||||
ROMBR EQU 0E8H ; ROM Boundary
|
||||
FIFOCTL EQU 0E9H ; FIFO Control Register
|
||||
RTOTC EQU 0EAH ; RX Time-Out Time Constant
|
||||
TTOTC EQU 0EBH ; TX Time-Out Time Constant
|
||||
FCR EQU 0ECH ; FIFO Register
|
||||
SCR EQU 0EFH ; System Pin Control
|
||||
RBR EQU 0F0H ; MIMIC RX Buffer Register (R)
|
||||
THR EQU 0F0H ; MIMIN TX Holding Register (W)
|
||||
IER EQU 0F1H ; Interrupt Enable Register
|
||||
LCR EQU 0F3H ; Line Control Register
|
||||
MCR EQU 0F4H ; Modem Control Register
|
||||
LSR EQU 0F5H ; Line Status Register
|
||||
MDMSR EQU 0F6H ; Modem Status Register
|
||||
MSCR EQU 0F7H ; MIMIC Scratch Register
|
||||
DLATL EQU 0F8H ; Divisor Latch (Low)
|
||||
DLATM EQU 0F9H ; Divisor Latch (High)
|
||||
TTCR EQU 0FAH ; TX Time Constant
|
||||
RTCR EQU 0FBH ; RX Time Constant
|
||||
IVEC EQU 0FCH ; MIMIC Interrupt Vector
|
||||
MIMIE EQU 0FDH ; MIMIC Interrupt Enable Register
|
||||
IUSIP EQU 0FEH ; MIMIC Interrupt Under-Service Register
|
||||
MMCR EQU 0FFH ; MIMIC Master Control Register
|
||||
|
||||
; Z80182 PIO Registers
|
||||
|
||||
DDRA EQU 0EDH ; Data Direction Register A
|
||||
DRA EQU 0EEH ; Port A Data
|
||||
DDRB EQU 0E4H ; Data Direction Register B
|
||||
DRB EQU 0E5H ; Data B Data
|
||||
DDRC EQU 0DDH ; Data Direction Register C
|
||||
DRC EQU 0DEH ; Data C Data
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; ESCC Registers on Z80182
|
||||
|
||||
SCCACNT EQU 0E0H ; ESCC Control Channel A
|
||||
SCCAD EQU 0E1H ; ESCC Data Channel A
|
||||
SCCBCNT EQU 0E2H ; ESCC Control Channel B
|
||||
SCCBD EQU 0E3H ; ESCC Data Channel B
|
||||
|
||||
; [E]SCC Internal Register Definitions
|
||||
|
||||
RR0 EQU 00H
|
||||
RR1 EQU 01H
|
||||
RR2 EQU 02H
|
||||
RR3 EQU 03H
|
||||
RR6 EQU 06H
|
||||
RR7 EQU 07H
|
||||
RR10 EQU 0AH
|
||||
RR12 EQU 0CH
|
||||
RR13 EQU 0DH
|
||||
RR15 EQU 0FH
|
||||
|
||||
WR0 EQU 00H
|
||||
WR1 EQU 01H
|
||||
WR2 EQU 02H
|
||||
WR3 EQU 03H
|
||||
WR4 EQU 04H
|
||||
WR5 EQU 05H
|
||||
WR6 EQU 06H
|
||||
WR7 EQU 07H
|
||||
WR9 EQU 09H
|
||||
WR10 EQU 0AH
|
||||
WR11 EQU 0BH
|
||||
WR12 EQU 0CH
|
||||
WR13 EQU 0DH
|
||||
WR14 EQU 0EH
|
||||
WR15 EQU 0FH
|
||||
|
||||
; FDC37C665/6 Parallel Port in Standard AT Mode
|
||||
|
||||
DPORT EQU 8CH ; Data Port
|
||||
SPORT EQU 8DH ; Status Port
|
||||
CPORT EQU 8EH ; Control Port
|
||||
|
||||
; FDC37C665/6 Configuration Control (access internal registers)
|
||||
|
||||
CFCNTL EQU 90H ; Configuration control port
|
||||
CFDATA EQU 91H ; Configuration data port
|
||||
|
||||
; FDC37C665/6 Floppy Controller on P112 (Intel 80277 compatible)
|
||||
|
||||
DCR EQU 92H ; Drive Control Register (Digital Output)
|
||||
MSR EQU 94H ; Main Status Register
|
||||
DR EQU 95H ; Data/Command Register
|
||||
DRR EQU 97H ; Data Rate Register/Disk Changed Bit in B7
|
||||
|
||||
_DMA EQU 0A0H ; Diskette DMA Address
|
||||
|
||||
; FDC37C665/6 Serial Port (National 16550 compatible)
|
||||
|
||||
_RBR EQU 68H ;R Receiver Buffer
|
||||
_THR EQU 68H ;W Transmit Holding Reg
|
||||
_IER EQU 69H ;RW Interrupt-Enable Reg
|
||||
_IIR EQU 6AH ;R Interrupt Ident. Reg
|
||||
_FCR EQU 6AH ;W FIFO Control Reg
|
||||
_LCR EQU 6BH ;RW Line Control Reg
|
||||
_MCR EQU 6CH ;RW Modem Control Reg
|
||||
_LSR EQU 6DH ;RW Line Status Reg
|
||||
_MMSR EQU 6EH ;RW Modem Status Reg
|
||||
_SCR EQU 6FH ;N/A Scratch Reg. (not avail in XT)
|
||||
_DDL EQU 68H ;RW Divisor LSB | wih DLAB
|
||||
_DLM EQU 69H ;RW Divisor MSB | set High
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates for the National DP8490/NCR 5380 Prototype SCSI controller
|
||||
|
||||
IF HARDDSK
|
||||
NCR EQU 40H ; Base of NCR 5380
|
||||
|
||||
; 5380 Chip Registers
|
||||
|
||||
NCRDAT EQU NCR ; Current SCSI Data (Read)
|
||||
; Output Data Register (Write)
|
||||
NCRCMD EQU NCR+1 ; Initiator Command Register (Read/Write)
|
||||
NCRMOD EQU NCR+2 ; Mode Register (Read/Write)
|
||||
NCRTGT EQU NCR+3 ; Target Command Register (Read/Write)
|
||||
NCRBUS EQU NCR+4 ; Current SCSI Bus Status (Read)
|
||||
NCRST EQU NCR+5 ; Bus & Status Register (Read)
|
||||
; Start DMA Send (Write)
|
||||
NCRINT EQU NCR+7 ; Reset Parity/Interrupt (Read)
|
||||
; Start DMA Initiator Receive (Write)
|
||||
DMAACK EQU NCR+8 ; SCSI Dack IO Port (Read/Write)
|
||||
|
||||
; Bit Assignments for NCR 5380 Ports as indicated
|
||||
|
||||
B_ARST EQU 10000000B ; Assert *RST (NCRCMD)
|
||||
B_AACK EQU 00010000B ; Assert *ACK (NCRCMD)
|
||||
B_ASEL EQU 00000100B ; Assert *SEL (NCRCMD)
|
||||
B_ABUS EQU 00000001B ; Assert *Data Bus (NCRCMD)
|
||||
|
||||
B_BSY EQU 01000000B ; *Busy (NCRBUS)
|
||||
B_REQ EQU 00100000B ; *Request (NCRBUS)
|
||||
B_MSG EQU 00010000B ; *Message (NCRBUS)
|
||||
B_CD EQU 00001000B ; *Command/Data (NCRBUS)
|
||||
B_IO EQU 00000100B ; *I/O (NCRBUS)
|
||||
B_SEL EQU 00000010B ; *Select (NCRBUS)
|
||||
|
||||
B_PHAS EQU 00001000B ; Phase Match (NCRST)
|
||||
B_BBSY EQU 00000100B ; Bus Busy (NCRST)
|
||||
|
||||
B_MBSY EQU 00000100B ; Monitor Busy Flag (NCRMOD)
|
||||
B_DMA EQU 00000010B ; DMA Mode of transfer (NCRMOD)
|
||||
ENDIF ;harddsk
|
||||
|
||||
;++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
||||
; Equates reflecting GIDE Base address from Address Jumpers (if GIDE added)
|
||||
; Set the base GIDE equate to the jumper setting on the GIDE board.
|
||||
|
||||
IF IDE
|
||||
GIDE EQU 50H ; Set base of 16 byte address range
|
||||
|
||||
IDEDOR EQU GIDE+6 ; Digital Output Register
|
||||
IDEDat EQU GIDE+8 ; IDE Data Register (16-bit wide)
|
||||
IDEErr EQU GIDE+9 ; IDE Error Register
|
||||
IDESCnt EQU GIDE+0AH ; IDE Sector Count Register
|
||||
IDESNum EQU GIDE+0BH ; IDE Sector Number Register
|
||||
IDECLo EQU GIDE+0CH ; IDE Cylinder Number (Low)
|
||||
IDECHi EQU GIDE+0DH ; IDE Cylinter Number (High)
|
||||
IDESDH EQU GIDE+0EH ; IDE S-Drive-Head Register
|
||||
IDECmd EQU GIDE+0FH ; IDE Command/Status Register
|
||||
|
||||
CMDHOM EQU 10H ; Home Drive Heads
|
||||
CMDRD EQU 20H ; Read Sector Command (w/retry)
|
||||
CMDWR EQU 30H ; Write Sector Command (w/retry)
|
||||
CMDVER EQU 40H ; Verify Sector(s) Command (w/retry)
|
||||
CMDFMT EQU 50H ; Format Track Command
|
||||
CMDDIAG EQU 90H ; Execute Diagnostics Command
|
||||
CMDINIT EQU 91H ; Initialize Drive Params Command
|
||||
CMDPW0 EQU 0E0H ; Low Range of Power Control Commands
|
||||
CMDPW3 EQU 0E3H ; High Range of Power Control Commands
|
||||
CMDPWQ EQU 0E5H ; Power Status Query Command
|
||||
CMDID EQU 0ECH ; Read Drive Ident Data Command
|
||||
ENDIF ;ide
|
||||
;=================== End Unique Equates =======================
|
||||
|
||||
@@ -33,7 +33,10 @@ MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU no ; Include IOP code into Jump table?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU NO ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU YES ; Set for Segment Configuration T
|
||||
CONF_N EQU NO ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
@@ -33,7 +33,10 @@ MHZ EQU 18 ; Set to Speed in MHZ (6/9/12/16/18/24)
|
||||
FASTWB EQU YES ; Yes if restoring CPR from banked RAM
|
||||
; ..No if restoring from Drive A
|
||||
Z3 EQU YES ; Include ZCPR init code?
|
||||
HAVIOP EQU no ; Include IOP code into Jump table?
|
||||
HAVIOP EQU NO ; Include IOP code into Jump table?
|
||||
INTPXY EQU YES ; Internal HBIOS Mini Proxy
|
||||
CONF_T EQU NO ; Set for Segment Configuration T
|
||||
CONF_N EQU YES ; Set for Segment Configuration N
|
||||
|
||||
;--- Memory configuration Section --- (Expansion Memory configured here)
|
||||
|
||||
|
||||
@@ -194,19 +194,32 @@ HDSK_RW:
|
||||
LD C,(HL) ; LOAD IT IN C FOR HBIOS CALL LATER
|
||||
PUSH BC ; SAVE FUNCTION AND DEVICE FOR LATER
|
||||
|
||||
LD DE,(HSTTRK)
|
||||
LD HL,0
|
||||
LD B,4 ; PREPARE TO LEFT SHIT BY 4 BITS
|
||||
; LD DE,(HSTTRK)
|
||||
; LD HL,0
|
||||
; LD B,4 ; PREPARE TO LEFT SHIT BY 4 BITS
|
||||
;HDSK_RW1:
|
||||
; SLA E ; SHIFT DE LEFT BY 4 BITS
|
||||
; RL D
|
||||
; RL L
|
||||
; RL H
|
||||
; DJNZ HDSK_RW1 ; LOOP TILL ALL BITS DONE
|
||||
; LD A,(HSTSEC) ; GET THE SECTOR INTO A
|
||||
; AND 0FH ; GET RID OF TOP NIBBLE FOR SAFETY
|
||||
; OR E ; COMBINE WITH E
|
||||
; LD E,A ; BACK IN E
|
||||
|
||||
LD HL,(HSTTRK) ; GET TRACK VALUE
|
||||
LD A,L ; LSB OF TRACK TO A
|
||||
AND 0FH ; ISOLATE HEAD IN LOW 4 BITS
|
||||
LD D,A ; STUFF IT IN D
|
||||
LD A,(HSTSEC) ; GET SECTOR
|
||||
LD E,A ; STUFF IT IN E
|
||||
LD B,4 ; PREPARE TO SHIFT OUT 4 BIT HEAD VALUE
|
||||
HDSK_RW1:
|
||||
SLA E ; SHIFT DE LEFT BY 4 BITS
|
||||
RL D
|
||||
RL L
|
||||
RL H
|
||||
DJNZ HDSK_RW1 ; LOOP TILL ALL BITS DONE
|
||||
LD A,(HSTSEC) ; GET THE SECTOR INTO A
|
||||
AND 0FH ; GET RID OF TOP NIBBLE FOR SAFETY
|
||||
OR E ; COMBINE WITH E
|
||||
LD E,A ; BACK IN E
|
||||
SRL H ; SHIFT ONE BIT OUT
|
||||
RR L ; ... OF HL
|
||||
DJNZ HDSK_RW1 ; DO ALL 4 BITS
|
||||
EX DE,HL ; HL <-> DE FOR HBIOS CALL
|
||||
|
||||
POP BC ; RECOVER FUNCTION AND DEVICE
|
||||
CALL HBX_INVOKE
|
||||
|
||||
@@ -9,7 +9,7 @@
|
||||
; HBIOS configuration.
|
||||
;
|
||||
HBIOS EQU YES ; Use HBIOS functions
|
||||
INTPXY EQU YES ; Internal HBIOS Proxy
|
||||
;INTPXY EQU YES ; Internal HBIOS Proxy
|
||||
HBLOC EQU 0FE00H ; Location of HBIOS proxy (used if not INTPXY)
|
||||
;
|
||||
; Set exactly one of the following to YES to specify platform
|
||||
|
||||
@@ -14,9 +14,8 @@
|
||||
; alternative, just leave this file alone and configure everything with
|
||||
; the utilities provided.
|
||||
|
||||
; FFE0 - FFFF 32 Bytes HBIOS Reserved
|
||||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack
|
||||
; FF00 - FFAF 176 Bytes Multiple Command Line Buffer
|
||||
; FFD0 - FFFF 48 Bytes ZCPR3 External Stack
|
||||
; FF00 - FFCF 208 Bytes Multiple Command Line Buffer
|
||||
; FE00 - FEFF 256 Bytes Environment Descriptor
|
||||
; Bytes 00H-7FH: Z3 Parameters
|
||||
; Bytes 80H-FFH: Z3 TCAP
|
||||
@@ -50,16 +49,14 @@ NO EQU FALSE
|
||||
; The External Stack is placed in the very top position in memory. It is
|
||||
; mandatory for B/P Bios and ZCPR 3.3.
|
||||
|
||||
;EXTSTK EQU 0FFD0H ; ZCPR3 External Stack
|
||||
EXTSTK EQU 0FFB0H ; ZCPR3 External Stack
|
||||
EXTSTK EQU 0FFD0H ; ZCPR3 External Stack
|
||||
EXTSTKS EQU YES
|
||||
|
||||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
|
||||
; place it above the Environment. It is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3CL EQU 0FF00H ; ZCPR3 Command Line Buffer
|
||||
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
Z3CLS EQU 176-5 ; Size of Command Line Buffer-5
|
||||
Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
|
||||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
|
||||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
|
||||
|
||||
128
Source/BPBIOS/z3basen.lib
Normal file
128
Source/BPBIOS/z3basen.lib
Normal file
@@ -0,0 +1,128 @@
|
||||
; B/P Bios System Z3 Definition File.
|
||||
|
||||
; This file is adapted from the basic Z3BASE.LIB configuration file used for
|
||||
; most ZCPR33 systems. It has added the new definitions for the Resident
|
||||
; User Space defined in B/P Bios descriptions.
|
||||
;=========================================================================
|
||||
;== NOTE: The Starting Address of the User Space marks the lower ==
|
||||
;== base of memory and MUST be entered. B/P Bios Utilities use ==
|
||||
;== this address to locate many portions of the operating system. ==
|
||||
;=========================================================================
|
||||
; To change your systems definition, first sketch out the memory map in the
|
||||
; comment table, then set the equates to reflect the memory map, doing any
|
||||
; required calculations for element sizes and required spaces. As an
|
||||
; alternative, just leave this file alone and configure everything with
|
||||
; the utilities provided.
|
||||
|
||||
; FFE0 - FFFF 32 Bytes HBIOS Reserved
|
||||
; FFB0 - FFDF 48 Bytes ZCPR3 External Stack
|
||||
; FF00 - FFAF 176 Bytes Multiple Command Line Buffer
|
||||
; FE00 - FEFF 256 Bytes Environment Descriptor
|
||||
; Bytes 00H-7FH: Z3 Parameters
|
||||
; Bytes 80H-FFH: Z3 TCAP
|
||||
; FDFF 1 Byte Wheel byte
|
||||
; FDF4 - FDFE 11 Bytes Path (5 elements)
|
||||
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB
|
||||
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers
|
||||
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack
|
||||
; FC00 - FCFF 256 Bytes Named Directory Buffer
|
||||
; FA00 - FBFF 512 Bytes Flow Command Package
|
||||
; F200 - F9FF 2.0 KBytes Resident Command Package
|
||||
; EC00 - F1FF 1.5 KBytes IO Package
|
||||
; E900 - EBFF .75 KBytes Resident User Space
|
||||
|
||||
; The remainder is for the Operating System. Exact sizes vary depending
|
||||
; primarily on the Number and sizes of Hard Drive Partitions, but may be:
|
||||
|
||||
; D100 - EBFF 5.0 KBytes B/P BIOS (unbanked version)
|
||||
; C300 - D0FF 3.5 KBytes ZSDOS 1.0 BDOS
|
||||
; BB00 - C2FF 2 KBytes ZCPR 3.3 Command Processor
|
||||
; 0100 - BAFF ~46 KBytes Transient Program Area
|
||||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
|
||||
;========================================================================
|
||||
|
||||
FALSE EQU 0
|
||||
TRUE EQU NOT FALSE
|
||||
|
||||
YES EQU TRUE
|
||||
NO EQU FALSE
|
||||
|
||||
; The External Stack is placed in the very top position in memory. It is
|
||||
; mandatory for B/P Bios and ZCPR 3.3.
|
||||
|
||||
;EXTSTK EQU 0FFD0H ; ZCPR3 External Stack
|
||||
EXTSTK EQU 0FFB0H ; ZCPR3 External Stack
|
||||
EXTSTKS EQU YES
|
||||
|
||||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
|
||||
; place it above the Environment. It is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3CL EQU 0FF00H ; ZCPR3 Command Line Buffer
|
||||
;Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
Z3CLS EQU 176-5 ; Size of Command Line Buffer-5
|
||||
|
||||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
|
||||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
|
||||
|
||||
Z3ENV EQU 0FE00H ; Environment Descriptors
|
||||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
|
||||
|
||||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3WHL EQU 0FDFFH ; Wheel Byte Address
|
||||
Z3WHLS EQU YES
|
||||
|
||||
; The Path is mandatory for ZCPR 3.3.
|
||||
|
||||
EXPATH EQU 0FDF4H ; External Path starting Address
|
||||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
|
||||
; This defines 5 2-byte Path Elements
|
||||
|
||||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
|
||||
|
||||
EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB
|
||||
EXTFCBS EQU YES
|
||||
|
||||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
|
||||
|
||||
Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer
|
||||
Z3MSGS EQU YES
|
||||
|
||||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
|
||||
|
||||
SHSTK EQU 0FD00H ; Shell Stack Starting Address
|
||||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
|
||||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
|
||||
|
||||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
|
||||
; the named directory buffer.
|
||||
|
||||
Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer
|
||||
Z3NDIRS EQU 14 ; Number of Named Directory Elements
|
||||
; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes)
|
||||
|
||||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
|
||||
|
||||
FCP EQU 0FA00H ; Start of Flow Command Package
|
||||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
|
||||
|
||||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
|
||||
|
||||
RCP EQU 0F200H ; Start of Resident Command Processor
|
||||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
|
||||
|
||||
; IO Package definition. Set IOPS to 0 to eliminate IOP
|
||||
|
||||
IOP EQU 0EC00H ; Start of IO Package
|
||||
IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
|
||||
|
||||
;=========================================================================
|
||||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
|
||||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
|
||||
; MUST BE PRESENT!
|
||||
|
||||
USPC EQU 0E900H ; Start of Resident User Space (MANDATORY)
|
||||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
|
||||
|
||||
;--- End of Z3BASE.LIB ---
|
||||
|
||||
126
Source/BPBIOS/z3baset.lib
Normal file
126
Source/BPBIOS/z3baset.lib
Normal file
@@ -0,0 +1,126 @@
|
||||
; B/P Bios System Z3 Definition File.
|
||||
|
||||
; This file is adapted from the basic Z3BASE.LIB configuration file used for
|
||||
; most ZCPR33 systems. It has added the new definitions for the Resident
|
||||
; User Space defined in B/P Bios descriptions.
|
||||
;=========================================================================
|
||||
;== NOTE: The Starting Address of the User Space marks the lower ==
|
||||
;== base of memory and MUST be entered. B/P Bios Utilities use ==
|
||||
;== this address to locate many portions of the operating system. ==
|
||||
;=========================================================================
|
||||
; To change your systems definition, first sketch out the memory map in the
|
||||
; comment table, then set the equates to reflect the memory map, doing any
|
||||
; required calculations for element sizes and required spaces. As an
|
||||
; alternative, just leave this file alone and configure everything with
|
||||
; the utilities provided.
|
||||
|
||||
; FE00 - FFFF 512 Bytes HBIOS Reserved
|
||||
; FDFF 1 Byte Wheel byte
|
||||
; FDF4 - FDFE 11 Bytes Path (5 elements)
|
||||
; FDD0 - FDF3 36 Bytes ZCPR3 External FCB
|
||||
; FD80 - FDCF 80 Bytes ZCPR3 Message Buffers
|
||||
; FD00 - FD7F 128 Bytes ZCPR3 Shell Stack
|
||||
; FC00 - FCFF 256 Bytes Named Directory Buffer
|
||||
; FA00 - FBFF 512 Bytes Flow Command Package
|
||||
; F200 - F9FF 2.0 KBytes Resident Command Package
|
||||
; EC00 - F1FF 1.5 KBytes IO Package
|
||||
; EBD0 - EBFF 48 Bytes ZCPR3 External Stack
|
||||
; EB00 - EBAF 176 Bytes Multiple Command Line Buffer
|
||||
; EA00 - EAFF 256 Bytes Environment Descriptor
|
||||
; Bytes 00H-7FH: Z3 Parameters
|
||||
; Bytes 80H-FFH: Z3 TCAP
|
||||
; E700 - E9FF .75 KBytes Resident User Space
|
||||
|
||||
; The remainder is for the Operating System. Exact sizes vary depending
|
||||
; primarily on the Number and sizes of Hard Drive Partitions, but may be:
|
||||
|
||||
; D300 - E6FF 5.0 KBytes B/P BIOS (unbanked version)
|
||||
; C500 - D2FF 3.5 KBytes ZSDOS 1.0 BDOS
|
||||
; BD00 - C4FF 2 KBytes ZCPR 3.3 Command Processor
|
||||
; 0100 - BCFF ~47 KBytes Transient Program Area
|
||||
; 0000 - 00FF 256 Bytes Standard CP/M Buffers
|
||||
;========================================================================
|
||||
|
||||
FALSE EQU 0
|
||||
TRUE EQU NOT FALSE
|
||||
|
||||
YES EQU TRUE
|
||||
NO EQU FALSE
|
||||
|
||||
; The External Stack is placed in the very top position in memory. It is
|
||||
; mandatory for B/P Bios and ZCPR 3.3.
|
||||
|
||||
EXTSTK EQU 0EBD0H ; ZCPR3 External Stack
|
||||
EXTSTKS EQU YES
|
||||
|
||||
; The Multiple Command Line Buffer is placed in the Top Page of Memory to
|
||||
; place it above the Environment. It is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3CL EQU 0EB00H ; ZCPR3 Command Line Buffer
|
||||
Z3CLS EQU 208-5 ; Size of Command Line Buffer-5
|
||||
|
||||
; The ZCPR3 External Environment Descriptor is mandatory B/P Bios & ZCPR 3.3.
|
||||
; The Environment Descriptor MUST begin on an even Page Boundary (xx00H).
|
||||
|
||||
Z3ENV EQU 0EA00H ; Environment Descriptors
|
||||
Z3ENVS EQU 2 ; Size of Env Descriptor in 128-Byte Blks
|
||||
|
||||
; The ZCPR3 Wheel Byte is mandatory for ZCPR 3.3.
|
||||
|
||||
Z3WHL EQU 0FDFFH ; Wheel Byte Address
|
||||
Z3WHLS EQU YES
|
||||
|
||||
; The Path is mandatory for ZCPR 3.3.
|
||||
|
||||
EXPATH EQU 0FDF4H ; External Path starting Address
|
||||
EXPATHS EQU 5 ; (Path Size = EXPATHS*2 + 1 = 11 bytes)
|
||||
; This defines 5 2-byte Path Elements
|
||||
|
||||
; The ZCPR3 External FCB is mandatory for ZCPR 3.3.
|
||||
|
||||
EXTFCB EQU 0FDD0H ; 36-Byte ZCPR3 External FCB
|
||||
EXTFCBS EQU YES
|
||||
|
||||
; The ZCPR3 Message Buffers are mandatory for ZCPR 3.3.
|
||||
|
||||
Z3MSG EQU 0FD80H ; 80-Byte ZCPR3 Message Buffer
|
||||
Z3MSGS EQU YES
|
||||
|
||||
; Shell Stack definition. Set SHSTKS to 0 to eliminate Shell Stack
|
||||
|
||||
SHSTK EQU 0FD00H ; Shell Stack Starting Address
|
||||
SHSTKS EQU 4 ; Number of SHSIZE-Byte Shell Stack entries
|
||||
SHSIZE EQU 32 ; (Stack Size = SHSTKS * SHSIZE = 128 Bytes)
|
||||
|
||||
; ZCPR3 Named Directory Buffer definition. Set Z3NDIRS to 0 to eliminate
|
||||
; the named directory buffer.
|
||||
|
||||
Z3NDIR EQU 0FC00H ; Start of Named Directory Buffer
|
||||
Z3NDIRS EQU 14 ; Number of Named Directory Elements
|
||||
; (NDIR Size = Z3NDIRS * 18 + 1 = 253 Bytes)
|
||||
|
||||
; Flow Command Package definition. Set FCPS to 0 to eliminate FCP
|
||||
|
||||
FCP EQU 0FA00H ; Start of Flow Command Package
|
||||
FCPS EQU 4 ; (FCP Size = 128 * FCPS = 512 Bytes)
|
||||
|
||||
; Resident Command Processor Definition. Set RCPS to 0 to eliminate RCP
|
||||
|
||||
RCP EQU 0F200H ; Start of Resident Command Processor
|
||||
RCPS EQU 16 ; (RCP Size = 128 * RCPS = 2 kBytes)
|
||||
|
||||
; IO Package definition. Set IOPS to 0 to eliminate IOP
|
||||
|
||||
IOP EQU 0EC00H ; Start of IO Package
|
||||
IOPS DEFL 12 ; (IOP Size = 128 * IOPS = 1.5 kBytes)
|
||||
|
||||
;=========================================================================
|
||||
; Resident User Space Definition. Set USPCS to 0 to eliminate USPC.
|
||||
; The USPC Value marks the Lower Limit of Reserved Common High Memory and
|
||||
; MUST BE PRESENT!
|
||||
|
||||
USPC EQU 0E700H ; Start of Resident User Space (MANDATORY)
|
||||
USPCS EQU 6 ; (USPC Size = 128 * USPCS = 0.75 kBytes)
|
||||
|
||||
;--- End of Z3BASE.LIB ---
|
||||
|
||||
Binary file not shown.
Binary file not shown.
BIN
Source/BPBIOS/zcpr33n.rel
Normal file
BIN
Source/BPBIOS/zcpr33n.rel
Normal file
Binary file not shown.
BIN
Source/BPBIOS/zcpr33t.rel
Normal file
BIN
Source/BPBIOS/zcpr33t.rel
Normal file
Binary file not shown.
@@ -6,7 +6,7 @@
|
||||
; TODO:
|
||||
; - IMPLEMENT IDE_INITDEVICE
|
||||
; - HANDLE SECONDARY INTERFACE ON DIDE
|
||||
; - BREAK OUT IDE_SELECT FROM UNITSEL
|
||||
; - IMPLEMENT INTELLIGENT RESET, CHECK IF DEVICE IS ACTUALLY BROKEN BEFORE RESET
|
||||
;
|
||||
; +-----------------------------------------------------------------------+
|
||||
; | CONTROL BLOCK REGISTERS |
|
||||
@@ -154,11 +154,11 @@ IDE_IO_DRVADR .EQU $IDE_IO_BASE + $0F ; DRIVE ADDRESS REGISTER (R)
|
||||
;
|
||||
; COMMAND BYTES
|
||||
;
|
||||
IDE_CIDE_RECAL .EQU $10
|
||||
IDE_CIDE_READ .EQU $20
|
||||
IDE_CIDE_WRITE .EQU $30
|
||||
IDE_CIDE_IDDEV .EQU $EC
|
||||
IDE_CIDE_SETFEAT .EQU $EF
|
||||
IDE_CMD_RECAL .EQU $10
|
||||
IDE_CMD_READ .EQU $20
|
||||
IDE_CMD_WRITE .EQU $30
|
||||
IDE_CMD_IDDEV .EQU $EC
|
||||
IDE_CMD_SETFEAT .EQU $EF
|
||||
;
|
||||
; FEATURE BYTES
|
||||
;
|
||||
@@ -195,6 +195,18 @@ IDE_STAT .EQU 0 ; LAST STATUS (1 BYTE)
|
||||
IDE_TYPE .EQU 1 ; DEVICE TYPE (1 BYTE)
|
||||
IDE_CAPACITY .EQU 2 ; DEVICE CAPACITY (1 DWORD/4 BYTES)
|
||||
;
|
||||
; THE IDE_WAITXXX FUNCTIONS ARE BUILT TO TIMEOUT AS NEEDED SO DRIVER WILL
|
||||
; NOT HANG IF DEVICE IS UNRESPONSIVE. DIFFERENT TIMEOUTS ARE USED DEPENDING
|
||||
; ON THE SITUATION. GENERALLY, THE FAST TIMEOUT IS USED TO PROBE FOR DEVICES
|
||||
; USING FUNCTIONS THAT PERFORM NO I/O. OTHERWISE THE NORMAL TIMEOUT IS USED.
|
||||
; IDE SPEC ALLOWS FOR UP TO 30 SECS MAX TO RESPOND. IN PRACTICE, THIS IS WAY
|
||||
; TOO LONG, BUT IF YOU ARE USING A VERY OLD DEVICE, THESE TIMEOUTS MAY NEED TO
|
||||
; BE ADJUSTED. NOTE THAT THESE ARE BYTE VALUES, SO YOU CANNOT EXCEED 255.
|
||||
; THE TIMEOUTS ARE IN UNITS OF .05 SECONDS.
|
||||
;
|
||||
IDE_TONORM .EQU 200 ; NORMAL TIMEOUT IS 10 SECS
|
||||
IDE_TOFAST .EQU 10 ; FAST TIMEOUT IS 0.5 SECS
|
||||
;
|
||||
; MACRO TO RETURN POINTER TO FIELD WITHIN UNIT DATA
|
||||
;
|
||||
#DEFINE IDE_DPTR(FIELD) CALL IDE_DPTRIMP \ .DB FIELD
|
||||
@@ -205,6 +217,14 @@ IDE_CAPACITY .EQU 2 ; DEVICE CAPACITY (1 DWORD/4 BYTES)
|
||||
;
|
||||
IDE_INIT:
|
||||
PRTS("IDE:$") ; LABEL FOR IO ADDRESS
|
||||
;
|
||||
; COMPUTE CPU SPEED COMPENSATED TIMEOUT SCALER
|
||||
; AT 1MHZ, THE SCALER IS 961 (50000US / 52TS = 961)
|
||||
; SCALER IS THEREFORE 961 * CPU SPEED IN MHZ
|
||||
LD DE,961 ; LOAD SCALER FOR 1MHZ
|
||||
LD A,(HCB + HCB_CPUMHZ) ; LOAD CPU SPEED IN MHZ
|
||||
CALL MULT8X16 ; HL := DE * A
|
||||
LD (IDE_TOSCALER),HL ; SAVE IT
|
||||
;
|
||||
#IF (IDEMODE == IDEMODE_DIO)
|
||||
PRTS(" MODE=DIO$")
|
||||
@@ -242,10 +262,6 @@ IDE_INIT1:
|
||||
RET ; DONE
|
||||
;
|
||||
IDE_INIT2:
|
||||
; ; DISPLAY DEVICE INFO
|
||||
; CALL IDE_SELUNIT ; SELECT UNIT
|
||||
; RET NZ ; ABORT ON ERROR
|
||||
;
|
||||
LD (IDE_UNIT),A ; SET CURRENT UNIT
|
||||
;
|
||||
; CHECK FOR BAD STATUS
|
||||
@@ -298,7 +314,6 @@ IDE_DISPATCH:
|
||||
CP IDE_UNITCNT
|
||||
CALL NC,PANIC ; PANIC IF TOO HIGH
|
||||
LD (IDE_UNIT),A ; SAVE IT
|
||||
;CALL IDE_SELUNIT ; SELECT DESIRED UNIT
|
||||
;
|
||||
; DISPATCH ACCORDING TO DISK SUB-FUNCTION
|
||||
LD A,B ; GET REQUESTED FUNCTION
|
||||
@@ -371,12 +386,7 @@ IDE_SENSE:
|
||||
; THE ENTIRE INTERFACE. SO, TO HANDLE POSSIBLE HOT
|
||||
; SWAP WE DO THAT, THEN RESELECT THE DESIRED UNIT AND
|
||||
; CONTINUE.
|
||||
LD A,(IDE_UNIT) ; GET UNIT SELECTION
|
||||
PUSH AF ; SAVE UNIT SELECTION
|
||||
CALL IDE_RESET ; RESET ALL DEVICES ON BUS
|
||||
POP AF ; RECOVER UNIT SELECTION
|
||||
LD (IDE_UNIT),A ; RESTORE UNIT SELECTION
|
||||
;CALL IDE_SELUNIT ; RESELECT DESIRED UNIT
|
||||
;
|
||||
IDE_DPTR(IDE_STAT) ; POINT TO UNIT STATUS
|
||||
LD A,(HL) ; GET STATUS
|
||||
@@ -440,7 +450,7 @@ IDE_SETFEAT:
|
||||
OUT (IDE_IO_FEAT),A ; SET THE FEATURE VALUE
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
LD A,IDE_CIDE_SETFEAT ; CMD = SETFEAT
|
||||
LD A,IDE_CMD_SETFEAT ; CMD = SETFEAT
|
||||
LD (IDE_CMD),A ; SAVE IT
|
||||
JP IDE_RUNCMD ; RUN COMMAND AND EXIT
|
||||
;
|
||||
@@ -455,7 +465,7 @@ IDE_IDENTIFY:
|
||||
OUT (IDE_IO_DRVHD),A
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
LD A,IDE_CIDE_IDDEV
|
||||
LD A,IDE_CMD_IDDEV
|
||||
LD (IDE_CMD),A
|
||||
CALL IDE_RUNCMD
|
||||
RET NZ
|
||||
@@ -477,7 +487,7 @@ IDE_RDSEC:
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
CALL IDE_SETADDR ; SETUP CYL, TRK, HEAD
|
||||
LD A,IDE_CIDE_READ
|
||||
LD A,IDE_CMD_READ
|
||||
LD (IDE_CMD),A
|
||||
CALL IDE_RUNCMD
|
||||
RET NZ
|
||||
@@ -499,7 +509,7 @@ IDE_WRSEC:
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
CALL IDE_SETADDR ; SETUP CYL, TRK, HEAD
|
||||
LD A,IDE_CIDE_WRITE
|
||||
LD A,IDE_CMD_WRITE
|
||||
LD (IDE_CMD),A
|
||||
CALL IDE_RUNCMD
|
||||
RET NZ
|
||||
@@ -510,7 +520,7 @@ IDE_WRSEC:
|
||||
;
|
||||
IDE_SETADDR:
|
||||
; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER
|
||||
; IDE_IO_LBA3 HAS ALREADY BEEN SET BY IDE_SELECT
|
||||
; IDE_IO_LBA3 HAS ALREADY BEEN SET
|
||||
; HSTLBA2-0 --> IDE_IO_LBA2-0
|
||||
LD C,IDE_IO_LBA0 + 3 ; STARTING IO PORT (NOT PRE-DEC BELOW)
|
||||
LD HL,HSTLBA + 2 ; STARTING LBA BYTE ADR
|
||||
@@ -662,25 +672,34 @@ IDE_GETRES:
|
||||
IDE_RESET:
|
||||
;
|
||||
#IF (PLATFORM == PLT_MK4)
|
||||
; USE HARDWARE RESET LINE
|
||||
LD A,$80 ; HIGH BIT OF XAR IS IDE RESET
|
||||
OUT (MK4_XAR),A
|
||||
LD DE,16 ; DELAY ~250US
|
||||
LD DE,2 ; DELAY 32US (SPEC IS >= 25US)
|
||||
CALL VDELAY
|
||||
XOR A ; CLEAR RESET BIT
|
||||
OUT (MK4_XAR),A
|
||||
#ELSE
|
||||
; INITIATE SOFT RESET
|
||||
LD A,%00001110 ; NO INTERRUPTS, ASSERT RESET BOTH DRIVES
|
||||
OUT (IDE_IO_CTRL),A
|
||||
#ENDIF
|
||||
;
|
||||
LD DE,16 ; DELAY ~250US
|
||||
LD DE,2 ; DELAY 32US (SPEC IS >= 25US)
|
||||
CALL VDELAY
|
||||
;
|
||||
; CONFIGURE OPERATION AND END SOFT RESET
|
||||
LD A,%00001010 ; NO INTERRUPTS, DEASSERT RESET
|
||||
OUT (IDE_IO_CTRL),A
|
||||
OUT (IDE_IO_CTRL),A ; PUSH TO REGISTER
|
||||
;
|
||||
;CALL LDELAY
|
||||
LD DE,$2000 ; DELAY N * 16US (~128MS)
|
||||
; SPEC ALLOWS UP TO 450MS FOR DEVICES TO ASSERT THEIR PRESENCE
|
||||
; VIA -DASP. I ENCOUNTER PROBLEMS LATER ON IF I DON'T WAIT HERE
|
||||
; FOR THAT TO OCCUR. THUS FAR, IT APPEARS THAT 150MS IS SUFFICIENT
|
||||
; FOR ANY DEVICE ENCOUNTERED. MAY NEED TO EXTEND BACK TO 500MS
|
||||
; IF A SLOWER DEVICE IS ENCOUNTERED.
|
||||
;
|
||||
;LD DE,500000/16 ; ~500MS
|
||||
LD DE,150000/16 ; ~???MS
|
||||
CALL VDELAY
|
||||
;
|
||||
; CLEAR OUT ALL DATA (FOR ALL UNITS)
|
||||
@@ -704,7 +723,7 @@ IDE_RESET1:
|
||||
DJNZ IDE_RESET1 ; LOOP AS NEEDED
|
||||
;
|
||||
POP AF ; RECOVER ORIGINAL UNIT NUMBER
|
||||
CALL IDE_SELUNIT ; ... AND SELECT IT
|
||||
LD (IDE_UNIT),A ; AND SAVE IT
|
||||
;
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; AND DONE
|
||||
@@ -713,54 +732,48 @@ IDE_RESET1:
|
||||
;
|
||||
IDE_INITUNIT:
|
||||
LD (IDE_UNIT),A ; SET ACTIVE UNIT
|
||||
|
||||
|
||||
CALL IDE_SELUNIT ; SELECT UNIT
|
||||
RET NZ ; ABORT IF ERROR
|
||||
|
||||
LD HL,IDE_TIMEOUT ; POINT TO TIMEOUT
|
||||
LD (HL),IDE_TOFAST ; USE FAST TIMEOUT DURING INIT
|
||||
|
||||
CALL IDE_PROBE ; DO PROBE
|
||||
RET NZ ; ABORT IF ERROR
|
||||
|
||||
OR $FF
|
||||
OUT (IDE_IO_COUNT),A ; ZERO KEY REGISTERS IN TESTED DEVICE
|
||||
OUT (IDE_IO_SECT),A ; ZERO KEY REGISTERS IN TESTED DEVICE
|
||||
|
||||
;RET
|
||||
|
||||
JP IDE_INITDEV ; INIT DEVICE AND RETURN
|
||||
CALL IDE_INITDEV ; ATTEMPT TO INIT DEVICE
|
||||
|
||||
LD HL,IDE_TIMEOUT ; POINT TO TIMEOUT
|
||||
LD (HL),IDE_TONORM ; BACK TO NORMAL TIMEOUT
|
||||
|
||||
RET
|
||||
;
|
||||
; TAKE ANY ACTIONS REQUIRED TO SELECT DESIRED PHYSICAL UNIT
|
||||
; UNIT IS SPECIFIED IN A
|
||||
; UNIT IS SPECIFIED IN IDE_UNIT
|
||||
; REGISTER A IS DESTROYED
|
||||
;
|
||||
IDE_SELUNIT:
|
||||
; LD HL,IDE_UNIT ; POINT TO PREVIOUSLY SELECTED UNIT
|
||||
; CP (HL) ; SAME?
|
||||
; RET Z ; IF SO, NOTHING MORE TO DO
|
||||
|
||||
LD A,(IDE_UNIT) ; GET UNIT
|
||||
CP IDE_UNITCNT ; CHECK VALIDITY (EXCEED UNIT COUNT?)
|
||||
JP NC,IDE_INVUNIT ; HANDLE INVALID UNIT
|
||||
;
|
||||
; ; NEW UNIT SELECTED, IMPLEMENT IT
|
||||
; LD (IDE_UNIT),A ; RECORD NEW UNIT NUMBER
|
||||
;
|
||||
;
|
||||
#IF (IDEMODE == IDEMODE_DIDE)
|
||||
; SELECT PRIMARY/SECONDARY INTERFACE FOR DIDE HARDWARE
|
||||
#ENDIF
|
||||
;
|
||||
; DETERMINE AND SAVE DRIVE/HEAD VALUE FOR SELECTED UNIT
|
||||
PUSH HL ; SAVE HL
|
||||
LD A,(IDE_UNIT) ; GET CURRENT UNIT
|
||||
AND $01 ; LS BIT DETERMINES MASTER/SLAVE
|
||||
LD HL,IDE_DRVSEL
|
||||
CALL ADDHLA
|
||||
LD A,(HL) ; LOAD DRIVE/HEAD VALUE
|
||||
POP HL ; RECOVER HL
|
||||
LD (IDE_DRVHD),A ; SAVE IT
|
||||
;
|
||||
OUT (IDE_IO_DRVHD),A ; SELECT DRIVE
|
||||
LD (IDE_DRVHD),A ; UPDATE SHADOW REGISTER
|
||||
;
|
||||
; SPEC REQUIRES 400NS DELAY BEFORE CHECKING STATUS REGISTER
|
||||
;
|
||||
XOR A
|
||||
RET
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; AND DONE
|
||||
;
|
||||
;
|
||||
;
|
||||
@@ -769,6 +782,23 @@ IDE_PROBE:
|
||||
CALL IDE_PRTPREFIX
|
||||
PRTS(" PROBE$") ; LABEL FOR IO ADDRESS
|
||||
#ENDIF
|
||||
;
|
||||
LD A,(IDE_DRVHD)
|
||||
OUT (IDE_IO_DRVHD),A
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
|
||||
CALL DELAY ; DELAY ~16US
|
||||
;
|
||||
DCALL IDE_REGDUMP
|
||||
;
|
||||
;JR IDE_PROBE1 ; *DEBUG*
|
||||
;
|
||||
IDE_PROBE0:
|
||||
CALL IDE_WAITBSY ; WAIT FOR BUSY TO CLEAR
|
||||
RET NZ ; ABORT ON TIMEOUT
|
||||
;
|
||||
DCALL IDE_REGDUMP
|
||||
;
|
||||
; CHECK STATUS
|
||||
IN A,(IDE_IO_STAT) ; GET STATUS
|
||||
@@ -777,19 +807,6 @@ IDE_PROBE:
|
||||
OR A ; SET FLAGS TO TEST FOR ZERO
|
||||
JP Z,IDE_NOMEDIA
|
||||
;
|
||||
IDE_PROBE0:
|
||||
;CALL IDE_WAITBSY ; WAIT FOR BUSY TO CLEAR
|
||||
;RET NZ ; ABORT ON TIMEOUT
|
||||
;
|
||||
;; CHECK STATUS
|
||||
;IN A,(IDE_IO_STAT) ; GET STATUS
|
||||
;DCALL PRTHEXBYTE ; IF DEBUG, PRINT STATUS
|
||||
;OR A ; SET FLAGS TO TEST FOR ZERO
|
||||
;JR NZ,IDE_PROBE1 ; CONTINUE IF NON-ZERO
|
||||
;DEC A ; ZERO MEANS NO MEDIA, SIGNAL ERROR
|
||||
;RET ; AND DONE
|
||||
;
|
||||
IDE_PROBE1:
|
||||
; CHECK SIGNATURE
|
||||
DCALL PC_SPACE
|
||||
IN A,(IDE_IO_COUNT)
|
||||
@@ -812,6 +829,7 @@ IDE_PROBE1:
|
||||
CP $00
|
||||
JP NZ,IDE_NOMEDIA
|
||||
;
|
||||
IDE_PROBE1:
|
||||
; SIGNATURE MATCHES ATA DEVICE, RECORD TYPE AND RETURN SUCCESS
|
||||
IDE_DPTR(IDE_TYPE) ; POINT HL TO UNIT TYPE FIELD, A IS TRASHED
|
||||
LD (HL),IDE_TYPEATA ; SET THE DEVICE TYPE
|
||||
@@ -845,6 +863,7 @@ IDE_INITDEV:
|
||||
#ELSE
|
||||
LD A,IDE_FEAT_DISABLE8BIT ; FEATURE VALUE = DISABLE 8-BIT PIO
|
||||
#ENDIF
|
||||
|
||||
CALL IDE_SETFEAT ; SET FEATURE
|
||||
RET NZ ; BAIL OUT ON ERROR
|
||||
;
|
||||
@@ -886,16 +905,16 @@ IDE_CHKDEVICE:
|
||||
;
|
||||
;
|
||||
IDE_WAITRDY:
|
||||
LD B,15 ; ~15 SECOND TIMEOUT?
|
||||
LD A,(IDE_TIMEOUT) ; GET TIMEOUT IN 0.05 SECS
|
||||
LD B,A ; PUT IN OUTER LOOP VAR
|
||||
IDE_WAITRDY1:
|
||||
LD DE,-1 ; ~1 SECOND INNER LOOP
|
||||
LD DE,(IDE_TOSCALER) ; CPU SPPED SCALER TO INNER LOOP VAR
|
||||
IDE_WAITRDY2:
|
||||
IN A,(IDE_IO_STAT) ; READ STATUS
|
||||
LD C,A ; SAVE IT
|
||||
AND %11000000 ; ISOLATE BUSY AND RDY BITS
|
||||
XOR %01000000 ; WE WANT BUSY(7) TO BE 0 AND RDY(6) TO BE 1
|
||||
RET Z ; ALL SET, RETURN WITH Z SET
|
||||
CALL DELAY ; DELAY 16US
|
||||
DEC DE
|
||||
LD A,D
|
||||
OR E
|
||||
@@ -906,17 +925,17 @@ IDE_WAITRDY2:
|
||||
;
|
||||
;
|
||||
IDE_WAITDRQ:
|
||||
LD B,3 ; ~3 SECOND TIMEOUT???
|
||||
LD A,(IDE_TIMEOUT) ; GET TIMEOUT IN 0.05 SECS
|
||||
LD B,A ; PUT IN OUTER LOOP VAR
|
||||
IDE_WAITDRQ1:
|
||||
LD DE,-1 ; ~1 SECOND INNER LOOP
|
||||
LD DE,(IDE_TOSCALER) ; CPU SPPED SCALER TO INNER LOOP VAR
|
||||
IDE_WAITDRQ2:
|
||||
IN A,(IDE_IO_STAT) ; WAIT FOR DRIVE'S 512 BYTE READ BUFFER
|
||||
LD C,A ; SAVE IT
|
||||
AND %10001000 ; TO FILL (OR READY TO FILL)
|
||||
XOR %00001000
|
||||
RET Z
|
||||
CALL DELAY ; DELAY 16US
|
||||
DEC DE
|
||||
DEC DE
|
||||
LD A,D
|
||||
OR E
|
||||
JR NZ,IDE_WAITDRQ2
|
||||
@@ -926,21 +945,21 @@ IDE_WAITDRQ2:
|
||||
;
|
||||
;
|
||||
IDE_WAITBSY:
|
||||
LD B,3 ; ~3 SECOND TIMEOUT???
|
||||
LD A,(IDE_TIMEOUT) ; GET TIMEOUT IN 0.05 SECS
|
||||
LD B,A ; PUT IN OUTER LOOP VAR
|
||||
IDE_WAITBSY1:
|
||||
LD DE,-1 ; ~1 SECOND INNER LOOP
|
||||
LD DE,(IDE_TOSCALER) ; CPU SPPED SCALER TO INNER LOOP VAR
|
||||
IDE_WAITBSY2:
|
||||
IN A,(IDE_IO_STAT) ; WAIT FOR DRIVE'S 512 BYTE READ BUFFER
|
||||
LD C,A ; SAVE IT
|
||||
AND %10000000 ; TO FILL (OR READY TO FILL)
|
||||
RET Z
|
||||
CALL DELAY ; DELAY 16US
|
||||
DEC DE
|
||||
LD A,D
|
||||
OR E
|
||||
JR NZ,IDE_WAITBSY2
|
||||
DJNZ IDE_WAITBSY1
|
||||
JP IDE_BSYTO ; EXIT WITH BSYTO ERR
|
||||
IN A,(IDE_IO_STAT) ; WAIT FOR DRIVE'S 512 BYTE READ BUFFER ; 11TS
|
||||
LD C,A ; SAVE IT ; 4TS
|
||||
AND %10000000 ; TO FILL (OR READY TO FILL) ; 7TS
|
||||
RET Z ; 5TS
|
||||
DEC DE ; 6TS
|
||||
LD A,D ; 4TS
|
||||
OR E ; 4TS
|
||||
JR NZ,IDE_WAITBSY2 ; 12TS
|
||||
DJNZ IDE_WAITBSY1 ; -----
|
||||
JP IDE_BSYTO ; EXIT WITH BSYTO ERR ; 52TS
|
||||
;
|
||||
;=============================================================================
|
||||
; ERROR HANDLING AND DIAGNOSTICS
|
||||
@@ -1042,7 +1061,8 @@ IDE_PRTSTAT3:
|
||||
POP AF
|
||||
RET
|
||||
;
|
||||
;
|
||||
; PRINT ALL REGISTERS DIRECTLY FROM DEVICE
|
||||
; DEVICE MUST BE SELECTED PRIOR TO CALL
|
||||
;
|
||||
IDE_REGDUMP:
|
||||
PUSH AF
|
||||
@@ -1116,6 +1136,9 @@ IDE_STR_NO .TEXT "NO$"
|
||||
; DATA STORAGE
|
||||
;=============================================================================
|
||||
;
|
||||
IDE_TIMEOUT .DB IDE_TONORM ; WAIT FUNCS TIMEOUT IN TENTHS OF SEC
|
||||
IDE_TOSCALER .DW CPUMHZ * 961 ; WAIT FUNCS SCALER FOR CPU SPEED
|
||||
;
|
||||
IDE_CMD .DB 0 ; PENDING COMMAND TO PROCESS
|
||||
IDE_DRVHD .DB 0 ; CURRENT DRIVE/HEAD MASK
|
||||
;
|
||||
|
||||
@@ -5,7 +5,8 @@
|
||||
;
|
||||
; TODO:
|
||||
; - IMPLEMENT PPIDE_INITDEVICE
|
||||
; - BREAK OUT PPIDE_SELECT FROM UNITSEL
|
||||
; - IMPLEMENT INTELLIGENT RESET, CHECK IF DEVICE IS ACTUALLY BROKEN BEFORE RESET
|
||||
; - FIX SCALER CONSTANT
|
||||
;
|
||||
;
|
||||
PPIDE_IO_DATALO .EQU PPIDEIOB + 0 ; IDE DATA BUS LSB (8255 PORT A)
|
||||
@@ -156,11 +157,11 @@ PPIDE_UNITCNT .EQU 2 ; ASSUME ONLY PRIMARY INTERFACE
|
||||
;
|
||||
; COMMAND BYTES
|
||||
;
|
||||
PPIDE_CPPIDE_RECAL .EQU $10
|
||||
PPIDE_CPPIDE_READ .EQU $20
|
||||
PPIDE_CPPIDE_WRITE .EQU $30
|
||||
PPIDE_CPPIDE_IDDEV .EQU $EC
|
||||
PPIDE_CPPIDE_SETFEAT .EQU $EF
|
||||
PPIDE_CMD_RECAL .EQU $10
|
||||
PPIDE_CMD_READ .EQU $20
|
||||
PPIDE_CMD_WRITE .EQU $30
|
||||
PPIDE_CMD_IDDEV .EQU $EC
|
||||
PPIDE_CMD_SETFEAT .EQU $EF
|
||||
;
|
||||
; FEATURE BYTES
|
||||
;
|
||||
@@ -197,6 +198,18 @@ PPIDE_STAT .EQU 0 ; LAST STATUS (1 BYTE)
|
||||
PPIDE_TYPE .EQU 1 ; DEVICE TYPE (1 BYTE)
|
||||
PPIDE_CAPACITY .EQU 2 ; DEVICE CAPACITY (1 DWORD/4 BYTES)
|
||||
;
|
||||
; THE IDE_WAITXXX FUNCTIONS ARE BUILT TO TIMEOUT AS NEEDED SO DRIVER WILL
|
||||
; NOT HANG IF DEVICE IS UNRESPONSIVE. DIFFERENT TIMEOUTS ARE USED DEPENDING
|
||||
; ON THE SITUATION. GENERALLY, THE FAST TIMEOUT IS USED TO PROBE FOR DEVICES
|
||||
; USING FUNCTIONS THAT PERFORM NO I/O. OTHERWISE THE NORMAL TIMEOUT IS USED.
|
||||
; IDE SPEC ALLOWS FOR UP TO 30 SECS MAX TO RESPOND. IN PRACTICE, THIS IS WAY
|
||||
; TOO LONG, BUT IF YOU ARE USING A VERY OLD DEVICE, THESE TIMEOUTS MAY NEED TO
|
||||
; BE ADJUSTED. NOTE THAT THESE ARE BYTE VALUES, SO YOU CANNOT EXCEED 255.
|
||||
; THE TIMEOUTS ARE IN UNITS OF .05 SECONDS.
|
||||
;
|
||||
PPIDE_TONORM .EQU 200 ; NORMAL TIMEOUT IS 10 SECS
|
||||
PPIDE_TOFAST .EQU 10 ; FAST TIMEOUT IS 0.5 SECS
|
||||
;
|
||||
; MACRO TO RETURN POINTER TO FIELD WITHIN UNIT DATA
|
||||
;
|
||||
#DEFINE PPIDE_DPTR(FIELD) CALL PPIDE_DPTRIMP \ .DB FIELD
|
||||
@@ -207,6 +220,15 @@ PPIDE_CAPACITY .EQU 2 ; DEVICE CAPACITY (1 DWORD/4 BYTES)
|
||||
;
|
||||
PPIDE_INIT:
|
||||
PRTS("PPIDE: IO=0x$") ; LABEL FOR IO ADDRESS
|
||||
;
|
||||
; COMPUTE CPU SPEED COMPENSATED TIMEOUT SCALER
|
||||
; AT 1MHZ, THE SCALER IS 961 (50000US / 52TS = 961)
|
||||
; SCALER IS THEREFORE 961 * CPU SPEED IN MHZ
|
||||
LD DE,961 ; LOAD SCALER FOR 1MHZ
|
||||
LD A,(HCB + HCB_CPUMHZ) ; LOAD CPU SPEED IN MHZ
|
||||
CALL MULT8X16 ; HL := DE * A
|
||||
LD (PPIDE_TOSCALER),HL ; SAVE IT
|
||||
;
|
||||
LD A,PPIDEIOB
|
||||
CALL PRTHEXBYTE
|
||||
#IF (PPIDE8BIT)
|
||||
@@ -233,10 +255,6 @@ PPIDE_INIT1:
|
||||
RET ; DONE
|
||||
;
|
||||
PPIDE_INIT2:
|
||||
; ; DISPLAY DEVICE INFO
|
||||
; CALL PPIDE_SELUNIT ; SELECT UNIT
|
||||
; RET NZ ; ABORT ON ERROR
|
||||
;
|
||||
LD (PPIDE_UNIT),A ; SET CURRENT UNIT
|
||||
;
|
||||
; CHECK FOR BAD STATUS
|
||||
@@ -289,7 +307,6 @@ PPIDE_DISPATCH:
|
||||
CP PPIDE_UNITCNT
|
||||
CALL NC,PANIC ; PANIC IF TOO HIGH
|
||||
LD (PPIDE_UNIT),A ; SAVE IT
|
||||
;CALL PPIDE_SELUNIT ; SELECT DESIRED UNIT
|
||||
;
|
||||
; DISPATCH ACCORDING TO DISK SUB-FUNCTION
|
||||
LD A,B ; GET REQUESTED FUNCTION
|
||||
@@ -332,6 +349,7 @@ PPIDE_READ:
|
||||
LD HL,PPIDE_PRTERR ; SET UP PPIDE_PRTERR
|
||||
PUSH HL ; ... TO FILTER ALL EXITS
|
||||
#ENDIF
|
||||
CALL PPIDE_SELUNIT ; HARDWARE SELECTION OF TARGET UNIT
|
||||
JP PPIDE_RDSEC
|
||||
;
|
||||
;
|
||||
@@ -342,6 +360,7 @@ PPIDE_WRITE:
|
||||
LD HL,PPIDE_PRTERR ; SET UP PPIDE_PRTERR
|
||||
PUSH HL ; ... TO FILTER ALL EXITS
|
||||
#ENDIF
|
||||
CALL PPIDE_SELUNIT ; HARDWARE SELECTION OF TARGET UNIT
|
||||
JP PPIDE_WRSEC
|
||||
;
|
||||
;
|
||||
@@ -360,12 +379,7 @@ PPIDE_SENSE:
|
||||
; THE ENTIRE INTERFACE. SO, TO HANDLE POSSIBLE HOT
|
||||
; SWAP WE DO THAT, THEN RESELECT THE DESIRED UNIT AND
|
||||
; CONTINUE.
|
||||
LD A,(PPIDE_UNIT) ; GET UNIT SELECTION
|
||||
PUSH AF ; SAVE UNIT SELECTION
|
||||
CALL PPIDE_RESET ; RESET ALL DEVICES ON BUS
|
||||
POP AF ; RECOVER UNIT SELECTION
|
||||
LD (PPIDE_UNIT),A ; RESTORE UNIT SELECTION
|
||||
;CALL PPIDE_SELUNIT ; RESELECT DESIRED UNIT
|
||||
;
|
||||
PPIDE_DPTR(PPIDE_STAT) ; POINT TO UNIT STATUS
|
||||
LD A,(HL) ; GET STATUS
|
||||
@@ -435,7 +449,7 @@ PPIDE_SETFEAT:
|
||||
.DB PPIDE_REG_FEAT
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
LD A,PPIDE_CPPIDE_SETFEAT ; CMD = SETFEAT
|
||||
LD A,PPIDE_CMD_SETFEAT ; CMD = SETFEAT
|
||||
LD (PPIDE_CMD),A ; SAVE IT
|
||||
JP PPIDE_RUNCMD ; RUN COMMAND AND EXIT
|
||||
;
|
||||
@@ -452,7 +466,7 @@ PPIDE_IDENTIFY:
|
||||
.DB PPIDE_REG_DRVHD
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
LD A,PPIDE_CPPIDE_IDDEV
|
||||
LD A,PPIDE_CMD_IDDEV
|
||||
LD (PPIDE_CMD),A
|
||||
CALL PPIDE_RUNCMD
|
||||
RET NZ
|
||||
@@ -476,7 +490,7 @@ PPIDE_RDSEC:
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
CALL PPIDE_SETADDR ; SETUP CYL, TRK, HEAD
|
||||
LD A,PPIDE_CPPIDE_READ
|
||||
LD A,PPIDE_CMD_READ
|
||||
LD (PPIDE_CMD),A
|
||||
CALL PPIDE_RUNCMD
|
||||
RET NZ
|
||||
@@ -498,7 +512,7 @@ PPIDE_WRSEC:
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
CALL PPIDE_SETADDR ; SETUP CYL, TRK, HEAD
|
||||
LD A,PPIDE_CPPIDE_WRITE
|
||||
LD A,PPIDE_CMD_WRITE
|
||||
LD (PPIDE_CMD),A
|
||||
CALL PPIDE_RUNCMD
|
||||
RET NZ
|
||||
@@ -508,6 +522,10 @@ PPIDE_WRSEC:
|
||||
;
|
||||
;
|
||||
PPIDE_SETADDR:
|
||||
; XXX
|
||||
; SEND 3 LOWEST BYTES OF LBA IN REVERSE ORDER
|
||||
; IDE_IO_LBA3 HAS ALREADY BEEN SET
|
||||
; HSTLBA2-0 --> IDE_IO_LBA2-0
|
||||
LD A,(HSTLBA + 2)
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
@@ -714,13 +732,11 @@ PPIDE_RESET:
|
||||
;
|
||||
LD A,PPIDE_CTL_RESET
|
||||
OUT (PPIDE_IO_CTL),A
|
||||
LD DE,16
|
||||
;LD DE,1024
|
||||
LD DE,2
|
||||
CALL VDELAY
|
||||
XOR A
|
||||
OUT (PPIDE_IO_CTL),A
|
||||
LD DE,16
|
||||
;LD DE,1024
|
||||
LD DE,2
|
||||
CALL VDELAY
|
||||
;
|
||||
LD A,%00001010 ; SET ~IEN, NO INTERRUPTS
|
||||
@@ -728,8 +744,14 @@ PPIDE_RESET:
|
||||
CALL PPIDE_OUT
|
||||
.DB PPIDE_REG_CTRL
|
||||
;
|
||||
;CALL LDELAY
|
||||
LD DE,$2000 ; DELAY N * 16US (~128MS)
|
||||
; SPEC ALLOWS UP TO 450MS FOR DEVICES TO ASSERT THEIR PRESENCE
|
||||
; VIA -DASP. I ENCOUNTER PROBLEMS LATER ON IF I DON'T WAIT HERE
|
||||
; FOR THAT TO OCCUR. THUS FAR, IT APPEARS THAT 150MS IS SUFFICIENT
|
||||
; FOR ANY DEVICE ENCOUNTERED. MAY NEED TO EXTEND BACK TO 500MS
|
||||
; IF A SLOWER DEVICE IS ENCOUNTERED.
|
||||
;
|
||||
;LD DE,500000/16 ; ~500MS
|
||||
LD DE,150000/16 ; ~???MS
|
||||
CALL VDELAY
|
||||
;
|
||||
; CLEAR OUT ALL DATA (FOR ALL UNITS)
|
||||
@@ -753,7 +775,7 @@ PPIDE_RESET1:
|
||||
DJNZ PPIDE_RESET1 ; LOOP AS NEEDED
|
||||
;
|
||||
POP AF ; RECOVER ORIGINAL UNIT NUMBER
|
||||
CALL PPIDE_SELUNIT ; ... AND RESELECT IT
|
||||
LD (PPIDE_UNIT),A ; AND SAVE IT
|
||||
;
|
||||
XOR A ; SIGNAL SUCCESS
|
||||
RET ; AND DONE
|
||||
@@ -766,48 +788,36 @@ PPIDE_INITUNIT:
|
||||
CALL PPIDE_SELUNIT ; SELECT UNIT
|
||||
RET NZ ; ABORT IF ERROR
|
||||
|
||||
LD HL,PPIDE_TIMEOUT ; POINT TO TIMEOUT
|
||||
LD (HL),PPIDE_TOFAST ; USE FAST TIMEOUT DURING INIT
|
||||
|
||||
CALL PPIDE_PROBE ; DO PROBE
|
||||
RET NZ ; ABORT IF ERROR
|
||||
|
||||
OR $FF
|
||||
CALL PPIDE_OUT
|
||||
.DB PPIDE_REG_COUNT
|
||||
CALL PPIDE_OUT
|
||||
.DB PPIDE_REG_SECT
|
||||
|
||||
;RET
|
||||
|
||||
JP PPIDE_INITDEV ; INIT DEVICE AND RETURN
|
||||
CALL PPIDE_INITDEV ; INIT DEVICE AND RETURN
|
||||
;
|
||||
LD HL,PPIDE_TIMEOUT ; POINT TO TIMEOUT
|
||||
LD (HL),PPIDE_TONORM ; BACK TO NORMAL TIMEOUT
|
||||
;
|
||||
RET
|
||||
;
|
||||
; TAKE ANY ACTIONS REQUIRED TO SELECT DESIRED PHYSICAL UNIT
|
||||
; UNIT IS SPECIFIED IN A
|
||||
;
|
||||
PPIDE_SELUNIT:
|
||||
;LD HL,PPIDE_UNIT ; POINT TO PREVIOUSLY SELECTED UNIT
|
||||
;CP (HL) ; SAME?
|
||||
;RET Z ; IF SO, NOTHING MORE TO DO
|
||||
|
||||
LD A,(PPIDE_UNIT) ; GET UNIT
|
||||
CP PPIDE_UNITCNT ; CHECK VALIDITY (EXCEED UNIT COUNT?)
|
||||
JP NC,PPIDE_INVUNIT ; HANDLE INVALID UNIT
|
||||
;
|
||||
; NEW UNIT SELECTED, IMPLEMENT IT
|
||||
;LD (PPIDE_UNIT),A ; RECORD NEW UNIT NUMBER
|
||||
;
|
||||
PUSH HL ; SAVE HL, IT IS DESTROYED BELOW
|
||||
;
|
||||
LD A,(PPIDE_UNIT) ; GET CURRENT UNIT
|
||||
AND $01 ; LS BIT DETERMINES MASTER/SLAVE
|
||||
LD HL,PPIDE_DRVSEL
|
||||
CALL ADDHLA
|
||||
LD A,(HL) ; LOAD DRIVE/HEAD VALUE
|
||||
;
|
||||
;OUT (PPIDE_REG_DRVHD),A ; SELECT DRIVE
|
||||
CALL PPIDE_OUT
|
||||
.DB PPIDE_REG_DRVHD
|
||||
LD (PPIDE_DRVHD),A ; UPDATE SHADOW REGISTER
|
||||
;
|
||||
; SPEC REQUIRES 400NS DELAY BEFORE CHECKING STATUS REGISTER
|
||||
;
|
||||
POP HL ; RECOVER HL
|
||||
LD (PPIDE_DRVHD),A ; SAVE IT
|
||||
;
|
||||
XOR A
|
||||
RET
|
||||
;
|
||||
@@ -818,6 +828,25 @@ PPIDE_PROBE:
|
||||
CALL PPIDE_PRTPREFIX
|
||||
PRTS(" PROBE$") ; LABEL FOR IO ADDRESS
|
||||
#ENDIF
|
||||
;
|
||||
LD A,(PPIDE_DRVHD)
|
||||
;OUT (IDE_IO_DRVHD),A
|
||||
CALL PPIDE_OUT
|
||||
.DB PPIDE_REG_DRVHD
|
||||
DCALL PC_SPACE
|
||||
DCALL PRTHEXBYTE
|
||||
|
||||
CALL DELAY ; DELAY ~16US
|
||||
;
|
||||
DCALL PPIDE_REGDUMP
|
||||
;
|
||||
;JR PPIDE_PROBE1 ; *DEBUG*
|
||||
;
|
||||
PPIDE_PROBE0:
|
||||
CALL PPIDE_WAITBSY ; WAIT FOR BUSY TO CLEAR
|
||||
RET NZ ; ABORT ON TIMEOUT
|
||||
;
|
||||
DCALL PPIDE_REGDUMP
|
||||
;
|
||||
; CHECK STATUS
|
||||
; IN A,(PPIDE_REG_STAT) ; GET STATUS
|
||||
@@ -828,19 +857,6 @@ PPIDE_PROBE:
|
||||
OR A ; SET FLAGS TO TEST FOR ZERO
|
||||
JP Z,PPIDE_NOMEDIA ; CONTINUE IF NON-ZERO
|
||||
;
|
||||
PPIDE_PROBE0:
|
||||
;CALL PPIDE_WAITBSY ; WAIT FOR BUSY TO CLEAR
|
||||
;RET NZ ; ABORT ON TIMEOUT
|
||||
;
|
||||
;; CHECK STATUS
|
||||
;IN A,(PPIDE_REG_STAT) ; GET STATUS
|
||||
;DCALL PRTHEXBYTE ; IF DEBUG, PRINT STATUS
|
||||
;OR A ; SET FLAGS TO TEST FOR ZERO
|
||||
;JR NZ,PPIDE_PROBE1 ; CONTINUE IF NON-ZERO
|
||||
;DEC A ; ZERO MEANS NO MEDIA, SIGNAL ERROR
|
||||
;RET ; AND DONE
|
||||
;
|
||||
PPIDE_PROBE1:
|
||||
; CHECK SIGNATURE
|
||||
DCALL PC_SPACE
|
||||
;IN A,(PPIDE_REG_COUNT)
|
||||
@@ -871,6 +887,7 @@ PPIDE_PROBE1:
|
||||
CP $00
|
||||
JP NZ,PPIDE_NOMEDIA
|
||||
;
|
||||
PPIDE_PROBE1:
|
||||
; SIGNATURE MATCHES ATA DEVICE, RECORD TYPE AND RETURN SUCCESS
|
||||
PPIDE_DPTR(PPIDE_TYPE) ; POINT HL TO UNIT TYPE FIELD, A IS TRASHED
|
||||
LD (HL),PPIDE_TYPEATA ; SET THE DEVICE TYPE
|
||||
@@ -945,9 +962,10 @@ PPIDE_CHKDEVICE:
|
||||
;
|
||||
;
|
||||
PPIDE_WAITRDY:
|
||||
LD B,15 ; ~15 SECOND TIMEOUT?
|
||||
LD A,(PPIDE_TIMEOUT) ; GET TIMEOUT IN 0.05 SECS
|
||||
LD B,A ; PUT IN OUTER LOOP VAR
|
||||
PPIDE_WAITRDY1:
|
||||
LD DE,-1 ; ~1 SECOND INNER LOOP
|
||||
LD DE,(PPIDE_TOSCALER) ; CPU SPPED SCALER TO INNER LOOP VAR
|
||||
PPIDE_WAITRDY2:
|
||||
;IN A,(PPIDE_REG_STAT) ; READ STATUS
|
||||
CALL PPIDE_IN
|
||||
@@ -956,7 +974,6 @@ PPIDE_WAITRDY2:
|
||||
AND %11000000 ; ISOLATE BUSY AND RDY BITS
|
||||
XOR %01000000 ; WE WANT BUSY(7) TO BE 0 AND RDY(6) TO BE 1
|
||||
RET Z ; ALL SET, RETURN WITH Z SET
|
||||
CALL DELAY ; DELAY 16US
|
||||
DEC DE
|
||||
LD A,D
|
||||
OR E
|
||||
@@ -967,9 +984,10 @@ PPIDE_WAITRDY2:
|
||||
;
|
||||
;
|
||||
PPIDE_WAITDRQ:
|
||||
LD B,3 ; ~3 SECOND TIMEOUT???
|
||||
LD A,(PPIDE_TIMEOUT) ; GET TIMEOUT IN 0.05 SECS
|
||||
LD B,A ; PUT IN OUTER LOOP VAR
|
||||
PPIDE_WAITDRQ1:
|
||||
LD DE,-1 ; ~1 SECOND INNER LOOP
|
||||
LD DE,(PPIDE_TOSCALER) ; CPU SPPED SCALER TO INNER LOOP VAR
|
||||
PPIDE_WAITDRQ2:
|
||||
;IN A,(PPIDE_REG_STAT) ; READ STATUS
|
||||
CALL PPIDE_IN
|
||||
@@ -978,7 +996,6 @@ PPIDE_WAITDRQ2:
|
||||
AND %10001000 ; TO FILL (OR READY TO FILL)
|
||||
XOR %00001000
|
||||
RET Z
|
||||
CALL DELAY ; DELAY 16US
|
||||
DEC DE
|
||||
LD A,D
|
||||
OR E
|
||||
@@ -989,9 +1006,10 @@ PPIDE_WAITDRQ2:
|
||||
;
|
||||
;
|
||||
PPIDE_WAITBSY:
|
||||
LD B,3 ; ~3 SECOND TIMEOUT???
|
||||
LD A,(PPIDE_TIMEOUT) ; GET TIMEOUT IN 0.05 SECS
|
||||
LD B,A ; PUT IN OUTER LOOP VAR
|
||||
PPIDE_WAITBSY1:
|
||||
LD DE,-1 ; ~1 SECOND INNER LOOP
|
||||
LD DE,(PPIDE_TOSCALER) ; CPU SPPED SCALER TO INNER LOOP VAR
|
||||
PPIDE_WAITBSY2:
|
||||
;IN A,(PPIDE_REG_STAT) ; READ STATUS
|
||||
CALL PPIDE_IN
|
||||
@@ -999,7 +1017,6 @@ PPIDE_WAITBSY2:
|
||||
LD C,A ; SAVE IT
|
||||
AND %10000000 ; TO FILL (OR READY TO FILL)
|
||||
RET Z
|
||||
CALL DELAY ; DELAY 16US
|
||||
DEC DE
|
||||
LD A,D
|
||||
OR E
|
||||
@@ -1072,7 +1089,6 @@ PPIDE_IOERR:
|
||||
JR PPIDE_ERR
|
||||
;
|
||||
PPIDE_RDYTO:
|
||||
CALL PC_COLON
|
||||
LD A,PPIDE_STRDYTO
|
||||
JR PPIDE_ERR
|
||||
;
|
||||
@@ -1150,7 +1166,8 @@ PPIDE_PRTSTAT3:
|
||||
POP AF
|
||||
RET
|
||||
;
|
||||
;
|
||||
; PRINT ALL REGISTERS DIRECTLY FROM DEVICE
|
||||
; DEVICE MUST BE SELECTED PRIOR TO CALL
|
||||
;
|
||||
PPIDE_REGDUMP:
|
||||
PUSH AF
|
||||
@@ -1232,6 +1249,9 @@ PPIDE_STR_NO .TEXT "NO$"
|
||||
; DATA STORAGE
|
||||
;=============================================================================
|
||||
;
|
||||
PPIDE_TIMEOUT .DB PPIDE_TONORM ; WAIT FUNCS TIMEOUT IN TENTHS OF SEC
|
||||
PPIDE_TOSCALER .DW CPUMHZ * 961 ; WAIT FUNCS SCALER FOR CPU SPEED
|
||||
;
|
||||
PPIDE_CMD .DB 0 ; PENDING COMMAND TO PROCESS
|
||||
PPIDE_DRVHD .DB 0 ; CURRENT DRIVE/HEAD MASK
|
||||
;
|
||||
|
||||
@@ -1358,11 +1358,11 @@ SD_GET1:
|
||||
OUT (SD_OPRREG),A ; DO IT
|
||||
DJNZ SD_GET1 ; REPEAT FOR ALL 8 BITS
|
||||
LD A,C ; GET BYTE RECEIVED INTO A
|
||||
#IF (SDMODE == SDMODE_UART)
|
||||
#IF (SDMODE == SDMODE_UART)
|
||||
XOR $FF ; DO IS INVERTED ON UART
|
||||
#ENDIF
|
||||
#ENDIF
|
||||
RET
|
||||
#ENDIF
|
||||
;
|
||||
;=============================================================================
|
||||
; ERROR HANDLING AND DIAGNOSTICS
|
||||
|
||||
@@ -213,10 +213,10 @@ HEXASCII:
|
||||
HEXCONV:
|
||||
AND 0FH ;LOW NIBBLE ONLY
|
||||
ADD A,90H
|
||||
DAA
|
||||
DAA
|
||||
ADC A,40H
|
||||
DAA
|
||||
RET
|
||||
DAA
|
||||
RET
|
||||
;
|
||||
; PRINT A BYTE BUFFER IN HEX POINTED TO BY DE
|
||||
; REGISTER A HAS SIZE OF BUFFER
|
||||
@@ -244,7 +244,7 @@ DUMP_BUFFER:
|
||||
POP HL
|
||||
INC D
|
||||
INC D
|
||||
|
||||
|
||||
DB_BLKRD:
|
||||
PUSH BC
|
||||
PUSH HL
|
||||
@@ -258,7 +258,7 @@ DB_NXTONE:
|
||||
LD A,(HL) ; GET BYTE
|
||||
CALL PRTHEXBYTE ; PRINT IT
|
||||
CALL PC_SPACE ;
|
||||
DB_UPDH:
|
||||
DB_UPDH:
|
||||
INC HL ; POINT NEXT
|
||||
DEC C ; DEC. LOC COUNT
|
||||
JR NZ,DB_NXTONE ; IF LINE NOT DONE
|
||||
@@ -273,10 +273,10 @@ DB_PCRLF0:
|
||||
LD A,(HL) ; O.K. TO GET
|
||||
JR NZ,DB_PDOT ;
|
||||
DB_DOT:
|
||||
LD A,2EH ; LOAD A DOT
|
||||
LD A,2EH ; LOAD A DOT
|
||||
DB_PDOT:
|
||||
CALL COUT ; PRINT IT
|
||||
INC HL ;
|
||||
INC HL ;
|
||||
LD A,D ;
|
||||
CP H ;
|
||||
JR NZ,DB_UPDH1 ;
|
||||
@@ -292,7 +292,7 @@ DB_CONTD:
|
||||
CALL NEWLINE ;
|
||||
JP DB_BLKRD ;
|
||||
|
||||
DB_END:
|
||||
DB_END:
|
||||
RET ;
|
||||
;
|
||||
; OUTPUT A '$' TERMINATED STRING
|
||||
@@ -346,11 +346,11 @@ PANIC:
|
||||
LD B,H
|
||||
LD C,L
|
||||
CALL PRTHEXWORD
|
||||
|
||||
|
||||
RST 38
|
||||
|
||||
|
||||
HALT
|
||||
|
||||
|
||||
JP 0
|
||||
;
|
||||
;==================================================================================================
|
||||
@@ -534,7 +534,7 @@ ADDHLA:
|
||||
RET
|
||||
;
|
||||
;****************************
|
||||
; A(BCD) => A(BIN)
|
||||
; A(BCD) => A(BIN)
|
||||
; [00H..99H] -> [0..99]
|
||||
;****************************
|
||||
;
|
||||
@@ -555,7 +555,7 @@ BCD2BYTE:
|
||||
RET
|
||||
;
|
||||
;*****************************
|
||||
; A(BIN) => A(BCD)
|
||||
; A(BIN) => A(BCD)
|
||||
; [0..99] => [00H..99H]
|
||||
;*****************************
|
||||
;
|
||||
@@ -720,6 +720,22 @@ MULT8_LOOP:
|
||||
MULT8_NOADD:
|
||||
DJNZ MULT8_LOOP
|
||||
RET
|
||||
;
|
||||
; MULTIPLY A 16 BIT BY 8 BIT INTO 16 BIT
|
||||
; IN: MULTIPLY DE BY A
|
||||
; OUT: HL = RESULT, B=0, A, C, DE UNCHANGED
|
||||
;
|
||||
MULT8X16:
|
||||
LD B,8
|
||||
LD HL,0
|
||||
MULT8X16_1:
|
||||
ADD HL,HL
|
||||
RLCA
|
||||
JR NC,MULT8X16_2
|
||||
ADD HL,DE
|
||||
MULT8X16_2:
|
||||
DJNZ MULT8X16_1
|
||||
RET
|
||||
;;
|
||||
;; COMPUTE HL / DE
|
||||
;; RESULT IN BC, REMAINDER IN HL, AND SET ZF DEPENDING ON REMAINDER
|
||||
@@ -1023,13 +1039,13 @@ KY_STATLOOP:
|
||||
; DECODE THE RAW VALUE
|
||||
KY_DECODE:
|
||||
LD D,00H
|
||||
LD HL,KY_KEYMAP ; POINT TO BEGINNING OF TABLE
|
||||
LD HL,KY_KEYMAP ; POINT TO BEGINNING OF TABLE
|
||||
KY_GET_LOOP:
|
||||
CP (HL) ; MATCH?
|
||||
JR Z,KY_GET_DONE ; FOUND, DONE
|
||||
INC HL
|
||||
INC D ; D + 1
|
||||
JR NZ,KY_GET_LOOP ; NOT FOUND, LOOP UNTIL EOT
|
||||
JR NZ,KY_GET_LOOP ; NOT FOUND, LOOP UNTIL EOT
|
||||
KY_GET_DONE:
|
||||
; CLEAR OUT KEY_BUF
|
||||
XOR A
|
||||
@@ -1037,7 +1053,7 @@ KY_GET_DONE:
|
||||
; RETURN THE INDEX POSITION WHERE THE RAW VALUE WAS FOUND
|
||||
LD A,D
|
||||
RET
|
||||
;
|
||||
;
|
||||
;__KY_SCAN____________________________________________________________________________________________
|
||||
;
|
||||
; SCAN KEYBOARD MATRIX FOR AN INPUT
|
||||
@@ -1051,7 +1067,7 @@ KY_SCAN:
|
||||
IN A,(PPIB) ; GET ROWS
|
||||
AND 7FH ;ignore PB7 for PPISD
|
||||
CP 00H ; ANYTHING PRESSED?
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
|
||||
LD C,0040H
|
||||
LD A,42H | 30H ; SCAN COL TWO
|
||||
@@ -1060,7 +1076,7 @@ KY_SCAN:
|
||||
IN A,(PPIB) ; GET ROWS
|
||||
AND 7FH ;ignore PB7 for PPISD
|
||||
CP 00H ; ANYTHING PRESSED?
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
|
||||
LD C,0080H
|
||||
LD A,44H | 30H ; SCAN COL THREE
|
||||
@@ -1069,7 +1085,7 @@ KY_SCAN:
|
||||
IN A,(PPIB) ; GET ROWS
|
||||
AND 7FH ;ignore PB7 for PPISD
|
||||
CP 00H ; ANYTHING PRESSED?
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
|
||||
LD C,00C0H ;
|
||||
LD A,48H | 30H ; SCAN COL FOUR
|
||||
@@ -1078,7 +1094,7 @@ KY_SCAN:
|
||||
IN A,(PPIB) ; GET ROWS
|
||||
AND 7FH ;ignore PB7 for PPISD
|
||||
CP 00H ; ANYTHING PRESSED?
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
JR NZ,KY_SCAN_FOUND ; YES, EXIT
|
||||
|
||||
LD A,040H | 30H ; TURN OFF ALL COLUMNS
|
||||
OUT (PPIC),A ; SEND TO COLUMN LINES
|
||||
@@ -1087,7 +1103,7 @@ KY_SCAN:
|
||||
|
||||
KY_SCAN_FOUND:
|
||||
AND 3FH ; CLEAR TOP TWO BITS
|
||||
OR C ; ADD IN ROW BITS
|
||||
OR C ; ADD IN ROW BITS
|
||||
LD C,A ; STORE VALUE
|
||||
|
||||
; WAIT FOR KEY TO BE RELEASED
|
||||
@@ -1107,7 +1123,7 @@ KY_CLEAR_LOOP: ; WAIT FOR KEY TO CLEAR
|
||||
RET
|
||||
;
|
||||
;_KEYMAP_TABLE_____________________________________________________________________________________________________________
|
||||
;
|
||||
;
|
||||
KY_KEYMAP:
|
||||
; 0 1 2 3 4 5 6 7
|
||||
.DB 041H,002H,042H,082H,004H,044H,084H,008H
|
||||
@@ -1156,7 +1172,7 @@ DSKY_HEXOUT2:
|
||||
JP Z,DSKY_STROBE ; DO FINAL STROBE AND RETURN
|
||||
CALL DSKY_STROBE
|
||||
JR DSKY_HEXOUT2
|
||||
|
||||
|
||||
DSKY_STROBEC:
|
||||
LD A,80H | 30H
|
||||
JP DSKY_STROBE0
|
||||
|
||||
Reference in New Issue
Block a user