diff --git a/.github/pull_request_template.md b/.github/pull_request_template.md index 3670d886..35fb3003 100644 --- a/.github/pull_request_template.md +++ b/.github/pull_request_template.md @@ -7,5 +7,7 @@ BEFORE YOU CREATE A PULL REQUEST: Thank you for contributing to RomWBW! I will review your pull request as soon as possible. +-Wayne + DELETE EVERYTHING IN THIS COMMENT BLOCK AND REPLACE WITH YOUR COMMENTS --> diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 8769dbd7..132fa966 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -6,6 +6,7 @@ Version 3.5.1 - WBW: Doc improvements (per Fraser and Rob Gowin) - WBW: Correct ZMP application crash - MAP: Contribution of the SLABEL.COM tool for displaying and changing slice labels. +- MAP: Hardware documentation, Significant new content added with project links. Version 3.5 ----------- diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf index c571d57c..755d8798 100644 Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf index c212d184..2c7fce85 100644 Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ diff --git a/Doc/RomWBW Hardware.pdf b/Doc/RomWBW Hardware.pdf index 6eb6d80b..6a450ac7 100644 Binary files a/Doc/RomWBW Hardware.pdf and b/Doc/RomWBW Hardware.pdf differ diff --git a/Doc/RomWBW Introduction.pdf b/Doc/RomWBW Introduction.pdf index cec152e5..38bb3e2d 100644 Binary files a/Doc/RomWBW Introduction.pdf and b/Doc/RomWBW Introduction.pdf differ diff --git a/Doc/RomWBW System Guide.pdf b/Doc/RomWBW System Guide.pdf index 7f761a11..08cfd621 100644 Binary files a/Doc/RomWBW System Guide.pdf and b/Doc/RomWBW System Guide.pdf differ diff --git a/Doc/RomWBW User Guide.pdf b/Doc/RomWBW User Guide.pdf index 1961413e..4eda25ad 100644 Binary files a/Doc/RomWBW User Guide.pdf and b/Doc/RomWBW User Guide.pdf differ diff --git a/ReadMe.md b/ReadMe.md index 9d886ff9..f7a884a4 100644 --- a/ReadMe.md +++ b/ReadMe.md @@ -7,7 +7,7 @@ **RomWBW Introduction** \ Version 3.5 \ Wayne Warthen ([wwarthen@gmail.com](mailto:wwarthen@gmail.com)) \ -03 May 2025 +18 May 2025 # Overview @@ -305,6 +305,7 @@ let me know if I missed you! - creation of the Introduction and Hardware documents - Z3PLUS operating system disk image - COPYSL utility + - SLABEL utility - a feature for RomWBW configuration by NVRAM - the /B bulk mode of disk assignment to the ASSIGN utility diff --git a/ReadMe.txt b/ReadMe.txt index f25e5d0f..3d12b649 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -1,6 +1,6 @@ RomWBW Introduction Wayne Warthen (wwarthen@gmail.com) -03 May 2025 +18 May 2025 @@ -312,6 +312,7 @@ let me know if I missed you! - creation of the Introduction and Hardware documents - Z3PLUS operating system disk image - COPYSL utility + - SLABEL utility - a feature for RomWBW configuration by NVRAM - the /B bulk mode of disk assignment to the ASSIGN utility diff --git a/Source/Doc/Applications.md b/Source/Doc/Applications.md index ddb66eb0..8dd5a8e6 100644 --- a/Source/Doc/Applications.md +++ b/Source/Doc/Applications.md @@ -2423,6 +2423,9 @@ If your RomWBW system has a sound card based on either an AY-3-8190 or YM2149F sound chip, you can use the `TUNE` application to play PT or MYM sound files. +Note: TUNE will detect an AY-3-8910/YM2149 Sound Module re-gardless of +whether support for it is included in the RomWBW HBIOS configuration + #### Syntax `TUNE `*``* `*``*` diff --git a/Source/Doc/Hardware.md b/Source/Doc/Hardware.md index 016687ab..9aa01173 100644 --- a/Source/Doc/Hardware.md +++ b/Source/Doc/Hardware.md @@ -3,7 +3,9 @@ $include{"Book.h"}$ $define{doc_author}{Mark Pruden \& Wayne Warthen}$ $define{doc_authmail}{}$ -# Supported Hardware Platforms +# Overview + +## Supported Platforms This section contains a summary of the system configuration target for each of the pre-built ROM images included in the RomWBW @@ -12,63 +14,112 @@ distribution. It is intended to help you select the correct ROM image and understand the basic hardware components supported. Detailed hardware system configuration information should be obtained -from your system provider/designer. +from your system provider/designer. The table below summarizes the hardware platforms currently supported by RomWBW along with the standard pre-built ROM image(s). +`\clearpage`{=latex} + +#### RCBUS - General Configurations + +RCBus refers to Spencer Owen's RC2014 bus specification and derivatives +including RC26, RC40, RC80, and BP80. + +| **Description** | **Bus** | **ROM Image File** | **Baud Rate** | +|-------------------------------------------------------------|---------|------------------------------|--------------:| +| [RCBus Z80 CPU Module], 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 | +| [RCBus Z80 CPU Module (KIO)], 512K w/KIO | RCBus | RCZ80_kio_std.rom | 115200 | +| [RCBus Z180 CPU Module (External)] | RCBus | RCZ180_ext_std.rom | 115200 | +| [RCBus Z180 CPU Module (Native)] | RCBus | RCZ180_nat_std.rom | 115200 | +| [RCBus Z280 CPU Module (External)] | RCBus | RCZ280_ext_std.rom | 115200 | +| [RCBus Z280 CPU Module (Native)] | RCBus | RCZ280_nat_std.rom | 115200 | + +KIO refers to a Zilog specific Serial/Parallel Counter/Timer (Z84C90). + +The RCBus Z180 & Z280 require a separate RAM/ROM memory module. There are two types +of these modules, you must pick the correct ROM for your type of memory module: + +* The RCBus Z180 & Z280 require a separate RAM/ROM memory module. There are two types + of these modules, you must pick the correct ROM for your type of memory module: +* The second type of RAM/ROM module has no bank switching logic – this is called + (“Native”) because the CPU itself provides the bank switching logic. + +Only Z180 and Z280 CPUs have the ability to do bank switching in the +CPU, so the ext/nat selection only applies to them. Z80 CPUs have no +built-in bank switching logic, so they are always configured for +external bank switching. + +`\clearpage`{=latex} + +#### Custom / Specific Configurations + +Andrew Lynch + +| **Description** | **Bus** | **ROM Image File** | **Baud Rate** | +|-------------------------------------------------------------|---------|------------------------------|--------------:| +| [RetroBrew Z80 SBC V2] | ECB | SBC_std.rom | 38400 | +| [RetroBrew Z80 SimH] | - | SBC_simh.rom | 38400 | +| [Duodyne Z80 System] | Duo | DUO_std.rom | 38400 | +| [Nhyodyne Z80 MBC] | MBC | MBC_std.rom | 38400 | +| [Rhyophyre Z180 SBC] | - | RPH_std.rom | 38400 | +| [N8 Z180 SBC] (date >= 2312) | ECB | N8_std.rom | 38400 | + +Bill Shen + +| **Description** | **Bus** | **ROM Image File** | **Baud Rate** | +|-------------------------------------------------------------|---------|------------------------------|--------------:| +| [EaZy80-512 Z80 CPU Module] | RCBus | RCZ80_ez512_std.rom | 115200 | +| [K80W Z80 CPU Module] | RCBus | RCZ80_k80w_std.rom | 115200 | +| [ZRC Z80 CPU Module] | RCBus | RCZ80_zrc_std.rom | 115200 | +| [ZRC Z80 CPU Module (RAM)] | RCBus | RCZ80_zrc_ram_std.rom | 115200 | +| [ZRC512 Z80 CPU Module] | RCBus | RCZ80_zrc512_std.rom | 115200 | +| [Z1RCC Z180 CPU Module] | RCBus | RCZ180_z1rcc_std.rom | 115200 | +| [ZZRCC Z280 CPU Module] | RCBus | RCZ280_zzrcc_std.rom | 115200 | +| [ZZRCC Z280 CPU Module (RAM)] | RCBus | RCZ280_zzrcc_ram_std.rom | 115200 | +| [ZZ80MB Z280 SBC] | RCBus | RCZ280_zz80mb_std.rom | 115200 | + +Sergey Kiselev + +| **Description** | **Bus** | **ROM Image File** | **Baud Rate** | +|-------------------------------------------------------------|---------|------------------------------|--------------:| +| [Easy Z80 SBC] | RCBus | EZZ80_easy_std.rom | 115200 | +| [Tiny Z80 SBC] | RCBus | EZZ80_tiny_std.rom | 115200 | +| [Z80-512K CPU/RAM/ROM Module] | RCBus | RCZ80_skz_std.rom | 115200 | +| [Zeta Z80 SBC] , ParPortProp | - | ZETA_std.rom | 38400 | +| [Zeta V2 Z80 SBC] , ParPortProp | - | ZETA2_std.rom | 38400 | + +`\clearpage`{=latex} + +Stephen Cousins + | **Description** | **Bus** | **ROM Image File** | **Baud Rate** | |-------------------------------------------------------------|---------|------------------------------|--------------:| -| [RetroBrew Z80 SBC]^1^ | ECB | SBC_std.rom | 38400 | -| [RetroBrew Z80 SimH]^1^ | - | SBC_simh.rom | 38400 | -| [RetroBrew N8 Z180 SBC]^1^ (date >= 2312) | ECB | N8_std.rom | 38400 | -| [Zeta Z80 SBC]^2^, ParPortProp | - | ZETA_std.rom | 38400 | -| [Zeta V2 Z80 SBC]^2^, ParPortProp | - | ZETA2_std.rom | 38400 | -| [Mark IV Z180 SBC]^3^ | ECB | MK4_std.rom | 38400 | -| [RCBus Z80 CPU Module]^4^, 512K RAM/ROM | RCBus | RCZ80_std.rom | 115200 | -| [RCBus Z80 CPU Module]^4^, 512K w/KIO | RCBus | RCZ80_kio_std.rom | 115200 | -| [RCBus Z180 CPU Module]^4^ w/ ext banking | RCBus | RCZ180_ext_std.rom | 115200 | -| [RCBus Z180 CPU Module]^4^ w/ native banking | RCBus | RCZ180_nat_std.rom | 115200 | -| [RCBus Z280 CPU Module]^4^ w/ ext banking | RCBus | RCZ280_ext_std.rom | 115200 | -| [RCBus Z280 CPU Module]^4^ w/ native banking | RCBus | RCZ280_nat_std.rom | 115200 | -| [RCBus eZ80 CPU Module]^13^, 512K RAM/ROM | RCBus | RCEZ80_std.rom | 115200 | -| [Easy Z80 SBC]^2^ | RCBus | RCZ80_easy_std.rom | 115200 | -| [Tiny Z80 SBC]^2^ | RCBus | RCZ80_tiny_std.rom | 115200 | -| [Z80-512K CPU/RAM/ROM Module]^2^ | RCBus | RCZ80_skz_std.rom | 115200 | -| [Small Computer SC126 Z180 SBC]^5^ | BP80 | SCZ180_sc126_std.rom | 115200 | -| [Small Computer SC130 Z180 SBC]^5^ | RCBus | SCZ180_sc130_std.rom | 115200 | -| [Small Computer SC131 Z180 Pocket Comp]^5^ | - | SCZ180_sc131_std.rom | 115200 | -| [Small Computer SC140 Z180 CPU Module]^5^ | Z50 | SCZ180_sc140_std.rom | 115200 | -| [Small Computer SC503 Z180 CPU Module]^5^ | Z50 | SCZ180_sc503_std.rom | 115200 | -| [Small Computer SC700 Z180 CPU Module]^5^ | RCBus | SCZ180_sc700_std.rom | 115200 | -| [Dyno Z180 SBC]^6^ | Dyno | DYNO_std.rom | 38400 | -| [Nhyodyne Z80 MBC]^1^ | MBC | MBC_std.rom | 38400 | -| [Rhyophyre Z180 SBC]^1^ | - | RPH_std.rom | 38400 | -| [Z80 ZRC CPU Module]^7^ | RCBus | RCZ80_zrc_std.rom | 115200 | -| [Z80 ZRC CPU Module]^7^ ROMless | RCBus | RCZ80_zrc_ram_std.rom | 115200 | -| [Z80 ZRC512 CPU Module]^7^ | RCBus | RCZ80_zrc512_std.rom | 115200 | -| [Z80 EaZy80-512 CPU Module]^7^ | RCBus | RCZ80_ez512_std.rom | 115200 | -| [Z80 K80W CPU Module]^7^ | RCBus | RCZ80_k80w_std.rom | 115200 | -| [Z180 Z1RCC CPU Module]^7^ | RCBus | RCZ180_z1rcc_std.rom | 115200 | -| [Z280 ZZRCC CPU Module]^7^ | RCBus | RCZ280_zzrcc_std.rom | 115200 | -| [Z280 ZZRCC CPU Module]^7^ ROMless | RCBus | RCZ280_zzrcc_ram_std.rom | 115200 | -| [Z280 ZZ80MB SBC]^7^ | RCBus | RCZ280_zz80mb_std.rom | 115200 | -| [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 | -| [S100 Computers Z180]^9^ | S100 | S100_std.rom | 57600 | -| [Duodyne Z80 System]^1^ | Duo | DUO_std.rom | 38400 | -| [Heath H8 Z80 System]^10^ | H8 | HEATH_std.rom | 115200 | -| [EP Mini-ITX Z180]^11^ | RCBus? | EPITX_std.rom | 115200 | -| [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 | -| [S100 FPGA Z80]^9^ | S100 | FZ80_std.rom | 9600 | -| [Genesis STD Z180]^12^ | STD | GMZ180_std.rom | 115200 | - -| ^1^Designed by Andrew Lynch -| ^2^Designed by Sergey Kiselev +| [SC126 Z180 SBC] | BP80 | SCZ180_sc126_std.rom | 115200 | +| [SC130 Z180 SBC] | RCBus | SCZ180_sc130_std.rom | 115200 | +| [SC131 Z180 Pocket Comp] | - | SCZ180_sc131_std.rom | 115200 | +| [SC140 Z180 CPU Module] | Z50 | SCZ180_sc140_std.rom | 115200 | +| [SC503 Z180 CPU Module] | Z50 | SCZ180_sc503_std.rom | 115200 | +| [SC700 Z180 CPU Module] | RCBus | SCZ180_sc700_std.rom | 115200 | + +Others + +| **Description** | **Bus** | **ROM Image File** | **Baud Rate** | +|-------------------------------------------------------------|----------|-----------------------------|--------------:| +| [Dyno Z180 SBC]^6^ | Dyno | DYNO_std.rom | 38400 | +| [EP Mini-ITX Z180]^11^ | UEXT | EPITX_std.rom | 115200 | +| [eZ80 for RCBus Module]^13^, 512K RAM/ROM | RCBus | RCEZ80_std.rom | 115200 | +| [Genesis Z180 System]^12^ | STD | GMZ180_std.rom | 115200 | +| [Heath H8 Z80 System]^10^ | H8 | HEATH_std.rom | 115200 | +| [NABU w/ RomWBW Option Board]^10^ | NABU | NABU_std.rom | 115200 | +| [S100 Computers Z180 SBC]^9^ | S100 | S100_std.rom | 57600 | +| [S100 Computers FPGA Z80 SBC]^9^ | S100 | FZ80_std.rom | 9600 | +| [UNA Hardware BIOS]^3^ | - | UNA_std.rom | - | +| [Z80-Retro SBC]^8^ | - | Z80RETRO_std.rom | 38400 | +| [Z180 Mark IV SBC]^3^ | ECB | MK4_std.rom | 38400 | + | ^3^Designed by John Coffman -| ^4^RCBus compliant (multiple products/designers) -| ^5^Designed by Stephen Cousins | ^6^Designed by Steve Garcia -| ^7^Designed by Bill Shen | ^8^Designed by Peter Wilson | ^9^Designed by John Monahan | ^10^Designed by Les Bird @@ -76,20 +127,9 @@ by RomWBW along with the standard pre-built ROM image(s). | ^12^Designed by Doug Jackson | ^13^Designed by Dean Netherton -RCBus refers to Spencer Owen's RC2014 bus specification and derivatives -including RC26, RC40, RC80, and BP80. +`\clearpage`{=latex} -The RCBus Z180 & Z280 require a separate RAM/ROM memory module. There -are two types of these modules and you must pick the correct ROM for -your type of memory module. The first option is the same as the 512K -RAM/ROM module for RC/BP80 Bus. This is called external ("ext") because -the bank switching is performed externally from the CPU. The second -type of RAM/ROM module has no bank switching logic -- this is called -native ("nat") because the CPU itself provides the bank switching logic. -Only Z180 and Z280 CPUs have the ability to do bank switching in the -CPU, so the ext/nat selection only applies to them. Z80 CPUs have no -built-in bank switching logic, so they are always configured for -external bank switching. +## General Guidance The standard ROM images will detect and install support for certain devices and peripherals that are on-board or frequently used with @@ -100,269 +140,253 @@ In some cases, support for multiple hardware components with potentially conflicting resource usage are handled by a single ROM image. It is up to the user to ensure that no conflicting hardware is in use. +CPU speed will be dynamically measured at startup if DSRTC is present + All pre-built ROM images are pure binary files (they are not "hex" files). They are intended to be programmed starting at the very start of the ROM chip (address 0). Most of the pre-built images are 512KB in size. If your system utilizes a larger ROM, you can just program the image into the first 512KB of the ROM for now. -`\clearpage`{=latex} - -# Platform Configurations - -## RetroBrew Z80 SBC +For this document port addresses `IO=xxx` are represented in decimal. -#### ROM Image File: SBC_std.rom +The PropIO support is based on RomWBW specific firmware. Be sure to +program/update your PropIO firmware with the corresponding firmware +image provided in the Binary directory of the RomWBW distribution. -| | | -|-------------------|---------------| -| Default CPU Speed | 8.000 MHz | -| Interrupts | None | -| System Timer | None | -| Serial Default | 38400 Baud | -| Memory Manager | SBC | -| ROM Size | 512 KB | -| RAM Size | 512 KB | +The use of high density floppy disks requires a CPU speed of 8 MHz or +greater. -#### Supported Hardware +`\clearpage`{=latex} -- DSRTC: MODE=STD, IO=112 -- UART: MODE=SBC, IO=104 -- UART: MODE=CAS, IO=128 -- UART: MODE=MFP, IO=104 -- UART: MODE=4UART, IO=192 -- UART: MODE=4UART, IO=200 -- UART: MODE=4UART, IO=208 -- UART: MODE=4UART, IO=216 -- VGA: IO=224, KBD MODE=PS/2, KBD IO=224 -- CVDU: MODE=ECB, IO=224, KBD MODE=PS/2, KBD IO=226 -- CVDU occupies 905 bytes. -- KBD: ENABLED -- PRP: IO=168 -- PRPCON: ENABLED -- PRPSD: ENABLED -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=DIO, IO=54, DRIVE 0, TYPE=3.5" HD -- FD: MODE=DIO, IO=54, DRIVE 1, TYPE=3.5" HD -- PPIDE: IO=96, MASTER -- PPIDE: IO=96, SLAVE +# Platform Configurations -#### Notes: +## Duodyne Z80 System -- CPU speed will be dynamically measured at startup if DSRTC is present +Duodyne is a third generation ROMWBW focused retrocomputer incorporating lessons +learned and improvements from my original ECB Z80 SBC (aka N8VEM) and the nhyodyne +modular computer. It is literally designed around ROMWBW from the start for a +robust OS and software environment. -`\clearpage`{=latex} +Duodyne is a new design which integrates many functions into larger, modular +boards on a backplane. The intent is to create a powerful and capable system +like an SBC, but with modularity and an expandable backplane. -## RetroBrew Z80 SimH +* Creator: Andrew Lynch +* Retrobrew Forums: [Introducing duodyne retrocomputer](https://www.retrobrewcomputers.org/forum/index.php?t=msg&th=765) +* Github: [DuoDyne](https://github.com/lynchaj/duodyne) -#### ROM Image File: SBC_simh.rom +#### ROM Image File: DUO_std.rom | | | |-------------------|---------------| +| Bus | Duo | | Default CPU Speed | 8.000 MHz | -| Interrupts | Mode 1 | -| System Timer | SimH | +| Interrupts | Mode 2 | +| System Timer | CTC | | Serial Default | 38400 Baud | -| Memory Manager | SBC | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- SIMRTC: IO=254 -- SSER: IO=109 +- FP: LEDIO=66, SWIO=66 +- DSRTC: MODE=STD, IO=148 +- PCF: IO=86 +- UART: IO=88 +- UART: IO=168 +- UART: IO=112 +- UART: IO=120 +- SIO MODE=ZP, IO=96, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=ZP, IO=96, CHANNEL B, INTERRUPTS ENABLED +- LPT: MODE=SPP, IO=72 +- DMA: MODE=DUO, IO=64 +- CH: IO=78 +- CHUSB: IO=78 +- CHSD: IO=78 - MD: TYPE=RAM - MD: TYPE=ROM -- HDSK: IO=253, DEVICE COUNT=2 - +- FD: MODE=DUO, IO=128, DRIVE 0, TYPE=3.5" HD +- FD: MODE=DUO, IO=128, DRIVE 1, TYPE=3.5" HD +- PPIDE: IO=136, MASTER +- PPIDE: IO=136, SLAVE +- SD: MODE=MT, IO=140, UNITS=1 +- SPK: IO=148 +- CTC: IO=96, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED -#### Notes: +`\clearpage`{=latex} -- Image for SimH emulator -- CPU speed and Serial configuration not relevant in emulator +## Dyno Z180 SBC -`\clearpage`{=latex} +The Dyno Computer is a Zilog Z180-based computer initially designed to run Wayne Warthen’s ROMWBW -## RetroBrew N8 Z180 SBC +* Creator: Steve García +* Google Groups: [An Introduction](https://groups.google.com/g/retro-comp/c/niwPLsuc8R0) +* Website: [Dyno Computer](http://dynocomputer.fun/) -#### ROM Image File: N8_std.rom +#### ROM Image File: DYNO_std.rom | | | |-------------------|---------------| +| Bus | Dyno•Bus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | | Serial Default | 38400 Baud | -| Memory Manager | N8 | +| Memory Manager | Z180 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- DSRTC: MODE=STD, IO=136 -- ASCI: IO=64, INTERRUPTS ENABLED -- ASCI: IO=65, INTERRUPTS ENABLED -- TMS: MODE=N8, IO=152, SCREEN=40X24, KEYBOARD=PPK -- PPK: ENABLED +- BQRTC: IO=80 +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=N8, IO=140, DRIVE 0, TYPE=3.5" HD -- FD: MODE=N8, IO=140, DRIVE 1, TYPE=3.5" HD -- SD: MODE=CSIO, IO=136, UNITS=1 -- AY38910: MODE=N8, IO=156, CLOCK=1789772 HZ +- FD: MODE=DYNO, IO=132, DRIVE 0, TYPE=3.5" HD +- FD: MODE=DYNO, IO=132, DRIVE 1, TYPE=3.5" HD +- PPIDE: IO=76, MASTER +- PPIDE: IO=76, SLAVE -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present -- SD Card interface is configured for CSIO (N8 date code >= 2312) +## EP Mini-ITX Z180 -`\clearpage`{=latex} +EtchedPixels Z180 Mini-ITX. The SC126 was almost my ideal retrobrew Z80/Z180 system but +with a couple of niggles and lack of a convenient case option. +This is the same core Z180 CPU/RAM/ROM design taken the other direction, of expandability. -## Zeta Z80 SBC +* Creator: Alan Cox +* Google Groups: [Another new board](https://groups.google.com/g/rc2014-z80/c/rhXBX9ff184) +* Github: [Z180MiniITX](https://github.com/EtchedPixels/Z180MiniITX) -#### ROM Image File: ZETA_std.rom +#### ROM Image File: EPITX_std.rom -| | | -|-------------------|---------------| -| Default CPU Speed | 8.000 MHz | -| Interrupts | None | -| System Timer | None | -| Serial Default | 38400 Baud | -| Memory Manager | SBC | -| ROM Size | 512 KB | -| RAM Size | 512 KB | +| | | +|-------------------|--------------| +| Bus | RCBus + UEXT | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | #### Supported Hardware -- DSRTC: MODE=STD, IO=112 -- UART: IO=104 -- PPP: IO=96 -- PPPCON: ENABLED -- PPPSD: ENABLED +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=160 +- UART: IO=168 +- TMS: MODE=MSX, IO=152, SCREEN=40X24, KEYBOARD=NONE - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=DIO, IO=54, DRIVE 0, TYPE=3.5" HD +- FD: MODE=EPFDC, IO=72, DRIVE 0, TYPE=3.5" HD +- FD: MODE=EPFDC, IO=72, DRIVE 1, TYPE=3.5" HD +- SD: MODE=EPITX, IO=66, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present -- If ParPortProp is installed, initial console output is - determined by JP1: - - Shorted: console to on-board serial port - - Open: console to ParPortProp video and keyboard +## Easy/Tiny Z80 -`\clearpage`{=latex} +### Easy Z80 SBC -## Zeta V2 Z80 SBC +This project is a simple, easy to understand, yet capable single board computer. +It reuses the same memory paging mechanism I've implemented in Zeta SBC V2. +It uses Zilog Z80 SIO/O and Z80 CTC peripheral ICs and implements daisy chain +mode 2 interrupt configuration -#### ROM Image File: ZETA2_std.rom +(Not to be confused with EaZy80) + +* Creator: Sergey Kiselev +* Google Groups: [Easy Z80 - Single Board Computer](https://groups.google.com/g/rc2014-z80/c/UfWIoJgm9Gs) +* Github: [Easy_Z80](https://github.com/skiselev/easy_z80) + +#### ROM Image File: EZZ80_easy_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 8.000 MHz | +| Bus | RCBus | +| Default CPU Speed | 10.000 MHz | | Interrupts | Mode 2 | | System Timer | CTC | -| Serial Default | 38400 Baud | +| Serial Default | 115200 Baud | | Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- DSRTC: MODE=STD, IO=112 -- UART: IO=104 -- PPP: IO=96 -- PPPCON: ENABLED -- PPPSD: ENABLED +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=STD, IO=192 +- INTRTC: ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=STD, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=STD, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=ZETA2, IO=48, DRIVE 0, TYPE=3.5" HD -- CTC: IO=32, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=PIO, IO=105, UNITS=1 +- CTC: IO=136, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present -- If ParPortProp is installed, initial console output is - determined by JP1: - - Shorted: console to on-board serial port - - Open: console to ParPortProp video and keyboard +### Tiny Z80 SBC -`\clearpage`{=latex} +Tiny Z80 is a business card sized (size?!) single board computer (SBC). +It is mostly compatible with Easy Z80, and offers similar capabilities +Tiny Z80 includes a USB to Serial converter IC on board connected to one +of the SIO ports, for ease of use with modern computers. -## Mark IV Z180 SBC +* Creator: Sergey Kiselev +* Github: [Tiny_Z80](https://github.com/skiselev/tiny_z80) -#### ROM Image File: MK4_std.rom +#### ROM Image File: EZZ80_tiny_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | +| Bus | RCBus | +| Default CPU Speed | 16.000 MHz | | Interrupts | Mode 2 | -| System Timer | Z180 | -| Serial Default | 38400 Baud | -| Memory Manager | Z180 | +| System Timer | CTC | +| Serial Default | 115200 Baud | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- DSRTC: MODE=STD, IO=138 -- ASCI: IO=64, INTERRUPTS ENABLED -- ASCI: IO=65, INTERRUPTS ENABLED -- UART: IO=24 -- UART: IO=128 -- UART: IO=192 -- UART: IO=200 -- UART: IO=208 -- UART: IO=216 -- VGA: IO=224, KBD MODE=PS/2, KBD IO=224 -- CVDU: MODE=ECB, IO=224, KBD MODE=PS/2, KBD IO=226 -- KBD: ENABLED -- PRP: IO=168 -- PRPCON: ENABLED -- PRPSD: ENABLED -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=DIDE, IO=42, DRIVE 0, TYPE=3.5" HD -- FD: MODE=DIDE, IO=42, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=MK4, IO=128, MASTER -- IDE: MODE=MK4, IO=128, SLAVE -- SD: MODE=MK4, IO=137, UNITS=1 - -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - -`\clearpage`{=latex} - -## RCBus Z80 CPU Module - -#### ROM Image File: RCZ80_std.rom - -| | | -|-------------------|---------------| -| Default CPU Speed | 7.372 MHz | -| Interrupts | Mode 1 | -| System Timer | None | -| Serial Default | 115200 Baud | -| Memory Manager | Z2 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | - -#### Supported Hardware - -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=STD, IO=192 +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=STD, IO=192 +- INTRTC: ENABLED - UART: IO=128 - UART: IO=136 - UART: IO=160 - UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=STD, IO=24, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=STD, IO=24, CHANNEL B, INTERRUPTS ENABLED - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- ACIA: IO=128, INTERRUPTS ENABLED - CH: IO=62 - CH: IO=60 - CHUSB: IO=62 @@ -371,642 +395,437 @@ program the image into the first 512KB of the ROM for now. - MD: TYPE=ROM - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE +- IDE: MODE=RC, IO=144, MASTER +- IDE: MODE=RC, IO=144, SLAVE - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 +- CTC: IO=16, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +## S100 Computers FPGA Z80 SBC -`\clearpage`{=latex} +An FPGA Z80 based S100 SBC -#### ROM Image File: RCZ80_kio_std.rom +* Creator: John Monahan | +* Website: [S100 Computers FPGA Z80 SBC](http://www.s100computers.com/My%20System%20Pages/FPGA%20Z80%20SBC/FPGA%20Z80%20SBC.htm) + +#### ROM Image File: FZ80_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 7.372 MHz | -| Interrupts | Mode 2 | -| System Timer | CTC | -| Serial Default | 115200 Baud | +| Bus | S100 | +| Default CPU Speed | 8.000 MHz | +| Interrupts | None | +| System Timer | None | +| Serial Default | 9600 Baud | | Memory Manager | Z2 | -| ROM Size | 512 KB | +| ROM Size | 0 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=STD, IO=192 -- INTRTC: ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=STD, IO=136, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=STD, IO=136, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 +- FP: LEDIO=255 +- DS5RTC: RTCIO=104, IO=104 +- SSER: IO=52 +- LPT: MODE=S100, IO=199 +- FV: IO=192, KBD MODE=FV, KBD IO=3 +- KBD: ENABLED +- SCON: IO=0 - MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 -- KIO: IO=128 -- CTC: IO=132, TIMER MODE=TIMER/16, DIVISOR=9216, HI=256, LO=36, INTERRUPTS ENABLED +- PPIDE: IO=48, MASTER +- PPIDE: IO=48, SLAVE +- SD: MODE=FZ80, IO=108, UNITS=2 #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present -- SIO Serial baud rate managed by CTC +- Requires matching FPGA code `\clearpage`{=latex} -## RCBus Z180 CPU Module +## Genesis Z180 System -#### ROM Image File: RCZ180_ext_std.rom +A Z180 based board with 512k ram, 512k rom, dual serial / parallel, RTC and SD Card, based on the STD bus. +This was inspired on Pulsar Little Big board and some designs of Stephen Cousins + +* Creator: [Doug Jackson](https://www.vk1zdj.net/) +* Specific Links not Available + +#### ROM Image File: GMZ180_std.rom | | | |-------------------|---------------| +| Bus | STD | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | | Serial Default | 115200 Baud | -| Memory Manager | Z2 | +| Memory Manager | Z180 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- DSRTC: MODE=STD, IO=12 +- GM7303: IO=48 +- DSRTC: MODE=STD, IO=132 - INTRTC: ENABLED - ASCI: IO=192, INTERRUPTS ENABLED - ASCI: IO=193, INTERRUPTS ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 +- IDE: MODE=GIDE, IO=32, MASTER +- IDE: MODE=GIDE, IO=32, SLAVE +- SD: MODE=GM, IO=132, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- For use with Z2 bank switched memory board (Z2 external memory management) -- CPU speed will be dynamically measured at startup if DSRTC is present +## Heath H8 Z80 System -`\clearpage`{=latex} +Turn your H8 into a RomWBW CP/M computer -#### ROM Image File: RCZ180_nat_std.rom +* Creator: Les Bird +* Github Wiki: [H8-Z80-ROMWBW-V1.0](https://github.com/sebhc/sebhc/wiki/H8-Z80-ROMWBW-V1.0) + +#### ROM Image File: HEATH_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | +| Bus | H8 | +| Default CPU Speed | 16.384 MHz | +| Interrupts | Mode 1 | +| System Timer | None | | Serial Default | 115200 Baud | -| Memory Manager | Z180 | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- DSRTC: MODE=STD, IO=12 +- H8P: IO=240 - INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 +- UART: IO=232 +- UART: IO=224 +- UART: IO=216 +- UART: IO=208 +- TMS: MODE=MSX, IO=152, SCREEN=80X24, KEYBOARD=NONE - MD: TYPE=RAM - MD: TYPE=ROM - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 +- AY38910: MODE=MSX, IO=160, CLOCK=1789772 HZ -#### Notes: +`\clearpage`{=latex} -- For use with linear memory board (Z180 native memory management) -- CPU speed will be dynamically measured at startup if DSRTC is present +## Z180 Mark IV SBC -`\clearpage`{=latex} +The Z180 Mark IV is a single board computer, meaning it may run stand-alone. +It also has an interface to the RetroBrew bus (ECB) for access to additional peripheral boards. -## RCBus Z280 CPU Module +* Creator: John Coffman +* Retrobrew Wiki: [Z180 Mark IV](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:z180_mark_iv:z180_mark_iv) -#### ROM Image File: RCZ280_ext_std.rom +#### ROM Image File: MK4_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 12.000 MHz | -| Interrupts | Mode 1 | -| System Timer | None | -| Serial Default | 115200 Baud | -| Memory Manager | Z2 | +| Bus | ECB | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 38400 Baud | +| Memory Manager | Z180 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=STD, IO=192 -- INTRTC: ENABLED -- Z2U: IO=16 +- DSRTC: MODE=STD, IO=138 +- ASCI: IO=64, INTERRUPTS ENABLED +- ASCI: IO=65, INTERRUPTS ENABLED +- UART: IO=24 - UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- ACIA: IO=128, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 +- UART: IO=192 +- UART: IO=200 +- UART: IO=208 +- UART: IO=216 +- VGA: IO=224, KBD MODE=PS/2, KBD IO=224 +- CVDU: MODE=ECB, IO=224, KBD MODE=PS/2, KBD IO=226 +- KBD: ENABLED +- PRP: IO=168 +- PRPCON: ENABLED +- PRPSD: ENABLED - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 +- FD: MODE=DIDE, IO=42, DRIVE 0, TYPE=3.5" HD +- FD: MODE=DIDE, IO=42, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=MK4, IO=128, MASTER +- IDE: MODE=MK4, IO=128, SLAVE +- SD: MODE=MK4, IO=137, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- For use with Z2 bank switched memory board (Z2 external memory management) +## NABU w/ RomWBW Option Board -`\clearpage`{=latex} +No modifications to the NABU motherboard needed. Leave the standard NABU ROM in its socket +on the motherboard, no need to remove it. You can switch back to standard NABU mode +by changing one jumper on the Option Card -#### ROM Image File: RCZ280_nat_std.rom +* Creator: Les Bird +* Github Wiki: [NABU RomWBW Option Card](https://github.com/sebhc/sebhc/wiki/NABU#nabu-romwbw-option-card) + +#### ROM Image File: NABU_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 12.000 MHz | -| Interrupts | Mode 3 | -| System Timer | Z280 | +| Bus | NABU | +| Default CPU Speed | 3.580 MHz | +| Interrupts | Mode 2 | +| System Timer | TMS | | Serial Default | 115200 Baud | -| Memory Manager | Z280 | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=STD, IO=192 +- NABU: IO=64 - INTRTC: ENABLED -- Z2U: IO=16, INTERRUPTS ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 -- MD: TYPE=RAM +- UART: IO=72 +- TMS: MODE=NABU, IO=160, SCREEN=80X24, KEYBOARD=NABU, INTERRUPTS ENABLED +- NABUKB: IO=144 +- MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 +- PPIDE: IO=96, MASTER +- PPIDE: IO=96, SLAVE +- AY38910: MODE=NABU, IO=65, CLOCK=1789772 HZ #### Notes: -- For use with linear memory board (Z280 native memory management) +- TMS video assumes F18A replacement for TMS9918 `\clearpage`{=latex} -## RCBus eZ80 CPU Module - -#### ROM Image File: RCEZ80_std.rom - -| | | -|-------------------|---------------| -| Default CPU Speed | 20.000 MHz | -| Interrupts | Mode 1 | -| System Timer | EZ80 | -| Serial Default | 115200 Baud | -| Memory Manager | Z2 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | - -#### Supported Hardware +## Nhyodyne Z80 MBC -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- EZ80: CPU DRIVER -- EZ80: SYS TIMER DRIVER -- EZ80: RTC DRIVER -- EZ80: UART DRIVER +Nhyodyne: A Modular Backplane Computer (MBC). -#### Notes: +The purpose of this project is to revisit the design concepts behind my original +Z80 SBC (aka test prototype) which has evolved into the SBC V2-005 over several +years. Attempt to introduce some new concepts to make the design more modular, +flexible, and less expensive. -`\clearpage`{=latex} +The MBC consists of four core boards: Z80 backplane, Z80 processor, Z80 clock, +and Z80 ROM. These are sufficient to build a working system of minimum capability. -## Easy Z80 SBC +* Creator: Andrew Lynch +* Retrobrew Forums: [Z80 Multi Board Computer](https://www.retrobrewcomputers.org/forum/index.php?t=msg&th=568) +* Github: [NhyoDyne](https://github.com/lynchaj/nhyodyne) +* Retrobrew Wiki: [Z80 Modular Backplane Computer](https://www.retrobrewcomputers.org/doku.php?id=builderpages:lynchaj:start) -#### ROM Image File: RCZ80_easy_std.rom +#### ROM Image File: MBC_std.rom -| | | -|-------------------|---------------| -| Default CPU Speed | 10.000 MHz | -| Interrupts | Mode 2 | -| System Timer | CTC | -| Serial Default | 115200 Baud | -| Memory Manager | Z2 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | +| | | +|-------------------|------------| +| Bus | MBC | +| Default CPU Speed | 8.000 MHz | +| Interrupts | None | +| System Timer | None | +| Serial Default | 38400 Baud | +| Memory Manager | MBC | +| ROM Size | 512 KB | +| RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=STD, IO=192 -- INTRTC: ENABLED +- PKD: IO=96, SIZE=8X1 +- DSRTC: MODE=STD, IO=112 +- UART: IO=104 - UART: IO=128 - UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=STD, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=STD, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 +- SIO MODE=ZP, IO=176, CHANNEL A +- SIO MODE=ZP, IO=176, CHANNEL B +- PIO: IO=184, CHANNEL A +- PIO: IO=184, CHANNEL B +- PIO: IO=188, CHANNEL A +- PIO: IO=188, CHANNEL B +- LPT: MODE=SPP, IO=232 +- CVDU: MODE=MBC, IO=224, KBD MODE=PS/2, KBD IO=226 +- TMS: MODE=MBC, IO=152, SCREEN=80X24, KEYBOARD=KBD +- KBD: ENABLED +- ESP: IO=156 +- ESPCON: ENABLED +- ESPSER: DEVICE=0 +- ESPSER: DEVICE=1 - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 -- CTC: IO=136, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED - -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present +- FD: MODE=MBC, IO=48, DRIVE 0, TYPE=3.5" HD +- FD: MODE=MBC, IO=48, DRIVE 1, TYPE=3.5" HD +- PPIDE: IO=96, MASTER +- PPIDE: IO=96, SLAVE +- SPK: IO=112 `\clearpage`{=latex} -## Tiny Z80 SBC - -#### ROM Image File: RCZ80_tiny_std.rom - -| | | -|-------------------|---------------| -| Default CPU Speed | 16.000 MHz | -| Interrupts | Mode 2 | -| System Timer | CTC | -| Serial Default | 115200 Baud | -| Memory Manager | Z2 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | - -#### Supported Hardware - -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=STD, IO=192 -- INTRTC: ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=STD, IO=24, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=STD, IO=24, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=144, MASTER -- IDE: MODE=RC, IO=144, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 -- CTC: IO=16, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED +## RetroBrew Z80 -#### Notes: +### RetroBrew Z80 SBC V2 -- CPU speed will be dynamically measured at startup if DSRTC is present +The SBC V2 is a Zilog Z80 processor board. It's a 100x160mm board that is capable of +functioning both as a standalone SBC or as attached to the ECB bus. -`\clearpage`{=latex} +Previously known as the N8VEM SBC, after Andrews Ham radio call sign, development +began in 2006 wth V1 and is currently still in development, it launched a tsunami +of developments based on the Euro Card Bus (ECB) standard. -## Z80-512K CPU/RAM/ROM Module +* Creator: Andrew Lynch +* Github: [SBC-V2-005](https://github.com/b1ackmai1er/SBC-V2-005) (May not be official) +* Github: [SBC-V2-004](https://github.com/b1ackmai1er/SBC-V2-004) +* Retrobrew Wiki: [SBC V2](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:sbc_v2:start) +* Blog: [Building the SBCV2 Z80](https://simmohacks.com/wordpress/2018/11/17/building-the-retrobrew-computers-ecb-sbcv2-z80-computer) -#### ROM Image File: RCZ80_skz_std.rom +#### ROM Image File: SBC_std.rom -| | | -|-------------------|---------------| -| Default CPU Speed | 7.372 MHz | -| Interrupts | Mode 1 | -| System Timer | None | -| Serial Default | 115200 Baud | -| Memory Manager | Z2 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | +| | | +|-------------------|------------| +| Bus | ECB | +| Default CPU Speed | 8.000 MHz | +| Interrupts | None | +| System Timer | None | +| Serial Default | 38400 Baud | +| Memory Manager | SBC | +| ROM Size | 512 KB | +| RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=STD, IO=192 -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- ACIA: IO=128, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 +- DSRTC: MODE=STD, IO=112 +- UART: MODE=SBC, IO=104 +- UART: MODE=CAS, IO=128 +- UART: MODE=MFP, IO=104 +- UART: MODE=4UART, IO=192 +- UART: MODE=4UART, IO=200 +- UART: MODE=4UART, IO=208 +- UART: MODE=4UART, IO=216 +- VGA: IO=224, KBD MODE=PS/2, KBD IO=224 +- CVDU: MODE=ECB, IO=224, KBD MODE=PS/2, KBD IO=226 +- CVDU occupies 905 bytes. +- KBD: ENABLED +- PRP: IO=168 +- PRPCON: ENABLED +- PRPSD: ENABLED - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=PIO, IO=105, UNITS=1 - -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present +- FD: MODE=DIO, IO=54, DRIVE 0, TYPE=3.5" HD +- FD: MODE=DIO, IO=54, DRIVE 1, TYPE=3.5" HD +- PPIDE: IO=96, MASTER +- PPIDE: IO=96, SLAVE `\clearpage`{=latex} -## Small Computer SC126 Z180 SBC - -#### ROM Image File: SCZ180_sc126_std.rom - -| | | -|-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | -| Serial Default | 115200 Baud | -| Memory Manager | Z180 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | - -#### Supported Hardware - -- FP: LEDIO=13, SWIO=0 -- DSRTC: MODE=STD, IO=12 -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=SC, IO=12, UNITS=1 - -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present -- When disabled, watchdog requires /IM to be pulsed. If an RCBus module - holds the CPU in WAIT for more than this, the watchdog will fire when - disabled with random consequences. The Pico SD does this at power-on. - -`\clearpage`{=latex} +### RetroBrew Z80 SimH -## Small Computer SC130 Z180 SBC +Image for Altair Z80 SimH emulator -#### ROM Image File: SCZ180_sc130_std.rom +#### ROM Image File: SBC_simh.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | -| Serial Default | 115200 Baud | -| Memory Manager | Z180 | +| Bus | - | +| Default CPU Speed | 8.000 MHz | +| Interrupts | Mode 1 | +| System Timer | SimH | +| Serial Default | 38400 Baud | +| Memory Manager | SBC | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0, SWIO=0 -- DSRTC: MODE=STD, IO=12 -- INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 +- SIMRTC: IO=254 +- SSER: IO=109 - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=SC, IO=12, UNITS=1 +- HDSK: IO=253, DEVICE COUNT=2 #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present +- CPU speed and Serial configuration not relevant in emulator `\clearpage`{=latex} -## Small Computer SC131 Z180 Pocket Comp - -#### ROM Image File: SCZ180_sc131_std.rom - -| | | -|-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | -| Serial Default | 115200 Baud | -| Memory Manager | Z180 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | - -#### Supported Hardware - -- INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED -- MD: TYPE=RAM -- MD: TYPE=ROM -- SD: MODE=SC, IO=12, UNITS=1 +## N8 Z180 SBC -#### Notes: +The N8 is intended to be a “home brew” style computer in the style of early 1980's +all-in-one home computers with a usable set of features such as color graphics, +audio, an assortment of mass storage options, a variety of ports, etc. Although +a bus expansion is supported no additional boards are required. -`\clearpage`{=latex} +This configuration is for the N8-2312 and latter (4314) revisions -## Small Computer SC140 Z180 CPU Module +* Creator: Andrew Lynch +* Retrobrew Wiki: [The N8](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:n8:n8) +* Blog: [A Z180 based SBC](https://www.vk1zdj.net/?p=525) -#### ROM Image File: SCZ180_sc140_std.rom +#### ROM Image File: N8_std.rom | | | |-------------------|---------------| +| Bus | ECB | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | -| Serial Default | 115200 Baud | -| Memory Manager | Z180 | +| Serial Default | 38400 Baud | +| Memory Manager | N8 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=160, SWIO=160 -- DSRTC: MODE=STD, IO=12 -- INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED -- UART: IO=128 -- UART: IO=136 -- UART: IO=160 -- UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED -- CH: IO=62 -- CH: IO=60 -- CHUSB: IO=62 -- CHUSB: IO=60 +- DSRTC: MODE=STD, IO=136 +- ASCI: IO=64, INTERRUPTS ENABLED +- ASCI: IO=65, INTERRUPTS ENABLED +- TMS: MODE=N8, IO=152, SCREEN=40X24, KEYBOARD=PPK +- PPK: ENABLED - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=144, MASTER -- IDE: MODE=RC, IO=144, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=SC, IO=12, UNITS=1 +- FD: MODE=N8, IO=140, DRIVE 0, TYPE=3.5" HD +- FD: MODE=N8, IO=140, DRIVE 1, TYPE=3.5" HD +- SD: MODE=CSIO, IO=136, UNITS=1 +- AY38910: MODE=N8, IO=156, CLOCK=1789772 HZ #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present +- SD Card interface is configured for CSIO (N8 date code >= 2312) `\clearpage`{=latex} -## Small Computer SC503 Z180 CPU Module +## RCBus Z80 -#### ROM Image File: SCZ180_sc503_std.rom +### RCBus Z80 CPU Module + +Generic Rom Image. + +#### ROM Image File: RCZ80_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | +| Bus | RCBus | +| Default CPU Speed | 7.372 MHz | +| Interrupts | Mode 1 | +| System Timer | None | | Serial Default | 115200 Baud | -| Memory Manager | Z180 | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=160, SWIO=160 -- DSRTC: MODE=STD, IO=12 -- INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=STD, IO=192 - UART: IO=128 - UART: IO=136 - UART: IO=160 @@ -1015,6 +834,7 @@ program the image into the first 512KB of the ROM for now. - SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED - SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED - SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED - CH: IO=62 - CH: IO=60 - CHUSB: IO=62 @@ -1023,185 +843,133 @@ program the image into the first 512KB of the ROM for now. - MD: TYPE=ROM - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=144, MASTER -- IDE: MODE=RC, IO=144, SLAVE +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -- SD: MODE=SC, IO=12, UNITS=1 - -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present +- SD: MODE=PIO, IO=105, UNITS=1 `\clearpage`{=latex} -## Small Computer SC700 Z180 CPU Module +### RCBus Z80 CPU Module (KIO) -#### ROM Image File: SCZ180_sc700_std.rom +Generic Rom Image. SIO Serial baud rate managed by CTC + +#### ROM Image File: RCZ80_kio_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | +| Bus | RCBus | +| Default CPU Speed | 7.372 MHz | | Interrupts | Mode 2 | -| System Timer | Z180 | +| System Timer | CTC | | Serial Default | 115200 Baud | -| Memory Manager | Z180 | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=0 -- LCD: IO=170, SIZE=20X4 -- DSRTC: MODE=STD, IO=12 +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=STD, IO=192 - INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED - UART: IO=128 - UART: IO=136 - UART: IO=160 - UART: IO=168 -- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=STD, IO=136, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=STD, IO=136, CHANNEL B, INTERRUPTS ENABLED - CH: IO=62 - CH: IO=60 - CHUSB: IO=62 -- CHUSB: IO=60 -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD -- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD -- IDE: MODE=RC, IO=16, MASTER -- IDE: MODE=RC, IO=16, SLAVE -- PPIDE: IO=32, MASTER -- PPIDE: IO=32, SLAVE -- SD: MODE=SC, IO=12, UNITS=1 - -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present - -`\clearpage`{=latex} - -## Dyno Z180 SBC - -#### ROM Image File: DYNO_std.rom - -| | | -|-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | -| Serial Default | 38400 Baud | -| Memory Manager | Z180 | -| ROM Size | 512 KB | -| RAM Size | 512 KB | - -#### Supported Hardware - -- BQRTC: IO=80 -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=DYNO, IO=132, DRIVE 0, TYPE=3.5" HD -- FD: MODE=DYNO, IO=132, DRIVE 1, TYPE=3.5" HD -- PPIDE: IO=76, MASTER -- PPIDE: IO=76, SLAVE - -#### Notes: - -`\clearpage`{=latex} - -## Nhyodyne Z80 MBC - -#### ROM Image File: MBC_std.rom - -| | | -|-------------------|---------------| -| Default CPU Speed | 8.000 MHz | -| Interrupts | None | -| System Timer | None | -| Serial Default | 38400 Baud | -| Memory Manager | MBC | -| ROM Size | 512 KB | -| RAM Size | 512 KB | - -#### Supported Hardware - -- PKD: IO=96, SIZE=8X1 -- DSRTC: MODE=STD, IO=112 -- UART: IO=104 -- UART: IO=128 -- UART: IO=136 -- SIO MODE=ZP, IO=176, CHANNEL A -- SIO MODE=ZP, IO=176, CHANNEL B -- PIO: IO=184, CHANNEL A -- PIO: IO=184, CHANNEL B -- PIO: IO=188, CHANNEL A -- PIO: IO=188, CHANNEL B -- LPT: MODE=SPP, IO=232 -- CVDU: MODE=MBC, IO=224, KBD MODE=PS/2, KBD IO=226 -- TMS: MODE=MBC, IO=152, SCREEN=80X24, KEYBOARD=KBD -- KBD: ENABLED -- ESP: IO=156 -- ESPCON: ENABLED -- ESPSER: DEVICE=0 -- ESPSER: DEVICE=1 -- MD: TYPE=RAM -- MD: TYPE=ROM -- FD: MODE=MBC, IO=48, DRIVE 0, TYPE=3.5" HD -- FD: MODE=MBC, IO=48, DRIVE 1, TYPE=3.5" HD -- PPIDE: IO=96, MASTER -- PPIDE: IO=96, SLAVE -- SPK: IO=112 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=PIO, IO=105, UNITS=1 +- KIO: IO=128 +- CTC: IO=132, TIMER MODE=TIMER/16, DIVISOR=9216, HI=256, LO=36, INTERRUPTS ENABLED -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +### Z80-512K CPU/RAM/ROM Module -`\clearpage`{=latex} +Z80-512K is an RCBus and RC2014* compatible module, designed to run RomWBW firmware +including CP/M, ZSDOS, and various applications under these OSes. Z80-512K combines +functionality of CPU, RAM, and ROM on a single module, thus saving space on the backplane. -## Rhyophyre Z180 SBC +* Creator: Sergey Kiselev +* Google Groups: [Z80-512K](https://groups.google.com/g/rc2014-z80/c/SkOqm_LX910) +* Github: [Z80-512K](https://github.com/skiselev/Z80-512K) -#### ROM Image File: RPH_std.rom +#### ROM Image File: RCZ80_skz_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | None | +| Bus | RCBus | +| Default CPU Speed | 7.372 MHz | +| Interrupts | Mode 1 | | System Timer | None | -| Serial Default | 38400 Baud | -| Memory Manager | RPH | +| Serial Default | 115200 Baud | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- DSRTC: MODE=STD, IO=132 -- ASCI: IO=64 -- ASCI: IO=65 -- GDC: MODE=RPH, DISPLAY=EGA, IO=144 -- KBD: ENABLED +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=STD, IO=192 +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 - MD: TYPE=RAM - MD: TYPE=ROM -- PPIDE: IO=136, MASTER -- PPIDE: IO=136, SLAVE +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZRC Z80 CPU Module -`\clearpage`{=latex} +ZRC is derived from the ZoRC experiment. The basic notion is that large RAM and fast +serial upload enable a diskless CP/M SBC. However, just in case that idea didn't work +out, ZRC has an optional compact flash interface. The targeted software for ZRC is ROMWBW. +ZRC physically contains no ROM and 2MB of RAM. + +In the STD configuration the first 512KB of RAM is loaded with a ROM image from disk +storage and then handled like ROM. Essentially, an area of the RAM is reserved to act as ROM. -## Z80 ZRC CPU Module +* Creator: Bill Shen +* Retrobrew Wiki: [ZRC, Z80 RAM CPLD for ROMWBW](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrc) +* Google Groups: [ZRC, Z80/RAM/CPLD, minimal CP/M-ready, Z80 SBC](https://groups.google.com/g/retro-comp/c/L3W7TaDnX5A/m/ZxOgl8EIAQAJ) #### ROM Image File: RCZ80_zrc_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -1240,18 +1008,27 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- ZRC is actually contains no ROM and 2MB of RAM. The first 512KB - of RAM is loaded from disk and then handled like ROM. -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZRC Z80 CPU Module (RAM) -`\clearpage`{=latex} +This profile differs (from STD) only in how the system boots, and how RAM is configured. +Boot occurs directly to RAM, loading HBIOS directly from disk storage rather than via +a pseudo ROM image copied into RAM. + +A RAM disk is configured preloaded with files that would normally be on the ROM disk. +There is no ROM disk in this configuration. + +The RAM config is the newer approach and provides a more efficient bank layout. +The intent to replace the STD config with the RAM config. + +* Creator: Bill Shen #### ROM Image File: RCZ80_zrc_ram_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -1289,19 +1066,22 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZRC512 Z80 CPU Module -`\clearpage`{=latex} +ZRC512 is a faster and hobbyist-friendly variant of ZRC. +It is designed specifically for ROM-less RomWBW. HBIOS is loaded from disk at boot -## Z80 ZRC512 CPU Module +* Creator: Bill Shen +* Google Groups: [Bill Shen's ZRC512 SBC / RC2014 board](https://groups.google.com/g/retro-comp/c/bILDMVI97vo) +* Retrobrew Wiki: [ZRC512, A Hobbyist-friendly Z80 SBC for ROM-less RomWBW](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zrc512:zrc512home) #### ROM Image File: RCZ80_zrc512_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 22.000 MHz | | Interrupts | Mode 1 | | System Timer | None | @@ -1339,19 +1119,27 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present +### EaZy80-512 Z80 CPU Module -`\clearpage`{=latex} +Eazy80-512 is Eazy80 rev2 pc board configured with 512K RAM to run RomWBW. +The design was derived from modifications to Eazy80 Rev1 that supported RomWBW. -## Z80 EaZy80-512 CPU Module +HBIOS is loaded from disk at boot by ROM monitor + +(Not to be confused with EasyZ80) + +* Creator: Bill Shen +* VCF Forums: [Eazy80, a glue-less, CP/M capable Z80 SBC](https://forum.vcfed.org/index.php?threads/eazy80-a-glue-less-cp-m-capable-z80-sbc.1251160) +* Retrobrew Wiki: [Eazy80 Rev2, Glue-less Configuration](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:eazy80:eazy80rev2:eazy80rev2home) +* Google Groups: [EaZy80, A Simple80 with KIO](https://groups.google.com/g/retro-comp/c/0cUDbZspHyQ) #### ROM Image File: RCZ80_ez512_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 22.000 MHz | | Interrupts | Mode 2 | | System Timer | None | @@ -1371,21 +1159,226 @@ program the image into the first 512KB of the ROM for now. - KIO: IO=0 - CTC: IO=4 -#### Notes: +`\clearpage`{=latex} + +### K80W Z80 CPU Module + +K80W is similar to K80. It is a 22MHz Z80 SBC with KIO (Z84C90) as the I/O device. +It is designed to run RomWBW. The current version is rev 2.1 replacing the older K80W rev 1 + +* Creator: Bill Shen +* Retrobrew Wiki: [K80W Rev2.1, A RomWBW-capable Z80 SBC](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:k80:k80w_r21) + +#### ROM Image File: RCZ80_k80w_std.rom + +| | | +|-------------------|---------------| +| Bus | RCBus | +| Default CPU Speed | 22.000 MHz | +| Interrupts | Mode 2 | +| System Timer | None | +| Serial Default | 115200 Baud | +| Memory Manager | Z2 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=K80W, IO=192 +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=STD, IO=136, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=STD, IO=136, CHANNEL B, INTERRUPTS ENABLED +- VRC: IO=0, KBD MODE=VRC, KBD IO=244 +- KBD: ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=EZ512, IO=130, UNITS=1 +- KIO: IO=128 +- CTC: IO=132 + +`\clearpage`{=latex} + +## RCBus Z180 + +### RCBus Z180 CPU Module (External) + +Generic Rom Image. For use with Z2 bank switched memory board (Z2 external memory management) + +#### ROM Image File: RCZ180_ext_std.rom + +| | | +|-------------------|---------------| +| Bus | RCBus | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z2 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=PIO, IO=105, UNITS=1 + +`\clearpage`{=latex} + +### RCBus Z180 CPU Module (Native) + +Generic Rom Image. For use with linear memory board (Z180 native memory management) + +#### ROM Image File: RCZ180_nat_std.rom + +| | | +|-------------------|---------------| +| Bus | RCBus | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=PIO, IO=105, UNITS=1 + +`\clearpage`{=latex} + +### Z1RCC Z180 CPU Module + +Z1RCC is a 2“x4” RomWBW-capable Z180 SBC. + +Z1RCC has no flash memory on board but has a small (64 bytes) bootstrap ROM in CPLD +so that Z180 boots from this bootstrap ROM, copies a loader from CF disk to top 32K of RAM, +runs the loader to bring in the 480K RomWBW image from CF disk, then start RomWBW from 0x0 + +* Creator: Bill Shen +* Google Groups: [RomWBW for Z80 with 512K RAM 0K ROM](https://groups.google.com/g/retro-comp/c/29DOV4eO6MU) +* Retrobrew Wiki: [Z1RCC, A RC2014-Compatible, RomWBW-Capable Z180 SBC](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:z1rcc:rev0:home) + +#### ROM Image File: RCZ180_z1rcc_std.rom + +| | | +|-------------------|---------------| +| Bus | RCBus | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | +| ROM Size | 0 KB | +| RAM Size | 512 KB | + +#### Supported Hardware -- HBIOS is loaded from disk at boot by ROM monitor -- CPU speed will be dynamically measured at startup if DSRTC is present +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=PIO, IO=105, UNITS=1 `\clearpage`{=latex} -## Z80 K80W CPU Module +## RCBus Z280 -#### ROM Image File: RCZ80_k80w_std.rom +### RCBus Z280 CPU Module (External) + +Generic Rom Image. For use with Z2 bank switched memory board (Z2 external memory management) + +#### ROM Image File: RCZ280_ext_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 22.000 MHz | -| Interrupts | Mode 2 | +| Bus | RCBus | +| Default CPU Speed | 12.000 MHz | +| Interrupts | Mode 1 | | System Timer | None | | Serial Default | 115200 Baud | | Memory Manager | Z2 | @@ -1396,15 +1389,18 @@ program the image into the first 512KB of the ROM for now. - FP: LEDIO=0, SWIO=0 - LCD: IO=218, SIZE=20X4 -- DSRTC: MODE=K80W, IO=192 +- DSRTC: MODE=STD, IO=192 +- INTRTC: ENABLED +- Z2U: IO=16 - UART: IO=128 - UART: IO=136 - UART: IO=160 - UART: IO=168 -- SIO MODE=STD, IO=136, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=STD, IO=136, CHANNEL B, INTERRUPTS ENABLED -- VRC: IO=0, KBD MODE=VRC, KBD IO=244 -- KBD: ENABLED +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- ACIA: IO=128, INTERRUPTS ENABLED - CH: IO=62 - CH: IO=60 - CHUSB: IO=62 @@ -1417,37 +1413,34 @@ program the image into the first 512KB of the ROM for now. - IDE: MODE=RC, IO=16, SLAVE - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -- SD: MODE=EZ512, IO=130, UNITS=1 -- KIO: IO=128 -- CTC: IO=132 - -#### Notes: - -- CPU speed will be dynamically measured at startup if DSRTC is present +- SD: MODE=PIO, IO=105, UNITS=1 `\clearpage`{=latex} -## Z180 Z1RCC CPU Module +### RCBus Z280 CPU Module (Native) -#### ROM Image File: RCZ180_z1rcc_std.rom +Generic Rom Image. For use with linear memory board (Z280 native memory management) + +#### ROM Image File: RCZ280_nat_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | -| Interrupts | Mode 2 | -| System Timer | Z180 | +| Bus | RCBus | +| Default CPU Speed | 12.000 MHz | +| Interrupts | Mode 3 | +| System Timer | Z280 | | Serial Default | 115200 Baud | -| Memory Manager | Z180 | -| ROM Size | 0 KB | +| Memory Manager | Z280 | +| ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware - FP: LEDIO=0, SWIO=0 -- DSRTC: MODE=STD, IO=12 +- LCD: IO=218, SIZE=20X4 +- DSRTC: MODE=STD, IO=192 - INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED +- Z2U: IO=16, INTERRUPTS ENABLED - UART: IO=128 - UART: IO=136 - UART: IO=160 @@ -1461,6 +1454,7 @@ program the image into the first 512KB of the ROM for now. - CHUSB: IO=62 - CHUSB: IO=60 - MD: TYPE=RAM +- MD: TYPE=ROM - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD - IDE: MODE=RC, IO=16, MASTER @@ -1469,19 +1463,28 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, SLAVE - SD: MODE=PIO, IO=105, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZZRCC Z280 CPU Module -`\clearpage`{=latex} +ZZRCC follows the basic concept of ZRCC that uses a small CPLD to bootstrap from CF disk. +Because Z280 has a native serial-bootstrap capability, the CPLD is even simpler than that +of ZRCC. ZZRCC is Z280 operating in Z80-compatible mode. It is designed for RC2014 bus +ZZRCC actually contains no ROM and 512KB of RAM. + +In the STD configuration the first 256KB of RAM is loaded with a ROM image from disk +storage and then handled like ROM. Essentially, an area of the RAM is reserved to act as ROM. -## Z280 ZZRCC CPU Module +* Creator: Bill Shen +* Retrobrew Wiki: [ZZRCC, a SBC for RC2014 based on Z280](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zzrcc) +* Google Groups: [ZZRCC, Z280 SBC replacing ZZ80RC and ZZ80CF](https://groups.google.com/g/retro-comp/c/lt1t3JEoiCM/m/NYeZdrFuAAAJ) +* Google Groups: [Help porting ROMWBW to ZZRCC](https://groups.google.com/g/retro-comp/c/mBIWW18WXTE/m/E_sehx5fAwAJ) #### ROM Image File: RCZ280_zzrcc_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 3 | | System Timer | Z280 | @@ -1520,18 +1523,27 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -#### Notes: +`\clearpage`{=latex} -- ZZRCC actually contains no ROM and 512KB of RAM. The first 256KB - of RAM is loaded from disk and then handled like ROM. -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZZRCC Z280 CPU Module (RAM) -`\clearpage`{=latex} +This profile differs (from STD) only in how the system boots, and how RAM is configured. +Boot occurs directly to RAM, loading HBIOS directly from disk storage rather than via +a pseudo ROM image copied into RAM. + +A RAM disk is configured preloaded with files that would normally be on the ROM disk. +There is no ROM disk in this configuration. + +The RAM config is the newer approach and provides a more efficient bank layout. +The intent to replace the STD config with the RAM config. + +* Creator: Bill Shen #### ROM Image File: RCZ280_zzrcc_ram_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 14.745 MHz | | Interrupts | Mode 3 | | System Timer | Z280 | @@ -1569,19 +1581,23 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -#### Notes: +`\clearpage`{=latex} -- ROMless boot -- HBIOS is loaded from disk at boot -- CPU speed will be dynamically measured at startup if DSRTC is present +### ZZ80MB Z280 SBC -`\clearpage`{=latex} +ZZ80MB is a Z280-based motherboard with RC2014 expansion slots. It is based on the ZZ80RC-CF design, +but with two additional expansion slots added. ZZ80MB is designed with an EPROM programmer function +such that it can boot from serial port, load EPROM programming image through the serial port +and program an EPROM. This feature can be used to program EPROM for other computers -## Z280 ZZ80MB SBC +* Creator: Bill Shen +* Retrobrew Wiki: [ZZ80MB, A Z280-based SBC with RC2014 Expansion](https://www.retrobrewcomputers.org/doku.php?id=builderpages:plasmo:zz80mb:zz80mbr3) #### ROM Image File: RCZ280_zz80mb_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 12.000 MHz | | Interrupts | Mode 3 | | System Timer | Z280 | @@ -1620,48 +1636,274 @@ program the image into the first 512KB of the ROM for now. - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -#### Notes: +`\clearpage`{=latex} + +## eZ80 for RCBus Module -- CPU speed will be dynamically measured at startup if DSRTC is present +The eZ80 for RCBus/RC2014 is a module designed for the RCBus and RC2014 backplanes. + +Its designed as a 'compatible upgrade' to the stock Z80 CPU. The eZ80 is a CPU that was +first released by Zilog about 20 years ago, and still available from the manufacturer today + +* Creator: Dean Netherton +* Github: [eZ80 for the RCBus/RC2014](https://github.com/dinoboards/ez80-for-rc) +* Hackaday: [eZ80 CPU for RC2014 and other backplanes](https://hackaday.io/project/196330-ez80-cpu-for-rc2014-and-other-backplanes) + +#### ROM Image File: RCEZ80_std.rom + +| | | +|-------------------|---------------| +| Bus | RCBus | +| Default CPU Speed | 20.000 MHz | +| Interrupts | Mode 1 | +| System Timer | EZ80 | +| Serial Default | 115200 Baud | +| Memory Manager | Z2 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- FP: LEDIO=0, SWIO=0 +- LCD: IO=218, SIZE=20X4 +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- EZ80: CPU DRIVER +- EZ80: SYS TIMER DRIVER +- EZ80: RTC DRIVER +- EZ80: UART DRIVER `\clearpage`{=latex} -## Z80-Retro SBC +## Rhyophyre Z180 SBC -#### ROM Image File: Z80RETRO_std.rom +Single Board Computer featuring Zilog Z180 processor and NEC µPD7220 +Graphics Display Controller + +* Creator: Andrew Lynch +* Retrobrew Forums: [Z180 upd7220 GDC SBC](https://www.retrobrewcomputers.org/forum/index.php?t=msg&th=699) +* Github: [rhyophyre](https://github.com/lynchaj/rhyophyre) + +#### ROM Image File: RPH_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 14.745 MHz | -| Interrupts | Mode 2 | +| Bus | - | +| Default CPU Speed | 18.432 MHz | +| Interrupts | None | | System Timer | None | | Serial Default | 38400 Baud | -| Memory Manager | Z2 | +| Memory Manager | RPH | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- SIO MODE=Z80R, IO=128, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=Z80R, IO=128, CHANNEL B, INTERRUPTS ENABLED +- DSRTC: MODE=STD, IO=132 +- ASCI: IO=64 +- ASCI: IO=65 +- GDC: MODE=RPH, DISPLAY=EGA, IO=144 +- KBD: ENABLED - MD: TYPE=RAM - MD: TYPE=ROM -- SD: MODE=Z80R, IO=104, UNITS=1 +- PPIDE: IO=136, MASTER +- PPIDE: IO=136, SLAVE + +`\clearpage`{=latex} + +## S100 Computers Z180 SBC + +A Z180 board which contains a flash RAM, a USB port interface and an SD Card that can immediately boot up CPM. +While it is on an S100 Bus board, initially that board has only 8 significant chips and works as a self contained +computer outside the bus with a simple 9V power supply. + +Later on it can be built up further with more chips, placed in an S100 bus and one by one programed to interface +with the 100's of S100 bus cards that are out there. It can in fact behave as a S100 bus master or slave +as defined by the IEEE-696 specs. + +* Creator: John Monahan | +* Website: [S100 Computers Z180 SBC](http://www.s100computers.com/My%20System%20Pages/Z180%20SBC/Z180%20SBC.htm) + +#### ROM Image File: S100_std.rom + +| | | +|-------------------|---------------| +| Bus | S100 | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 57600 Baud | +| Memory Manager | Z180 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- SCON: IO=0 +- MD: TYPE=RAM +- MD: TYPE=ROM +- SD: MODE=SC, IO=12, UNITS=1 + +#### Notes: + +- Z180 SBC SW2 (IOBYTE) Dip Switches: + +| Bit | Setting | Function | +|-----|---------|-------------------------------------| +| 0 | Off | Use Z180 ASCI Channel A for console | +| | On | Use Propeller Console | +| | | | +| 1 | Off | Boot to RomWBW Boot Loader | +| | On | Boot to S100 Monitor | + +`\clearpage`{=latex} + +## Small Computer Central Z180 + +Small Computer Central provides an extensive range hardware based around the +Zilog ecosystem. This section lists configurations specifically for the Z180 processor + +If you are using a Z80 processor you will probably be using the general `RCZ80_std` +configuration - [RCBus Z80 CPU Module]. However, please consult +[Firmware, RomWBW, RCZ80_std](https://smallcomputercentral.com/firmware/firmware-romwbw-rcz80_std/) +for further information and to ensure compatibility with your Z80 system. + +* Creator: Stephen Cousins +* Website: [Small Computer Central](https://smallcomputercentral.com) + +### SC126 Z180 SBC + +SC126 is a Z180 Motherboard. + +* Website: [SC126 – Z180 Motherboard](https://smallcomputercentral.com/rcbus/sc100-series/sc126-z180-motherboard-rc2014/) + +#### ROM Image File: SCZ180_sc126_std.rom + +| | | +|-------------------|---------------| +| Bus | BP80 | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- FP: LEDIO=13, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 #### Notes: +- When disabled, watchdog requires /IM to be pulsed. If an RCBus module + holds the CPU in WAIT for more than this, the watchdog will fire when + disabled with random consequences. The Pico SD does this at power-on. + +`\clearpage`{=latex} + +### SC130 Z180 SBC + +SC130 is an entry-level Z180 Motherboard designed primarily to run RomWBW (and CP/M) + +* Website: [SC130 – Z180 Motherboard](https://smallcomputercentral.com/rcbus/sc100-series/sc130-z180-motherboard) + +#### ROM Image File: SCZ180_sc130_std.rom + +| | | +|-------------------|---------------| +| Bus | RCBus | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | +| ROM Size | 512 KB | +| RAM Size | 512 KB | + +#### Supported Hardware + +- FP: LEDIO=0, SWIO=0 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 +- MD: TYPE=RAM +- MD: TYPE=ROM +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 + `\clearpage`{=latex} -## S100 Computers Z180 +### SC131 Z180 Pocket Comp -#### ROM Image File: S100_std.rom +SC131 is a pocket-sized Z180 RomWBW CP/M computer. + +* Website: [SC131 – Z180 Pocket Computer](https://smallcomputercentral.com/sc131-z180-pocket-computer/) + +#### ROM Image File: SCZ180_sc131_std.rom | | | |-------------------|---------------| +| Bus | - | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | -| Serial Default | 57600 Baud | +| Serial Default | 115200 Baud | | Memory Manager | Z180 | | ROM Size | 512 KB | | RAM Size | 512 KB | @@ -1671,112 +1913,126 @@ program the image into the first 512KB of the ROM for now. - INTRTC: ENABLED - ASCI: IO=192, INTERRUPTS ENABLED - ASCI: IO=193, INTERRUPTS ENABLED -- SCON: IO=0 - MD: TYPE=RAM - MD: TYPE=ROM - SD: MODE=SC, IO=12, UNITS=1 -#### Notes: - -- Z180 SBC SW2 (IOBYTE) Dip Switches: +`\clearpage`{=latex} -| Bit | Setting | Function | -|-----|---------|-------------------------------------| -| 0 | Off | Use Z180 ASCI Channel A for console | -| | On | Use Propeller Console | -| | | | -| 1 | Off | Boot to RomWBW Boot Loader | -| | On | Boot to S100 Monitor | +### SC140 Z180 CPU Module -`\clearpage`{=latex} +SC140 is a Z180 SBC / Z50Bus Card card. -## Duodyne Z80 System +* Website: [SC140 – Z180 SBC / Z50Bus Card](https://smallcomputercentral.com/z50bus-4/sc140-z180-sbc-z50bus-card/) -#### ROM Image File: DUO_std.rom +#### ROM Image File: SCZ180_sc140_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 8.000 MHz | +| Bus | Z50 | +| Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | -| System Timer | CTC | -| Serial Default | 38400 Baud | -| Memory Manager | Z2 | +| System Timer | Z180 | +| Serial Default | 115200 Baud | +| Memory Manager | Z180 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=66, SWIO=66 -- DSRTC: MODE=STD, IO=148 -- PCF: IO=86 -- UART: IO=88 +- FP: LEDIO=160, SWIO=160 +- DSRTC: MODE=STD, IO=12 +- INTRTC: ENABLED +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 - UART: IO=168 -- UART: IO=112 -- UART: IO=120 -- SIO MODE=ZP, IO=96, CHANNEL A, INTERRUPTS ENABLED -- SIO MODE=ZP, IO=96, CHANNEL B, INTERRUPTS ENABLED -- LPT: MODE=SPP, IO=72 -- DMA: MODE=DUO, IO=64 -- CH: IO=78 -- CHUSB: IO=78 -- CHSD: IO=78 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=DUO, IO=128, DRIVE 0, TYPE=3.5" HD -- FD: MODE=DUO, IO=128, DRIVE 1, TYPE=3.5" HD -- PPIDE: IO=136, MASTER -- PPIDE: IO=136, SLAVE -- SD: MODE=MT, IO=140, UNITS=1 -- SPK: IO=148 -- CTC: IO=96, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=144, MASTER +- IDE: MODE=RC, IO=144, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- CPU speed will be dynamically measured at startup if DSRTC is present +### SC503 Z180 CPU Module -`\clearpage`{=latex} +SC503 is a Z180 Processor card designed for Z50Bus. -## Heath H8 Z80 System +* Website: [SC503 – Z180 Processor (Z50Bus)](https://smallcomputercentral.com/z50bus-4/sc503-z180-processor-z50bus/) -#### ROM Image File: HEATH_std.rom +#### ROM Image File: SCZ180_sc503_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 16.384 MHz | -| Interrupts | Mode 1 | -| System Timer | None | +| Bus | Z50 | +| Default CPU Speed | 18.432 MHz | +| Interrupts | Mode 2 | +| System Timer | Z180 | | Serial Default | 115200 Baud | -| Memory Manager | Z2 | +| Memory Manager | Z180 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- H8P: IO=240 +- FP: LEDIO=160, SWIO=160 +- DSRTC: MODE=STD, IO=12 - INTRTC: ENABLED -- UART: IO=232 -- UART: IO=224 -- UART: IO=216 -- UART: IO=208 -- TMS: MODE=MSX, IO=152, SCREEN=80X24, KEYBOARD=NONE +- ASCI: IO=192, INTERRUPTS ENABLED +- ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 +- UART: IO=160 +- UART: IO=168 +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 - MD: TYPE=RAM - MD: TYPE=ROM - FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD - FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=144, MASTER +- IDE: MODE=RC, IO=144, SLAVE - PPIDE: IO=32, MASTER - PPIDE: IO=32, SLAVE -- AY38910: MODE=MSX, IO=160, CLOCK=1789772 HZ - -#### Notes: +- SD: MODE=SC, IO=12, UNITS=1 `\clearpage`{=latex} -## EP Mini-ITX Z180 +### SC700 Z180 CPU Module -#### ROM Image File: EPITX_std.rom +This configuration is specifically for systems based on the +Z180 CPU (eg. SC722) with 1MB linear memory (eg. SC721) + +* Website: [SC700 Series](https://smallcomputercentral.com/rcbus/sc700-series/) +* Website: [SC721 – RCBus Memory Module](https://smallcomputercentral.com/rcbus/sc700-series/sc721-rcbus-memory-module/) +* Website: [SC722 – RCBus Z180 CPU Module](https://smallcomputercentral.com/rcbus/sc700-series/sc722-rcbus-z180-cpu-module/) + +#### ROM Image File: SCZ180_sc700_std.rom | | | |-------------------|---------------| +| Bus | RCBus | | Default CPU Speed | 18.432 MHz | | Interrupts | Mode 2 | | System Timer | Z180 | @@ -1787,118 +2043,159 @@ program the image into the first 512KB of the ROM for now. #### Supported Hardware +- FP: LEDIO=0 +- LCD: IO=170, SIZE=20X4 +- DSRTC: MODE=STD, IO=12 - INTRTC: ENABLED - ASCI: IO=192, INTERRUPTS ENABLED - ASCI: IO=193, INTERRUPTS ENABLED +- UART: IO=128 +- UART: IO=136 - UART: IO=160 - UART: IO=168 -- TMS: MODE=MSX, IO=152, SCREEN=40X24, KEYBOARD=NONE +- SIO MODE=RC, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=128, CHANNEL B, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=RC, IO=132, CHANNEL B, INTERRUPTS ENABLED +- CH: IO=62 +- CH: IO=60 +- CHUSB: IO=62 +- CHUSB: IO=60 - MD: TYPE=RAM - MD: TYPE=ROM -- FD: MODE=EPFDC, IO=72, DRIVE 0, TYPE=3.5" HD -- FD: MODE=EPFDC, IO=72, DRIVE 1, TYPE=3.5" HD -- SD: MODE=EPITX, IO=66, UNITS=1 +- FD: MODE=RCWDC, IO=80, DRIVE 0, TYPE=3.5" HD +- FD: MODE=RCWDC, IO=80, DRIVE 1, TYPE=3.5" HD +- IDE: MODE=RC, IO=16, MASTER +- IDE: MODE=RC, IO=16, SLAVE +- PPIDE: IO=32, MASTER +- PPIDE: IO=32, SLAVE +- SD: MODE=SC, IO=12, UNITS=1 -#### Notes: +\clearpage`{=latex} -`\clearpage`{=latex} +## Z80-Retro SBC -## NABU w/ RomWBW Option Board +The system comprises a Z80 retro computer board, and optonal VGA text video card, +and PIO Keyboard and Sound Card. The system uses a custom 60 pin bus on a standard header. -#### ROM Image File: NABU_std.rom +(Not to be confused with a similar named project by +John Winans presented by John's Basement on youTube) + +* Creator: Peter Wilson +* Github: [Z80-Retro](https://github.com/peterw8102/Z80-Retro) +* Github Wiki: [Welcome to the Z80-Retro wiki!](https://github.com/peterw8102/Z80-Retro/wiki) +* OSHWLab: [Simple Z80 SBC](https://oshwlab.com/peterw8102/simple-z80) + +#### ROM Image File: Z80RETRO_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 3.580 MHz | +| Bus | 60 pin | +| Default CPU Speed | 14.745 MHz | | Interrupts | Mode 2 | -| System Timer | TMS | -| Serial Default | 115200 Baud | +| System Timer | None | +| Serial Default | 38400 Baud | | Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- NABU: IO=64 -- INTRTC: ENABLED -- UART: IO=72 -- TMS: MODE=NABU, IO=160, SCREEN=80X24, KEYBOARD=NABU, INTERRUPTS ENABLED -- NABUKB: IO=144 +- SIO MODE=Z80R, IO=128, CHANNEL A, INTERRUPTS ENABLED +- SIO MODE=Z80R, IO=128, CHANNEL B, INTERRUPTS ENABLED - MD: TYPE=RAM - MD: TYPE=ROM -- PPIDE: IO=96, MASTER -- PPIDE: IO=96, SLAVE -- AY38910: MODE=NABU, IO=65, CLOCK=1789772 HZ +- SD: MODE=Z80R, IO=104, UNITS=1 -#### Notes: +`\clearpage`{=latex} -- TMS video assumes F18A replacement for TMS9918 +## Zeta Z80 SBC -`\clearpage`{=latex} +Zeta SBC is an Zilog Z80 based single board computer. It is inspired by Ampro Little Board Z80 +and N8VEM project. Zeta SBC is software compatible with N8VEM SBC and Disk I/O boards. -## S100 FPGA Z80 +* Creator: Sergey Kiselev +* Retrobrew Wiki: [Zeta SBC](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:zeta:start) -#### ROM Image File: FZ80_std.rom +#### ROM Image File: ZETA_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 8.000 MHz | +| Bus | - | +| Default CPU Speed | 8.000 MHz | | Interrupts | None | | System Timer | None | -| Serial Default | 9600 Baud | -| Memory Manager | Z2 | -| ROM Size | 0 KB | +| Serial Default | 38400 Baud | +| Memory Manager | SBC | +| ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- FP: LEDIO=255 -- DS5RTC: RTCIO=104, IO=104 -- SSER: IO=52 -- LPT: MODE=S100, IO=199 -- FV: IO=192, KBD MODE=FV, KBD IO=3 -- KBD: ENABLED -- SCON: IO=0 +- DSRTC: MODE=STD, IO=112 +- UART: IO=104 +- PPP: IO=96 +- PPPCON: ENABLED +- PPPSD: ENABLED - MD: TYPE=RAM -- PPIDE: IO=48, MASTER -- PPIDE: IO=48, SLAVE -- SD: MODE=FZ80, IO=108, UNITS=2 +- MD: TYPE=ROM +- FD: MODE=DIO, IO=54, DRIVE 0, TYPE=3.5" HD #### Notes: -- Requires matching FPGA code +- If ParPortProp is installed, initial console output is + determined by JP1: + - Shorted: console to on-board serial port + - Open: console to ParPortProp video and keyboard -## Genesis STD Z180 +`\clearpage`{=latex} -#### ROM Image File: GMZ180_std.rom +## Zeta V2 Z80 SBC + +Zeta SBC V2 is a redesigned version of Zeta SBC. + +Compared to the first version this version features updated MMU with four banks, each one of +those banks can be mapped to any 16 KiB page in 1 MiB on-board memory. It adds Z80 CTC which +is used for generating periodic interrupts and as a vectored interrupt controller for UART +and PPI. The FDC is replaced with 37C65. Compared to FDC9266 used in Zeta SBC it integrates +input/output buffers and floppy disk control latch. Additionally 37C65 FDC is easier to obtain +than FDC9266. And lastly it is made using CMOS technology and more power efficient than FDC9266 + +* Creator: Sergey Kiselev +* Github: [Zeta SBC V2](https://github.com/skiselev/zeta_sbc) +* Retrobrew Wiki: [Zeta SBC V2](https://www.retrobrewcomputers.org/doku.php?id=boards:sbc:zetav2:start) + +#### ROM Image File: ZETA2_std.rom | | | |-------------------|---------------| -| Default CPU Speed | 18.432 MHz | +| Bus | - | +| Default CPU Speed | 8.000 MHz | | Interrupts | Mode 2 | -| System Timer | Z180 | -| Serial Default | 115200 Baud | -| Memory Manager | Z180 | +| System Timer | CTC | +| Serial Default | 38400 Baud | +| Memory Manager | Z2 | | ROM Size | 512 KB | | RAM Size | 512 KB | #### Supported Hardware -- GM7303: IO=48 -- DSRTC: MODE=STD, IO=132 -- INTRTC: ENABLED -- ASCI: IO=192, INTERRUPTS ENABLED -- ASCI: IO=193, INTERRUPTS ENABLED +- DSRTC: MODE=STD, IO=112 +- UART: IO=104 +- PPP: IO=96 +- PPPCON: ENABLED +- PPPSD: ENABLED - MD: TYPE=RAM - MD: TYPE=ROM -- IDE: MODE=GIDE, IO=32, MASTER -- IDE: MODE=GIDE, IO=32, SLAVE -- SD: MODE=GM, IO=132, UNITS=1 +- FD: MODE=ZETA2, IO=48, DRIVE 0, TYPE=3.5" HD +- CTC: IO=32, TIMER MODE=COUNTER, DIVISOR=18432, HI=256, LO=72, INTERRUPTS ENABLED #### Notes: -- CPU speed will be dynamically measured at startup if DSRTC is present - +- If ParPortProp is installed, initial console output is + determined by JP1: + - Shorted: console to on-board serial port + - Open: console to ParPortProp video and keyboard # Device Drivers @@ -1947,7 +2244,7 @@ the active platform and configuration. |-----------|--------------------------------------------------------| | CHSD | CH37x SD Card Interface | | CHUSB | CH37x USB Drive Interface | -| FD | 8272 or compatible Floppy Disk Controller | +| FD | Intel 8272 or compatible Floppy Disk Controller | | HDSK | SIMH Simulator Hard Disk | | IDE | IDE/ATA/ATAPI Hard Disk Interface | | IMM | Zip Drive on PPI (IMM variant) | @@ -1969,10 +2266,18 @@ the active platform and configuration. | FV | S100 FPGA Z80 Onboard VGA/Keyboard | | GDC | uPD7220 Video Display Controller | | TMS | TMS9918/38/58 Video Display Controller | -| VDU | MC6845 Family Video Display Controller | +| VDU | MC6845 Family Video Display Controller (*) | | VGA | HD6445CP4-based Video Display Controller | | VRC | VGARC Video Display Controller | +Note: + +* Reading bytes from the video memory of the VDU board (not Color + VDU) appears to be problematic. This is only an issue when the driver + needs to scroll a portion of the screen which is done by applications + such as WordStar or ZDE. You are likely to see screen corruption in + this case. + ## Keyboard | **ID** | **Description** | @@ -2026,7 +2331,7 @@ the active platform and configuration. | DMA | Zilog DMA Controller | | ESP | ESP32 Firmware-based interface | | EZ80TIMER | eZ80 System Timer | -| KIO | Zilog Serial/ Parallel Counter/Timer | +| KIO | Zilog Serial/ Parallel Counter/Timer (Z84C90) | | PPP | ParPortProp Host Interface Controller | | PRP | PropIO Host Interface Controller | @@ -2088,24 +2393,3 @@ for more information on UNA. CP/M 3, ZPM3, and p-System. - Some of the RomWBW-specific applications are not UNA compatible. - -# Errata - -The following errata apply to $doc_product$ $doc_ver$: - -* The use of high density floppy disks requires a CPU speed of 8 MHz or - greater. - -* The PropIO support is based on RomWBW specific firmware. Be sure to - program/update your PropIO firmware with the corresponding firmware - image provided in the Binary directory of the RomWBW distribution. - -* Reading bytes from the video memory of the VDU board (not Color - VDU) appears to be problematic. This is only an issue when the driver - needs to scroll a portion of the screen which is done by applications - such as WordStar or ZDE. You are likely to see screen corruption in - this case. - -* The RomWBW `TUNE` application will detect an AY-3-8910/YM2149 - Sound Module regardless of whether support for it is included in - the RomWBW HBIOS configuration. diff --git a/Source/Doc/Introduction.md b/Source/Doc/Introduction.md index ec7813c3..0aa09e08 100644 --- a/Source/Doc/Introduction.md +++ b/Source/Doc/Introduction.md @@ -288,6 +288,7 @@ please let me know if I missed you! - creation of the Introduction and Hardware documents - Z3PLUS operating system disk image - COPYSL utility + - SLABEL utility - a feature for RomWBW configuration by NVRAM - the /B bulk mode of disk assignment to the ASSIGN utility diff --git a/Source/Doc/SystemGuide.md b/Source/Doc/SystemGuide.md index 2d1dcf97..40799d6e 100644 --- a/Source/Doc/SystemGuide.md +++ b/Source/Doc/SystemGuide.md @@ -2497,26 +2497,34 @@ version 3.1.0, build 2. The hardware Platform (L) is identified as follows: -| **Name** | **Id** | **Platform ** | +| **Name** | **Id** | **Platform ** | |---------------|-------:|-----------------------------------------| -| PLT_SBC |1 | ECB Z80 SBC | -| PLT_ZETA |2 | ZETA Z80 SBC | -| PLT_ZETA2 |3 | ZETA Z80 V2 SBC | -| PLT_N8 |4 | N8 (HOME COMPUTER) Z180 SBC | -| PLT_MK4 |5 | MARK IV | -| PLT_UNA |6 | UNA BIOS | -| PLT_RCZ80 |7 | RCBUS W/ Z80 | -| PLT_RCZ180 |8 | RCBUS W/ Z180 | -| PLT_EZZ80 |9 | EASY/TINY Z80 | -| PLT_SCZ180 |10 | RCBUS SC126, SC130, SC131, SC140 | -| PLT_DYNO |11 | DYNO MICRO-ATX MOTHERBOARD | -| PLT_RCZ280 |12 | RCBUS W/ Z280 | -| PLT_MBC |13 | NHYODYNE MULTI-BOARD COMPUTER | -| PLT_RPH |14 | RHYOPHYRE GRAPHICS SBC | -| PLT_Z80RETRO |15 | Z80 RETRO COMPUTER | -| PLT_S100 |16 | S100 COMPUTERS Z180 | -| PLT_DUO |17 | DUODYNE Z80 SYSTEM | -| PLT_RCEZ80 |24 | RCBUS W/ eZ80 | +| PLT_SBC | 1 | ECB Z80 SBC | +| PLT_ZETA | 2 | ZETA Z80 SBC | +| PLT_ZETA2 | 3 | ZETA Z80 V2 SBC | +| PLT_N8 | 4 | N8 (HOME COMPUTER) Z180 SBC | +| PLT_MK4 | 5 | MARK IV | +| PLT_UNA | 6 | UNA BIOS | +| PLT_RCZ80 | 7 | RCBUS W/ Z80 | +| PLT_RCZ180 | 8 | RCBUS W/ Z180 | +| PLT_EZZ80 | 9 | EASY/TINY Z80 | +| PLT_SCZ180 | 10 | SMALL COMPUTER CENTRAL Z180 | +| PLT_DYNO | 11 | DYNO MICRO-ATX MOTHERBOARD | +| PLT_RCZ280 | 12 | RCBUS W/ Z280 | +| PLT_MBC | 13 | NHYODYNE MULTI-BOARD COMPUTER | +| PLT_RPH | 14 | RHYOPHYRE GRAPHICS SBC | +| PLT_Z80RETRO | 15 | Z80 RETRO COMPUTER | +| PLT_S100 | 16 | S100 COMPUTERS Z180 | +| PLT_DUO | 17 | DUODYNE Z80 SYSTEM | +| PLT_HEATH | 18 | HEATHKIT H8 Z80 SYSTEM | +| PLT_EPITX | 19 | Z180 MINI-ITX | +| PLT_MON | 20 | MONSPUTER (DEPRECATED) | +| PLT_GMZ180 | 21 | GENESIS Z180 SYSTEM | +| PLT_NABU | 22 | NABU PC W/ ROMWBW OPTION BOARD | +| PLT_FZ80 | 23 | S100 FPGA Z80 | +| PLT_RCEZ80 | 24 | RCBUS W/ eZ80 | + +For more information on these platforms see $doc_hardware$ ### Function 0xF2 -- System Set Bank (SYSSETBNK) diff --git a/Source/HBIOS/Build.cmd b/Source/HBIOS/Build.cmd index ac1e5d05..505aa599 100644 --- a/Source/HBIOS/Build.cmd +++ b/Source/HBIOS/Build.cmd @@ -229,8 +229,8 @@ call Build MK4 std || exit /b call Build RCZ80 std || exit /b call Build RCEZ80 std || exit /b call Build RCZ80 kio_std || exit /b -call Build RCZ80 easy_std || exit /b -call Build RCZ80 tiny_std || exit /b +call Build EZZ80 easy_std || exit /b +call Build EZZ80 tiny_std || exit /b call Build RCZ80 skz_std || exit /b call Build RCZ80 zrc_std || exit /b call Build RCZ80 zrc_ram_std || exit /b diff --git a/Source/HBIOS/Build.ps1 b/Source/HBIOS/Build.ps1 index 9e390302..f98f5d99 100644 --- a/Source/HBIOS/Build.ps1 +++ b/Source/HBIOS/Build.ps1 @@ -27,7 +27,7 @@ $ErrorAction = 'Stop' # UNA BIOS is simply imbedded, it is not built here. # -$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80", "RCEZ80" +$PlatformListZ80 = "SBC", "MBC", "ZETA", "ZETA2", "RCZ80", "EZZ80", "Z80RETRO", "DUO", "UNA", "HEATH", "MON", "NABU", "FZ80", "RCEZ80" $PlatformListZ180 = "N8", "MK4", "RCZ180", "SCZ180", "DYNO", "RPH", "S100", "EPITX", "GMZ180" $PlatformListZ280 = "RCZ280" diff --git a/Source/HBIOS/Build.sh b/Source/HBIOS/Build.sh index 7517d9ac..f947e06b 100755 --- a/Source/HBIOS/Build.sh +++ b/Source/HBIOS/Build.sh @@ -21,8 +21,8 @@ if [ "${ROM_PLATFORM}" == "dist" ] ; then ROM_PLATFORM="RCEZ80"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="std"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="kio_std"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="easy_std"; bash Build.sh - ROM_PLATFORM="RCZ80"; ROM_CONFIG="tiny_std"; bash Build.sh + ROM_PLATFORM="EZZ80"; ROM_CONFIG="easy_std"; bash Build.sh + ROM_PLATFORM="EZZ80"; ROM_CONFIG="tiny_std"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="skz_std"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_std"; bash Build.sh ROM_PLATFORM="RCZ80"; ROM_CONFIG="zrc_ram_std"; bash Build.sh diff --git a/Source/HBIOS/Config/RCZ80_easy_std.asm b/Source/HBIOS/Config/EZZ80_easy_std.asm similarity index 94% rename from Source/HBIOS/Config/RCZ80_easy_std.asm rename to Source/HBIOS/Config/EZZ80_easy_std.asm index 89d7513b..977e0019 100644 --- a/Source/HBIOS/Config/RCZ80_easy_std.asm +++ b/Source/HBIOS/Config/EZZ80_easy_std.asm @@ -46,9 +46,7 @@ #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED #DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION ; -#INCLUDE "cfg_RCZ80.asm" -; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +#INCLUDE "cfg_EZZ80.asm" ; BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME diff --git a/Source/HBIOS/Config/RCZ80_tiny_std.asm b/Source/HBIOS/Config/EZZ80_tiny_std.asm similarity index 95% rename from Source/HBIOS/Config/RCZ80_tiny_std.asm rename to Source/HBIOS/Config/EZZ80_tiny_std.asm index 8233bbbf..1413fe4c 100644 --- a/Source/HBIOS/Config/RCZ80_tiny_std.asm +++ b/Source/HBIOS/Config/EZZ80_tiny_std.asm @@ -46,9 +46,7 @@ #DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED #DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION ; -#INCLUDE "cfg_RCZ80.asm" -; -PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +#INCLUDE "cfg_EZZ80.asm" ; BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME diff --git a/Source/HBIOS/Makefile.new b/Source/HBIOS/Makefile.new index f7b8a02e..38ab8fef 100644 --- a/Source/HBIOS/Makefile.new +++ b/Source/HBIOS/Makefile.new @@ -1,7 +1,7 @@ DIST_OBJECTS := \ DYNO_std MK4_std N8_std RCZ180_ext RCZ180_nat RCZ180_z1rcc \ RCZ280_ext RCZ280_nat RCZ280_zz80mb RCZ280_zzrcc RCZ280_zzrcc_ram \ - RCZ80_std RCZ80_kio RCZ80_easy RCZ80_tiny RCZ80_skz RCZ80_zrc \ + RCZ80_std RCZ80_kio EZZ80_easy EZZ80_tiny RCZ80_skz RCZ80_zrc \ RCZ80_zrc_ram RCZ80_zrc512 RPH_std SBC_std SBC_simh MBC_std \ DUO_std SCZ180_sc126 SCZ180_sc130 SCZ180_sc131 SCZ180_sc140 \ SCZ180_sc503 SCZ180_sc700 S100_std UNA_std Z80RETRO_std \ diff --git a/Source/HBIOS/cfg_EZZ80.asm b/Source/HBIOS/cfg_EZZ80.asm new file mode 100644 index 00000000..577d25b4 --- /dev/null +++ b/Source/HBIOS/cfg_EZZ80.asm @@ -0,0 +1,399 @@ +; +;================================================================================================== +; ROMWBW PLATFORM CONFIGURATION DEFAULTS FOR PLATFORM: EZZ80 +;================================================================================================== +; +; THIS FILE DEFINES THE DEFAULT CONFIGURATION SETTINGS FOR THE PLATFORM +; INDICATED ABOVE. THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. INSTEAD, +; YOU SHOULD OVERRIDE SETTINGS YOU WANT USING A CONFIGURATION FILE IN +; THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; THIS FILE SHOULD *NOT* NORMALLY BE CHANGED. IT IS MAINTAINED BY THE +; AUTHORS OF ROMWBW. TO OVERRIDE SETTINGS YOU SHOULD USE A +; CONFIGURATION FILE IN THE CONFIG DIRECTORY UNDER THIS DIRECTORY. +; +; ROMWBW USES CASCADING CONFIGURATION FILES AS INDICATED BELOW: +; +; cfg_MASTER.asm - MASTER: CONFIGURATION FILE DEFINES ALL POSSIBLE ROMWBW SETTINGS +; | +; +-> cfg_.asm - PLATFORM: DEFAULT SETTINGS FOR SPECIFIC PLATFORM +; | +; +-> Config/_std.asm - BUILD: SETTINGS FOR EACH OFFICIAL DIST BUILD +; | +; +-> Config/_.asm - USER: CUSTOM USER BUILD SETTINGS +; +; THE TOP (MASTER CONFIGURATION) FILE DEFINES ALL POSSIBLE ROMWBW +; CONFIGURATION SETTINGS. EACH FILE BELOW THE MASTER CONFIGURATION FILE +; INHERITS THE CUMULATIVE SETTINGS OF THE FILES ABOVE IT AND MAY +; OVERRIDE THESE SETTINGS AS DESIRED. +; +; OTHER THAN THE TOP MASTER FILE, EACH FILE MUST "#INCLUDE" ITS PARENT +; FILE (SEE #INCLUDE STATEMENT BELOW). THE TOP TWO FILES SHOULD NOT BE +; MODIFIED. TO CUSTOMIZE YOUR BUILD SETTINGS YOU SHOULD MODIFY THE +; DEFAULT BUILD SETTINGS (Config/_std.asm) OR PREFERABLY +; CREATE AN OPTIONAL CUSTOM USER SETTINGS FILE THAT INCLUDES THE DEFAULT +; BUILD SETTINGS FILE (SEE EXAMPLE Config/SBC_user.asm). +; +; BY CREATING A CUSTOM USER SETTINGS FILE, YOU ARE LESS LIKELY TO BE +; IMPACTED BY FUTURE CHANGES BECAUSE YOU WILL BE INHERITING MOST +; OF YOUR SETTINGS WHICH WILL BE UPDATED BY AUTHORS AS ROMWBW EVOLVES. +; +; *** WARNING: ASIDE FROM THE MASTER CONFIGURATION FILE, YOU MUST USE +; ".SET" TO OVERRIDE SETTINGS. THE ASSEMBLER WILL ERROR IF YOU ATTEMPT +; TO USE ".EQU" BECAUSE IT WON'T LET YOU REDEFINE A SETTING WITH ".EQU". +; +#DEFINE PLATFORM_NAME "EZZ80", " [", CONFIG, "]" ; TEXT LABEL OF THIS CONFIG IN STARTUP MESSAGES +#DEFINE BOOT_DEFAULT "H" ; DEFAULT BOOT LOADER CMD FOR EMPTY CMD LINE +#DEFINE AUTO_CMD "" ; AUTO CMD WHEN BOOT_TIMEOUT IS ENABLED +#DEFINE DEFSERCFG SER_115200_8N1 | SER_RTS ; DEFAULT SERIAL CONFIGURATION +; +#INCLUDE "cfg_MASTER.asm" +; +PLATFORM .SET PLT_EZZ80 ; PLT_[SBC|ZETA|ZETA2|N8|MK4|UNA|RCZ80|RCEZ80|RCZ180|EZZ80|SCZ180|GMZ180|DYNO|RCZ280|MBC|RPH|Z80RETRO|S100|DUO|HEATH|EPITX|MON|STDZ180|NABU|FZ80] +CPUFAM .SET CPU_Z80 ; CPU FAMILY: CPU_[Z80|Z180|Z280|EZ80] +BIOS .SET BIOS_WBW ; HARDWARE BIOS: BIOS_[WBW|UNA] +BATCOND .SET FALSE ; ENABLE LOW BATTERY WARNING MESSAGE +HBIOS_MUTEX .SET FALSE ; ENABLE REENTRANT CALLS TO HBIOS (ADDS OVERHEAD) +USELZSA2 .SET TRUE ; ENABLE FONT COMPRESSION +TICKFREQ .SET 50 ; DESIRED PERIODIC TIMER INTERRUPT FREQUENCY (HZ) +; +BOOT_TIMEOUT .SET -1 ; AUTO BOOT TIMEOUT IN SECONDS, -1 TO DISABLE, 0 FOR IMMEDIATE +BOOT_DELAY .SET 0 ; FIXED BOOT DELAY IN SECONDS PRIOR TO CONSOLE OUTPUT +BOOT_PRETTY .SET FALSE ; BOOT WITH PRETTY PLATFORM NAME +BT_REC_TYPE .SET BT_REC_NONE ; BOOT RECOVERY METHOD TO USE: BT_REC_[NONE|FORCE|SBCB0|SBC1B|SBCRI|DUORI] +AUTOCON .SET TRUE ; ENABLE CONSOLE TAKEOVER AT LOADER PROMPT +STRICTPART .SET TRUE ; ENFORCE STRICT PARTITION TABLE VALIDATION +; +CPUSPDCAP .SET SPD_FIXED ; CPU SPEED CHANGE CAPABILITY SPD_FIXED|SPD_HILO +CPUSPDDEF .SET SPD_HIGH ; CPU SPEED DEFAULT SPD_UNSUP|SPD_HIGH|SPD_LOW +CPUOSC .SET 7372800 ; CPU OSC FREQ IN MHZ +INTMODE .SET 1 ; INTERRUPTS: 0=NONE, 1=MODE 1, 2=MODE 2, 3=MODE 3 (Z280) +; +RAMSIZE .SET 512 ; SIZE OF RAM IN KB (MUST MATCH YOUR HARDWARE!!!) +ROMSIZE .SET 512 ; SIZE OF ROM IN KB (MUST MATCH YOUR HARDWARE!!!) +APP_BNKS .SET $FF ; BANKS TO RESERVE FOR APP USE ($FF FOR AUTO SIZING) +MEMMGR .SET MM_Z2 ; MEMORY MANAGER: MM_[SBC|Z2|N8|Z180|Z280|MBC|RPH|MON|EZ512] +MPGSEL_0 .SET $78 ; Z2 MEM MGR BANK 0 PAGE SELECT REG (WRITE ONLY) +MPGSEL_1 .SET $79 ; Z2 MEM MGR BANK 1 PAGE SELECT REG (WRITE ONLY) +MPGSEL_2 .SET $7A ; Z2 MEM MGR BANK 2 PAGE SELECT REG (WRITE ONLY) +MPGSEL_3 .SET $7B ; Z2 MEM MGR BANK 3 PAGE SELECT REG (WRITE ONLY) +MPGENA .SET $7C ; Z2 MEM MGR PAGING ENABLE REGISTER (BIT 0, WRITE ONLY) +; +RTCIO .SET $C0 ; RTC LATCH REGISTER ADR +; +KIOENABLE .SET FALSE ; ENABLE ZILOG KIO SUPPORT +KIOBASE .SET $80 ; KIO BASE I/O ADDRESS +; +CTCENABLE .SET FALSE ; ENABLE ZILOG CTC SUPPORT +CTCDEBUG .SET FALSE ; ENABLE CTC DRIVER DEBUG OUTPUT +CTCBASE .SET $88 ; CTC BASE I/O ADDRESS +CTCTIMER .SET FALSE ; ENABLE CTC PERIODIC TIMER +CTCMODE .SET CTCMODE_TIM16 ; CTC MODE: CTCMODE_[NONE|CTR|TIM16|TIM256] +CTCPRE .SET 256 ; PRESCALE CONSTANT (1-256) +CTCPRECH .SET 2 ; PRESCALE CHANNEL (0-3) +CTCTIMCH .SET 3 ; TIMER CHANNEL (0-3) +CTCOSC .SET CPUOSC ; CTC CLOCK FREQUENCY +; +PCFENABLE .SET FALSE ; ENABLE PCF8584 I2C CONTROLLER +PCFBASE .SET $F0 ; PCF8584 BASE I/O ADDRESS +; +EIPCENABLE .SET FALSE ; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION +; +SKZENABLE .SET FALSE ; ENABLE SERGEY'S Z80-512K FEATURES +SKZDIV .SET DIV_1 ; UART CLK (CLK2) DIVIDER FOR Z80-512K +; +WDOGMODE .SET WDOG_NONE ; WATCHDOG MODE: WDOG_[NONE|EZZ80|SKZ] +WDOGIO .SET $6F ; WATCHDOG REGISTER ADR +; +FPLED_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL LEDS +FPLED_IO .SET $00 ; FP: PORT ADDRESS FOR FP LEDS +FPLED_INV .SET FALSE ; FP: LED BITS ARE INVERTED +FPLED_DSKACT .SET TRUE ; FP: ENABLES DISK I/O ACTIVITY ON FP LEDS +FPSW_ENABLE .SET FALSE ; FP: ENABLES FRONT PANEL SWITCHES +FPSW_IO .SET $00 ; FP: PORT ADDRESS FOR FP SWITCHES +FPSW_INV .SET FALSE ; FP: SWITCH BITS ARE INVERTED +; +DIAGLVL .SET DL_CRITICAL ; ERROR LEVEL REPORTING +; +LEDENABLE .SET FALSE ; ENABLES STATUS LED (SINGLE LED) +LEDMODE .SET LEDMODE_STD ; LEDMODE_[STD|SC|RTC|NABU] +LEDPORT .SET $0E ; STATUS LED PORT ADDRESS +LEDDISKIO .SET TRUE ; ENABLES DISK I/O ACTIVITY ON STATUS LED +; +DSKYENABLE .SET FALSE ; ENABLES DSKY FUNCTIONALITY +DSKYDSKACT .SET TRUE ; ENABLES DISK ACTIVITY ON DSKY DISPLAY +ICMENABLE .SET FALSE ; ENABLES ORIGINAL DSKY ICM DRIVER (7218) +ICMPPIBASE .SET $60 ; BASE I/O ADDRESS OF ICM PPI +PKDENABLE .SET FALSE ; ENABLES DSKY NG PKD DRIVER (8259) +PKDPPIBASE .SET $60 ; BASE I/O ADDRESS OF PKD PPI +PKDOSC .SET 3000000 ; OSCILLATOR FREQ FOR PKD (IN HZ) +H8PENABLE .SET FALSE ; ENABLES HEATH H8 FRONT PANEL +LCDENABLE .SET FALSE ; ENABLE LCD DISPLAY +LCDBASE .SET $DA ; BASE I/O ADDRESS OF LCD CONTROLLER +GM7303ENABLE .SET FALSE ; ENABLES THE GM7303 BOARD WITH 16X2 LCD +; +BOOTCON .SET 0 ; BOOT CONSOLE DEVICE +SECCON .SET $FF ; SECONDARY CONSOLE DEVICE +CRTACT .SET FALSE ; ACTIVATE CRT (VDU,CVDU,PROPIO,ETC) AT STARTUP +VDAEMU .SET EMUTYP_ANSI ; VDA EMULATION: EMUTYP_[TTY|ANSI] +VDAEMU_SERKBD .SET $FF ; VDA EMULATION: SERIAL KBD UNIT #, OR $FF FOR HW KBD +ANSITRACE .SET 1 ; ANSI DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKTRACE .SET 1 ; PPK DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +KBDTRACE .SET 1 ; KBD DRIVER TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPKKBLOUT .SET KBD_US ; PPK KEYBOARD LANGUAGE: KBD_[US|DE] +KBDKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +MKYKBLOUT .SET KBD_US ; KBD KEYBOARD LANGUAGE: KBD_[US|DE] +KBDINTS .SET FALSE ; ENABLE KBD (PS2) KEYBOARD INTERRUPTS +; +DSRTCENABLE .SET TRUE ; DSRTC: ENABLE DS-1302 CLOCK DRIVER (DSRTC.ASM) +DSRTCMODE .SET DSRTCMODE_STD ; DSRTC: OPERATING MODE: DSRTCMODE_[STD|MFPIC|K80W] +DSRTCCHG .SET FALSE ; DSRTC: FORCE BATTERY CHARGE ON (USE WITH CAUTION!!!) +; +DS1501RTCENABLE .SET FALSE ; DS1501RTC: ENABLE DS-1501 CLOCK DRIVER (DS1501RTC.ASM) +DS1501RTC_BASE .SET $50 ; DS1501RTC: I/O BASE ADDRESS +; +BQRTCENABLE .SET FALSE ; BQRTC: ENABLE BQ4845 CLOCK DRIVER (BQRTC.ASM) +BQRTC_BASE .SET $50 ; BQRTC: I/O BASE ADDRESS +; +INTRTCENABLE .SET FALSE ; ENABLE PERIODIC INTERRUPT CLOCK DRIVER (INTRTC.ASM) +; +RP5RTCENABLE .SET FALSE ; RP5C01 RTC BASED CLOCK (RP5RTC.ASM) +; +HTIMENABLE .SET FALSE ; ENABLE SIMH TIMER SUPPORT +SIMRTCENABLE .SET FALSE ; ENABLE SIMH CLOCK DRIVER (SIMRTC.ASM) +; +DS7RTCENABLE .SET FALSE ; DS7RTC: ENABLE DS-1307 I2C CLOCK DRIVER (DS7RTC.ASM) +DS7RTCMODE .SET DS7RTCMODE_PCF ; DS7RTC: OPERATING MODE: DS7RTCMODE_[PCF] +; +DS5RTCENABLE .SET FALSE ; DS5RTC: ENABLE DS-1305 SPI CLOCK DRIVER (DS5RTC.ASM) +; +SSERENABLE .SET FALSE ; SSER: ENABLE SIMPLE SERIAL DRIVER (SSER.ASM) +SSERCFG .SET SER_9600_8N1 ; SSER: SERIAL LINE CONFIG +SSERSTATUS .SET $FF ; SSER: STATUS PORT +SSERDATA .SET $FF ; SSER: DATA PORT +SSERIRDY .SET %00000001 ; SSER: INPUT READY BIT MASK +SSERIINV .SET FALSE ; SSER: INPUT READY BIT INVERTED +SSERORDY .SET %00000010 ; SSER: OUTPUT READY BIT MASK +SSEROINV .SET FALSE ; SSER: OUTPUT READY BIT INVERTED +; +DUARTENABLE .SET FALSE ; DUART: ENABLE 2681/2692 SERIAL DRIVER (DUART.ASM) +DUARTCNT .SET 1 ; DUART: NUMBER OF CHIPS TO DETECT (1-2) +DUART0BASE .SET $A0 ; DUART 0: BASE ADDRESS OF CHIP +DUART0ACFG .SET DEFSERCFG ; DUART 0A: SERIAL LINE CONFIG +DUART0BCFG .SET DEFSERCFG ; DUART 0B: SERIAL LINE CONFIG +DUART1BASE .SET $40 ; DUART 1: BASE ADDRESS OF CHIP +DUART1ACFG .SET DEFSERCFG ; DUART 1A: SERIAL LINE CONFIG +DUART1BCFG .SET DEFSERCFG ; DUART 1B: SERIAL LINE CONFIG +; +UARTENABLE .SET FALSE ; UART: ENABLE 8250/16550-LIKE SERIAL DRIVER (UART.ASM) +UARTCNT .SET 4 ; UART: NUMBER OF CHIPS TO DETECT (1-8) +UARTOSC .SET 1843200 ; UART: OSC FREQUENCY IN MHZ +UARTINTS .SET FALSE ; UART: INCLUDE INTERRUPT SUPPORT UNDER IM1/2/3 +UART4UART .SET FALSE ; UART: SUPPORT 4UART ECB BOARD +UART4UARTBASE .SET $C0 ; UART: BASE IO ADDRESS OF 4UART ECB BOARD +UART0BASE .SET $80 ; UART 0: REGISTERS BASE ADR +UART0CFG .SET DEFSERCFG ; UART 0: SERIAL LINE CONFIG +UART1BASE .SET $88 ; UART 1: REGISTERS BASE ADR +UART1CFG .SET DEFSERCFG ; UART 1: SERIAL LINE CONFIG +UART2BASE .SET $A0 ; UART 2: REGISTERS BASE ADR +UART2CFG .SET DEFSERCFG ; UART 2: SERIAL LINE CONFIG +UART3BASE .SET $A8 ; UART 3: REGISTERS BASE ADR +UART3CFG .SET DEFSERCFG ; UART 3: SERIAL LINE CONFIG +UART4BASE .SET $FF ; UART 4: REGISTERS BASE ADR +UART4CFG .SET DEFSERCFG ; UART 4: SERIAL LINE CONFIG +UART5BASE .SET $FF ; UART 5: REGISTERS BASE ADR +UART5CFG .SET DEFSERCFG ; UART 5: SERIAL LINE CONFIG +UART6BASE .SET $FF ; UART 6: REGISTERS BASE ADR +UART6CFG .SET DEFSERCFG ; UART 6: SERIAL LINE CONFIG +UART7BASE .SET $FF ; UART 7: REGISTERS BASE ADR +UART7CFG .SET DEFSERCFG ; UART 7: SERIAL LINE CONFIG +; +ASCIENABLE .SET FALSE ; ASCI: ENABLE Z180 ASCI SERIAL DRIVER (ASCI.ASM) +; +Z2UENABLE .SET FALSE ; Z2U: ENABLE Z280 UART SERIAL DRIVER (Z2U.ASM) +; +ACIAENABLE .SET FALSE ; ACIA: ENABLE MOTOROLA 6850 ACIA DRIVER (ACIA.ASM) +ACIADEBUG .SET FALSE ; ACIA: ENABLE DEBUG OUTPUT +ACIACNT .SET 1 ; ACIA: NUMBER OF CHIPS TO DETECT (1-2) +ACIA0BASE .SET $80 ; ACIA 0: REGISTERS BASE ADR +ACIA0CLK .SET CPUOSC ; ACIA 0: OSC FREQ IN HZ +ACIA0DIV .SET 1 ; ACIA 0: SERIAL CLOCK DIVIDER +ACIA0CFG .SET DEFSERCFG ; ACIA 0: SERIAL LINE CONFIG (SEE STD.ASM) +ACIA1BASE .SET $40 ; ACIA 1: REGISTERS BASE ADR +ACIA1CLK .SET CPUOSC ; ACIA 1: OSC FREQ IN HZ +ACIA1DIV .SET 1 ; ACIA 1: SERIAL CLOCK DIVIDER +ACIA1CFG .SET DEFSERCFG ; ACIA 1: SERIAL LINE CONFIG (SEE STD.ASM) +; +SIOENABLE .SET FALSE ; SIO: ENABLE ZILOG SIO SERIAL DRIVER (SIO.ASM) +SIODEBUG .SET FALSE ; SIO: ENABLE DEBUG OUTPUT +SIOBOOT .SET 0 ; SIO: REBOOT ON RCV CHAR (0=DISABLED) +SIOCNT .SET 2 ; SIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SIOINTS .SET TRUE ; SIO: INCLUDE SIO INTERRUPT SUPPORT UNDER IM1/2/3 +SIO0MODE .SET SIOMODE_RC ; SIO 0: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO0BASE .SET $80 ; SIO 0: REGISTERS BASE ADR +SIO0ACLK .SET CPUOSC ; SIO 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0ACFG .SET DEFSERCFG ; SIO 0A: SERIAL LINE CONFIG +SIO0ACTCC .SET -1 ; SIO 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO0BCLK .SET CPUOSC ; SIO 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO0BCFG .SET DEFSERCFG ; SIO 0B: SERIAL LINE CONFIG +SIO0BCTCC .SET -1 ; SIO 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1MODE .SET SIOMODE_RC ; SIO 1: CHIP TYPE: SIOMODE_[STD|RC|SMB|ZP|Z80R] +SIO1BASE .SET $84 ; SIO 1: REGISTERS BASE ADR +SIO1ACLK .SET CPUOSC ; SIO 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1ACFG .SET DEFSERCFG ; SIO 1A: SERIAL LINE CONFIG +SIO1ACTCC .SET -1 ; SIO 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SIO1BCLK .SET CPUOSC ; SIO 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG +SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +; +XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG +; +VDUENABLE .SET FALSE ; VDU: ENABLE VDU VIDEO/KBD DRIVER (VDU.ASM) +CVDUENABLE .SET FALSE ; CVDU: ENABLE CVDU VIDEO/KBD DRIVER (CVDU.ASM) +GDCENABLE .SET FALSE ; GDC: ENABLE 7220 GDC VIDEO/KBD DRIVER (GDC.ASM) +TMSENABLE .SET FALSE ; TMS: ENABLE TMS9918 VIDEO/KBD DRIVER (TMS.ASM) +TMSMODE .SET TMSMODE_MSX ; TMS: DRIVER MODE: TMSMODE_[SCG|N8|MSX|MSXKBD|MSXMKY|MBC|COLECO|DUO|NABU] +TMS80COLS .SET FALSE ; TMS: ENABLE 80 COLUMN SCREEN, REQUIRES V9958 +TMSTIMENABLE .SET FALSE ; TMS: ENABLE TIMER INTERRUPTS (REQUIRES IM1) +VGAENABLE .SET FALSE ; VGA: ENABLE VGA VIDEO/KBD DRIVER (VGA.ASM) +VRCENABLE .SET FALSE ; VRC: ENABLE VGARC VIDEO/KBD DRIVER (VRC.ASM) +SCONENABLE .SET FALSE ; SCON: ENABLE S100 CONSOLE DRIVER (SCON.ASM) +EFENABLE .SET FALSE ; EF: ENABLE EF9345 VIDEO DRIVER (EF.ASM) +FVENABLE .SET FALSE ; FV: ENABLE FPGA VGA VIDEO DRIVER (FV.ASM) +; +MDENABLE .SET TRUE ; MD: ENABLE MEMORY (ROM/RAM) DISK DRIVER (MD.ASM) +MDROM .SET TRUE ; MD: ENABLE ROM DISK +MDRAM .SET TRUE ; MD: ENABLE RAM DISK +MDTRACE .SET 1 ; MD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +MDFFENABLE .SET FALSE ; MD: ENABLE FLASH FILE SYSTEM +; +FDENABLE .SET FALSE ; FD: ENABLE FLOPPY DISK DRIVER (FD.ASM) +FDMODE .SET FDMODE_RCWDC ; FD: DRIVER MODE: FDMODE_[DIO|ZETA|ZETA2|DIDE|N8|DIO3|RCSMC|RCWDC|DYNO|EPFDC|MBC] +FDCNT .SET 2 ; FD: NUMBER OF FLOPPY DRIVES ON THE INTERFACE (1-2) +FDTRACE .SET 1 ; FD: TRACE LEVEL (0=NO,1=FATAL,2=ERRORS,3=ALL) +FDMAUTO .SET TRUE ; FD: AUTO SELECT DEFAULT/ALTERNATE MEDIA FORMATS +FD0TYPE .SET FDT_3HD ; FD 0: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +FD1TYPE .SET FDT_3HD ; FD 1: DRIVE TYPE: FDT_[3DD|3HD|5DD|5HD|8] +; +RFENABLE .SET FALSE ; RF: ENABLE RAM FLOPPY DRIVER +; +IDEENABLE .SET FALSE ; IDE: ENABLE IDE DISK DRIVER (IDE.ASM) +IDETRACE .SET 1 ; IDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IDECNT .SET 1 ; IDE: NUMBER OF IDE INTERFACES TO DETECT (1-3), 2 DRIVES EACH +IDE0MODE .SET IDEMODE_RC ; IDE 0: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE0BASE .SET $10 ; IDE 0: IO BASE ADDRESS +IDE0DATLO .SET $00 ; IDE 0: DATA LO PORT FOR 16-BIT I/O +IDE0DATHI .SET $00 ; IDE 0: DATA HI PORT FOR 16-BIT I/O +IDE0A8BIT .SET TRUE ; IDE 0A (MASTER): 8 BIT XFER +IDE0B8BIT .SET TRUE ; IDE 0B (MASTER): 8 BIT XFER +IDE1MODE .SET IDEMODE_RC ; IDE 1: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE1BASE .SET $18 ; IDE 1: IO BASE ADDRESS +IDE1DATLO .SET $00 ; IDE 1: DATA LO PORT FOR 16-BIT I/O +IDE1DATHI .SET $00 ; IDE 1: DATA HI PORT FOR 16-BIT I/O +IDE1A8BIT .SET TRUE ; IDE 1A (MASTER): 8 BIT XFER +IDE1B8BIT .SET TRUE ; IDE 1B (MASTER): 8 BIT XFER +IDE2MODE .SET IDEMODE_RC ; IDE 2: DRIVER MODE: IDEMODE_[DIO|DIDE|MK4|RC|GIDE] +IDE2BASE .SET $20 ; IDE 2: IO BASE ADDRESS +IDE2DATLO .SET $00 ; IDE 2: DATA LO PORT FOR 16-BIT I/O +IDE2DATHI .SET $00 ; IDE 2: DATA HI PORT FOR 16-BIT I/O +IDE2A8BIT .SET TRUE ; IDE 2A (MASTER): 8 BIT XFER +IDE2B8BIT .SET TRUE ; IDE 2B (MASTER): 8 BIT XFER +; +PPIDEENABLE .SET FALSE ; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM) +PPIDETRACE .SET 1 ; PPIDE: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPIDECNT .SET 1 ; PPIDE: NUMBER OF PPI CHIPS TO DETECT (1-3), 2 DRIVES PER CHIP +PPIDE0BASE .SET $20 ; PPIDE 0: PPI REGISTERS BASE ADR +PPIDE0A8BIT .SET FALSE ; PPIDE 0A (MASTER): 8 BIT XFER +PPIDE0B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE1BASE .SET $00 ; PPIDE 1: PPI REGISTERS BASE ADR +PPIDE1A8BIT .SET FALSE ; PPIDE 1A (MASTER): 8 BIT XFER +PPIDE1B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +PPIDE2BASE .SET $00 ; PPIDE 2: PPI REGISTERS BASE ADR +PPIDE2A8BIT .SET FALSE ; PPIDE 2A (MASTER): 8 BIT XFER +PPIDE2B8BIT .SET FALSE ; PPIDE 0B (SLAVE): 8 BIT XFER +; +SDENABLE .SET FALSE ; SD: ENABLE SD CARD DISK DRIVER (SD.ASM) +SDMODE .SET SDMODE_PIO ; SD: DRIVER MODE: SDMODE_[JUHA|N8|CSIO|PPI|UART|DSD|MK4|SC|MT|USR|PIO|Z80R|EPITX|FZ80|GM|EZ512|K80W] +SDPPIBASE .SET $60 ; SD: BASE I/O ADDRESS OF PPI FOR PPI MODDE +SDCNT .SET 2 ; SD: NUMBER OF SD CARD DEVICES (1-2), FOR DSD/SC/MT ONLY +SDTRACE .SET 1 ; SD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SDCSIOFAST .SET FALSE ; SD: ENABLE TABLE-DRIVEN BIT INVERTER IN CSIO MODE +SDMTSWAP .SET FALSE ; SD: SWAP THE LOGICAL ORDER OF THE SPI PORTS OF THE MT011 +; +CHENABLE .SET FALSE ; CH: ENABLE CH375/376 USB SUPPORT +CHTRACE .SET 1 ; CH: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHUSBTRACE .SET 1 ; CHUSB: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHSDTRACE .SET 1 ; CHSD: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +CHCNT .SET 2 ; CH: NUMBER OF BOARDS TO DETECT (1-2) +CH0BASE .SET $3E ; CH 0: BASE I/O ADDRESS +CH0USBENABLE .SET TRUE ; CH 0: ENABLE USB DISK +CH0SDENABLE .SET FALSE ; CH 0: ENABLE SD DISK +CH1BASE .SET $3C ; CH 1: BASE I/O ADDRESS +CH1USBENABLE .SET TRUE ; CH 1: ENABLE USB DISK +CH1SDENABLE .SET FALSE ; CH 1: ENABLE SD DISK +; +PRPENABLE .SET FALSE ; PRP: ENABLE ECB PROPELLER IO BOARD DRIVER (PRP.ASM) +; +PPPENABLE .SET FALSE ; PPP: ENABLE ZETA PARALLEL PORT PROPELLER BOARD DRIVER (PPP.ASM) +; +ESPENABLE .SET FALSE ; ESP: ENABLE ESP32 IO BOARD DRIVER (ESP.ASM) +; +HDSKENABLE .SET FALSE ; HDSK: ENABLE SIMH HDSK DISK DRIVER (HDSK.ASM) +; +PIOENABLE .SET FALSE ; PIO: ENABLE ZILOG PIO DRIVER (PIO.ASM) +PIOCNT .SET 2 ; PIO: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +PIO0BASE .SET $B8 ; PIO 0: REGISTERS BASE ADR +PIO1BASE .SET $BC ; PIO 1: REGISTERS BASE ADR +; +LPTENABLE .SET FALSE ; LPT: ENABLE CENTRONICS PRINTER DRIVER (LPT.ASM) +LPTMODE .SET LPTMODE_MG014 ; LPT: DRIVER MODE: LPTMODE_[NONE|SPP|MG014] +LPTCNT .SET 1 ; LPT: NUMBER OF CHIPS TO DETECT (1-2) +LPTTRACE .SET 1 ; LPT: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +LPT0BASE .SET $0C ; LPT 0: REGISTERS BASE ADR +LPT1BASE .SET $00 ; LPT 1: REGISTERS BASE ADR +; +PPAENABLE .SET FALSE ; PPA: ENABLE IOMEGA ZIP DRIVE (PPA) DISK DRIVER (PPA.ASM) +PPACNT .SET 1 ; PPA: NUMBER OF PPA DEVICES (1-2) +PPATRACE .SET 1 ; PPA: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +PPAMODE .SET PPAMODE_MG014 ; PPA: DRIVER MODE: PPAMODE_[NONE|SPP|MG014] +PPA0BASE .SET LPT0BASE ; PPA 0: BASE I/O ADDRESS OF PPI FOR PPA +PPA1BASE .SET LPT1BASE ; PPA 1: BASE I/O ADDRESS OF PPI FOR PPA +; +IMMENABLE .SET FALSE ; IMM: ENABLE IOMEGA ZIP PLUS DRIVE (IMM) DISK DRIVER (IMM.ASM) +IMMCNT .SET 1 ; IMM: NUMBER OF IMM DEVICES (1-2) +IMMTRACE .SET 1 ; IMM: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +IMMMODE .SET IMMMODE_MG014 ; IMM: DRIVER MODE: IMMMODE_[NONE|SPP|MG014] +IMM0BASE .SET LPT0BASE ; IMM 0: BASE I/O ADDRESS OF PPI FOR IMM +IMM1BASE .SET LPT1BASE ; IMM 1: BASE I/O ADDRESS OF PPI FOR IMM +; +SYQENABLE .SET FALSE ; SYQ: ENABLE SYQUEST SPARQ DISK DRIVER (SYQ.ASM) +SYQCNT .SET 1 ; SYQ: NUMBER OF SYQ DEVICES (1-2) +SYQTRACE .SET 1 ; SYQ: TRACE LEVEL (0=NO,1=ERRORS,2=ALL) +SYQMODE .SET IMMMODE_MG014 ; SYQ: DRIVER MODE: SYQMODE_[NONE|SPP|MG014] +SYQ0BASE .SET LPT0BASE ; SYQ 0: BASE I/O ADDRESS OF PPI FOR SYQ +SYQ1BASE .SET LPT1BASE ; SYQ 1: BASE I/O ADDRESS OF PPI FOR SYQ +; +PIO_4P .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB 4P BOARD +PIO_ZP .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR ECB ZILOG PERIPHERALS BOARD (PIO.ASM) +PIO_SBC .SET FALSE ; PIO: ENABLE PARALLEL PORT DRIVER FOR 8255 CHIP +; +UFENABLE .SET FALSE ; UF: ENABLE ECB USB FIFO DRIVER (UF.ASM) +; +SN76489ENABLE .SET FALSE ; SN: ENABLE SN76489 SOUND DRIVER +AUDIOTRACE .SET FALSE ; ENABLE TRACING TO CONSOLE OF SOUND DRIVER +SN7CLK .SET 3579545 ; SN: PSG CLOCK FREQ, ASSUME MSX STD +SNMODE .SET SNMODE_RC ; SN: DRIVER MODE: SNMODE_[NONE|RC|VGM|DUO] +; +AY38910ENABLE .SET FALSE ; AY: ENABLE AY-3-8910 / YM2149 SOUND DRIVER +AY_CLK .SET 1789772 ; AY: PSG CLOCK FREQ, ASSUME MSX STD +AYMODE .SET AYMODE_RCZ80 ; AY: DRIVER MODE: AYMODE_[SCG|N8|RCZ80|RCZ180|MSX|LINC|MBC|DUO|NABU] +AY_FORCE .SET FALSE ; AY: BYPASS AUTO-DETECT, FORCED PRESENT +; +SPKENABLE .SET FALSE ; SPK: ENABLE RTC LATCH IOBIT SOUND DRIVER (SPK.ASM) +; +DMAENABLE .SET FALSE ; DMA: ENABLE DMA DRIVER (DMA.ASM) +DMABASE .SET $E0 ; DMA: DMA BASE ADDRESS +DMAMODE .SET DMAMODE_RC ; DMA: DMA MODE (NONE|ECB|Z180|Z280|RC|MBC|DUO) +; +YM2612ENABLE .SET FALSE ; YM2612: ENABLE YM2612 DRIVER +VGMBASE .SET $C0 ; YM2612: BASE ADDRESS FOR VGM BOARD (YM2612/SN76489s/CTC) diff --git a/Source/HBIOS/hbios.inc b/Source/HBIOS/hbios.inc index 14fe29ec..c542a497 100644 --- a/Source/HBIOS/hbios.inc +++ b/Source/HBIOS/hbios.inc @@ -194,7 +194,7 @@ PLT_UNA .EQU 6 ; UNA BIOS PLT_RCZ80 .EQU 7 ; RCBUS W/ Z80 PLT_RCZ180 .EQU 8 ; RCBUS W/ Z180 PLT_EZZ80 .EQU 9 ; EASY Z80 -PLT_SCZ180 .EQU 10 ; SCZ180 +PLT_SCZ180 .EQU 10 ; SMALL COMPUTER CENTRAL Z180 PLT_DYNO .EQU 11 ; DYNO MICRO-ATX MOTHERBOARD PLT_RCZ280 .EQU 12 ; RCBUS W/ Z280 PLT_MBC .EQU 13 ; MULTI BOARD COMPUTER diff --git a/Source/Images/d_cowgol/u0/CGEN.COM b/Source/Images/d_cowgol/u0/CGEN.COM index 9f978d6a..3604a64b 100644 Binary files a/Source/Images/d_cowgol/u0/CGEN.COM and b/Source/Images/d_cowgol/u0/CGEN.COM differ diff --git a/Source/ver.inc b/Source/ver.inc index cf624b55..a5fff33d 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 5 #DEFINE RUP 1 #DEFINE RTP 0 -#DEFINE BIOSVER "3.5.1-rc.2" +#DEFINE BIOSVER "3.5.1-rc.5" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index 2276c581..f9ba8e7e 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 5 rup equ 1 rtp equ 0 biosver macro - db "3.5.1-rc.2" + db "3.5.1-rc.5" endm