diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt
index 89b01af9..4cfe9fef 100644
--- a/Doc/ChangeLog.txt
+++ b/Doc/ChangeLog.txt
@@ -7,6 +7,7 @@ Version 3.1.1
 - C?O: Add DUART driver
 - WBW: Early Z280 support (requires 512K RAM/ROM board)
 - HCS: ZRC memory manager support
+- S?K: Support for Tiny Z80 by Sergey
 
 Version 3.1
 -----------
@@ -121,7 +122,7 @@ Version 2.9.1
 - PMS: Added Forth, Nascom BASIC, and Tasty BASIC to ROM
 - PMS: Refactored ROM Loader to support more ROM images, now table driven
 - WBW: Refactored DSKY code
-- SK:  Initial support for Easy Z80
+- S?K:  Initial support for Easy Z80
 - PMS: Enhance VDU driver to support alternative screen dimensions
 - WBW: DDT and DDTZ modified to use RST 30 instead of RST 38 to avoid conflicts with IM 1 interrupts
 - WBW: Added timer interrupt support for CTC under Zeta 2 and Easy Z80
diff --git a/Doc/RomWBW Applications.pdf b/Doc/RomWBW Applications.pdf
index 97f306dd..64eb7ea4 100644
Binary files a/Doc/RomWBW Applications.pdf and b/Doc/RomWBW Applications.pdf differ
diff --git a/Doc/RomWBW Architecture.pdf b/Doc/RomWBW Architecture.pdf
index aecb9c57..4260e3e2 100644
Binary files a/Doc/RomWBW Architecture.pdf and b/Doc/RomWBW Architecture.pdf differ
diff --git a/Doc/RomWBW Disk Catalog.pdf b/Doc/RomWBW Disk Catalog.pdf
index 4f47338e..05aa5486 100644
Binary files a/Doc/RomWBW Disk Catalog.pdf and b/Doc/RomWBW Disk Catalog.pdf differ
diff --git a/Doc/RomWBW Getting Started.pdf b/Doc/RomWBW Getting Started.pdf
index fbfdd8ef..607b60df 100644
Binary files a/Doc/RomWBW Getting Started.pdf and b/Doc/RomWBW Getting Started.pdf differ
diff --git a/ReadMe.md b/ReadMe.md
index 7680b0e8..80cec877 100644
--- a/ReadMe.md
+++ b/ReadMe.md
@@ -3,7 +3,7 @@
 ## Z80/Z180 System Software
 
 Version 3.1 Pre-release  
-Tuesday 19 May 2020
+Tuesday 18 August 2020
 
 Wayne Warthen <wwarthen@gmail.com>
 
diff --git a/ReadMe.txt b/ReadMe.txt
index d7c946d6..918d3bb3 100644
--- a/ReadMe.txt
+++ b/ReadMe.txt
@@ -3,7 +3,7 @@ RomWBW
 Z80/Z180 System Software
 
 Version 3.1 Pre-release
-Tuesday 19 May 2020
+Tuesday 18 August 2020
 
 Wayne Warthen wwarthen@gmail.com
 
diff --git a/Source/HBIOS/Config/EZZ80_tz80.asm b/Source/HBIOS/Config/EZZ80_tz80.asm
new file mode 100644
index 00000000..93a45e94
--- /dev/null
+++ b/Source/HBIOS/Config/EZZ80_tz80.asm
@@ -0,0 +1,41 @@
+;
+;==================================================================================================
+;   EASY Z80 STANDARD CONFIGURATION
+;==================================================================================================
+;
+; THE COMPLETE SET OF DEFAULT CONFIGURATION SETTINGS FOR THIS PLATFORM ARE FOUND IN THE
+; CFG_<PLT>.ASM INCLUDED FILE WHICH IS FOUND IN THE PARENT DIRECTORY.  THIS FILE CONTAINS
+; COMMON CONFIGURATION SETTINGS THAT OVERRIDE THE DEFAULTS.  IT IS INTENDED THAT YOU MAKE
+; YOUR CUSTOMIZATIONS IN THIS FILE AND JUST INHERIT ALL OTHER SETTINGS FROM THE DEFAULTS.
+; EVEN BETTER, YOU CAN MAKE A COPY OF THIS FILE WITH A NAME LIKE <PLT>_XXX.ASM AND SPECIFY
+; YOUR FILE IN THE BUILD PROCESS.
+;
+; THE SETTINGS BELOW ARE THE SETTINGS THAT ARE MOST COMMONLY MODIFIED FOR THIS PLATFORM.
+; MANY OF THEM ARE EQUAL TO THE SETTINGS IN THE INCLUDED FILE, SO THEY DON'T REALLY DO
+; ANYTHING AS IS.  THEY ARE LISTED HERE TO MAKE IT EASY FOR YOU TO ADJUST THE MOST COMMON
+; SETTINGS.
+;
+; N.B., SINCE THE SETTINGS BELOW ARE REDEFINING VALUES ALREADY SET IN THE INCLUDED FILE,
+; TASM INSISTS THAT YOU USE THE .SET OPERATOR AND NOT THE .EQU OPERATOR BELOW. ATTEMPTING
+; TO REDEFINE A VALUE WITH .EQU BELOW WILL CAUSE TASM ERRORS!
+;
+; PLEASE REFER TO THE CUSTOM BUILD INSTRUCTIONS (README.TXT) IN THE SOURCE DIRECTORY (TWO
+; DIRECTORIES ABOVE THIS ONE).
+;
+#DEFINE PLATFORM_NAME "TINYZ80"
+;
+#include "cfg_ezz80.asm"
+;
+CPUOSC		.SET	16000000	; CPU OSC FREQ IN MHZ
+;
+IDEENABLE	.SET	TRUE		; IDE: ENABLE IDE DISK DRIVER (IDE.ASM)
+;
+PPIDEENABLE	.SET	TRUE		; PPIDE: ENABLE PARALLEL PORT IDE DISK DRIVER (PPIDE.ASM)
+;
+EIPCENABLE	.SET	TRUE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
+CTCBASE		.SET	$10		; CTC BASE I/O ADDRESS
+LEDENABLE	.SET	TRUE		; ENABLES STATUS LED (SINGLE LED)
+LEDPORT		.SET	$6E		; STATUS LED PORT ADDRESS
+SIO0BASE	.SET	$18		; SIO 0: REGISTERS BASE ADR
+IDE0BASE	.SET	$90		; IDE 0: IO BASE ADDRESS
diff --git a/Source/HBIOS/Makefile b/Source/HBIOS/Makefile
index 85bbcfe2..20c273fe 100644
--- a/Source/HBIOS/Makefile
+++ b/Source/HBIOS/Makefile
@@ -7,6 +7,7 @@ ifdef ROM_PLATFORM
 else
 	OBJECTS += DYNO_std.rom DYNO_std.com
 	OBJECTS += EZZ80_std.rom EZZ80_std.com
+	OBJECTS += EZZ80_tz80.rom EZZ80_tz80.com
 	OBJECTS += MK4_std.rom MK4_std.com
 	OBJECTS += N8_std.rom N8_std.com
 	OBJECTS += RCZ180_ext.rom RCZ180_ext.com
diff --git a/Source/HBIOS/cfg_dyno.asm b/Source/HBIOS/cfg_dyno.asm
index 41144b15..2e3b1adb 100644
--- a/Source/HBIOS/cfg_dyno.asm
+++ b/Source/HBIOS/cfg_dyno.asm
@@ -48,6 +48,8 @@ KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_ezz80.asm b/Source/HBIOS/cfg_ezz80.asm
index ff063ab9..5d8b1fd0 100644
--- a/Source/HBIOS/cfg_ezz80.asm
+++ b/Source/HBIOS/cfg_ezz80.asm
@@ -51,6 +51,8 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_master.asm b/Source/HBIOS/cfg_master.asm
index 0a8155fc..95680f9c 100644
--- a/Source/HBIOS/cfg_master.asm
+++ b/Source/HBIOS/cfg_master.asm
@@ -73,6 +73,8 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_mk4.asm b/Source/HBIOS/cfg_mk4.asm
index e1d14fba..d2e61d32 100644
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@@ -51,6 +51,8 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_n8.asm b/Source/HBIOS/cfg_n8.asm
index 334ad863..6db938cd 100644
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@@ -54,6 +54,8 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$B0		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_rcz180.asm b/Source/HBIOS/cfg_rcz180.asm
index 4b937cee..c68e7406 100644
--- a/Source/HBIOS/cfg_rcz180.asm
+++ b/Source/HBIOS/cfg_rcz180.asm
@@ -51,6 +51,8 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_rcz280.asm b/Source/HBIOS/cfg_rcz280.asm
index 16c34e37..99ea07a4 100644
--- a/Source/HBIOS/cfg_rcz280.asm
+++ b/Source/HBIOS/cfg_rcz280.asm
@@ -54,6 +54,8 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	7372800		; CTC CLOCK FREQUENCY
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_rcz80.asm b/Source/HBIOS/cfg_rcz80.asm
index 856904c2..050bbe10 100644
--- a/Source/HBIOS/cfg_rcz80.asm
+++ b/Source/HBIOS/cfg_rcz80.asm
@@ -50,6 +50,8 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	CPUOSC		; CTC CLOCK FREQUENCY
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_sbc.asm b/Source/HBIOS/cfg_sbc.asm
index d31ef336..e7ee36c0 100644
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@@ -48,6 +48,8 @@ CTCPRECH	.EQU	2		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	3		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	614400		; CTC CLOCK FREQUENCY
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_scz180.asm b/Source/HBIOS/cfg_scz180.asm
index 7b9a5f34..37e07b37 100644
--- a/Source/HBIOS/cfg_scz180.asm
+++ b/Source/HBIOS/cfg_scz180.asm
@@ -46,6 +46,8 @@ CTCDEBUG	.EQU	FALSE		; ENABLE CTC DRIVER DEBUG OUTPUT
 CTCBASE		.EQU	$88		; CTC BASE I/O ADDRESS
 CTCTIMER	.EQU	FALSE		; ENABLE CTC PERIODIC TIMER
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	TRUE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$0D		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_zeta.asm b/Source/HBIOS/cfg_zeta.asm
index 2486bb6a..6fdf350e 100644
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@@ -40,6 +40,8 @@ KIOBASE		.EQU	$80		; KIO BASE I/O ADDRESS
 ;
 CTCENABLE	.EQU	FALSE		; ENABLE ZILOG CTC SUPPORT
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/cfg_zeta2.asm b/Source/HBIOS/cfg_zeta2.asm
index 4b66428d..daf6eb27 100644
--- a/Source/HBIOS/cfg_zeta2.asm
+++ b/Source/HBIOS/cfg_zeta2.asm
@@ -51,6 +51,8 @@ CTCPRECH	.EQU	0		; PRESCALE CHANNEL (0-3)
 CTCTIMCH	.EQU	1		; TIMER CHANNEL (0-3)
 CTCOSC		.EQU	921600		; CTC CLOCK FREQUENCY
 ;
+EIPCENABLE	.EQU	FALSE		; EIPC: ENABLE Z80 EIPC (Z84C15) INITIALIZATION
+;
 DIAGENABLE	.EQU	FALSE		; ENABLES OUTPUT TO 8 BIT LED DIAGNOSTIC PORT
 DIAGPORT	.EQU	$00		; DIAGNOSTIC PORT ADDRESS
 DIAGDISKIO	.EQU	TRUE		; ENABLES DISK I/O ACTIVITY ON DIAGNOSTIC LEDS
diff --git a/Source/HBIOS/eipc.inc b/Source/HBIOS/eipc.inc
new file mode 100644
index 00000000..6497e63d
--- /dev/null
+++ b/Source/HBIOS/eipc.inc
@@ -0,0 +1,75 @@
+;
+; Z80 EIPC (Z84C15) REGISTERS
+;
+EIPC_SCRP	.EQU	$EE		; SYSTEM CONTROL REGISTER POINTER
+EIPC_SCDP	.EQU	$EF		; SYSTEM CONTROL DATA PORT
+EIPC_WDTMR	.EQU	$F0		; WATCHDOG TIMER MASTER REGISTER
+EIPC_WDTCR	.EQU	$F1		; WATCHDOG TIMER COMMAND REGISTER
+EIPC_INTPR	.EQU	$F4		; INTERRUPT PRIORITY REGISTER
+;
+; SYSTEM CONTROL REGISTERS (REGISTER NUMBER TO BE WRITTEN TO EIPC_SCRP)
+;
+EIPC_WCR	.EQU	$00		; WAIT STATE CONTROL REGISTER
+EIPC_MWBR	.EQU	$01		; MEMORY WAIT BOUNDARY REGISTER
+EIPC_CSBR	.EQU	$02		; CHIP SELECT BOUNDARY REGISTER
+EIPC_MCR	.EQU	$03		; MISCELLANEOUS CONTROL REGISTER
+;
+; WAIT STATE VALUES (FOR EIPC_WCR)
+;
+EIPC_IO_0WS	.EQU	$00		; NO (ZERO) I/O WAIT STATES
+EIPC_IO_2WS	.EQU	$01		; 2 I/O WAIT STATES
+EIPC_IO_4WS	.EQU	$02		; 4 I/O WAIT STATES
+EIPC_IO_6WS	.EQU	$03		; 6 I/O WAIT STATES
+EIPC_MEM_OWS	.EQU	$00		; NO (ZERO) MEMORY WAIT STATES
+EIPC_MEM_1WS	.EQU	$04		; 1 MEMORY WAIT STATE
+EIPC_MEM_2WS	.EQU	$08		; 2 MEMORY WAIT STATES
+EIPC_MEM_3WS	.EQU	$0C		; 3 MEMORY WAIT STATES
+EIPC_OCF_0WS	.EQU	$00		; NO ADDITIONAL WAIT ON OP-CODE FETCH
+EIPC_OCF_1WS	.EQU	$10		; +1 WAIT STATE ON OP-CODE FETCH
+EIPC_INT_0WS	.EQU	$00		; NO WAIT ON INTERRUPT VECTOR READ
+EIPC_INT_1WS	.EQU	$20		; 1 WAIT STATE ON INT. VECTOR READ
+EIPC_CHAIN_0WS	.EQU	$00		; 0 WAIT ON INT ACK. / 0 WAIT ON RETI
+EIPC_CHAIN_2WS	.EQU	$40		; 2 WAIT ON INT ACK. / 0 WAIT ON RETI
+EIPC_CHAIN_4WS	.EQU	$80		; 4 WAIT ON INT ACK. / 2 WAIT ON RETI
+EIPC_CHAIN_6WS	.EQU	$C0		; 6 WAIT ON INT ACK. / 4 WAIT ON RETI
+;
+; MISCELLANEOUS CONTROL REGISTER VALUES
+;
+EIPC_CS0_DIS	.EQU	$00		; DISABLE /CS0
+EIPC_CS0_ENA	.EQU	$01		; ENABLE /CS0
+EIPC_CS1_DIS	.EQU	$00		; DISABLE /CS1
+EIPC_CS1_ENA	.EQU	$02		; ENABLE /CS1
+EIPC_32CRC_DIS	.EQU	$00		; DISABLE 32-BIT CRC FOR SIO CHANNEL A
+EIPC_32CRC_ENA	.EQU	$04		; ENABLE 32-BIT CRC FOR SIO CHANNEL A
+EIPC_RSTOUT_DIS	.EQU	$08		; DISABLE RESET OUTPUT
+EIPC_RSTOUT_ENA	.EQU	$00		; ENABLE RESET OUTPUT
+EIPC_CLKDIV1	.EQU	$10		; DIVIDE XTAL/CGC CLOCK BY ONE
+EIPC_CLKDIV2	.EQU	$00		; DIVIDE XTAL/CGC CLOCK BY TWO
+;
+; WATCHDOG TIMER MASTER REGISTER VALUES
+;
+EIPC_WDT_CONST	.EQU	$03		; MUST SET LOWER THREE BITS TO 011
+EIPC_HALT_IDLE1 .EQU	$00		; HALT / POWER DOWN MODE - IDLE 1 MODE
+EIPC_HALT_IDLE2 .EQU	$08		; HALT / POWER DOWN MODE - IDLE 2 MODE
+EIPC_HALT_STOP	.EQU	$10		; HALT / POWER DOWN MODE - STOP MODE
+EIPC_HALT_RUN	.EQU	$18		; HALT / POWER DOWN MODE - RUN MODE
+EIPC_WDT_P2_16	.EQU	$00		; SET WATCHDOG PERIOD TO TOC * 2^16
+EIPC_WDT_P2_18	.EQU	$20		; SET WATCHDOG PERIOD TO TOC * 2^18
+EIPC_WDT_P2_20	.EQU	$40		; SET WATCHDOG PERIOD TO TOC * 2^20
+EIPC_WDT_P2_22	.EQU	$60		; SET WATCHDOG PERIOD TO TOC * 2^22
+EIPC_WDTE	.EQU	$80		; ENABLE WATCHDOG TIMER
+;
+; WATCHDOG TIMER COMMAND REGISTER VALUES
+; 
+EIPC_DIS_WDT	.EQU	$B1		; DISABLE WATCHDOG TIMER
+EIPC_CLR_WDT	.EQU	$4E		; CLEAR WATCHDOG TIMER
+EIPC_HLT_MODE	.EQU	$DB		; CHANGE HALT MODE
+;
+; INTERRUPT PRIORITY REGISTER VALUES
+;
+EIPC_CTC_SIO_PIO	.EQU	$00	; PRIORITY HIGH TO LOW: CTC, SIO, PIO
+EIPC_SIO_CTC_PIO	.EQU	$01	; PRIORITY HIGH TO LOW: SIO, CTC, PIO
+EIPC_CTC_PIO_SIO	.EQU	$02	; PRIORITY HIGH TO LOW: CTC, PIO, SIO
+EIPC_PIO_SIO_CTC	.EQU	$03	; PRIORITY HIGH TO LOW: PIO, SIO, CTC
+EIPC_PIC_CTC_SIO	.EQU	$04	; PRIORITY HIGH TO LOW: PIO, CTC, SIO
+EIPC_SIO_PIO_CTC	.EQU	$05	; PRIORITY HIGH TO LOW: SIO, PIO, CTC
diff --git a/Source/HBIOS/hbios.asm b/Source/HBIOS/hbios.asm
index bb7b55ee..0dcbe16c 100644
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@@ -920,6 +920,22 @@ HB_START:
 ;
 #ENDIF
 ;
+#IF (EIPCENABLE)
+	LD	A,(EIPC_WDT_CONST | EIPC_HALT_RUN | EIPC_WDT_P2_22)
+	OUT	(EIPC_WDTMR),A		; CLEAR WDTE BIT (DISABLE WATCHDOG)
+	LD	A,EIPC_DIS_WDT		; DISABLE WDT - SECOND KEY
+	OUT 	(EIPC_WDTCR),A
+	LD	A,EIPC_WCR		; SET SYSTEM CONTROL REGISTER POINTER
+					; (SCRP) TO POINT TO WAIT STATE
+	OUT	(EIPC_SCRP),A		; CONTROL REGISTER (WCR)
+	LD	A,(EIPC_IO_0WS | EIPC_MEM_OWS | EIPC_OCF_0WS | EIPC_INT_0WS | EIPC_CHAIN_0WS)
+	OUT	(EIPC_SCDP),A		; NO WAIT STATES
+	LD	A,EIPC_MCR		; SET SCRP TO POINT TO MISCELLANEOUS
+	OUT	(EIPC_SCRP),A		; CONTROL REGISTER (MCR)
+	LD	A,EIPC_CLKDIV1		; DIVIDE CLOCK BY 1, /CS0 DISABLE
+	OUT	(EIPC_SCDP),A		; SET SYSTEM CONTROL DATA PORT (SCDP)
+#ENDIF
+;
 #IF (MEMMGR == MM_Z2)
 	; SET PAGING REGISTERS
 #IFDEF ROMBOOT
diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm
index b039cf84..90478171 100644
--- a/Source/HBIOS/std.asm
+++ b/Source/HBIOS/std.asm
@@ -336,6 +336,9 @@ FORCECON	.EQU	0	; DEFAULT IS TO FOLLOW NORMAL SEQUENCE
   #IF (CPUFAM == CPU_Z280)
     #INCLUDE "z280.inc"
   #ENDIF
+  #IF (EIPCENABLE)
+    #INCLUDE "eipc.inc"
+  #ENDIF
 #ENDIF
 ;
 ; SETUP DEFAULT CPU SPEED VALUES
diff --git a/Source/ver.inc b/Source/ver.inc
index 56be76f6..a6197fe2 100644
--- a/Source/ver.inc
+++ b/Source/ver.inc
@@ -2,4 +2,4 @@
 #DEFINE	RMN	1
 #DEFINE	RUP	1
 #DEFINE	RTP	0
-#DEFINE BIOSVER	"3.1.1-pre.21"
+#DEFINE BIOSVER	"3.1.1-pre.22"
diff --git a/Source/ver.lib b/Source/ver.lib
index 3c6a3648..3ac52dcf 100644
--- a/Source/ver.lib
+++ b/Source/ver.lib
@@ -3,5 +3,5 @@ rmn	equ	1
 rup	equ	1
 rtp	equ	0
 biosver	macro
-	db	"3.1.1-pre.21"
+	db	"3.1.1-pre.22"
 	endm