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Add SC126 DSRTC Support 

Updated DSRTC support to avoid mangling bits used for other purposes in RTC latch port.
pull/48/head
Wayne Warthen 7 years ago
parent
9a3e3e443c
commit
5958f7760e
16 changed files with 93 additions and 65 deletions
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  1. 4
      Source/HBIOS/Config/MK4_std.asm
  2. 4
      Source/HBIOS/Config/N8_std.asm
  3. 4
      Source/HBIOS/Config/RCZ180_ext.asm
  4. 4
      Source/HBIOS/Config/RCZ180_nat.asm
  5. 7
      Source/HBIOS/Config/RCZ180_sc126.asm
  6. 2
      Source/HBIOS/cfg_ezz80.asm
  7. 10
      Source/HBIOS/cfg_mk4.asm
  8. 6
      Source/HBIOS/cfg_n8.asm
  9. 6
      Source/HBIOS/cfg_rcz180.asm
  10. 2
      Source/HBIOS/cfg_rcz80.asm
  11. 2
      Source/HBIOS/cfg_sbc.asm
  12. 2
      Source/HBIOS/cfg_zeta.asm
  13. 72
      Source/HBIOS/dsrtc.asm
  14. 14
      Source/HBIOS/hbios.asm
  15. 18
      Source/HBIOS/sd.asm
  16. 1
      Source/HBIOS/std.asm

4
Source/HBIOS/Config/MK4_std.asm
View File

@ -6,8 +6,8 @@
#include "cfg_mk4.asm"
;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .SET 1 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
FDENABLE .SET FALSE ; TRUE FOR FLOPPY DEVICE SUPPORT
FDMODE .SET FDMODE_DIDE ; FDMODE_DIO, FDMODE_DIDE, FDMODE_DIO3

4
Source/HBIOS/Config/N8_std.asm
View File

@ -6,8 +6,8 @@
#include "cfg_n8.asm"
;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 1 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .SET 3 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .SET 1 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 3 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
SDMODE .SET SDMODE_CSIO ; FOR N8 PROTOTYPE (DATECODE 2511), USE SDMODE_N8
;

4
Source/HBIOS/Config/RCZ180_ext.asm
View File

@ -7,8 +7,8 @@
;
MEMMGR .SET MM_Z2 ; 512K RAM/ROM MODULE MEM MGR
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .SET 1 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG

4
Source/HBIOS/Config/RCZ180_nat.asm
View File

@ -6,8 +6,8 @@
#include "cfg_rcz180.asm"
;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .SET 1 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG

7
Source/HBIOS/Config/RCZ180_sc126.asm
View File

@ -6,13 +6,14 @@
#include "cfg_rcz180.asm"
;
Z180_CLKDIV .SET 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .SET 1 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .SET 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .SET 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
DIAGPORT .SET $0D ; DIAGNOSTIC PORT ADDRESS
;
CPUOSC .SET 18432000 ; CPU OSC FREQ
DEFSERCFG .SET SER_38400_8N1 ; DEFAULT SERIAL LINE CONFIG
DSRTCMODE .SET DSRTCMODE_SC126 ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
;
ASCIENABLE .SET TRUE ; TRUE FOR Z180 ASCI SUPPORT
SIOENABLE .SET FALSE ; TRUE TO AUTO-DETECT ZILOG SIO/2
@ -30,5 +31,5 @@ DSRTCENABLE .SET TRUE ; DS-1302 CLOCK DRIVER
;
SDENABLE .SET TRUE ; TRUE FOR SD SUPPORT
SDMODE .SET SDMODE_SC126 ; SDMODE_JUHA, SDMODE_CSIO, SDMODE_UART, SDMODE_PPI, SDMODE_DSD
SDTRACE .SET 2 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDTRACE .SET 1 ; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF IDEENABLE = TRUE)
SDCSIOFAST .SET TRUE ; TABLE-DRIVEN BIT INVERTER

2
Source/HBIOS/cfg_ezz80.asm
View File

@ -21,7 +21,7 @@ DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU FALSE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT

10
Source/HBIOS/cfg_mk4.asm
View File

@ -21,7 +21,7 @@ DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
@ -100,14 +100,14 @@ BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
; 18.432MHz OSC @ FULL SPEED
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .EQU 1 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
; 18.432MHz OSC @ DOUBLE SPEED
;
;Z180_CLKDIV .EQU 2 ; 0=OSC/2, 1=OSC, 2=OSC*2
;Z180_MEMWAIT .EQU 1 ; MEMORY WAIT STATES TO INSERT (0-3)
;Z180_IOWAIT .EQU 1 ; IO WAIT STATES TO INSERT (0-3)
;Z180_MEMWAIT .EQU 1 ; MEMORY WAIT STATES (0-3)
;Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD

6
Source/HBIOS/cfg_n8.asm
View File

@ -21,7 +21,7 @@ DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
@ -94,8 +94,8 @@ BOOT_TIMEOUT .EQU 20 ; APPROX TIMEOUT IN SECONDS FOR AUTOBOOT, 0 FOR IMMEDIATE
BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 1 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .EQU 3 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .EQU 1 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 3 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD

6
Source/HBIOS/cfg_rcz180.asm
View File

@ -21,7 +21,7 @@ DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU FALSE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU TRUE ; TRUE FOR Z180 ASCI SUPPORT
@ -90,8 +90,8 @@ BOOT_DEFAULT .EQU 'Z' ; SELECTION TO INVOKE AT TIMEOUT
; 18.432MHz OSC @ FULL SPEED
;
Z180_CLKDIV .EQU 1 ; 0=OSC/2, 1=OSC, 2=OSC*2
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES TO INSERT (0-3)
Z180_IOWAIT .EQU 1 ; IO WAIT STATES TO INSERT (0-3)
Z180_MEMWAIT .EQU 0 ; MEMORY WAIT STATES (0-3)
Z180_IOWAIT .EQU 1 ; ADD (0-3) I/O WAIT STATES ABOVE 1 W/S BUILT-IN
;
PIO_4P .EQU FALSE ; TRUE FOR ECB-4PIO PIO SUPPORT
PIO_ZP .EQU FALSE ; TRUE FOR ECB-ZILOG PERIPHERALS BOARD

2
Source/HBIOS/cfg_rcz80.asm
View File

@ -21,7 +21,7 @@ DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU FALSE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT

2
Source/HBIOS/cfg_sbc.asm
View File

@ -21,7 +21,7 @@ DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT

2
Source/HBIOS/cfg_zeta.asm
View File

@ -21,7 +21,7 @@ DSKYENABLE .EQU FALSE ; TRUE FOR DSKY SUPPORT (DO NOT COMBINE WITH PPIDE)
HTIMENABLE .EQU FALSE ; TRUE FOR SIMH TIMER SUPPORT
SIMRTCENABLE .EQU FALSE ; SIMH CLOCK DRIVER
DSRTCENABLE .EQU TRUE ; DS-1302 CLOCK DRIVER
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC
DSRTCMODE .EQU DSRTCMODE_STD ; DSRTCMODE_STD, DSRTCMODE_MFPIC, DSRTCMODE_126
DSRTCCHG .EQU FALSE ; DS-1302 CONFIGURE CHARGE ON (TRUE) OR OFF (FALSE)
;
ASCIENABLE .EQU FALSE ; TRUE FOR Z180 ASCI SUPPORT

72
Source/HBIOS/dsrtc.asm
View File

@ -63,6 +63,26 @@
;
; CONSTANTS
;
; RTC SBC SBC-004 N8 N8-CSIO SC126
; ----- ------- ------- ------- ------- -------
; D7 WR RTC_OUT RTC_OUT RTC_OUT RTC_OUT RTC_OUT, I2C_SDA
; D6 WR RTC_CLK RTC_CLK RTC_CLK RTC_CLK RTC_CLK
; D5 WR /RTC_WE /RTC_WE /RTC_WE /RTC_WE /RTC_WE
; D4 WR RTC_CE RTC_CE RTC_CE RTC_CE RTC_CE
; D3 WR NC SPK NC NC /SPI_CS1
; D2 WR NC CLKHI SPI_CS SPI_CS /SPI_CS2
; D1 WR -- -- SPI_CLK NC FS
; D0 WR -- -- SPI_DI NC I2C_SCL
;
; D7 RD -- -- -- -- I2C_SDA
; D6 RD CFG CFG SPI_DO CFG --
; D5 RD -- -- -- -- --
; D4 RD -- -- -- -- --
; D3 RD -- -- -- -- --
; D2 RD -- -- -- -- --
; D1 RD -- -- -- -- --
; D0 RD RTC_IN RTC_IN RTC_IN RTC_IN RTC_IN
;
#IF (DSRTCMODE == DSRTCMODE_STD)
;
DSRTC_BASE .EQU RTC ; RTC PORT ON ALL SBC SERIES Z80 PLATFORMS
@ -75,6 +95,21 @@ DSRTC_CE .EQU %00010000 ; BIT 4 CONTROLS RTC CE LINE, 1 = HIGH (ENABLED)
DSRTC_RESET .EQU %00000000 ; ALL LOW
;
#ENDIF
;
#IF (DSRTCMODE == DSRTCMODE_SC126)
;
DSRTC_BASE .EQU RTC ; RTC PORT
;
DSRTC_DATA .EQU %10000000 ; BIT 7 CONTROLS RTC DATA (I/O) LINE
DSRTC_CLK .EQU %01000000 ; BIT 6 CONTROLS RTC CLOCK LINE, 1 = HIGH
DSRTC_RD .EQU %00100000 ; BIT 5 CONTROLS DATA DIRECTION, 1 = READ
DSRTC_CE .EQU %00010000 ; BIT 4 CONTROLS RTC CE LINE, 1 = HIGH (ENABLED)
;
DSRTC_RESET .EQU %00001101 ; /SPI_CS1, /SPI_CS2, & I2C_SCL HIGH
;
#ENDIF
;
#IF (DSRTCMODE == DSRTCMODE_MFPIC)
;
@ -103,6 +138,9 @@ DSRTC_INIT:
#IF (DSRTCMODE == DSRTCMODE_MFPIC)
PRTS("MFPIC$")
#ENDIF
#IF (DSRTCMODE == DSRTCMODE_SC126)
PRTS("SC126$")
#ENDIF
;
; CHECK FOR CLOCK HALTED
CALL DSRTC_TSTCLK
@ -123,22 +161,22 @@ DSRTC_INIT1:
LD HL,DSRTC_TIMBUF
CALL PRTDT
#IF DSRTCCHG ; FORCE_RTC_CHARGE_ENABLE
LD C,$8E ; ACCESS WRITE PROT REG
#IF DSRTCCHG ; FORCE_RTC_CHARGE_ENABLE
LD C,$8E ; ACCESS WRITE PROT REG
CALL DSRTC_CMD ;
LD A,$00 ; WRITE PROTECT OFF
LD A,$00 ; WRITE PROTECT OFF
CALL DSRTC_PUT ;
CALL DSRTC_END ; FINISH CMD
LD C,$90 ; ACCESS CHARGE REGISTER
LD C,$90 ; ACCESS CHARGE REGISTER
CALL DSRTC_CMD ;
LD A,$A5 ; STD CHARGE VALUES
LD A,$A5 ; STD CHARGE VALUES
CALL DSRTC_PUT ;
CALL DSRTC_END ; FINISH REG WRITE
LD C,$8E ; ACCESS WRITE PROT REG
LD C,$8E ; ACCESS WRITE PROT REG
CALL DSRTC_CMD ;
LD A,$80 ; WRITE PROTECT ON
LD A,$80 ; WRITE PROTECT ON
CALL DSRTC_PUT ;
CALL DSRTC_END ; FINISH CMD
#ENDIF
@ -362,7 +400,7 @@ DSRTC_WRCLK1:
CALL DSRTC_PUT ; WRITE REQUIRED 8TH BYTE
JP DSRTC_END ; FINISH IT
;
#IF (DSRTCMODE == DSRTCMODE_STD)
#IF ((DSRTCMODE == DSRTCMODE_STD) | (DSRTCMODE == DSRTCMODE_SC126))
;
; SEND COMMAND IN C TO RTC
; ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND.
@ -378,7 +416,7 @@ DSRTC_WRCLK1:
; 5) PUT COMMAND
;
DSRTC_CMD:
XOR A ; ALL LINES LOW TO RESET
LD A,DSRTC_RESET ; QUIESCENT STATE
OUT (DSRTC_BASE),A ; WRITE TO RTC PORT
CALL DLY2 ; DELAY 2 * 27 T-STATES
XOR DSRTC_CE ; NOW SET CE HIGH
@ -406,14 +444,14 @@ DSRTC_PUT:
LD B,8 ; LOOP FOR 8 BITS
LD C,A ; SAVE THE WORKING VALUE
DSRTC_PUT1:
LD A,DSRTC_CE ; SET CLOCK LOW
LD A,DSRTC_RESET | DSRTC_CE ; SET CLOCK LOW
OUT (DSRTC_BASE),A ; DO IT
CALL DLY1 ; DELAY 27 T-STATES
LD A,C ; RECOVER WORKING VALUE
RRCA ; ROTATE NEXT BIT TO SEND INTO BIT 7
LD C,A ; SAVE WORKING VALUE
AND %10000000 ; ISOLATE THE DATA BIT
OR DSRTC_CE ; KEEP CE HIGH
OR DSRTC_RESET | DSRTC_CE ; KEEP CE HIGH
OUT (DSRTC_BASE),A ; ASSERT DATA BIT ON BUS
OR DSRTC_CLK ; SET CLOCK HI
OUT (DSRTC_BASE),A ; DO IT
@ -439,7 +477,7 @@ DSRTC_GET:
LD C,0 ; INITIALIZE WORKING VALUE TO 0
LD B,8 ; LOOP FOR 8 BITS
DSRTC_GET1:
LD A,DSRTC_CE | DSRTC_RD ; SET CLK LO
LD A,DSRTC_RESET | DSRTC_CE | DSRTC_RD ; SET CLK LO
OUT (DSRTC_BASE),A ; WRITE TO RTC PORT
CALL DLY2 ; DELAY 2 * 27 T-STATES
IN A,(DSRTC_BASE) ; READ THE RTC PORT
@ -447,7 +485,7 @@ DSRTC_GET1:
OR C ; COMBINE WITH WORKING VALUE
RRCA ; ROTATE FOR NEXT BIT
LD C,A ; SAVE WORKING VALUE
LD A,DSRTC_CE | DSRTC_CLK | DSRTC_RD ; CLOCK BACK TO HI
LD A,DSRTC_RESET | DSRTC_CE | DSRTC_CLK | DSRTC_RD ; CLOCK BACK TO HI
OUT (DSRTC_BASE),A ; WRITE TO RTC PORT
CALL DLY1 ; DELAY 27 T-STATES
DJNZ DSRTC_GET1 ; LOOP IF NOT DONE (13)
@ -462,7 +500,7 @@ DSRTC_GET1:
;
DSRTC_END:
PUSH AF ; SAVE AF
XOR A ; ALL LINES OFF TO CLEAN UP
LD A,DSRTC_RESET ; QUIESCENT STATE
OUT (DSRTC_BASE),A ; WRITE TO RTC PORT
POP AF ; RESTORE AF
RET
@ -514,7 +552,7 @@ DSRTC_CMD:
DSRTC_PUT:
LD B,8 ; LOOP FOR 8 BITS
LD C,A ; SAVE THE WORKING VALUE
LD A,DSRTC_WR | DSRTC_CLK ; MODE=WRITE, CLOCK ON, CE ACTIVE (0)
LD A,DSRTC_RESET | DSRTC_WR | DSRTC_CLK ; MODE=WRITE, CLOCK ON, CE ACTIVE (0)
DSRTC_PUT1:
XOR DSRTC_CLK ; FLIP CLOCK OFF
OUT (DSRTC_BASE),A ; DO IT
@ -546,7 +584,7 @@ DSRTC_PUT1:
DSRTC_GET:
LD C,0 ; INITIALIZE WORKING VALUE TO 0
LD B,8 ; LOOP FOR 8 BITS
LD A,DSRTC_CLK ; MODE=READ, CLOCK ON, CE ACTIVE (0)
LD A,DSRTC_RESET | DSRTC_CLK ; MODE=READ, CLOCK ON, CE ACTIVE (0)
DSRTC_GET1:
XOR DSRTC_CLK ; FLIP CLOCK OFF
OUT (DSRTC_BASE),A ; DO IT
@ -554,7 +592,7 @@ DSRTC_GET1:
IN A,(DSRTC_BASE) ; READ THE RTC PORT
RRA ; DATA BIT TO CARRY
RR C ; SHIFT INTO WORKING VALUE
LD A,DSRTC_CLK ; CLOCK ON
LD A,DSRTC_RESET | DSRTC_CLK ; CLOCK ON
OUT (DSRTC_BASE),A ; WRITE TO RTC PORT
CALL DLY1 ; DELAY 27 T-STATES
DJNZ DSRTC_GET1 ; LOOP IF NOT DONE

14
Source/HBIOS/hbios.asm
View File

@ -2882,31 +2882,19 @@ HB_WAITSEC1:
JP $ + 3 ; 10 TSTATES
JP $ + 3 ; 10 TSTATES
JP $ + 3 ; 10 TSTATES
;LD A,R ; 9 TSTATES
INC BC ; 6 TSTATES
;LD A,(BC) ; 7 TSTATES
;NOP ; 4 TSTATES
NOP ; 4 TSTATES
#ENDIF
#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RCZ180))
; LOOP TARGET IS 8000 T-STATES, SO CPU FREQ IN KHZ = LOOP COUNT * 8
;CALL DLY64
CALL DLY32
CALL DLY16
CALL DLY8
CALL DLY4
CALL DLY2
CALL DLY1 ; CALL (25TS) & RET (18TS) = 43TS
OR A ; 7 TSTATES
OR A ; 7 TSTATES
;OR A ; 7 TSTATES
;OR A ; 7 TSTATES
ADD A,A ; 4 TSTATES
NOP ; 6 TSTATES
;NOP ; 6 TSTATES
;NOP ; 6 TSTATES
;NOP ; 6 TSTATES
;NOP ; 6 TSTATES
#ENDIF
;
PUSH DE

18
Source/HBIOS/sd.asm
View File

@ -9,14 +9,14 @@
; - TEST XC CARD TYPE DETECTION
; - TRY TO GET INIT TO FAIL, REMOVE DELAYS AT START OF GOIDLE?
;
;------------------------------------------------------------------------------
; SD Signal Active JUHA N8 CSIO PPI UART DSD MK4
; ------------ ------- ------- ------- ------- ------- ------- ------- -------
; CS (DAT3) LO -> RTC:2 RTC:2 RTC:2 ~PC:4 ~MCR:3 OPR:2 MK4_SD:2
; CLK HI -> RTC:1 RTC:1 N/A PC:1 ~MCR:2 OPR:1 N/A
; DI (CMD) HI -> RTC:0 RTC:0 N/A PC:0 ~MCR:0 OPR:0 N/A
; DO (DAT0) HI -> RTC:7 RTC:6 N/A PB:7 ~MSR:5 OPR:0 N/A
;------------------------------------------------------------------------------
;--------------------------------------------------------------------------------------
; SD Signal Active JUHA N8 CSIO PPI UART DSD MK4 SC126
; ------------ ------- ------- ------- ------- ------- ------- ------- ------- -------
; CS (DAT3) LO -> RTC:2 RTC:2 RTC:2 ~PC:4 ~MCR:3 OPR:2 SD:2 ~RTC:2
; CLK HI -> RTC:1 RTC:1 CSIO PC:1 ~MCR:2 OPR:1 CSIO CSIO
; DI (CMD) HI -> RTC:0 RTC:0 CSIO PC:0 ~MCR:0 OPR:0 CSIO CSIO
; DO (DAT0) HI -> RTC:7 RTC:6 CSIO PB:7 ~MSR:5 OPR:0 CSIO CSIO
;--------------------------------------------------------------------------------------
;
; CS = CHIP SELECT (AKA DAT3 FOR NON-SPI MODE)
; CLK = CLOCK
@ -158,7 +158,7 @@ SD_CNTR .EQU Z180_CNTR
SD_TRDR .EQU Z180_TRDR
#ENDIF
;
#IF (SDMODE == SDMODE_SC126) ; N8-2312
#IF (SDMODE == SDMODE_SC126) ; SC126
SD_DEVCNT .EQU 1 ; NUMBER OF PHYSICAL UNITS (SOCKETS)
SD_OPRREG .EQU RTC ; USES RTC LATCHES FOR OPERATION
SD_OPRDEF .EQU %00001101 ; QUIESCENT STATE

1
Source/HBIOS/std.asm
View File

@ -90,6 +90,7 @@ MID_FD111 .EQU 9
DSRTCMODE_NONE .EQU 0 ; NO DSRTC
DSRTCMODE_STD .EQU 1 ; ORIGINAL DSRTC CIRCUIT (SBC, ZETA, MK4)
DSRTCMODE_MFPIC .EQU 2 ; MF/PIC VARIANT
DSRTCMODE_SC126 .EQU 3 ; SC126 VARIANT
;
; SIO MODE SELECTIONS
;

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