Beep Support Updates

8 years ago · 5b08693ba2
10 changed files with 176 additions and 166 deletions
--- a/Source/HBIOS/ay.asm
+++ b/Source/HBIOS/ay.asm
@ -0,0 +1,101 @@
+;
+;======================================================================
+; PSG AY-3-8910 DRIVER FOR CONSOLE BELL
+; WILL ALSO WORK WITH YM2149
+;======================================================================
+;
+AY_RSEL		.EQU	$9A
+AY_RDAT		.EQU	$9B
+AY_ACR		.EQU	$9C
+AY_R0CHAP	.EQU	$00
+AY_R1CHAP	.EQU	$01
+AY_R2CHBP	.EQU	$02
+AY_R3CHBP	.EQU	$03
+AY_R7ENAB	.EQU	$07
+AY_R8AVOL	.EQU	$08
+AY_R9BVOL	.EQU	$09 
+;
+;======================================================================
+; PSG AY-3-8910 DRIVER - INITIALIZATION
+;======================================================================
+;
+AY_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("AY: IO=0x$")
+	LD	A,AY_RSEL
+	CALL	PRTHEXBYTE
+	CALL	AY_PROBE		; CHECK FOR HW EXISTENCE
+	JR	Z,AY_INIT1		; CONTINUE IF PRESENT
+;
+;	HARDWARE NOT PRESENT
+;
+	PRTS(" NOT PRESENT$")
+	OR	$FF			; SIGNAL FAILURE
+	RET
+;	
+AY_INIT1:
+	CALL	AY_INIT2
+	CALL	AY_BEEP
+AY_INIT2:
+	LD	D,AY_R7ENAB		; SET MIXER CONTROL / IO ENABLE
+	LD	E,$FF			; $FF - 11 111 111
+	CALL	AY_WRTPSG		; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A DISABLE
+;  
+	LD	B,2
+	LD	D,AY_R8AVOL		; SET VOLUME TO 0
+	LD	E,$00	
+AY_QUIET:
+	CALL	AY_WRTPSG		; CYCLING THROUGH ALL CHANNELS
+	INC	A
+	DJNZ	AY_QUIET
+	RET
+;
+;	PLAY A BEEP TONE ON CENTER CHANNEL (LEFT AND RIGHT SPEAKERS)
+;	
+AY_BEEP:
+	LD	D,AY_R2CHBP		; SET TONE PERIOD 
+	LD	E,$55			; CHANNEL B  - R00 & R01
+	CALL	AY_WRTPSG		; $0055 = XXXX0000 01010101 
+	LD	D,AY_R3CHBP
+	LD	E,0
+	CALL	AY_WRTPSG
+;
+	LD	D,AY_R7ENAB		; $FD = 11 111 101
+	LD	E,$FD			; SET MIXER CONTROL / IO ENABLE
+	CALL	AY_WRTPSG		; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL B ENABLE
+;  
+	LD	D,AY_R9BVOL
+	LD	E,$07			; SET CHANNEL B VOLUME TO 50% (7/16)
+	CALL	AY_WRTPSG
+;  
+	CALL	LDELAY			; HALF SECOND 
+	RET	
+;	
+; WRITE DATA E TO PSG REG A  
+; 
+AY_WRTPSG:
+	HB_DI
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+	IN0	A,(Z180_DCNTL)		; GET WAIT STATES
+	PUSH	AF			; SAVE VALUE
+	OR	%00110000		; FORCE SLOW OPERATION (I/O W/S=3)
+	OUT0	(Z180_DCNTL),A		; AND UPDATE DCNTL
+#ENDIF
+	LD	A,D
+	OUT	(AY_RSEL),A
+	LD	A,E
+	OUT	(AY_RDAT),A
+#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4) | (PLATFORM == PLT_RC180))
+	POP	AF			; GET SAVED DCNTL VALUE
+	OUT0	(Z180_DCNTL),A		; AND RESTORE IT
+#ENDIF
+	HB_EI
+	RET	
+;
+; CHECK THERE IS A DEVICE PRESENT
+;
+AY_PROBE:
+	LD	A,$FF
+	OUT	(AY_ACR),A		; INIT AUX CONTROL REG
+	XOR	A
+	RET
--- a/Source/HBIOS/cfg_mk4.asm
+++ b/Source/HBIOS/cfg_mk4.asm
@ -32,7 +32,9 @@ CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
 TMSENABLE	.EQU	FALSE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
 VGAENABLE	.EQU	FALSE		; TRUE FOR VGA VIDEO/KBD SUPPORT
-SNDENABLE	.EQU	FALSE		; TRUE FOR PSG OR IOBIT SOUND
+;
+SPKENABLE	.EQU	FALSE		; TRUE FOR RTC LATCH IOBIT SOUND
+AYENABLE	.EQU	FALSE		; TRUE FOR AY PSG SOUND
 ;
 MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
 MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
--- a/Source/HBIOS/cfg_n8.asm
+++ b/Source/HBIOS/cfg_n8.asm
@ -32,7 +32,9 @@ CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
 TMSENABLE	.EQU	TRUE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
 VGAENABLE	.EQU	FALSE		; TRUE FOR VGA VIDEO/KBD SUPPORT
-SNDENABLE	.EQU	FALSE		; TRUE FOR PSG OR IOBIT SOUND
+;
+SPKENABLE	.EQU	FALSE		; TRUE FOR RTC LATCH IOBIT SOUND
+AYENABLE	.EQU	FALSE		; TRUE FOR AY PSG SOUND
 ;
 MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
 MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
--- a/Source/HBIOS/cfg_rc.asm
+++ b/Source/HBIOS/cfg_rc.asm
@ -38,7 +38,9 @@ CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
 TMSENABLE	.EQU	FALSE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
 VGAENABLE	.EQU	FALSE		; TRUE FOR VGA VIDEO/KBD SUPPORT
-SNDENABLE	.EQU	FALSE		; TRUE FOR PSG OR IOBIT SOUND
+;
+SPKENABLE	.EQU	FALSE		; TRUE FOR RTC LATCH IOBIT SOUND
+AYENABLE	.EQU	FALSE		; TRUE FOR AY PSG SOUND
 ;
 MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
 MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
--- a/Source/HBIOS/cfg_rc180.asm
+++ b/Source/HBIOS/cfg_rc180.asm
@ -32,7 +32,9 @@ CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
 TMSENABLE	.EQU	FALSE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
 VGAENABLE	.EQU	FALSE		; TRUE FOR VGA VIDEO/KBD SUPPORT
-SNDENABLE	.EQU	FALSE		; TRUE FOR PSG OR IOBIT SOUND
+;
+SPKENABLE	.EQU	FALSE		; TRUE FOR RTC LATCH IOBIT SOUND
+AYENABLE	.EQU	FALSE		; TRUE FOR AY PSG SOUND
 ;
 MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
 MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
--- a/Source/HBIOS/cfg_sbc.asm
+++ b/Source/HBIOS/cfg_sbc.asm
@ -38,9 +38,9 @@ CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
 TMSENABLE	.EQU	FALSE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
 VGAENABLE	.EQU	FALSE		; TRUE FOR VGA VIDEO/KBD SUPPORT
-SNDENABLE	.EQU	TRUE		; TRUE FOR PSG OR IOBIT SOUND
-CONBELL		.EQU	CONBELL_PSG ; CONBELL_IOBIT / CONBELL_PSG
-
+;
+SPKENABLE	.EQU	FALSE		; TRUE FOR RTC LATCH IOBIT SOUND
+AYENABLE	.EQU	FALSE		; TRUE FOR AY PSG SOUND
 ;
 MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
 MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
--- a/Source/HBIOS/cfg_zeta.asm
+++ b/Source/HBIOS/cfg_zeta.asm
@ -32,7 +32,9 @@ CVDUENABLE	.EQU	FALSE		; TRUE FOR CVDU BOARD SUPPORT
 NECENABLE	.EQU	FALSE		; TRUE FOR uPD7220 BOARD SUPPORT
 TMSENABLE	.EQU	FALSE		; TRUE FOR N8 (TMS9918) VIDEO/KBD SUPPORT
 VGAENABLE	.EQU	FALSE		; TRUE FOR VGA VIDEO/KBD SUPPORT
-SNDENABLE	.EQU	FALSE		; TRUE FOR PSG OR IOBIT SOUND
+;
+SPKENABLE	.EQU	FALSE		; TRUE FOR RTC LATCH IOBIT SOUND
+AYENABLE	.EQU	FALSE		; TRUE FOR AY PSG SOUND
 ;
 MDENABLE	.EQU	TRUE		; TRUE FOR ROM/RAM DISK SUPPORT (ALMOST ALWAYS WANT THIS ENABLED)
 MDTRACE		.EQU	1		; 0=SILENT, 1=ERRORS, 2=EVERYTHING (ONLY RELEVANT IF MDENABLE = TRUE)
--- a/Source/HBIOS/hbios.asm
+++ b/Source/HBIOS/hbios.asm
@ -348,10 +348,6 @@ HBX_BNKSEL1:
 ;::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::::
 ;
 HBX_BNKCPY:
-;#IF (INTMODE < 2)
-;	DI
-;#ENDIF
-
 	LD	(HBX_BC_SP),SP		; PUT STACK
 	LD	SP,HBX_TMPSTK		; ... IN HI MEM

@ -381,10 +377,6 @@ HBX_BC_LAST:

 	LD	SP,$FFFF		; RESTORE STACK
 HBX_BC_SP	.EQU	$ - 2		; ... TO ORIGINAL VALUE
-
-;#IF (INTMODE == 1)
-;	EI
-;#ENDIF
 	RET
 ;
 HBX_BC_ITER:
@ -437,9 +429,6 @@ HBX_TGTADR	.EQU	$ + 1
 ;   CALLER MUST DISABLE INTS IF IM1 AND ACCESSING PAGE W/O IM1 INT VECTOR
 ;
 HBX_PEEK:
-;#IF (INTMODE < 2)
-;	DI
-;#ENDIF
 	LD	(HBX_PPSP),SP		; SAVE ORIGINAL STACK FRAME
 	LD	SP,HBX_TMPSTK		; USE SMALL TEMP STACK FRAME IN HI MEM
 	LD	A,(HB_CURBNK)
@ -450,9 +439,6 @@ HBX_PEEK:
 	JR	HBX_PPRET
 ;
 HBX_POKE:
-;#IF (INTMODE < 2)
-;	DI
-;#ENDIF
 	LD	(HBX_PPSP),SP		; SAVE ORIGINAL STACK FRAME
 	LD	SP,HBX_TMPSTK		; USE SMALL TEMP STACK FRAME IN HI MEM
 	LD	A,(HB_CURBNK)
@ -466,9 +452,6 @@ HBX_PPRET:
 	CALL	HBX_BNKSEL
 	LD	SP,0			; RESTORE ORIGINAL STACK FRAME
 HBX_PPSP	.EQU	$ - 2
-;#IF (INTMODE == 1)
-;	EI
-;#ENDIF
 	RET
 ;
 ; SMALL TEMPORARY STACK FOR USE BY INVOKE, PEEK, AND POKE
@ -930,7 +913,7 @@ PSCNX	.EQU	$ + 1

 #IF (PLATFORM == PLT_SBC)
 ;
-  #IF (HTIMENABLE)
+  #IF (HTIMENABLE)			; SIMH TIMER
 ;
    #IF (INTMODE == 1)
 	LD	HL,HB_TIMINT
@ -1135,8 +1118,11 @@ INITSYS3:
 ;==================================================================================================
 ;
 HB_INITTBL:
-#IF (SNDENABLE)
-	.DW	SND_INIT						; AUDIBLE INDICATOR OF BOOT START
+#IF (SPKENABLE)
+	.DW	SPK_INIT		; AUDIBLE INDICATOR OF BOOT START
+#ENDIF
+#IF (AYENABLE)
+	.DW	AY_INIT			; AUDIBLE INDICATOR OF BOOT START
 #ENDIF
 #IF (ASCIENABLE)
 	.DW	ASCI_INIT
@ -2231,15 +2217,23 @@ SIZ_TERM	.EQU	$ - ORG_TERM
 		.ECHO	" bytes.\n"
 #ENDIF
 ;
-#IF (SNDENABLE)
-ORG_SND	.EQU	$
-  #INCLUDE "sound.asm"
-SIZ_SND	.EQU	$ - ORG_SND
-		.ECHO	"SND occupies "
-		.ECHO	SIZ_SND
+#IF (SPKENABLE)
+ORG_SPK	.EQU	$
+  #INCLUDE "spk.asm"
+SIZ_SPK	.EQU	$ - ORG_SPK
+		.ECHO	"SPK occupies "
+		.ECHO	SIZ_SPK
+		.ECHO	" bytes.\n"
+#ENDIF
+;
+#IF (AYENABLE)
+ORG_AY	.EQU	$
+  #INCLUDE "ay.asm"
+SIZ_AY	.EQU	$ - ORG_AY
+		.ECHO	"AY occupies "
+		.ECHO	SIZ_AY
 		.ECHO	" bytes.\n"
 #ENDIF
-
 ;
 #DEFINE USEDELAY
 #INCLUDE "util.asm"
--- a/Source/HBIOS/sound.asm
+++ b/Source/HBIOS/sound.asm
@ -1,131 +0,0 @@
-;
-;======================================================================
-; PSG AY-3-8910 DRIVER FOR CONSOLE BELL
-;======================================================================
-;
-#IF (CONBELL == CONBELL_PSG)
-
-PSG_RSEL	.EQU	$9A
-PSG_RDAT	.EQU	$9B
-PSG_ACR		.EQU	$9C
-AYR0CHAP	.EQU	$00
-AYR1CHAP	.EQU	$01
-AYR2CHBP	.EQU	$02
-AYR3CHBP	.EQU	$03
-AYR7ENAB	.EQU	$07
-AYR8AVOL	.EQU	$08
-AYR9BVOL	.EQU	$09 
-;
-;======================================================================
-; PSG AY-3-8910 DRIVER - INITIALIZATION
-;======================================================================
-;
-SND_INIT:
-	CALL	NEWLINE			; FORMATTING
-	PRTS("PSG: IO=0x$")
-	LD		A,PSG_RSEL
-	CALL	PRTHEXBYTE
-	CALL	PSG_PROBE		; CHECK FOR HW EXISTENCE
-	JR		Z,PSG_INIT1			; CONTINUE IF PRESENT
-;
-;	HARDWARE NOT PRESENT
-;
-	PRTS(" NOT PRESENT$")
-	OR		$FF					; SIGNAL FAILURE
-	RET
-;	
-PSG_INIT1:
-	CALL	PSG_INIT2
-	CALL	BEEP
-PSG_INIT2:
-	LD		A,AYR7ENAB		; SET MIXER CONTROL / IO ENABLE
-	LD		E,$FF			; $FF - 11 111 111
-	CALL	WRTPSG			; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A DISABLE
-;  
-	LD B,2
-	LD A,AYR8AVOL		; SET VOLUME TO 0
-	LD E,$00	
-AYQUIET:
-	CALL WRTPSG			; CYCLING THROUGH ALL CHANNELS
-	INC A
-	DJNZ AYQUIET
-	RET
-;
-;	PLAY A BEEP TONE ON CENTER CHANNEL (LEFT AND RIGHT SPEAKERS)
-;	
-BEEP:
-  LD A,AYR2CHBP		; SET TONE PERIOD 
-  LD E,$55			; CHANNEL B  - R00 & R01
-  CALL WRTPSG		; $0055 = XXXX0000 01010101 
-  LD E,0
-  LD A,AYR3CHBP
-  CALL WRTPSG
-;
-  LD E,$FD			; SET MIXER CONTROL / IO ENABLE
-  LD A,AYR7ENAB		; $FD = 11 111 101
-  CALL WRTPSG		; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL B ENABLE
-;  
-  LD E,$07			; SET CHANNEL B VOLUME TO 50% (7/16)
-  LD A,AYR9BVOL		;
-  CALL WRTPSG
-;  
-  CALL LDELAY		; HALF SECOND 
-  RET	
-;	
-; WRITE DATA E TO PSG REG A  
-; 
-WRTPSG:
-	HB_DI
-	OUT (PSG_RSEL),A
-	PUSH AF
-	LD A,E
-	OUT (PSG_RDAT),A
-	HB_EI
-	POP AF
-	RET	
-;
-; CHECK THERE IS A DEVICE PRESENT
-;
-PSG_PROBE:
-	LD	A,$FF
-	OUT	(PSG_ACR),A		; INIT AUX CONTROL REG
-	XOR A
-	RET
-;
-#ENDIF
-;
-;======================================================================
-; I/O BIT DRIVER FOR CONSOLE BELL FOR SBC V2 USING BIT 0 OF RTC DRIVER
-;======================================================================
-;
-#IF (CONBELL == CONBELL_IOBIT)
-
-SND_INIT:
-	CALL	NEWLINE			; FORMATTING
-	PRTS("SND: IO=0x$")
-	LD		A,DSRTC_BASE
-	CALL	PRTHEXBYTE
-	CALL	BEEP
-	XOR		A
-	RET
-
-BEEP:	
-	PUSH	DE
-	PUSH	HL
-	LD		HL,400		; Cycles of tone
-	LD		B,%00000100	; D2 mapped to Q0
-BEEP1:
-	LD		A,B
-	OUT		(DSRTC_BASE),A
-	XOR		%00000100
-	LD		B,A
-	LD		DE,17
-	CALL	VDELAY
-	DEC		HL
-	LD		A,H
-	OR		L
-	JR		NZ,BEEP1
-	POP		HL
-	POP		DE
-	RET
-#ENDIF
--- a/Source/HBIOS/spk.asm
+++ b/Source/HBIOS/spk.asm
@ -0,0 +1,36 @@
+;
+;======================================================================
+; I/O BIT DRIVER FOR CONSOLE BELL FOR SBC V2 USING BIT 0 OF RTC DRIVER
+;======================================================================
+;
+SPK_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("SPK: IO=0x$")
+	LD	A,DSRTC_BASE
+	CALL	PRTHEXBYTE
+	CALL	SPK_BEEP
+	XOR		A
+	RET
+;
+SPK_BEEP:
+	PUSH	DE
+	PUSH	HL
+	LD	HL,400			; CYCLES OF TONE
+	;LD	B,%00000100		; D2 MAPPED TO Q0
+	LD	A,DSRTC_RESET
+	OR	%00000100		; D2 MAPPED TO Q0
+	LD	B,A
+SPK_BEEP1:
+	LD	A,B
+	OUT	(DSRTC_BASE),A
+	XOR	%00000100
+	LD	B,A
+	LD	DE,17
+	CALL	VDELAY
+	DEC	HL
+	LD	A,H
+	OR	L
+	JR	NZ,SPK_BEEP1
+	POP	HL
+	POP	DE
+	RET