best so far, assembles without errors but not all

I/O addresses are right yet...

branches/s100/Source/std-s100.inc

@@ -3,174 +3,62 @@
 ;===============================================================================
 ;------------------------------------------------------------------------------
 ;
+; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
 ;
-VDADEV_NONE	.EQU	$00		; NO VDA DEVICE
+MPCL_RAM	.EQU 	78H		; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
+MPCL_ROM	.EQU 	7CH		; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
+RTC		.EQU	70H		; ADDRESS OF RTC LATCH AND INPUT PORT
+
 ;
 ; CHARACTER DEVICES
 ;
-CIODEV_UART	.EQU	$00
+;CIODEV_UART	.EQU	$00
+CIODEV_N8V	.EQU    $50
+CIODEV_PRPCON	.EQU	$60
+CIODEV_PPPCON	.EQU	$70
+CIODEV_CRT	.EQU	$D0
+;CIODEV_BAT	.EQU	$E0
 CIODEV_NUL	.EQU	$F0
+
 ;
 ; DISK DEVICES (ONLY FIRST NIBBLE RELEVANT, SECOND NIBBLE RESERVED FOR UNIT)
 ;
-DIODEV_MD	.EQU	$00
+;DIODEV_MD	.EQU	$00
 DIODEV_FD	.EQU	$10
 DIODEV_IDE	.EQU	$20
-;
-; RAM DISK INITIALIZATION OPTIONS
-;
-CLR_NEVER	.EQU	0		; NEVER CLEAR RAM DISK
-CLR_AUTO	.EQU	1		; CLEAR RAM DISK IF INVALID DIR ENTRIES
-CLR_ALWAYS	.EQU	2		; ALWAYS CLEAR RAM DISK
-;
-; DISK MAP SELECTION OPTIONS
-;
-DM_ROM		.EQU	1		; ROM DRIVE PRIORITY
-DM_RAM		.EQU	2		; RAM DRIVE PRIORITY
-DM_FD		.EQU	3		; FLOPPY DRIVE PRIORITY
-DM_IDE		.EQU	4		; IDE DRIVE PRIORITY
-DM_HDSK		.EQU	9		; SIMH HARD DISK DRIVE PRIORITY
-;
-; FLOPPY DISK MEDIA SELECTIONS (ID'S MUST BE INDEX OF ENTRY IN FCD_TBL)
-;
-FDM720		.EQU	0		; 3.5" FLOPPY, 720KB, 2 SIDES, 80 TRKS, 9 SECTORS
-FDM144		.EQU	1		; 3.5" FLOPPY, 1.44MB, 2 SIDES, 80 TRKS, 18 SECTORS
-FDM360		.EQU	2		; 5.25" FLOPPY, 360KB, 2 SIDES, 40 TRKS, 9 SECTORS
-FDM120		.EQU	3		; 5.25" FLOPPY, 1.2MB, 2 SIDES, 80 TRKS, 15 SECTORS
-FDM111		.EQU	4		; 8" FLOPPY, 1.11MB, 2 SIDES, 74 TRKS, 15 SECTORS
-;
-; MEDIA ID VALUES
-;
-MID_NONE	.EQU	0
-MID_MDROM	.EQU	1
-MID_MDRAM	.EQU	2
-MID_HD		.EQU	3
-MID_FD720	.EQU	4
-MID_FD144	.EQU	5
-MID_FD360	.EQU	6
-MID_FD120	.EQU	7
-MID_FD111	.EQU	8
-;
-; FD MODE SELECTIONS
-;
-FDMODE_ZFDC	.EQU	1		; 
+DIODEV_ATAPI	.EQU	$30
+DIODEV_PPIDE	.EQU	$40
+DIODEV_SD	.EQU	$50
+DIODEV_PRPSD	.EQU	$60
+DIODEV_PPPSD	.EQU	$70
+DIODEV_HDSK	.EQU	$80
 
+;__HARDWARE_INTERFACES________________________________________________________________________________________________________________ 
 ;
-; IDE MODE SELECTIONS
-;
-IDEMODE_DIO	.EQU	1		; DISKIO V1
-IDEMODE_DIDE	.EQU	2		; DUAL IDE
-;
-; PPIDE MODE SELECTIONS
-;
-PPIDEMODE_STD	.EQU	1		; STANDARD N8VEM PARALLEL PORT
-PPIDEMODE_DIO3	.EQU	2		; DISKIO V3 PARALLEL PORT
-;
-; CONSOLE TERMINAL TYPE CHOICES
-;
-TERM_TTY	.EQU	0
-TERM_ANSI	.EQU	1
-TERM_WYSE	.EQU	2
-TERM_VT52	.EQU	3
-;
-; EMULATION TYPES
-;
-EMUTYP_NONE	.EQU	0
-EMUTYP_TTY	.EQU	1
-EMUTYP_ANSI	.EQU	2
-;
-; SYSTEM GENERATION SETTINGS
-;
-SYS_CPM		.EQU	1		; CPM (IMPLIES BDOS + CCP)
-SYS_ZSYS	.EQU	2		; ZSYSTEM OS (IMPLIES ZSDOS + ZCPR)
-;
-DOS_BDOS	.EQU	1		; BDOS
-DOS_ZDDOS	.EQU	2		; ZDDOS VARIANT OF ZSDOS
-DOS_ZSDOS	.EQU	3		; ZSDOS
-;
-CP_CCP		.EQU	1		; CCP COMMAND PROCESSOR
-CP_ZCPR		.EQU	2		; ZCPR COMMAND PROCESSOR
-;
-; CONFIGURE DOS (DOS) AND COMMAND PROCESSOR (CP) BASED ON SYSTEM SETTING (SYS)
+; PPI 82C55 I/O IS DECODED TO PORT 60-67
 ;
-#IFNDEF BLD_SYS
-SYS		.EQU	SYS_CPM
-#ELSE
-SYS		.EQU	BLD_SYS
-#ENDIF
-;
-#IF (SYS == SYS_CPM)
-DOS		.EQU	DOS_BDOS
-CP		.EQU	CP_CCP
-#DEFINE		OSLBL	"CP/M-80 2.2"
-#ENDIF
-;
-#IF (SYS == SYS_ZSYS)
-DOS		.EQU	DOS_ZSDOS
-CP		.EQU	CP_ZCPR
-#DEFINE		OSLBL	"ZSDOS 1.1"
-#ENDIF
-;
-; INCLUDE VERSION AND BUILD SETTINGS
-;
-#INCLUDE "ver.inc"			; ADD BIOSVER
-;
-#INCLUDE "build.inc"			; INCLUDE USER CONFIG, ADD VARIANT, TIMESTAMP, & ROMSIZE
-;
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Support for S100COMPUTERS.COM Hardware ;
-; Phase One Support - Minimum Board Set  ;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-#IF (PLATFORM == PLT_S100)
-;
-#IFDEF S100_CPU
-#INCLUDE "S100CPU.INC"
-#ENDIF
-;
-#IFDEF S100_IOB
-#INCLUDE "S100IOB.INC"
-#ENDIF
-;
-#IFDEF S100_RRF
-#INCLUDE "S100RRF.INC"
-#ENDIF
-;
-#IFDEF S100_DIDE
-#INCLUDE "S100DIDE.INC"
-#ENDIF
-;
-#ENDIF
+PPIBASE		.EQU	60H
+PPIA		.EQU 	PPIBASE + 0	; PORT A
+PPIB		.EQU 	PPIBASE + 1	; PORT B
+PPIC		.EQU 	PPIBASE + 2	; PORT C
+PPIX	 	.EQU 	PPIBASE + 3	; PPI CONTROL PORT
 
-
-;
-; N8VEM HARDWARE IO PORT ADDRESSES AND MEMORY LOCATIONS
-;
-MPCL_RAM	.EQU 	78H		; BASE IO ADDRESS OF RAM MEMORY PAGER CONFIGURATION LATCH
-MPCL_ROM	.EQU 	7CH		; BASE IO ADDRESS OF ROM MEMORY PAGER CONFIGURATION LATCH
-RTC		.EQU	70H		; ADDRESS OF RTC LATCH AND INPUT PORT
-
-;
-; MEMORY LAYOUT
-;
-CPM_LOC		.EQU	0D000H			; CONFIGURABLE: LOCATION OF CPM FOR RUNNING SYSTEM
-CPM_SIZ		.EQU	2F00H			; SIZE OF CPM IMAGE (CCP + BDOS + CBIOS (INCLUDING DATA))
-CPM_END		.EQU	CPM_LOC + CPM_SIZ
-;
-CCP_LOC		.EQU	CPM_LOC			; START OF COMMAND PROCESSOR
-CCP_SIZ		.EQU	800H
-CCP_END		.EQU	CCP_LOC + CCP_SIZ
-;
-BDOS_LOC	.EQU	CCP_END			; START OF BDOS
-BDOS_SIZ	.EQU	0E00H
-BDOS_END	.EQU	BDOS_LOC + BDOS_SIZ
-;
-CBIOS_LOC	.EQU	BDOS_END
-CBIOS_SIZ	.EQU	CPM_END - CBIOS_LOC
-CBIOS_END	.EQU	CBIOS_LOC + CBIOS_SIZ
-;
+; 16C550 SERIAL LINE UART
+;
+SIO_BASE	.EQU	68H
+SIO_RBR		.EQU	SIO_BASE + 0	; DLAB=0: RCVR BUFFER REG (READ ONLY)
+SIO_THR		.EQU	SIO_BASE + 0	; DLAB=0: XMIT HOLDING REG (WRITE ONLY)
+SIO_IER		.EQU	SIO_BASE + 1	; DLAB=0: INT ENABLE REG
+SIO_IIR		.EQU	SIO_BASE + 2	; INT IDENT REGISTER (READ ONLY)
+SIO_FCR		.EQU	SIO_BASE + 2	; FIFO CONTROL REG (WRITE ONLY)
+SIO_LCR		.EQU	SIO_BASE + 3	; LINE CONTROL REG
+SIO_MCR		.EQU	SIO_BASE + 4	; MODEM CONTROL REG
+SIO_LSR		.EQU	SIO_BASE + 5	; LINE STATUS REG
+SIO_MSR		.EQU	SIO_BASE + 6	; MODEM STATUS REG
+SIO_SCR		.EQU	SIO_BASE + 7	; SCRATCH REGISTER
+SIO_DLL		.EQU	SIO_BASE + 0	; DLAB=1: DIVISOR LATCH (LS)
+SIO_DLM		.EQU	SIO_BASE + 1	; DLAB=1: DIVISOR LATCH (MS)
 
 ;;;;;;;;;;;;;;;;;;;;;;
 ; eof - std-s100.inc ;
 ;;;;;;;;;;;;;;;;;;;;;;
-