From 5e08740456157363bcaecbf6d6933cd860d526ea Mon Sep 17 00:00:00 2001 From: wwarthen Date: Sat, 18 Oct 2014 19:02:13 +0000 Subject: [PATCH] Reintegrate wbw26 -> trunk --- Doc/ChangeLog.txt | 6 ++- ReadMe.txt | 4 +- Source/BIOS/dsrtc.asm | 107 +++++++++++++++++------------------------- Source/BIOS/util.asm | 27 ++++++++++- Source/BIOS/ver.inc | 8 ++-- 5 files changed, 79 insertions(+), 73 deletions(-) diff --git a/Doc/ChangeLog.txt b/Doc/ChangeLog.txt index 81279518..65c71bf2 100644 --- a/Doc/ChangeLog.txt +++ b/Doc/ChangeLog.txt @@ -1,4 +1,8 @@ -Version 2.6.2 +Version 2.6.4 +------------- +- WBW: Yet more DS1302 clock driver delay mods + +Version 2.6.3 ------------- - WBW: DS1302 clock driver modified to observe proper delays diff --git a/ReadMe.txt b/ReadMe.txt index 5718c7db..6c6adc7d 100644 --- a/ReadMe.txt +++ b/ReadMe.txt @@ -8,8 +8,8 @@ Builders: Wayne Warthen (wwarthen@gmail.com) Douglas Goodall (douglas_goodall@mac.com) David Giles (vk5dg@internode.on.net) -Updated: 2014-10-13 -Version: 2.6.3 +Updated: 2014-10-18 +Version: 2.6.4 This is an adaptation of CP/M-80 2.2 and ZSDOS/ZCPR targeting ROMs for all N8VEM Z80 hardware variations diff --git a/Source/BIOS/dsrtc.asm b/Source/BIOS/dsrtc.asm index 94b37d73..0e3c7b60 100644 --- a/Source/BIOS/dsrtc.asm +++ b/Source/BIOS/dsrtc.asm @@ -141,17 +141,6 @@ DSRTC_GETTIM: CALL DSRTC_RDCLK ; READ THE CLOCK LD HL,DSRTC_TIMBUF ; POINT TO TIME BUFFER CALL DSRTC_CLK2TIM ; CONVERT CLOCK TO TIME -;; -; ; NOW COPY TO REAL DESTINATION (INTERBANK SAFE) -; LD C,BID_BIOS ; SOURCE BANK IS HBIOS -; LD A,(HBX_CURBNK) ; GET CURRENT BANK -; LD B,A ; .. AND USE AS DEST BANK -; LD (HBX_SRCBNK),BC ; SET COPY BANKS -; LD HL,DSRTC_TIMBUF ; SOURCE ADR -; POP DE ; DEST ADR -; LD BC,6 ; LENGTH IS 6 BYTES -; LD A,BID_BIOS ; RET BANK IS HBIOS -; CALL HB_COPY ; COPY THE CLOCK DATA ; LD C,BID_HB ; SOURCE BANK IS OUR BANK CALL HBXX_GETBNK ; GET USER BANK @@ -174,16 +163,7 @@ DSRTC_GETTIM: ; DSRTC_SETTIM: ; -; ; COPY INCOMING TIME DATA TO OUR TIME BUFFER -; LD A,(HBX_CURBNK) ; GET CURRENT BANK -; LD C,A ; .. AND USE AS SOURCE BANK -; LD B,BID_BIOS ; DESTINATION BANK IS HBIOS -; LD (HBX_SRCBNK),BC ; SET COPY BANKS -; LD DE,DSRTC_TIMBUF ; DEST ADR -; LD BC,6 ; LENGTH IS 6 BYTES -; LD A,BID_BIOS ; RET BANK IS HBIOS -; CALL HB_COPY ; COPY THE CLOCK DATA -; + ; COPY INCOMING TIME DATA TO OUR TIME BUFFER CALL HBXX_GETBNK LD C,A LD B,BID_HB @@ -276,7 +256,7 @@ DSRTC_RDCLK1: INC HL ; INC BUF POINTER POP BC ; RESTORE BC DJNZ DSRTC_RDCLK1 ; LOOP IF NOT DONE - JR DSRTC_END ; FINISH IT + JP DSRTC_END ; FINISH IT ; ; BURST WRITE CLOCK DATA FROM BUFFER AT HL ; @@ -299,7 +279,7 @@ DSRTC_WRCLK1: DJNZ DSRTC_WRCLK1 ; LOOP IF NOT DONE LD A,$80 ; ADD CONTROL REG BYTE, $80 = PROTECT ON CALL DSRTC_PUT ; WRITE REQUIRED 8TH BYTE - JR DSRTC_END ; FINISH IT + JP DSRTC_END ; FINISH IT ; ; SEND COMMAND IN C TO RTC ; ALL RTC SEQUENCES MUST CALL THIS FIRST TO SEND THE RTC COMMAND. @@ -310,47 +290,51 @@ DSRTC_WRCLK1: ; 0) ASSUME ALL LINES UNDEFINED AT ENTRY ; 1) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA) ; 2) WAIT 1US -; 3) ASSERT CE +; 3) SET CE HI ; 4) WAIT 1US ; 5) PUT COMMAND ; DSRTC_CMD: - XOR A ; ALL LINES OFF TO CLEAN UP + XOR A ; ALL LINES LOW TO RESET OUT (DSRTC_BASE),A ; WRITE TO RTC PORT - EX (SP), IX \ EX (SP), IX ; WAIT 1US - XOR DSRTC_CE ; RUN ON CE + CALL DLY2MS ; DELAY 2MS + XOR DSRTC_CE ; NOW SET CE HIGH OUT (DSRTC_BASE),A ; WRITE TO RTC PORT - EX (SP), IX \ EX (SP), IX ; WAIT 1US + CALL DLY2MS ; DELAY 2MS LD A,C ; LOAD COMMAND CALL DSRTC_PUT ; WRITE IT RET ; ; WRITE BYTE IN A TO THE RTC ; WRITE BYTE IN A TO THE RTC. CE IS IMPLICITY ASSERTED AT -; THE START. CE AND CLK ARE LEFT HIGH AT THE END. CLOCK -; *MUST* BE LEFT HIGH FROM DSRTC_CMD! -; -; 0) ASSUME ENTRY WITH CE & CLK ASSERTED, RD DEASSERTED, DATA UNKNOWN -; 1) WAIT 250NS (COMPLETE ANY PENDING WRITE) -; 2) DEASSERT CLOCK (LOW) -; 3) WAIT 250NS -; 4) (DE)ASSERT DATA (ACCORDING TO BIT VALUE) -; 5) ASSERT CLOCK (HIGH) +; THE START. CE AND CLK ARE LEFT HIGH AT THE END IN CASE +; NEXT ACTION IS A READ. +; +; 0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED +; 1) SET CLK LO +; 2) WAIT 250NS +; 3) SET DATA ACCORDING TO BIT VALUE +; 4) SET CLOCK HI +; 5) WAIT 250NS (CLOCK READS DATA BIT FROM BUS) ; 6) LOOP FOR 8 DATA BITS +; 7) EXIT WITH CE,CLK HI ; DSRTC_PUT: LD B,8 ; LOOP FOR 8 BITS + LD C,A ; SAVE THE WORKING VALUE DSRTC_PUT1: - NOP \ NOP \ NOP ; WAIT 250NS + LD A,DSRTC_CE ; SET CLOCK LOW + OUT (DSRTC_BASE),A ; DO IT + CALL DLY1MS ; DELAY 1MS + LD A,C ; RECOVER WORKING VALUE RRCA ; ROTATE NEXT BIT TO SEND INTO BIT 7 LD C,A ; SAVE WORKING VALUE AND %10000000 ; ISOLATE THE DATA BIT - OR DSRTC_CE ; SET CHIP ENABLE BIT - OUT (DSRTC_BASE),A ; WRITE TO PORT (CLOCK IS LOW) - NOP \ NOP \ NOP ; WAIT 250NS - XOR DSRTC_CLK ; TURN CLOCK ON - OUT (DSRTC_BASE),A ; WRITE TO PORT TO SET CLOCK HIGH - LD A,C ; RECOVER WORKING VALUE + OR DSRTC_CE ; KEEP CE HIGH + OUT (DSRTC_BASE),A ; ASSERT DATA BIT ON BUS + OR DSRTC_CLK ; SET CLOCK HI + OUT (DSRTC_BASE),A ; DO IT + CALL DLY1MS ; DELAY 1MS DJNZ DSRTC_PUT1 ; LOOP IF NOT DONE RET ; @@ -359,33 +343,32 @@ DSRTC_PUT1: ; ASSERTED AT THE START. CE AND CLK ARE LEFT HIGH AT ; THE END. CLOCK *MUST* BE LEFT HIGH FROM DSRTC_CMD! ; -; 0) ASSUME ENTRY WITH CE & CLK ASSERTED, RD DEASSERTED, DATA UNKNOWN -; 1) WAIT 250NS (COMPLETE ANY PENDING WRITE) -; 2) ASSERT RD AND DEASSERT DATA -; 3) DEASSERT CLOCK (LOW) -; 4) WAIT 250NS -; 5) READ DATA BIT -; 5) ASSERT CLOCK (HIGH) -; 6) LOOP FOR 8 DATA BITS +; 0) ASSUME ENTRY WITH CE HI, OTHERS UNDEFINED +; 1) SET RD HI AND CLOCK LOW +; 3) WAIT 250NS (CLOCK PUTS DATA BIT ON BUS) +; 4) READ DATA BIT +; 5) SET CLOCK HI +; 6) WAIT 250NS +; 7) LOOP FOR 8 DATA BITS +; 8) EXIT WITH CE,CLK,RD HI ; DSRTC_GET: - NOP \ NOP \ NOP ; WAIT 250NS LD C,0 ; INITIALIZE WORKING VALUE TO 0 LD B,8 ; LOOP FOR 8 BITS DSRTC_GET1: - LD A,DSRTC_RD | DSRTC_CE | DSRTC_CLK ; ASSERT RD, DEASSERT DATA - OUT (DSRTC_BASE),A ; WRITE TO RTC PORT - XOR DSRTC_CLK ; DEASSERT CLOCK + LD A,DSRTC_CE | DSRTC_RD ; SET CLK LO OUT (DSRTC_BASE),A ; WRITE TO RTC PORT - NOP \ NOP \ NOP ; WAIT 250NS + CALL DLY1MS ; DELAY 1MS + ;CALL DLY1MS ; DELAY 1MS IN A,(DSRTC_BASE) ; READ THE RTC PORT AND %00000001 ; ISOLATE THE DATA BIT OR C ; COMBINE WITH WORKING VALUE RRCA ; ROTATE FOR NEXT BIT LD C,A ; SAVE WORKING VALUE - LD A,DSRTC_CLK | DSRTC_RD | DSRTC_CE ; CLOCK BACK TO HIGH NOW + LD A,DSRTC_CE | DSRTC_CLK | DSRTC_RD ; CLOCK BACK TO HI OUT (DSRTC_BASE),A ; WRITE TO RTC PORT - DJNZ DSRTC_GET1 ; LOOP IF NOT DONE + CALL DLY1MS ; DELAY 1MS + DJNZ DSRTC_GET1 ; LOOP IF NOT DONE (13) LD A,C ; GET RESULT INTO A RET ; @@ -393,18 +376,14 @@ DSRTC_GET1: ; FINISHES UP A COMMAND SEQUENCE. ; DOES NOT DESTROY ANY REGISTERS. ; -; 1) WAIT 250NS (COMPLETE ANY PENDING WRITE) -; 2) DEASSERT ALL LINES (CE, RD, CLOCK, & DATA) +; 1) SET ALL LINES LO ; DSRTC_END: - NOP \ NOP \ NOP ; WAIT 250NS PUSH AF ; SAVE AF XOR A ; ALL LINES OFF TO CLEAN UP OUT (DSRTC_BASE),A ; WRITE TO RTC PORT POP AF ; RESTORE AF RET - - ; ; WORKING VARIABLES ; diff --git a/Source/BIOS/util.asm b/Source/BIOS/util.asm index 688e2ffe..02c17579 100644 --- a/Source/BIOS/util.asm +++ b/Source/BIOS/util.asm @@ -514,12 +514,15 @@ DIV10: INC C ;******************************* ; ; DELAY ABOUT 25us (100 TSTATES INCLUDING CALL AND RET) +; NO REGISTERS DESTROYED ; ; TOTAL T STATES = ((B*13) + 51) -; 4MHZ CPU, B=4, 103 T STATES = 25.75us -; 8MHZ CPU, B=12, 207 TSTATES = 25.875us ; B = ((2 * FREQ) - 4) ; +; 4MHZ CPU, B=4, 103 T STATES = 25.75us +; 8MHZ CPU, B=12, 207 T STATES = 25.875us +; 32MHZ CPU, B=60, 831 T STATES = 25.969us +; DELAY: ; 17 T STATES (FOR CALL) PUSH BC ; 11 T STATES LD B,((CPUFREQ * 2) - 4) ; 8 T STATES @@ -546,6 +549,26 @@ LDELAY: POP DE RET ; +; SHORT DELAY FUNCTIONS. THESE ASSUME A CLOCK SPEED OF 33MHZ, +; SO THEY WILL RUN LONGER FOR SLOWER CLOCK SPEEDS. SO, THESE +; ARE ONLY APPROPRIATE FOR VERY SHORT DELAYS. +; +DLY64MS: + CALL DLY32MS +DLY32MS: + CALL DLY16MS +DLY16MS: + CALL DLY8MS +DLY8MS: + CALL DLY4MS +DLY4MS: + CALL DLY2MS +DLY2MS: + CALL DLY1MS +DLY1MS: + RET + +; ; MULTIPLY 8-BIT VALUES ; IN: MULTIPLY H BY E ; OUT: HL = RESULT, E = 0, B = 0 diff --git a/Source/BIOS/ver.inc b/Source/BIOS/ver.inc index abf0ef21..8d8b483b 100644 --- a/Source/BIOS/ver.inc +++ b/Source/BIOS/ver.inc @@ -1,7 +1,7 @@ #DEFINE RMJ 2 #DEFINE RMN 6 -#DEFINE RUP 3 -#DEFINE RTP 14 -#DEFINE BIOSVER "2.6.3" -#DEFINE BIOSBLD "Build 15" +#DEFINE RUP 4 +#DEFINE RTP 16 +#DEFINE BIOSVER "2.6.4" +#DEFINE BIOSBLD "Build 16" #DEFINE REVISION 500