mirror of https://github.com/wwarthen/RomWBW.git
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Revised hbios.asm to compile in 3 modes (ROM/APP/IMG boot). Updated and simplified ROM bank assignments.pull/3/head
Wayne Warthen
10 years ago
14 changed files with 366 additions and 1311 deletions
File diff suppressed because it is too large
@ -1,270 +0,0 @@ |
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; |
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;================================================================================================== |
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; LOADER |
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;================================================================================================== |
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; |
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P2LOC .EQU $F000 ; PHASE 2 RUN LOCATION |
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; |
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#IFDEF ROMLOAD |
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CURBNK .EQU BID_BOOT |
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#ELSE |
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CURBNK .EQU BID_USR |
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#ENDIF |
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; |
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;================================================================================================== |
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; HBIOS CONFIGURATION BLOCK (HCB) |
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;================================================================================================== |
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; |
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.ORG $ + P2LOC |
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CB: |
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.DB 'W',~'W' ; MARKER |
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.DB RMJ << 4 | RMN ; FIRST BYTE OF VERSION INFO |
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.DB RUP << 4 | RTP ; SECOND BYTE OF VERSION INFO |
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; |
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CB_PLT .DB PLATFORM |
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CB_CPUMHZ .DB CPUMHZ |
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CB_CPUKHZ .DW CPUKHZ |
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CB_RAMBANKS .DB RAMSIZE / 32 |
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CB_ROMBANKS .DB ROMSIZE / 32 |
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; |
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CB_BOOTVOL .DW 0 ; BOOT VOLUME IS UNIT/SLICE, SET BY LOADER |
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CB_BOOTBID .DB 0 ; BOOT BANK ID, SET BY LOADER |
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CB_SERDEV .DB 0 ; PRIMARY SERIAL UNIT IS UNIT #0 BY FIAT |
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CB_CRTDEV .DB $FF ; PRIMARY CRT UNIT, $FF UNTIL AFTER HBIOS INIT |
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CB_CONDEV .DB $FF ; CONSOLE UNIT, $FF UNTIL AFTER HBIOS INIT |
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; |
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;CB_CUREMU .DB VDAEMU ; CURRENT VDA TERMINAL EMULATION (DEPRECATED) |
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;CB_CURVDA .DB VDADEV ; CURRENT VDA TARGET FOR EMULATION (DEPRECATED) |
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; |
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; MEMORY MANAGEMENT VARIABLES START AT $20 |
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; |
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.FILL (CB + $20 - $),0 |
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; |
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CB_HEAP .DW 0 |
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CB_HEAPTOP .DW 0 |
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; |
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; STANDARD BANK ID'S START AT $D8 |
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; |
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.FILL (CB + $D8 - $),0 |
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; |
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CB_BIDCOM .DB BID_COM |
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CB_BIDUSR .DB BID_USR |
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CB_BIDBIOS .DB BID_BIOS |
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CB_BIDAUX .DB BID_AUX |
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CB_BIDRAMD0 .DB BID_RAMD0 |
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CB_BIDRAMDN .DB BID_RAMDN |
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CB_BIDROMD0 .DB BID_ROMD0 |
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CB_BIDROMDN .DB BID_ROMDN |
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; |
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.FILL (CB + HCB_SIZ - $),0 ; PAD REMAINDER OF HCB |
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; |
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.ORG $ - P2LOC |
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; |
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;================================================================================================== |
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; COLD START |
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;================================================================================================== |
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; |
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START: |
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DI ; NO INTERRUPTS |
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IM 1 ; INTERRUPT MODE 1 |
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LD SP,HBX_LOC ; SETUP INITIAL STACK JUST BELOW HBIOS PROXY |
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; |
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; HARDWARE BOOTSTRAP FOR Z180 |
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; FOR N8, ACR & RMAP ARE ASSUMED TO BE ALREADY SET OR THIS CODE |
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; WOULD NOT BE EXECUTING |
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; |
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#IF ((PLATFORM == PLT_N8) | (PLATFORM == PLT_MK4)) |
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; SET BASE FOR CPU IO REGISTERS |
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LD A,Z180_BASE |
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OUT0 (Z180_ICR),A |
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|
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; DISABLE REFRESH |
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XOR A |
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OUT0 (Z180_RCR),A |
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|
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; SET DEFAULT CPU CLOCK MULTIPLIERS (XTAL / 2) |
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XOR A |
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OUT0 (Z180_CCR),A |
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OUT0 (Z180_CMR),A |
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|
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; SET DEFAULT WAIT STATES |
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LD A,$F0 |
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OUT0 (Z180_DCNTL),A |
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|
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; MMU SETUP |
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LD A,$80 |
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OUT0 (Z180_CBAR),A ; SETUP FOR 32K/32K BANK CONFIG |
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#IFDEF ROMLOAD |
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XOR A |
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OUT0 (Z180_BBR),A ; BANK BASE = 0 |
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#ENDIF |
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LD A,(RAMSIZE + RAMBIAS - 64) >> 2 |
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OUT0 (Z180_CBR),A ; COMMON BASE = LAST (TOP) BANK |
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|
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#IF (Z180_CLKDIV >= 1) |
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; SET CLOCK DIVIDE TO 1 RESULTING IN FULL XTAL SPEED |
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LD A,$80 |
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OUT0 (Z180_CCR),A |
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#ENDIF |
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|
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#IF (Z180_CLKDIV >= 2) |
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; SET CPU MULTIPLIER TO 1 RESULTING IN XTAL * 2 SPEED |
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LD A,$80 |
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OUT0 (Z180_CMR),A |
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#ENDIF |
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|
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; SET DESIRED WAIT STATES |
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LD A,0 + (Z180_MEMWAIT << 6) | (Z180_IOWAIT << 4) |
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OUT0 (Z180_DCNTL),A |
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#ENDIF |
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; |
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; HARDWARE BOOTSTRAP FOR ZETA 2 |
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; |
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#IF (PLATFORM == PLT_ZETA2) |
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; SET PAGING REGISTERS |
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#IFDEF ROMLOAD |
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XOR A |
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OUT (MPGSEL_0),A |
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INC A |
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OUT (MPGSEL_1),A |
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#ENDIF |
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LD A,62 |
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OUT (MPGSEL_2),A |
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INC A |
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OUT (MPGSEL_3),A |
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; ENABLE PAGING |
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LD A,1 |
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OUT (MPGENA),A |
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#ENDIF |
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; |
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; EMIT FIRST SIGN OF LIFE TO SERIAL PORT |
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; |
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CALL XIO_INIT ; INIT SERIAL PORT |
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#IFNDEF ROMLOAD |
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CALL XIO_CRLF ; FORMATTING |
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#ENDIF |
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LD HL,STR_BOOT ; POINT TO MESSAGE |
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CALL XIO_OUTS ; SAY HELLO |
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; |
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; COPY OURSELVES AND LOADER TO HI RAM FOR PHASE 2 |
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; |
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LD HL,0 ; COPY FROM START OF ROM IMAGE |
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LD DE,P2LOC ; TO HIMEM RUN LOCATION |
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LD BC,LDR_END ; COPY FULL IMAGE |
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LDIR |
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; |
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CALL XIO_DOT ; MARK PROGRESS |
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; |
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JP PHASE2 ; JUMP TO PHASE 2 BOOT IN UPPER MEMORY |
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; |
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STR_BOOT .DB "RomWBW$" |
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; |
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; IMBED DIRECT SERIAL I/O ROUTINES |
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; |
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#INCLUDE "xio.asm" |
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#INCLUDE "decode.asm" |
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; |
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;______________________________________________________________________________________________________________________ |
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; |
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; THIS IS THE PHASE 2 CODE THAT MUST EXECUTE IN UPPER MEMORY |
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; |
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.ORG $ + P2LOC ; WE ARE NOW EXECUTING IN UPPER MEMORY |
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; |
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PHASE2: |
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CALL XIO_DOT ; MARK PROGRESS |
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; |
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; INSTALL HBIOS PROXY IN UPPER MEMORY |
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; |
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#IFDEF ROMLOAD |
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LD A,BID_BIOSIMG ; HBIOS IMAGE ROM BANK |
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CALL BNKSEL ; SELECT IT |
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#ENDIF |
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LD HL,HBX_IMG ; HL := SOURCE OF HBIOS PROXY IMAGE |
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#IFNDEF ROMLOAD |
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LD BC,LDR_END ; SIZE OF LOADER |
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ADD HL,BC ; OFFSET SOURCE ADDRESS |
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#ENDIF |
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LD DE,HBX_LOC ; DE := DESTINATION TO INSTALL IT |
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LD BC,HBX_SIZ ; SIZE |
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LDIR ; DO THE COPY |
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LD A,CURBNK ; BOOT/SETUP BANK |
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LD (HB_CURBNK),A ; INIT CURRENT BANK |
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#IFDEF ROMLOAD |
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CALL BNKSEL ; SELECT IT |
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#ENDIF |
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CALL XIO_DOT ; MARK PROGRESS |
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; |
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; INSTALL HBIOS CODE BANK |
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; |
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#IFDEF ROMLOAD |
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LD A,BID_BIOSIMG ; SOURCE BANK |
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#ELSE |
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LD A,(HB_CURBNK) ; SOURCE BANK |
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#ENDIF |
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LD (HB_SRCBNK),A ; SET IT |
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LD A,BID_BIOS ; DESTINATION BANK |
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LD (HB_DSTBNK),A ; SET IT |
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LD HL,0 ; SOURCE ADDRESS IS ZERO |
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#IFNDEF ROMLOAD |
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LD BC,LDR_END ; SIZE OF LOADER |
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ADD HL,BC ; OFFSET SOURCE ADDRESS |
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#ENDIF |
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LD DE,0 ; TARGET ADDRESS IS ZERO |
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LD BC,HB_END ; COPY ALL OF HBIOS IMAGE |
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CALL XIO_DOT ; MARK PROGRESS |
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CALL HB_BNKCPY ; DO IT |
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CALL XIO_DOT ; MARK PROGRESS |
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; |
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; INSTALL HCB INTO HBIOS CODE BANK |
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; |
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LD A,BID_BIOS ; GET BIOS BANK |
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LD (HB_SRCBNK),A ; SET AS SOURCE (IRRELEVANT) |
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LD (HB_DSTBNK),A ; SET AS DEST |
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LD HL,CB ; LOCAL LOADER HCB ADDRESS |
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LD DE,HCB_LOC ; DEST HBIOS HCB ADDRESS |
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LD BC,HCB_SIZ ; ONE PAGE IN LENGTH |
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CALL HB_BNKCPY ; DO IT |
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CALL XIO_DOT ; MARK PROGRESS |
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; |
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; |
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; INITIALIZE HBIOS |
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; |
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CALL XIO_SYNC ; FLUSH OUTPUT FIFO |
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LD A,BID_BIOS ; HBIOS BANK |
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LD HL,0 ; ADDRESS 0 IS HBIOS INIT ENTRY ADDRESS |
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CALL HB_BNKCALL ; DO IT |
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; |
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; CHAIN TO OS LOADER |
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; |
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#IFDEF ROMLOAD |
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; PERFORM BANK CALL TO OS IMAGES BANK |
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LD A,BID_OSIMG ; CHAIN TO OS IMAGES BANK |
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LD HL,0 ; ENTER AT ADDRESS 0 |
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CALL HB_BNKCALL ; GO THERE |
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HALT ; WE SHOULD NEVER COME BACK! |
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#ELSE |
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; SLIDE OS IMAGES BLOB DOWN TO $0000 |
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LD HL,LDR_END ; SOURCE IS LOADER END |
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LD BC,HB_END ; PLUS HBIOS IMAGE SIZE |
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ADD HL,BC ; FINAL SOURCE ADDRESS |
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LD DE,0 ; TARGET ADDRESS IS ZERO |
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LD BC,BNKTOP ; MAX SIZE OF OS IMAGES |
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LDIR ; DO IT |
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; JUMP TO START |
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JP 0 ; AND CHAIN |
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#ENDIF |
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; |
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;================================================================================================== |
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; MEMORY MANAGER |
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;================================================================================================== |
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; |
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#IFDEF ROMLOAD |
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#INCLUDE "memmgr.asm" |
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#ENDIF |
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; |
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;================================================================================================== |
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; CLEAN UP |
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;================================================================================================== |
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; |
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.ORG $ - P2LOC ; BACK TO IMAGE-BASED ADDRESSING |
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LDR_END .EQU $ ; MARK END OF LOADER |
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