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Finalize RC2014 floppy updates

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RC2014 floppy controller support completed and tested for Scott Baker
SMC and WDC controller modules.  FDU application updated as well.
This commit is contained in:
Wayne Warthen
2018-01-08 16:45:43 -08:00
parent 768e41c933
commit 5fc01b4100
13 changed files with 246 additions and 98 deletions
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70
Source/HBIOS/fd.asm
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@@ -8,7 +8,7 @@
;
; PORTS
;
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
FDC_MSR .EQU $36 ; 8272 MAIN STATUS REGISTER
FDC_DATA .EQU $37 ; 8272 DATA PORT
FDC_DIR .EQU $38 ; DATA INPUT REGISTER
@@ -41,14 +41,18 @@ FDC_DACK .EQU $90 ; DACK
FDC_TC .EQU $93 ; TERMINAL COUNT (W/ DACK)
FDC_DMA .EQU $3C ; NOT USED BY N8
#ENDIF
#IF (FDMODE = FDMODE_SMBWDC)
#IF (FDMODE == FDMODE_RCSMC)
FDC_MSR .EQU $50 ; 8272 MAIN STATUS REGISTER
FDC_DATA .EQU $51 ; 8272 DATA PORT
FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER (LATCH)
#ENDIF
#IF (FDMODE = FDMODE_RCWDC)
FDC_MSR .EQU $50 ; 8272 MAIN STATUS REGISTER
FDC_DATA .EQU $51 ; 8272 DATA PORT
FDC_DOR .EQU $58 ; DIGITAL OUTPUT REGISTER
FDC_DCR .EQU $48 ; CONFIGURATION CONTROL REGISTER
FDC_TC .EQU $58 ; TERMINAL COUNT (W/ DACK)
#ENDIF
;
; DISK OPERATIONS
;
@@ -352,7 +356,7 @@ DOR_INIT .EQU 11010010B ; INITIAL DEFAULT LATCH VALUE
;D1 MOTOR 0 (OFF) 0 (OFF)
;D0 TC 0 (OFF) 0 (OFF)
;
; MOTOR AND DENSITY SELECT ARE INVERTED ON ZETA/DISKIO3
; MOTOR AND DENSITY SELECT ARE INVERTED ON ZETA/DISKIO3 VS. DIO
;
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
DOR_BR250 .EQU 11100110B ; 250KBPS W/ MOTOR ON
@@ -360,17 +364,34 @@ DOR_BR500 .EQU 10100010B ; 500KBPS W/ MOTOR ON
DOR_INIT .EQU 10100000B ; INITIAL DEFAULT LATCH VALUE
#ENDIF
;
; MOTOR INVERTED, DENSITY SELECT NORMAL FOR SMB SMC
; RCSMC 250KBPS 500KBPS
; ------------ ------- -------
;D7 /FDC_RST 1 (RUN) 1 (RUN)
;D6 DENSEL 0 (DD) 1 (HD)
;D5 P0 (PRECOMP BIT 0) 1 \ 1 \
;D4 P1 (PRECOMP BIT 1) 0 (125NS) 0 (125NS)
;D3 P2 (PRECOMP BIT 2) 0 / 0 /
;D2 MOTORB 0 (OFF) 0 (OFF)
;D1 MOTORA 0 (OFF) 0 (OFF)
;D0 TC 0 (OFF) 0 (OFF)
;
#IF (FDMODE == FDMODE_SMBSMC)
DOR_BR250 .EQU 10100110B ; 250KBPS W/ MOTOR ON
DOR_BR500 .EQU 11100010B ; 500KBPS W/ MOTOR ON
; MOTOR INVERTED VS. DIO, DENSITY SELECT LIKE DIO
;
#IF (FDMODE == FDMODE_RCSMC)
; RCSMC HAS NO MINI (BITRATE) LATCH AT D2. INSTEAD, D1 AND
; D2 PROVIDE INDEPENDENT MOTOR CONTROL FOR EACH DRIVE.
; MINI (BITRATE) IS A HARDWARE JUMPER (JP3)
; JP3: 1-2 IS DD (MINI HIGH) AND 2-3 IS HD (MINI LOW)
; JP3 *MUST* BE SET CORRECTLY FOR MEDIA USED
; THE CORRECT MOTOR BIT IS SET IN MOTOR ON, NEITHER SET HERE
DOR_BR250 .EQU 10100000B ; 250KBPS W/ MOTOR OFF!
DOR_BR500 .EQU 11100000B ; 500KBPS W/ MOTOR OFF!
DOR_INIT .EQU 11100000B ; INITIAL DEFAULT LATCH VALUE
#ENDIF
;
; *** DIDE/N8/ZETA V2 ***
;
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
DOR_INIT .EQU 00001100B ; SOFT RESET INACTIVE, DMA ENABLED
DOR_BR250 .EQU DOR_INIT
DOR_BR500 .EQU DOR_INIT
@@ -1174,7 +1195,7 @@ FC_SETDOR
;
; SET FST_DCR
;
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
;
FC_SETDCR
LD (FST_DCR),A
@@ -1203,10 +1224,10 @@ FC_RESETFDC:
LD A,(FST_DOR)
PUSH AF
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_RCSMC))
RES 7,A
#ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
LD A,0
#ENDIF
CALL FC_SETDOR
@@ -1221,7 +1242,7 @@ FC_RESETFDC:
; PULSE TERMCT TO TERMINATE ANY ACTIVE EXECUTION PHASE
;
FC_PULSETC:
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
IN A,(FDC_TC)
#ELSE
LD A,(FST_DOR)
@@ -1243,7 +1264,7 @@ FC_MOTORON:
LD DE,FDSTR_MOTON
CALL WRITESTR
#ENDIF
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_DIO) | (FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
LD A,(FST_DOR)
PUSH AF
@@ -1251,13 +1272,30 @@ FC_MOTORON:
CALL FC_SETDOR ; AND IMPLEMENT IT
POP AF
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3) | (FDMODE == FDMODE_SMBSMC))
#IF ((FDMODE == FDMODE_ZETA) | (FDMODE == FDMODE_DIO3))
XOR 00000010B ; MOTOR BIT INVERTED ON ZETA
#ENDIF
BIT 1,A ; SET FLAGS SET BASED ON CURRENT MOTOR BIT
RET Z ; MOTOR WAS PREVIOUSLY ON, WE ARE DONE
#ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_SMBWDC))
#IF (FDMODE == FDMODE_RCSMC)
LD A,(FCD_DS) ; GET DRIVE SELECTED (0 OR 1)
LD C,%00000010 ; MASK FOR MOTORA ON (BIT 1 IS MOTORA)
OR A ; SET FLAGS BASED ON FCD_DS
JR Z,FC_MOTORON1 ; IF FCD_DS == 0, MOTORA IS CORRECT
LD C,%00000100 ; ELSE MASK FOR MOTORB ON (BIT 2 IS MOTORB)
FC_MOTORON1:
LD A,(FST_DOR) ; GET CURRENT DOR VALUE
PUSH AF ; SAVE IT
LD A,(FCD_DOR) ; GET NEW DOR VALUE (W/O MOTOR BITS SET)
OR C ; ADD THE MOTOR BITS
CALL FC_SETDOR ; AND IMPLEMENT NEW VALUE
POP AF ; RECOVER PREVIOUS DOR VALUE
AND %00000110 ; ISOLATE PREVIOUS MOTOR BITS
CP C ; COMPARE TO NEW MOTOR BITS
RET Z ; SKIP DELAY, MOTOR WAS ALREADY ON
#ENDIF
#IF ((FDMODE == FDMODE_DIDE) | (FDMODE == FDMODE_N8) | (FDMODE == FDMODE_ZETA2) | (FDMODE == FDMODE_RCWDC))
; SETUP DCR FOR DIDE HARDWARE
LD A,(FCD_DCR) ; GET NEW DCR VALUE
CALL FC_SETDCR ; AND IMPLEMENT IT