From 60c4f58fb444a02d47a857034fea353fc14e33bf Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Fri, 16 Jan 2026 13:56:17 -0800 Subject: [PATCH] SCC Tweaks for Interrupt Mode 2 --- Source/HBIOS/cfg_RCZ180.asm | 21 +++++++++++++++++++++ Source/HBIOS/cfg_RCZ280.asm | 21 +++++++++++++++++++++ Source/HBIOS/scc.asm | 4 +++- Source/HBIOS/std.asm | 4 ++++ Source/ver.inc | 2 +- Source/ver.lib | 2 +- 6 files changed, 51 insertions(+), 3 deletions(-) diff --git a/Source/HBIOS/cfg_RCZ180.asm b/Source/HBIOS/cfg_RCZ180.asm index 6ec9e120..0b419911 100644 --- a/Source/HBIOS/cfg_RCZ180.asm +++ b/Source/HBIOS/cfg_RCZ180.asm @@ -257,6 +257,27 @@ SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +SCCDEBUG .SET FALSE ; SCC: ENABLE DEBUG OUTPUT +SCCBOOT .SET 0 ; SCC: REBOOT ON RCV CHAR (0=DISABLED) +SCCCNT .SET 1 ; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SCCINTS .SET TRUE ; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3 +SCCPCLK .SET TRUE ; SCC: USE PROCESSOR CLOCK AS BAUD CLOCK +SCC0MODE .SET SCCMODE_SZ80 ; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80] +SCC0BASE .SET $A0 ; SCC 0: REGISTERS BASE ADR +SCC0ACLK .SET 7372800 ; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC0ACFG .SET DEFSERCFG ; SCC 0A: SERIAL LINE CONFIG +SCC0ACTCC .SET -1 ; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC0BCLK .SET 7372800 ; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC0BCFG .SET DEFSERCFG ; SCC 0B: SERIAL LINE CONFIG +SCC0BCTCC .SET -1 ; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC1MODE .SET SCCMODE_SZ80 ; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80] +SCC1BASE .SET $FF ; SCC 1: REGISTERS BASE ADR +SCC1ACLK .SET 7372800 ; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC1ACFG .SET DEFSERCFG ; SCC 1A: SERIAL LINE CONFIG +SCC1ACTCC .SET -1 ; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC1BCLK .SET 7372800 ; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC1BCFG .SET DEFSERCFG ; SCC 1B: SERIAL LINE CONFIG +SCC1BCTCC .SET -1 ; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/cfg_RCZ280.asm b/Source/HBIOS/cfg_RCZ280.asm index a381c77b..0b26a1e2 100644 --- a/Source/HBIOS/cfg_RCZ280.asm +++ b/Source/HBIOS/cfg_RCZ280.asm @@ -267,6 +267,27 @@ SIO1BCFG .SET DEFSERCFG ; SIO 1B: SERIAL LINE CONFIG SIO1BCTCC .SET -1 ; SIO 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; SCCENABLE .SET FALSE ; SCC: ENABLE ZILOG SCC SERIAL DRIVER (SCC.ASM) +SCCDEBUG .SET FALSE ; SCC: ENABLE DEBUG OUTPUT +SCCBOOT .SET 0 ; SCC: REBOOT ON RCV CHAR (0=DISABLED) +SCCCNT .SET 1 ; SCC: NUMBER OF CHIPS TO DETECT (1-2), 2 CHANNELS PER CHIP +SCCINTS .SET TRUE ; SCC: INCLUDE SCC INTERRUPT SUPPORT UNDER IM1/2/3 +SCCPCLK .SET TRUE ; SCC: USE PROCESSOR CLOCK AS BAUD CLOCK +SCC0MODE .SET SCCMODE_SZ80 ; SCC 0: CHIP TYPE: SCCMODE_[STD|SZ80] +SCC0BASE .SET $A0 ; SCC 0: REGISTERS BASE ADR +SCC0ACLK .SET 7372800 ; SCC 0A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC0ACFG .SET DEFSERCFG ; SCC 0A: SERIAL LINE CONFIG +SCC0ACTCC .SET -1 ; SCC 0A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC0BCLK .SET 7372800 ; SCC 0B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC0BCFG .SET DEFSERCFG ; SCC 0B: SERIAL LINE CONFIG +SCC0BCTCC .SET -1 ; SCC 0B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC1MODE .SET SCCMODE_SZ80 ; SCC 1: CHIP TYPE: SIOMODE_[STD|SZ80] +SCC1BASE .SET $FF ; SCC 1: REGISTERS BASE ADR +SCC1ACLK .SET 7372800 ; SCC 1A: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC1ACFG .SET DEFSERCFG ; SCC 1A: SERIAL LINE CONFIG +SCC1ACTCC .SET -1 ; SCC 1A: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE +SCC1BCLK .SET 7372800 ; SCC 1B: OSC FREQ IN HZ, ZP=2457600/4915200, RC/SMB=7372800 +SCC1BCFG .SET DEFSERCFG ; SCC 1B: SERIAL LINE CONFIG +SCC1BCTCC .SET -1 ; SCC 1B: CTC CHANNEL 0=A, 1=B, 2=C, 3=D, -1 FOR NONE ; XIOCFG .SET DEFSERCFG ; XIO: SERIAL LINE CONFIG ; diff --git a/Source/HBIOS/scc.asm b/Source/HBIOS/scc.asm index 72f0511a..db5e0747 100644 --- a/Source/HBIOS/scc.asm +++ b/Source/HBIOS/scc.asm @@ -721,6 +721,7 @@ SCC_INITGO1: SCC_INITDEFS: .DB 4, $44 ; ASYNC MODE, X16, 1 STOP, NO PARITY ; 0100 0100 .DB 1, SCC_WR1VAL ; CONFIGURE INTERRUPTS + .DB 2, $00 ; INTERRUPT VECTOR ; 0000 0000 .DB 3, $C0 ; RX 8 BITS PER CHAR ; 1100 0000 .DB 5, $E2 ; TX 8 BITS PER CHAR ; 1110 0010 .DB 11, $56 ; RTxC VIA BRG ; 0101 0110 @@ -746,7 +747,8 @@ SCC_INITVALS .FILL SCC_INITLEN,0 ; SCC_WR4 .EQU SCC_INITVALS + 1 SCC_WR1 .EQU SCC_WR4 + 2 -SCC_WR3 .EQU SCC_WR1 + 2 +SCC_WR2 .EQU SCC_WR1 + 2 +SCC_WR3 .EQU SCC_WR2 + 2 SCC_WR5 .EQU SCC_WR3 + 2 SCC_WR11 .EQU SCC_WR5 + 2 SCC_WR12 .EQU SCC_WR11 + 2 diff --git a/Source/HBIOS/std.asm b/Source/HBIOS/std.asm index 3126140f..edfa318c 100644 --- a/Source/HBIOS/std.asm +++ b/Source/HBIOS/std.asm @@ -1104,6 +1104,8 @@ INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B INT_SIO0 .EQU 13 ; ZILOG SIO 0, CHANNEL A & B INT_SIO1 .EQU 14 ; ZILOG SIO 1, CHANNEL A & B +INT_SCC0 .EQU 13 ; ZILOG SCC 0, CHANNEL A & B ; OVERLAPS SIO0!!! +INT_SCC1 .EQU 14 ; ZILOG SCC 1, CHANNEL A & B ; OVERLAPS SIO1!!! #ENDIF #IF ((CPUFAM == CPU_Z280) & (INTMODE >= 2)) @@ -1125,6 +1127,8 @@ INT_PIO0A .EQU 9 ; ZILOG PIO 0, CHANNEL A INT_PIO0B .EQU 10 ; ZILOG PIO 0, CHANNEL B INT_PIO1A .EQU 11 ; ZILOG PIO 1, CHANNEL A INT_PIO1B .EQU 12 ; ZILOG PIO 1, CHANNEL B +INT_SCC0 .EQU 13 ; ZILOG SCC 0, CHANNEL A & B +INT_SCC1 .EQU 14 ; ZILOG SCC 1, CHANNEL A & B #ENDIF diff --git a/Source/ver.inc b/Source/ver.inc index dddea178..d54f1bac 100644 --- a/Source/ver.inc +++ b/Source/ver.inc @@ -2,7 +2,7 @@ #DEFINE RMN 6 #DEFINE RUP 0 #DEFINE RTP 0 -#DEFINE BIOSVER "3.6.0-dev.51" +#DEFINE BIOSVER "3.6.0-dev.52" #define rmj RMJ #define rmn RMN #define rup RUP diff --git a/Source/ver.lib b/Source/ver.lib index e9329b18..390eb9d2 100644 --- a/Source/ver.lib +++ b/Source/ver.lib @@ -3,5 +3,5 @@ rmn equ 6 rup equ 0 rtp equ 0 biosver macro - db "3.6.0-dev.51" + db "3.6.0-dev.52" endm