From 6156c4c7657680303ac75b67f69c2a5463b34553 Mon Sep 17 00:00:00 2001 From: Wayne Warthen Date: Sun, 29 Mar 2020 15:42:46 -0700 Subject: [PATCH] XModem Timing Refinements --- Source/Apps/XM/xmdm125.asm | 3 ++- Source/Apps/XM/xmhb.180 | 14 +++++++++++++- 2 files changed, 15 insertions(+), 2 deletions(-) diff --git a/Source/Apps/XM/xmdm125.asm b/Source/Apps/XM/xmdm125.asm index af648a08..ac881800 100644 --- a/Source/Apps/XM/xmdm125.asm +++ b/Source/Apps/XM/xmdm125.asm @@ -2232,7 +2232,8 @@ RCVRPT: IF CONFUN ; Check for function key? JNZ RCVSABT ; If so, bail out now... ENDIF ; - MVI B,10-1 ; 10-second timeout + ;MVI B,10-1 ; 10-second timeout + MVI B,5-1 ; WBW: 5-second timeout CALL RECV ; Get any character received JC RCVSTOT ; Timeout ; diff --git a/Source/Apps/XM/xmhb.180 b/Source/Apps/XM/xmhb.180 index 2abd3a2e..8f926794 100644 --- a/Source/Apps/XM/xmhb.180 +++ b/Source/Apps/XM/xmhb.180 @@ -243,7 +243,7 @@ EXTRA3: ; BIOID DB 0 ; BIOS ID, 1=HBIOS, 2=UBIOS CPUSPD DB 10 ; CPU speed in MHz -RCVSCL DW 2800 ; RECV loop timeout scalar +RCVSCL DW 6600 ; RECV loop timeout scalar ; RBC DB "RBC, 28-Aug-2019$" ; @@ -302,6 +302,9 @@ U_JPTBL: ; UART initialization ; U_INIT: + LD HL,13000 ; Receive loop timeout scalar + LD (RCVSCL),HL ; ... for UART RCVRDY timing +; LD HL,U_JPTBL LD DE,U_LBL JP MINIT_RET @@ -429,6 +432,9 @@ A_JPTBL: ; ASCI initialization ; A_INIT: + LD HL,7500 ; Receive loop timeout scalar + LD (RCVSCL),HL ; ... for ASCI RCVRDY timing +; ; Test for location of Z180 internal registers ; and use appropriate I/O address. LD B,0 ; set MSB for 16 bit I/O @@ -601,6 +607,9 @@ S_JPTBL: ; SIO initialization ; S_INIT: + LD HL,12000 ; Receive loop timeout scalar + LD (RCVSCL),HL ; ... for UART RCVRDY timing +; ; Suppress interrupts LD A,01H ; WR1 OUT (S_CTLP),A ; Select WR1 @@ -841,6 +850,9 @@ UF_JPTBL: ; USB-FIFO initialization ; UF_INIT: + LD HL,12000 ; Receive loop timeout scalar + LD (RCVSCL),HL ; ... for UART RCVRDY timing +; LD HL,UF_JPTBL LD DE,UF_LBL JP MINIT_RET