diff --git a/Source/Images/d_zpm3/u15/tcap.z3t b/Source/Images/d_zpm3/u15/tcap.z3t
index 1a43a949..5f905f8a 100644
Binary files a/Source/Images/d_zpm3/u15/tcap.z3t and b/Source/Images/d_zpm3/u15/tcap.z3t differ
diff --git a/Source/Images/d_zpm3/u15/tcselect.com b/Source/Images/d_zpm3/u15/tcselect.com
new file mode 100644
index 00000000..53f5a38b
Binary files /dev/null and b/Source/Images/d_zpm3/u15/tcselect.com differ
diff --git a/Source/Images/d_zpm3/u15/z3tcap.lbr b/Source/Images/d_zpm3/u15/z3tcap.lbr
new file mode 100644
index 00000000..ae7afa22
Binary files /dev/null and b/Source/Images/d_zpm3/u15/z3tcap.lbr differ
diff --git a/Source/ZZR/ZZR Disk Layout.txt b/Source/ZZR/ZZR Disk Layout.txt
index 18f06fc7..a584b166 100644
--- a/Source/ZZR/ZZR Disk Layout.txt	
+++ b/Source/ZZR/ZZR Disk Layout.txt	
@@ -1,29 +1,35 @@
-CF Boot Loader: Sector 0 (bytes 0-255)
-RomWBW Partition Table: Sector 0 (bytes 256-511)
-ZZRCC Monitor: Sectors 0xF8-0xFF (bytes 0x1F000-0x1FFFF)
-RomWBW: Sectors 0x120-0x31F (bytes 0x24000-0x63FFF)
-Start of Slices (0x1E partition): Sector 0x800 (byte 0x100000)
-
-Start	Length	Description
--------	-------	---------------------------
-0x00000 0x00100	CF Boot Loader
-0x00100 0x00100	RomWBW Partition Table
-0x00200 0x1EE00	Filler
-0x1F000 0x01000	ZZRCC Monitor
-0x20000 0x04000	Filler
-0x24000 0x40000	RomWBW
-0x64000 0x9C000	Filler
-0x100000: Start of slices (partition 0x1E)
+Start   Length  Sector  Count   Description
+------- ------- ------- ------- -----------------------------------------
+0x00000 0x00100 0x000   0x001   CF Boot Loader (first 256 bytes)
+0x00100 0x00100 0x000   0x001   RomWBW Partition Table (last 256 bytes)
+0x00200 0x1EE00 0x001   0x0F7   Filler
+0x1F000 0x01000 0x0F8   0x008   ZZRCC Monitor / RomWBW Loader
+0x20000 0x04000 0x100   0x020   Filler
+0x24000 0x40000 0x120   0x200   RomWBW (256KB ROM image)
+0x64000 0x9C000 0x320   0x4E0   Filler
+0x100000        0x800           Slices
 
 Notes
 -----
 
 - At startup CPLD ROM is mapped to Z80 CPU address space 0x0000-0x003F, CPU begins execution at 0x0000
-- CPLD ROM (CF bootstrap mode) reads CF Boot Loader (256B) from start of CF (MBR) to 0xB000 and runs it
-- CF Boot Loader reads ZRC Monitor (4KB) from sectors 0xF8-0xFF of CF to 0xB400 and runs it
-- User sends ZZRCC RomWBW Loader hex file (?KB) at 0x5000, then runs it using G5000
-- User sends RomWBW ROM hex file, then runs it using G0000
+- CPLD ROM (CF bootstrap mode) loads CF Boot Loader (256B) at 0xB000 and runs it
+- CF Boot Loader loads ZRC Monitor at 0xB400 and runs it
+- User loads ZZRCC RomWBW Loader hex file at 0x5000, then runs it using G5000
+- User loads RomWBW ROM hex file to contents of RAM, then runs it using G0000
 
 
 ;;- ZZRCC Monitor reads 512KB (RomWBW) from sectors 0x120-0x51F of CF into first 512KB of RAM
 
+Possible new layout:
+
+Start   Length  Sector  Count   Description
+------- ------- ------- ------- -----------------------------------------
+0x00000 0x00100 0       1       CF Boot Loader (first 256 bytes)
+0x00100 0x00100 0       1       RomWBW Partition Table (last 256 bytes)
+0x00200 0x01000 0x001   0x008   ZZRCC Monitor / RomWBW Loader
+0x01200 0x7EE00 0x009   0x3F7   Filler
+0x80000 0x40000 0x400   0x200   RomWBW (256KB ROM image)
+0xC0000 0x40000 0x600   0x200   Filler
+0x100000        0x800           Slices (0x1E partition start)
+