Add beep driver for PSG and IOPort

2026-02-06 22:43:15 -06:00 · 2018-08-20 16:58:45 +08:00
parent 2e8d44d005
commit 64901dcbbb
1 changed files with 130 additions and 0 deletions
--- a/Source/HBIOS/sound.asm
+++ b/Source/HBIOS/sound.asm
@@ -0,0 +1,130 @@
+;
+;======================================================================
+; PSG AY-3-8910 DRIVER FOR CONSOLE BELL
+;======================================================================
+;
+#IF (CONBELL == CONBELL_PSG)
+
+PSG_RSEL	.EQU	$9A
+PSG_RDAT	.EQU	$9B
+AYR0CHAP	.EQU	$00
+AYR1CHAP	.EQU	$01
+AYR2CHBP	.EQU	$02
+AYR3CHBP	.EQU	$03
+AYR7ENAB	.EQU	$07
+AYR8AVOL	.EQU	$08
+AYR9BVOL	.EQU	$09 
+;
+;======================================================================
+; PSG AY-3-8910 DRIVER - INITIALIZATION
+;======================================================================
+;
+SND_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("PSG: IO=0x$")
+	LD	A,PSG_RSEL
+	CALL	PRTHEXBYTE
+	CALL	PSG_PROBE		; CHECK FOR HW EXISTENCE
+	JR	Z,PSG_INIT1			; CONTINUE IF PRESENT
+;
+;	HARDWARE NOT PRESENT
+;
+	PRTS(" NOT PRESENT$")
+	OR	$FF					; SIGNAL FAILURE
+	RET
+;	
+PSG_INIT1:
+	CALL	PSG_INIT2
+	CALL	BEEP
+PSG_INIT2:
+	LD A,AYR7ENAB		; SET MIXER CONTROL / IO ENABLE
+	LD E,$FF			; $FF - 11 111 111
+	CALL WRTPSG			; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL C, B, A DISABLE
+;  
+	LD B,2
+	LD A,AYR8AVOL		; SET VOLUME TO 0
+	LD E,$00	
+AYQUIET:
+	CALL WRTPSG			; CYCLING THROUGH ALL CHANNELS
+	INC A
+	DJNZ AYQUIET
+	RET
+;
+;	PLAY A BEEP TONE ON CENTER CHANNEL (LEFT AND RIGHT SPEAKERS)
+;	
+BEEP:
+  LD A,AYR2CHBP		; SET TONE PERIOD 
+  LD E,$55			; CHANNEL B  - R00 & R01
+  CALL WRTPSG		; $0055 = XXXX0000 01010101 
+  LD E,0
+  LD A,AYR3CHBP
+  CALL WRTPSG
+;
+  LD E,$FD			; SET MIXER CONTROL / IO ENABLE
+  LD A,AYR7ENAB		; $FD = 11 111 101
+  CALL WRTPSG		; I/O PORTS DISABLED, NOISE CHANNEL C, B, A DISABLE, TONE CHANNEL B ENABLE
+;  
+  LD E,$07			; SET CHANNEL B VOLUME TO 50% (7/16)
+  LD A,AYR9BVOL		;
+  CALL WRTPSG
+;  
+  CALL LDELAY		; HALF SECOND 
+  RET	
+;	
+; WRITE DATA E TO PSG REG A  
+; 
+WRTPSG:
+	HB_DI
+	OUT (PSG_RSEL),A
+	PUSH AF
+	LD A,E
+	OUT (PSG_RDAT),A
+	HB_EI
+	POP AF
+	RET	
+;
+; CHECK THERE IS A DEVICE PRESENT
+;
+PSG_PROBE:
+	LD	A,$FF
+	OUT	(TMS_ACR),A		; INIT AUX CONTROL REG
+	XOR A
+	RET
+;
+#ENDIF
+;
+;======================================================================
+; I/O BIT DRIVER FOR CONSOLE BELL FOR SBC V2 USING BIT 0 OF RTC DRIVER
+;======================================================================
+;
+#IF (CONBELL == CONBELL_IOBIT)
+
+SND_INIT:
+	CALL	NEWLINE			; FORMATTING
+	PRTS("SND: IO=0x$")
+	LD		A,DSRTC_BASE
+	CALL	PRTHEXBYTE
+	CALL	BEEP
+	XOR		A
+	RET
+
+BEEP:	
+	PUSH	DE
+	PUSH	HL
+	LD		HL,400		; Cycles of tone
+	LD		B,%00000100	; D2 mapped to Q0
+BEEP1:
+	LD		A,B
+	OUT		(DSRTC_BASE),A
+	XOR		%00000100
+	LD		B,A
+	LD		DE,17
+	CALL	VDELAY
+	DEC		HL
+	LD		A,H
+	OR		L
+	JR		NZ,BEEP1
+	POP		HL
+	POP		DE
+	RET
+#ENDIF